Integrated Device Technology Inc IDT72211L12J, IDT72211L12L, IDT72211L12PF, IDT72211L15J, IDT72201L12J Datasheet
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IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMOS SyncFIFO
64 X 9, 256 x 9, 512 x 9,
1024 X 9, 2048 X 9 and 4096 x 9
IDT72421
IDT72201
IDT72211
IDT72221
IDT72231
Integrated Device Technology, Inc.
IDT72241
FEATURES:
• 64 x 9-bit organization (IDT72421)
• 256 x 9-bit organization (IDT72201)
• 512 x 9-bit organization (IDT72211)
• 1024 x 9-bit organization (IDT72221)
• 2048 x 9-bit organization (IDT72231)
• 4096 x 9-bit organization (IDT72241)
• 12 ns read/write cycle time (IDT72421/72201/72211)
• 15 ns read/write cycle time (IDT72221/72231/72241)
• Read and write clocks can be independent
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can
be set to any depth
• Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
• Output enable puts output data bus in high-impedance
state
• Advanced submicron CMOS technology
• Available in 32-pin plastic leaded chip carrier (PLCC),
ceramic leadless chip carrier (LCC), and 32-pin Thin
Quad Flat Pack (TQFP)
• For Through-Hole product please see the IDT72420/
72200/72210/72220/72230/72240 data sheet
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT72421/72201/72211/72221/72231/72241
SyncFIFO are very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.
The IDT72421/72201/72211/72221/72231/72241 have a 64,
256, 512, 1024, 2048, and 4096 x 9-bit memory array,
respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics, local area networks
and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and two
write enable pins (
WEN1
, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (
REN2
). The read clock can be tied to the write clock for single
REN1
clock operation or the two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF)
and Full (FF). Two programmable flags, Almost-Empty (
and Almost-Full (
PAF
), are provided for improved system
PAE
control. The programmable flags default to Empty+7 and Full7 for
PAE
and
PAF
, respectively. The programmable flag
offset loading is controlled by a simple state machine and is
initiated by asserting the load pin (LD).
The IDT72421/72201/72211/72221/72231/72241 are
fabricated using IDT’s high-speed submicron CMOS
technology. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B.
,
)
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN1
WEN2
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
RS
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
OE
0 - D8
D
INPUT REGISTER
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1024 x 9,
2048 x 9, 4096 x 9
OUTPUT REGISTER
Q
0 - Q8
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
RCLK
REN1
REN2
LD
EF
PAE
PAF
FF
2655 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1995
1996 Integrated Device Technology, Inc DSC-2655/6
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.07 1
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
INDEX
23456
DDDDD
7
D
8
D
RS
INDEX
2
3
4
DDDDD
5
6
7
8
D
D
432132 31 30
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
EF
FF
J32-1
L32-1
Q
LCC/PLCC
TOP VIEW
29
28
27
26
25
24
23
22
21
3
2Q1Q0
Q4Q
D
D
PAF
PAE
GND
REN1
RCLK
REN2
29 28
PR32-1
Q
27 26 25
2
1Q0
D
24
WEN1
23
WCLK
22
WEN2/LD
21
V
20
19
18
17
16
3
4
QQQ
CC
8
Q
7
Q
Q
6
5
Q
2655 drw 02a
D
PAF
PAE
GND
REN1
RCLK
REN2
OE
1
0
32 31 30
1
1
0
2
3
4
5
6
7
8
9 101112131415
EFOEFF
TQFP
TOP VIEW
PIN DESCRIPTIONS
Symbol Name I/O Description
0-D8 Data Inputs I Data inputs for a 9-bit bus.
D
RS
WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
WEN1
WEN2/
Q
0-Q8 Data Outputs O Data outputs for a 9-bit bus.
RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN1
REN2
OE
EF
PAE
PAF
FF
V
CC Power One +5 volt power supply pin.
GND Ground One 0 volt ground pin.
Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and EF go LOW. A reset is required before an initial WRITE after
power-up.
Enable(s) are asserted.
Write Enable 1 I If the FIFO is configured to have programmable flags,
When
WEN1
is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables,
WEN1
is the only write enable pin.
WEN1
must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW.
LD
Write Enable 2/ I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
Load
LD
is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables,
WEN1
must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag
offsets.
REN1
and
asserted.
Read Enable 1 I When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
Read Enable 2 I When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
Programmable O When
Almost-Empty The default offset at reset is Empty+7.
PAE
is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
PAE
is synchronized to RCLK.
Flag
Programmable O When
Almost-Full Flag default offset at reset is Full-7.
PAF
is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
PAF
is synchronized to WCLK.
Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full. FF is synchronized to WCLK.
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
2655 drw 02
REN2
are
2655 tbl 01
5.07 2
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
V
with Respect to
GND
T
A Operating 0 to +70 –55 to +125 °C
Temperature
T
BIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
STG Storage –55 to +125 –65 to +135 °C
T
Temperature
OUT DC Output 50 50 mA
I
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CCM Military Supply Voltage 4.5 5.0 5.5 V
CCC Commercial 4.5 5.0 5.5 V
V
Supply Voltage
GND Supply Voltage 0 0 0 V
IH Input High Voltage 2.0 — — V
V
Commercial
IH Input High Voltage 2.2 — — V
V
Military
V
IL Input Low Voltage — — 0.8 V
Commercial & Military
Current
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2655 tbl 02
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter Conditions Max. Unit
(2)
C
IN
OUT
C
NOTES:
1. With output deselected (OE = HIGH).
2. Characterized values, not currently tested.
Input Capacitance VIN = 0V 10 pF
(1,2)
Output Capacitance VOUT = 0V 10 pF
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C)
2655 tbl 03
2655 tbl 04
IDT72421 IDT72421
IDT72201 IDT72201
IDT72211 IDT72211
Commercial Military
CLK = 12, 15, 20, 25,35, 50ns tCLK = 20, 25,35, 50ns
t
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
(1)
LI
I
I
LO
V
OH Output Logic “1” Voltage, IOH = –2mA 2.4 — — 2.4 — — V
OL Output Logic “0” Voltage, IOL = 8mA — — 0.4 — — 0.4 V
V
I
CC
Input Leakage Current (Any Input) –1 — 1 –10 — 10 µA
(2)
Output Leakage Current –10 — 10 –10 — 10 µA
(3)
Active Power Supply Current — — 80 — — 100 mA
2655 tbl 05
IDT72221 IDT72221
IDT72231 IDT72231
IDT72241 IDT72241
Commercial Military
CLK = 15, 20, 25, 35, 50ns tCLK = 25, 35, 50ns
t
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
(1)
LI
I
I
LO
V
OH Output Logic “1” Voltage, IOH = –2mA 2.4 — — 2.4 — — V
OL Output Logic “0” Voltage, IOL = 8mA — — 0.4 — — 0.4 V
V
I
CC1
NOTES:
1. Measurements with 0.4 ≤ V
2.
OE
3 & 4. Measurements are made with outputs unloaded. Tested at f
Input Leakage Current (Any Input) –1 — 1 –10 — 10 µA
(2)
Output Leakage Current –10 — 10 –10 — 10 µA
(4)
Active Power Supply Current — — 80 — — 100 mA
IH, 0.4 ≤ VOUT ≤ VCC.
≥ V
(3) Typical I
(4) Typical I
CLK = 1/tCLK.
f
CL = external capacitive load (30pF typical)
CC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA
CC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA
IN ≤ VCC.
CLK = 20MHz.
2655 tbl 06
5.07 3
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Com'l. Commercial & Military
72421L12 72421L15 72421L20 72421L25 72421L35 72421L50
72201L12 72201L15 72201L20 72201L25 72201L35 72201L50
72211L12 72211L15 72211L20 72211L25 72211L35 72211L50
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
f
S Clock Cycle Frequency — 83.3 — 66.7 — 50 — 40 — 28.6 — 20 MHz
t
A Data Access Time 2 8 2 10 2 12 3 15 3 20 3 25 ns
t
CLK Clock Cycle Time 12 — 15 — 20 — 25 — 35 — 50 — ns
t
CLKH Clock High Time 5 — 6 — 8 — 10 — 14 — 20 — ns
t
CLKL Clock Low Time 5 — 6 — 8 — 10 — 14 — 20 — ns
t
DS Data Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns
t
DH Data Hold Time 0 — 1 — 1 — 1 — 2 — 2 — ns
t
ENS Enable Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns
t
ENH Enable Hold Time 0 — 1 — 1 — 1 — 2 — 2 — ns
t
RS Reset Pulse Width
t
RSS Reset Set-up Time 12 — 15 — 20 — 25 — 35 — 50 — ns
t
RSR Reset Recovery Time 12 — 15 — 20 — 25 — 35 — 50 — ns
t
RSF Reset to Flag and Output Time — 12 — 15 — 20 — 25 — 35 — 50 ns
t
OLZ Output Enable to Output in Low-Z
t
OE Output Enable to Output Valid 3 7 3 8 3 10 3 13 3 15 3 28 ns
t
OHZ Output Enable to Output in High-Z
t
WFF Write Clock to Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns
t
REF Read Clock to Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns
t
AF Write Clock to Almost-Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns
t
AE Read Clock to Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns
t
SKEW1 Skew time between Read Clock & 5 — 6 — 8 — 10 — 12 — 15 — ns
Write Clock for Empty Flag &Full Flag
t
SKEW2 Skew time between Read Clock & 22 — 28 — 35 — 40 — 42 — 45 — ns
Write Clock for Almost-Empty Flag &
Almost-Full Flag
NOTES: 2655 tbl 07
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
(1)
12 — 15 — 20 — 25 — 35 — 50 — ns
(2)
0 — 0 —0— 0— 0—0— ns
(2)
3 7 3 8 3 10 3 13 3 15 3 28 ns
5.07 4
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125 °C)
Commercial Commercial and Military
72221L15 72221L20 72221L25 72221L35 72221L50
72231L15 72231L20 72231L25 72231L35 72231L50
72241L15 72241L20 72241L25 72241L35 72241L50
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
f
S Clock Cycle Frequency — 66.7 — 50 — 40 — 28.6 — 20 MHz
t
A Data Access Time 2 10 2 12 3 15 3 20 3 25 ns
t
CLK Clock Cycle Time 15 — 20 — 25 — 35 — 50 — ns
t
CLKH Clock HIGH Time 6 — 8 — 10 — 14 — 20 — ns
t
CLKL Clock LOW Time 6 — 8 — 10 — 14 — 20 — ns
t
DS Data Set-up Time 4 — 5 — 6 — 8 — 10 — ns
t
DH Data Hold Time 1 — 1 — 1 — 2 — 2 — ns
t
ENS Enable Set-up Time 4 — 5 — 6 — 8 — 10 — ns
t
ENH Enable Hold Time 1 — 1 — 1 — 2 — 2 — ns
t
RS Reset Pulse Width
t
RSS Reset Set-up Time 15 — 20 — 25 — 35 — 50 — ns
t
RSR Reset Recovery Time 15 — 20 — 25 — 35 — 50 — ns
t
RSF Reset to Flag Time and Output Time — 15 — 20 — 25 — 35 — 50 ns
t
OLZ Output Enable to Output in Low-Z
t
OE Output Enable to Output Valid 3 8 3 10 3 13 3 15 3 28 ns
t
OHZ Output Enable to Output in High-Z
t
WFF Write Clock to Full Flag — 10 — 12 — 15 — 20 — 30 ns
t
REF Read Clock to Empty Flag — 10 — 12 — 15 — 20 — 30 ns
t
PAF Write Clock to Programmable Almost-Full Flag — 10 — 12 — 15 — 20 — 30 ns
t
PAE Read Clock to Programmable Almost-Empty Flag — 10 — 12 — 15 — 20 — 30 ns
t
SKEW1 Skew Time Between Read Clock and Write Clock 6 — 8 — 10 — 12 — 15 — ns
for Empty Flag and Full Flag
SKEW2 Skew Time Between Read Clock and Write Clock 28 — 35 — 40 — 42 — 45 — ns
t
for Programmable Almost-Empty Flag and
Programmable Almost-Full Flag
NOTES: 2655 tbl 08
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
(1)
(2)
(2)
15 — 20 — 25 — 35 — 50 — ns
0 —0— 0 —0— 0— ns
3 8 310 3 13315 328 ns
AC TEST CONDITIONS
In Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
5V
1.1K
D.U.T.
680Ω
30pF*
or equivalent circuit
Figure 1. Output Load
2655 tbl 09
5.07 5
*Includes jig and scope capacitances.
2655 drw 03
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS
Data In (D
:
0 - D8) — Data inputs for 9-bit wide data.
CONTROLS:
Reset (
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full Flag
(
PAF
Programmable Almost-Empty Flag (
after tRSF. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Write Clock (WCLK) — A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Programmable Almost-Full Flag (
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or
coincident.
Write Enable 1 (
programmable flags, Write Enable 1 (
enable control pin. In this configuration, when Write Enable 1
(
WEN1
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable 1 (
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after t
allowing a valid write to begin. Write Enable 1 (
ignored when the FIFO is full.
Read Clock (RCLK) — Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (EF) and Programmable Almost-Empty Flag (
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or
coincident.
RSRS) — Reset is accomplished whenever the Reset
) will be reset to HIGH after tRSF. The Empty Flag (EF) and
PAE
) will be reset to LOW
PAF
) are synchronized with
WEN1
) — If the FIFO is configured for
WEN1
WEN1
) is the only
) is low, data can be loaded into the input register and
WEN1
) is HIGH,
WFF,
WEN1
) is
PAE
Read Enables (
(
REN1, REN2
REN1
,
REN2
REN1
) — When both Read Enables
REN2
) are LOW, data is read from the RAM array to
the output register on the LOW-to-HIGH transition of the read
clock (RCLK).
When either Read Enable (
REN1, REN2
) is HIGH, the
output register holds the previous data and no new data is
allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
The Read Enables (
REN1, REN2
) are ignored when the FIFO
is empty.
Output Enable (
OEOE) — When Output Enable (OE) is
enabled (LOW), the parallel output buffers receive data from
the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
Write Enable 2/Load (WEN2/
LLDD) — This is a dual-
purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which
allows depth expansion. If Write Enable 2/Load (WEN2/LD)
is set high at Reset (
RS
= LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when
Write Enable (
LD
) is HIGH, data can be loaded into the input register and
WEN1
) is LOW and Write Enable 2/Load (WEN2/
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable (
WEN1
) is HIGH
and/or Write Enable 2/Load (WEN2/LD) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after t
allowing a valid write to begin. Write Enable 1 (
WEN1
) and Write
Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/LD) is set LOW at Reset
(RS=low). The IDT72421/72201/72211/72221/72231/72241
devices contain four 8-bit offset registers which can be loaded
with data on the inputs, or read on the outputs. See Figure 3
for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when
the Write Enable 1 (
LD
) are set low, data on the inputs D is written into the Empty
WEN1
) and Write Enable 2/Load (WEN2/
(Least Significant Bit) offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). Data is written into the
Empty (Most Significant Bit) offset register on the second
)
LOW-to-HIGH transition of the write clock (WCLK), into the
Full (Least Significant Bit) offset register on the third transition,
and into the Full (Most Significant Bit) offset register on the
fourth transition. The fifth transition of the write clock (WCLK)
again writes to the Empty (Least Significant Bit) offset register.
WFF,
5.07 6
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