Integrated Device Technology Inc IDT72401L15PB, IDT72401L15SO, IDT72401L15SOB, IDT72401L25D, IDT72401L25DB Datasheet

Integrated Device Technology, Inc.

CMOS PARALLEL FIFO
64 x 4-BIT AND 64 x 5-BIT

IDT72401
IDT72402
IDT72403
IDT72404

FEATURES:

• First-ln/First-Out Dual-Port memory

• 64 x 4 organization (IDT72401/03)

• 64 x 5 organization (IDT72402/04)

• IDT72401/02 pin and functionally compatible with
MMI67401/02

• RAM-based FIFO with low falI-through time

• Low-power consumption
— Active: 175mW (typ.)

• Maximum shift rate — 45MHz

• High data output drive capability

• Asynchronous and simultaneous read and write

• Fully expandable by bit width

• Fully expandable by word depth

• IDT72403/04 have Output Enable pin to enable output
data

• High-speed data communications applications

• High-performance CMOS technology

• Available in CERDIP, plastic DIP and SOIC

• Military product compliant to MlL-STD-883, Class B

• Standard Military Drawing #5962-86846 and
5962-89523 is listed on this function.

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

DESCRIPTION:

The IDT72401 and IDT72403 are asynchronous high­performance First-ln/First-Out memories organized 64 words
by 4 bits. The IDT72402 and IDT72404 are asynchronous
high-performance First-ln/First-Out memories organized as
64 words by 5 bits. The IDT72403 and IDT72404 also have an

Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data

at the data input (D

0-D3, 4). The stored data stack up on a first-

in/first-out basis.

A Shift Out (SO) signal causes the data at the next to last
word to be shifted to the output while all other data shifts down
one location in the stack. The Input Ready (IR) signal acts like
a flag to indicate when the input is ready for new data
(IR = HIGH) or to signal when the FIFO is full (IR = LOW). The
Input Ready signal can also be used to cascade multiple
devices together. The Output Ready (OR) signal is a flag to
indicate that the output remains valid data (OR = HIGH) or to
indicate that the FIFO is empty (OR = LOW). The Output
Ready can also be used to cascade multiple devices together.

Width expansion is accomplished by logically ANDing the
Input Ready (IR) and Output Ready (OR) signals to form
composite signals.

Depth expansion is accomplished by tying the data inputs
of one device to the data outputs of the previous device. The
Input Ready pin of the receiving device is connected to the
Shift Out pin of the sending device and the Output Ready pin
of the sending device is connected to the Shift In pin of the
receiving device.

Reading and writing operations are completely asynchro­nous allowing the FIFO to be used as a buffer between two
digital machines of widely varying operating frequencies. The
45MHz speed makes these FlFOs ideal for high-speed
communication and controller applications.

Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

SI
IR

D

0-3

D

4

(IDT72402

and IDT72404)

MR

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.

INPUT

CONTROL

LOGIC

DATA

IN

MASTER

RESET

WRITE POINTER

WRITE MULTIPLEXER

MEMORY

ARRAY

READ MULTIPLEXER

READ POINTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES SEPTEMBER 1996

1996 Integrated Device Technology, Inc. DSC-2747/7

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.01 1

OUTPUT

ENABLE

DATA

OUT

OUTPUT

CONTROL

LOGIC

OE (IDT72403 and
IDT72404)

Q

0-3

Q4

(IDT72402 and
IDT72404)

SO
OR

2747 drw 01

IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

IDT72401/IDT72403

(1)

NC/OE

GND

NOTES:

1. Pin 1: NC - No Connection IDT72401,

2. Pin 1: NC - No Connection IDT72402,

1
2

IR

3

SI

0

D
D1
D2
D

3 3

P16-1,

4
5

S016-1

6
7
8

DIP/SOIC

TOP VIEW

D16-1

16

Vcc

15

SO

14

OR

13

Q

&

12
11
10

9

0

Q1
Q

2

Q
MR

2747 drw 02

OE - IDT72403

OE - IDT72404

ABSOLUTE MAXIMUM RATINGS

NC/OE

GND

(1)

IDT72402/IDT72404

(2)

1
2

IR

3

SI

4

0

D

5

D

1

6

D

2

7

D

3 3

8

D

4

9

DIP/SOIC

TOP VIEW

Symbol Rating Commercial Military Unit

V

TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with Respect
to GND

T

A Operating Temp. 0 to +70 –55 to +125 ° C
BIAS Temperature –55 to +125 –65 to +135 °C

T

Under Bias

T

STG Storage Temp. –55 to +125 –65 to +150 ° C

OUT DC Output 50 50 mA

I

Current

NOTE: 2747 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

(IDT72404 Only)

18

P18-1,

D18-1

&

S018-1

17
16
15
14
13
12
11
10

Vcc
SO
OR
Q

0

Q

1

Q

2

Q
Q

4

MR

2747 drw 03

OE
NC

GND

IR

SI
D0
D1
D2
D3
D4

1
2
3
4
5
6
7
8
9

10

CERPACK
TOP VIEW

20
19
18
17
16
15
14
13
12
11

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Mil. Supply Voltage 4.5 5.0 5.5 V

V
V

CC Com'l. Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — — V

V

(1)

IL

V

NOTE: 2747 tbl 02

1. 1.5V undershoots are allowed for 10ns once per cycle.

Input High Voltage — — 0.8 V

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

IN Input Capacitance VIN = 0V 5 pF

C

OUT Output Capacitance VOUT = 0V 7 pF

C

NOTE: 2747 tbl 03

1. This parameter is sampled and not 100% tested.

(1)

Conditions Max. Unit

Vcc
NC
SO

OR

0

Q
Q1
Q2
Q3

4

Q
MR

2747 drw 04

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Symbol Parameter Test Conditions Min. Max. Unit

IL Low-Level Input Current VCC = Max., GND ≤ VI ≤ VCC –10 — µA

I
I

IH High-Level Input Current VCC = Max., GND ≤ VI ≤ VCC —10µA

OL Low-Level Output Voltage VCC = Min., IOL = 8mA — 0.4 V

V

OH High-Level Output Voltage VCC = Min., IOH = -4mA 2.4 — V

V

(1)

I

OS
HZ Off-State Output Current VCC = Max., VO = 2.4V — 20 µA

I

LZ (IDT72403 and IDT72404) VCC = Max., VO = 0.4V –20 — µA

I

(2,3)

CC

I

NOTES: 2747 tbl 04

1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.

CC measurements are made with outputs open. OE is HIGH for IDT72403/72404.

2. I
3 For frequencies greater than 10MHZ, I

Output Short-Circuit Current VCC = Max., VO = GND –20 –110 mA

Supply Current VCC = Max., f = 10MHz Com'l. — 35 mA

Military — 45 mA

CC = 35mA + (1.5mA x [f - 10MHz]) commercial, and ICC = 45mA + (1.5mA x [f - 10MHz]) military.

5.01 2

IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONDITIONS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Commercial Military and Commercial

IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10
IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10
IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10
IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10

Symbol Parameters FIgure Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

(1)

t

SIH
SIL Shift in LOW TIme 2 11 — 17 — 24 — 25 — 30 — ns

t
t

IDS Input Data Set-up 2 0 — 0 — 0 — 0 — 0 — ns

t

IDH Input Data Hold Time 2 13 — 15 — 20 — 30 — 40 — ns
SOH

t
t

SOL Shift Out LOW Time 5 11 — 17 — 24 — 25 — 25 — ns
MRW Master Reset Pulse 8 20 — 25 — 25 — 25 — 30 — ns

t
t

MRS Master Reset Pulse to SI 8 10 — 10 — 10 — 25 — 35 — ns

t

SIR Data Set-up to IR 4 3 — 3 — 5 — 5 — 5 — ns
HIR Data Hold from IR 4 13 — 15 — 20 — 30 — 30 — ns

t
t

SOR

Shift in HIGH Time 2 9 — 9 — 11 — 11 — 11 — ns

(1)

Shift Out HIGH Time 5 9 — 9 — 11 — 11 — 11 — ns

(4)

Data Set-up to OR HIGH 7 0 — 0 — 0 — 0 — 0 — ns

2747 tbl 05

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Commercial Military and Commercial

IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10
IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10
IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10
IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10

Symbol Parameters FIgure Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

t

IN Shift In Rate 2 — 45 — 35 — 25 — 15 — 10 MHz

(1)

t

IRL

t

IRH
OUT Shift Out Rate 5 — 45 — 35 — 25 — 15 — 10 MHz

t
t

ORL
ORH

t
t

ODH Output Data Hold (Previous Word) 5 5 — 5 — 5 — 5 — 5 — ns
ODS Output Data Shift (Next Word) 5 — 19 — 20 — 34 — 40 — 55 ns

t
t

PT Data Throughput or "Fall-Through" 4, 7 — 30 — 34 — 40 — 65 — 65 ns

t

MRORL Master Reset to OR LOW 8 — 25 — 28 — 35 — 35 — 40 ns
MRIRH Master Reset to IR HIGH 8 — 25 — 28 — 35 — 35 — 40 ns

t

MRQ Master Reset to Data Output LOW 8 — 20 — 20 — 25 — 35 — 40 ns

t

OOE

t
t

HZOE
IPH

t

OPH

t

NOTES:

1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between V

2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of
like speed grades.

3. IDT72403 and IDT72404 only.

4. Guaranteed by design but not currently tested.

Shift In to Input Ready LOW 2 — 18 — 18 — 21 — 35 — 40 ns

(1)

Shift In to Input Ready HIGH 2 — 18 — 20 — 28 — 40 — 45 ns

(1)

Shift Out to Output Ready LOW 5 — 18 — 18 — 19 — 35 — 40 ns

(1)

Shift Out to Output Ready HIGH 5 — 19 — 20 — 34 — 40 — 55 ns

(3)

Output Valid from OE LOW 9 — 12 — 15 — 20 — 30 — 35 ns

(3,4)

Output High-Z from OE HIGH 9 — 12 — 12 — 15 — 25 — 30 ns

(2,4)

Input Ready Pulse HIGH 4 9 — 9 — 11 — 11 — 11 — ns

(2,4)

Ouput Ready Pulse HIGH 7 9 — 9 — 11 — 11 — 11 — ns

CC and GND with very short lead length is recommended.

2747 tbl 06

5.01 3