IDT IDT723626, IDT723636, IDT723646 User Manual

查询IDT723626供应商

CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2
1,024 x 36 x 2

FEATURES:

••

Memory storage capacity:

•

••

IDT723626 – 256 x 36 x 2
IDT723636 – 512 x 36 x 2
IDT723646 – 1,024 x 36 x 2

••

Clock frequencies up to 83 MHz (8ns access time)

•

••

••

Two independent FIFOs buffer data between one bidirectional

•

••

36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)

••

18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on

•

••

Ports B and C

••

Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag

•

••

functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)

••

Programmable Almost-Empty and Almost-Full flags; each has

•

••

three default offsets (8, 16 and 64)

FUNCTIONAL BLOCK DIAGRAM

CLKA

CSA

W/RA

ENA

MBA

MRS1

PRS1

FFA/IRA

AFA

SPM

FS0/SD

FS1/SEN

0-A35

A

EFA/ORA

AEA

Port-A

Control

Logic

FIFO1,
Mail1
Reset
Logic

36 36

Input

Register

Write

36

FIFO1

10

FIFO2

Pointer

Status Flag

Programmable Flag

Offset Registers

Status Flag

Mail 1

Register

RAM ARRAY

256 x 36
512 x 36

1,024 x 36

Logic

Logic

TM

IDT723626
IDT723636
IDT723646

••

Serial or parallel programming of partial flags

•

••

••

Big- or Little-Endian format for word and byte bus sizes

•

••

••

Master Reset clears data and configures FIFO, Partial Reset

•

••

clears data but retains configuration settings

••

Mailbox bypass registers for each FIFO

•

••

••

Free-running CLKA, CLKB and CLKC may be asynchronous or

•

••

coincident (simultaneous reading and writing of data on a single
clock edge is permitted)

••

Auto power down minimizes power dissipation

•

••

••

Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

•

••

••

Industrial temperature range (–40

•

••

°°

°

C to +85

°°

DESCRIPTION:

The IDT723626/723636/723646 is a monolithic, high-speed, low­power, CMOS Triple Bus synchronous (clocked) FIFO memory which
supports clock frequencies up to 83 MHz and has read access times as fast as

Output

Register

Read

Pointer

Timing

Mode

Matching

Output Bus-

°°

°

C) is available

°°

18

Port-B

Control

Logic

Common

Port

Control

Logic

(B and C)

MBF1

B

0-B17

CLKB

RENB

CSB

MBB
SIZEB

EFB/ORB
AEB

BE

FWFT
FFC/IRC

AFC

Mail 2

Write

Pointer

36

Matching

Input Bus-

Input

Register

FIFO2,
Mail2
Reset
Logic

18

Port-C

Control

Logic

MRS2

PRS2

C0-C
CLKC

WENC
MBC
SIZEC

3271 drw01

17

AUGUST 2001

Read

Output

Register

Pointer

36

RAM ARRAY

256 x 36
512 x 36

1,024 x 36

Register

36

MBF2

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

1



2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3271/3

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DESCRIPTION (CONTINUED)

8 ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board
each chip buffer data between a bidirectional 36-bit bus (Port A) and two
unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO
data can be read out of Port B and written into Port C using either 18-bit or 9­bit formats with a choice of Big- or Little-Endian configurations.

PIN CONFIGURATION

INDEX

W/RA

ENA

CLKA

GND

A35
A34
A33
A32

Vcc

A31

A30

GND

A29
A28
A27
A26
A25

A24

A23

BE/FWFT

GND

A22

Vcc

A21

A20
A19

A18

GND

A17

A16

A15

A14

A13

Vcc

A12

GND

A11

A10

CSA

PRS1

FFA/IRA

EFA/ORA

125

127

126

128

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39

40

42

41

Vcc

124

43

AFA

123

44

AEA

122

45

MBF2

MBA

121

120

46

47

FS0/SD

MRS1

118

119

48

49

These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple

MBF1

CLKC

117

50

GND

116

51

FS1/SEN

115

52

MRS2

MBB

114

113

54

53

112

55

Vcc

111

56

AEB

110

57

AFC

109

58

EFB/ORB

108

59

FFC/IRC

107

60

GND

106

61

CSB

105

62

RENB

WENC

103

104

102
101
100

64

63

CLKB

PRS2

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

Vcc
C17
C16
C15
C14

GND
MBC
C13
C12
C11
C10
C9
C8
Vcc
C7
C6
SIZEB
GND
C5
C4
C3
C2
C1
C0
GND
B17
B16
SIZEC
Vcc
B15
B14
B13
B12
GND
B11
B10

A9

A8

A7

B0

A0

GND

B1

B2

B3

B7

B4

B5

GND

B8

Vcc

B6

A2

Vcc

A1

A4

A6

A3

SPM

A5

GND

3271 drw02

B9

TQFP (PK128-1, order code: PF)

TOP VIEW

2

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

bidirectional interface between microprocessors and/or buses with synchro­nous control.

Communication between each port may bypass the FIFOs via two mailbox
registers. The mailbox registers' width matches the selected bus width of ports
B and C. Each mailbox register has a flag (MBF1 and MBF2) to signal when
new mail has been stored.

Two kinds of reset are available on these FIFOs: Master Reset and Partial
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array and selects serial flag programming, parallel flag program­ming, or one of three possible default flag offset settings, 8, 16 or 64. Each FIFO
has its own, independent Master Reset pin, MRS1 and MRS2.

Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.

These devices have two modes of operation: In the IDT Standard
mode, the first word written to an empty FIFO is deposited into the memory
array. A read operation is required to access that word (along with all other
words residing in memory). In the First Word Fall Through mode (FWFT),
the first word written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/FWFT pin
during Master Reset determines the mode in use.

Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC).
The EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty. FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through

mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.

Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and
a programmable Almost-Full flag (AFA and AFC). AEA and AEB indicate when
a selected number of words remain in the FIFO memory. AFA and AFC indicate
when the FIFO contains more than a selected number of words.

FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the Port
Clock that writes data into its array. EFA/ORA, EFB/ORB, AEA, and AEB are
two-stage synchronized to the Port Clock that reads data from its array.
Programmable offsets for AEA, AEB, AFA, AFC are loaded in parallel using Port
A or in serial via the SD input. The Serial Programming Mode pin (SPM) makes
this selection. Three default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16 or 64 locations from the empty boundary and the
AFA and AFC threshold can be set at 8, 16 or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs during Master Reset.

Two or more FIFOs may be used in parallel to create wider data paths.
Such a width expansion requires no additional, external components. Further­more, two IDT723626/723636/723646 FIFOs can be combined with unidirec­tional FIFOs capable of First Word Fall Through timing (i.e. the SuperSync FIFO
family) to form a depth expansion.

If, at any time, the FIFO is not actively performing a function, the chip
will automatically power down. During the power down state, supply current
consumption (ICC) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.

The IDT723626/723636/723646s are characterized for operation from
0°C to 70°C. Industrial temperature range (–40°C to +85°C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.

3

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol Name I/O Description

A0-A35 Port A Data I/O 36-bit bidirectional data port for side A.
AEA Port A Almost-Empty O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is

Flag less than or equal to the value in the Almost-Empty A Offset register, X2.

AEB Port B Almost-Empty O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is

Flag less than or equal to the value in the Almost-Empty B Offset register, X1.

AFA Port A Almost-Full O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in

Flag FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.

AFC Port C Almost-Full O Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of empty locations in

Flag FIFO2 is less than or equal to the value in the Almost-Full C Offset register, Y2.
B0-B17 Port B Data O 18-bit output data port for side B.
BE/FWFT Big-Endian/ I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this

First Word case, depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B

Fall Through data flow) or is written to Port C first (C-to-A data flow). A LOW on BE will select Little-Endian operation.

Select In this case, the least significant byte or word on Port A is read from Port B first (A-to-B data flow) or is

written to Port C first (C-to-A data flow).
After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode,a LOW

selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must

be static throughout device operation.
C0-C17 Port C Data I 18-bit input data port for side C.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or

coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH

transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or

coincident to CLKA. EFB/ORB and AEB are synchronized to the LOW-to-HIGH transition of CLKB.
CLKC Port C Clock I CLKC is a continuous clock that synchronizes all data transfers through Port C and can be asynchronous

or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGH transition of CLKC.
CSA Port A Chip Select I CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35

outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read data on Port B. The B0-B17

outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA Port A Empty/ O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates whether

Output Ready Flag or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the

presence of valid data on the A0-A35 outputs, available for reading. EFA/ORA is synchronized to the

LOW-to-HIGH transition of CLKA.
EFB/ORB Port B Empty/ O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates whether

Output Ready Flag or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the

presence of valid data on the B0-B17 outputs, available for reading. EFB/ORB is synchronized to the

LOW-to-HIGH transition of CLKB.
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
FFA/IRA Port A Full/ O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether

Input Ready Flag or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA

indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is

synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC Port C Full/ O This is a dual function pin. In the IDT Standard mode, the FFC function is selected. FFC indicates whether

Input Ready Flag or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC indicates whether or

not there is space available for writing to the FIFO2 memory. FFC/IRC is synchronized to the

LOW-to-HIGH transition of CLKC.

4

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol Name I/O Description

FS1/SEN Flag Offset I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,

Select 1/ FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three Offset register
Serial Enable, programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load

from Port A, and serial FS0/SD load.

Flag Offset I
Select 0/ When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to
Serial Data the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on

FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 32 for the
IDT723626, 36 for the IDT723636, and 40 for the IDT723646. The first bit write stores the Y-register (Y1) MSB
and the last bit write stores the X-register (X2) LSB.

MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 outputs

Select are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2

output-register data for output.

MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are

Select active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output

register data for output.

MBC Port C Mailbox I A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during

Select Master Reset.

MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1

register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.

MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2

register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.

MRS1 Master Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B

output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or parallel)
and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and C for bus size
and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while MRS1 is LOW.

MRS2 Master Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A output

register to all zeroes. A LOW-to-HIGH transition on MRS2 toggled simultaneously with MRS1, selects the programming
method (serial or parallel) and one of the three flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA
and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.

PRS1 Partial Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B

output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming
method (serial or parallel), and programmable flag settings are all retained.

PRS2 Partial Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A

output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming
method (serial or parallel), and programmable flag settings are all retained.

RENB Port B Read Enable I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.

(1)

SIZEB

SIZEC

SPM

WENC Port C Write Enable I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.
W/RA Port A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of

NOTE:

1. SIZEB, SIZEC and SPM are not TTL compatible. These inputs should be tied to GND or VCC.

Port B I SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement for

ports B and C. The level of SIZEB must be static throughout device operation.

(1)

Port C I SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement for

ports B and C. The level of SIZEC must be static throughout device operation.

(1)

Serial Programming I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming
Mode or default offsets (8, 16, or 64).

Select CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

5

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR

TEMPERATURE RANGE (Unless otherwise noted)

Symbol Rating Commercial Unit

CC Supply Voltage Range –0.5 to 7 V

V

(2)

V

I

(2)

O

V

IK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA

I
I

OK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA
OUT Continuous Output Current (VO = 0 to VCC) ±50 mA

I

CC Continuous Current Through VCC or GND ±400 mA

I
T

STG Storage Temperature Range –65 to 150 °C

NOTES:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device
at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

Input Voltage Range –0.5 to VCC+0.5 V
Output Voltage Range –0.5 to VCC+0.5 V

(1)

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage (Commercial) 4.5 5 .0 5.5 V

V

IH High-Level Input Voltage (Commercial) 2 — V

V

IL Low-Level Input Voltage (Commercial) — — 0.8 V

V

OH High-Level Output Current (Commercial) — — –4 mA

I

OL Low-Level Output Current (Commercial) — — 8 mA

I

A Operating Free-Air Temperature (Commercial) 0 — 70 °C

T

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-

AIR TEMPERATURE RANGE (Unless otherwise noted)

IDT723626
IDT723636
IDT723646

Commercial

tCLK = 12, 15 ns

Symbol Parameter Test Conditions Min. Typ.

VOH Output Logic "1" Voltage VCC = 4.5V, IOH = –4 mA 2.4 — — V

OL Output Logic "0" Voltage VCC = 4.5V, IOL = 8 mA — — 0.5 V

V

LI Input Leakage Current (Any Input) VCC = 5.5V, VI = VCC or 0 — — ±10 µA

I

LO Output Leakage Current VCC = 5.5V, VO = VCC or 0 — — ±10 µ A

I

(2)

CC2

I

CC3

I

IN

C

OUT

C

NOTES:

1. All typical values are at V

2. For additional I

3. Characterized values, not currently tested.

4. Industrial temperature range product is available by special order.

Standby Current (with CLKA, CLKB and CLKC running) VCC = 5.5V, VI = VCC - 0.2V or 0 — — 8 mA

(2)

Standby Current (no clocks running) VCC = 5.5V, VI = VCC - 0.2V or 0 — — 1 mA

(3)

Input Capacitance VI = 0, f = 1 MHz — 4 — pF

(3)

Output Capacitance VO = 0, f = 1 MHZ — 8 — pF

CC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).

CC = 5V, TA = 25°C.

(1)

Max. Unit

6

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

The I

CC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723626/723636/723646 with CLKA,

CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT723626/723636/
723646 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.

CALCULATING POWER DISSIPATION

With I

CC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

P

T = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC

2

X fo)

N

where:
N = number of inputs driven by TTL levels
∆ICC = increase in power supply current for each input at a TTL HIGH level
dc = duty cycle of inputs at a TTL HIGH level of 3.4V
CL = output capacitance load
fo = switching frequency of an output

300

250

200

mA

150

Supply Current

CC(f)

I

100

50

0

010 20 30 40 50 60 70

f

data

= 1/2 f

TA = 25°C

L

= 0 pF

C

S

VCC = 5.5V

V

CC

= 5.0V

VCC = 4.5V

S



Clock Frequency

f



80 90

MHz

3271 drw02a

Figure 1. Typical Characteristics: Supply Current (I

7

CC) vs. Clock Frequency (fS)

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLT-

AGE AND OPERATING FREE-AIR TEMPERATURE

(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C)

Commercial

IDT723626L12 IDT723626L15
IDT723636L12 IDT723636L15
IDT723646L12 IDT723646L15

Symbol Parameter Min. Max. Min. Max. Unit

fS Clock Frequency, CLKA, CLKB, or CLKC — 83 — 66.7 MHz
tCLK Clock Cycle Time, CLKA, CLKB, or CLKC 12 — 15 — ns
tCLKH Pulse Duration, CLKA, CLKB, or CLKC HIGH 5 — 6 — n s
tCLKL Pulse Duration, CLKA, CLKB, OR CLKC LOW 5 — 6 — n s
tDS Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑ 3—4—ns
tENS1 Setup Time, CSA and W/RA before CLKA↑; CSB before CLKB↑ 4 — 4.5 — ns
t

ENS2 Setup Time, ENA and MBA before CLKA↑; RENB and MBB before CLKB↑ ; 3 — 4.5 — ns

WENC and MBC before CLKC↑
tRSTS Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑ or CLKB↑
tFSS Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns
tBES Setup Time, BE/FWFT before MRS1 and MRS2 HIGH 7.5 — 7.5 — n s
tSPMS Setup Time, SPM before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns
tSDS Setup Time, FS0/SD before CLKA↑ 3—4—ns
tSENS Setup Time, FS1/SEN before CLKA↑ 3—4—ns
tFWS Setup Time, BE/FWFT before CLKA↑ 0—0—ns
tDH Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑ 0.5 — 1 — ns
t

ENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, RENB, and MBB 0.5 — 1 — ns

after CLKB↑; WENC and MBC after CLKC↑
tRSTH Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑
tFSH Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH 2 — 2 — n s
tBEH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 2 — 2 — n s
tSPMH Hold Time, SPM after MRS1 and MRS2 HIGH 2 — 2 — ns
tSDH Hold Time, FS0/SD after CLKA↑ 0.5 — 1 — ns
tSENH Hold Time, FS1/SEN HIGH after CLKA↑ 0.5 — 1 — ns
tSPH Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH 2 — 2 — ns

(3)

t

SKEW1

Skew Time, between CLKA↑and CLKB↑ for EFB/ORB and FFA/IRA; between 5 — 7.5 — n s

CLKA↑ and CLKC↑ for EFA/ORA and FFC/IRC

(3,4)

SKEW2

t

Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA; between CLKA↑ and 12 — 12 — ns

CLKC↑ for AEA and AFC

NOTES:

1. Industrial temperature range product is available by special order.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.

4. Design simulated, not tested (typical values).

(2)

(2)

5—5—ns

4—4—ns

8

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF

(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C)

Commercial

IDT723626L12 IDT723626L15
IDT723636L12 IDT723636L15
IDT723646L12 IDT723646L15

Symbol Parameter Min. Max. Min. Max. Unit

tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B17 2 8 2 10 ns
tWFF Propagation Delay Time, CLKA↑ to FFA/IRA and CLKC↑ to FFC/IRC 2828ns
tREF Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to EFB/ORB 1818ns
tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 1818ns
tPAF Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC 1818ns
t

PMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH, CLKB↑ to MBF1 0808ns

HIGH, and CLKC↑ to MBF2 LOW

tPMR Propagation Delay Time, CLKA↑ to B0-B17

(2)

and CLKC↑ to A0-A35
tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B17 valid 2 8 2 10 ns
t

RSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and 1 10 1 15 ns

MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFC HIGH, and MBF2 HIGH

tEN Enable Time, CSA or W/RA LOW to A0-A35 Active and CSB LOW to B0-B17 Active 2 6 2 10 ns

DIS Disable Time, CSA or W/RA HIGH to A0-A35 at HIGH impedance and CSB HIGH 1618ns

t

to B0-B17 at HIGH impedance

(3)

28210ns

NOTES:

1. Industrial temperature range product is available by special order.

2. Writing data to the mail1 register when the B0-B17 outputs are active and MBB is HIGH.

3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.

9

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

SIGNAL DESCRIPTION

MASTER RESET (MRS1, MRS2)

After power up, a Master Reset operation must be performed by providing
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT723626/723636/723646 undergoes a complete reset by
taking its associated Master Reset (MRS1) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a complete reset by taking its associated Master Reset
(MRS2) input LOW for at least four Port A Clock (CLKA) and four Port C Clock
(CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch asyn­chronously to the clocks. A Master Reset initializes the associated read and write
pointers to the first location of the memory and forces the Full/Input Ready flag
(FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the Almost-Full flag
(AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the
FIFO’s Full/Input Ready flag is set HIGH after two Write clock cycles. Then the
FIFO is ready to be written to.

A LOW-to-HIGH transition on a FlFO1 Master Reset (MRS1, MRS2) input
latches the value of the Big-Endian (BE) input for determining the order by which
bytes are transferred through ports B and C. It also latches the values of the Flag
Select (FS0, FS1) and Serial Programming Mode (SPM) inputs for choosing
the Almost-Full and Almost-Empty offset programming mode.

A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears the flag
offset registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2 Master
Reset input (MRS2) latches the value of the Big-Endian (BE) input for Ports B and
C and also latches the values of the Flag Select (FS0, FS1) and Serial Programming
Mode (SPM) inputs for choosing the Almost-Full and Almost-Empty offset program­ming method (for details see Table 1, Flag Programming, and Almost-Empty and
Almost-Full Flag Offset Programming section). The relevant Master Reset timing
diagrams can be found in Figure 4 and 5.

Note that MBC must be HIGH during Master Reset (until FFA/IRA and FFC/
IRC go HIGH). MBA and MBB are "don't care" inputs

PARTIAL RESET (PRS1, PRS2)

The FIFO1 memory of these devices undergoes a limited reset by taking
its associated Partial Reset (PRS1) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a limited reset by taking its associated Partial Reset (PRS2)
input LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC)
LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously
to the clocks. A Partial Reset initializes the internal read and write pointers and
forces the Full/Input Ready flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output
Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB)
LOW, and the Almost-Full flag (AFA, AFC) HIGH. A Partial Reset also forces
the Mailbox Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two Write clock
cycles.

Whatever flag offsets, programming method (parallel or serial), and timing
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will remain unchanged upon completion of the

1

during Master Reset.

reset operation. A Partial Reset may be useful in the case where reprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.

BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)



 ENDIAN SELECTION



This is a dual purpose pin. At the time of Master Reset, the BE select
function is active, permitting a choice of Big- or Little-Endian byte arrange­ment for data written to Port C or read from Port B. This selection determines
the order by which bytes (or words) of data are transferred through those
ports. For the following illustrations, note that both ports B and C are configured
to have a byte (or a word) bus size.

A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
go from LOW to HIGH will select a Big-Endian arrangement. When data is
moving in the direction from Port A to Port B, the most significant byte (word) of
the long word written to Port A will be read from Port B first; the least significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.

A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
go from LOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction from Port A to Port B, the least significant byte (word) of
the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figures 2 and 3 for illustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.



 TIMING MODE SELECTION



After Master Reset, the FWFT select function is available, permitting a
choice between two possible timing modes: IDT Standard mode or First
Word Fall Through (FWFT) mode. Once the Master Reset (MRS1, MRS2)
input is HIGH, a HIGH on the BE/FWFT input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKC (for FIFO2) will select IDT Standard
mode. This mode uses the Empty Flag function (EFA, EFB) to indicate whether
or not there are any words present in the FIFO memory. It uses the Full Flag
function (FFA, FFC) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using a formal read operation.

Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and
CLKC (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B17). It also uses the Input Ready function (IRA, IRC)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to the data

NOTE:

1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.

10

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation. Refer to Figure 4 (FIFO1 Master Reset)
and Figure 5 (FIFO2 Master Reset) for First Word Fall Through select timing
diagrams.

Following Master Reset, the level applied to the BE/FWFT input to choose

the desired timing mode must remain static throughout FIFO operation.

PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS

Four registers in these FIFOs are used to hold the offset values for the
Almost-Empty and Almost-Full flags. The Port B Almost-Empty flag (AEB) Offset
register is labeled X1 and the Port A Almost-Empty flag (AEA) Offset register is
labeled X2. The Port A Almost-Full flag (AFA) Offset register is labeled Y1 and
the Port C Almost-Full flag (AFC) Offset register is labeled Y2. The index of each
register name corresponds to its FIFO number. The Offset registers can be
loaded with preset values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs, or programmed in serial using the Serial
Data (SD) input (see Table 1).

SPM, FS0/SD, and FS1/SEN function the same way in both IDT Standard
and FWFT modes.



 PRESET VALUES



To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers
with one of the three preset values listed in Table 1, the Serial Program Mode
(SPM) and at least one of the flag-select inputs must be HIGH during the LOW-
to-HIGH transition of its Master Reset (MRS1 and MRS2) input. For example, to
load the preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH
when FlFO1 reset (MRS1) returns HIGH. Flag Offset registers associated with
FIFO2 are loaded with one of the preset values in the same way with FIFO2
Master Reset (MRS2) toggled simultaneously with FIFO1 Master Reset (MRS1).
For relevant Preset value loading timing diagrams, see Figure 4 and 5.



 PARALLEL LOAD FROM PORT A



To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with SPM HIGH and FS0 and FS1 LOW
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is

complete, the first four writes to FIFO1 do not store data in RAM but load the Offset
registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the Offset
registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723626, IDT723636,
or IDT723646, respectively. The highest numbered input is used as the most
significant bit of the binary number in each case. Valid programming values for
the registers range from 1 to 252 for the IDT723626; 1 to 508 for the IDT723636;
and 1 to 1,020 for the IDT723646. After all the Offset registers are programmed
from Port A, the Port C Full/Input Ready flag (FFC/IRC) is set HIGH, and both
FIFOs begin normal operation.

Refer to Figure 8 for a timing diagram illustration for parallel programming

of the flag offset values.



 SERIAL LOAD



To program the X1, X2, Y1, and Y2 registers serially, initiate a Master
Reset with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to­HIGH transition of MRS1 and MRS2. After this reset is complete, the X and Y
register values are loaded bit-wise through the FS0/SD input on each LOW­to-HIGH transition of CLKA that the FS1/SEN input is LOW. There are 32-, 36­, or 40-bit writes needed to complete the programming for the IDT723626,
IDT723636, or IDT723646, respectively. The four registers are written in the
order Y1, X1, Y2 and finally, X2. The first-bit write stores the most significant bit
of the Y1 register and the last-bit write stores the least significant bit of the X2
register. Each register value can be programmed from 1 to 252 (IDT723626),
1 to 508 (IDT723636), or 1 to 1,020 (IDT723646).

When the option to program the Offset registers serially is chosen, the Port
A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written.
FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFC/
IRC) flag also remains LOW throughout the serial programming process, until
all register bits are written. FFC/IRC is set HIGH by the LOW-to-HIGH transition
of CLKC after the last bit is loaded to allow normal FIFO2 operation.

See Figure 9 timing diagram, Serial Programming of the Almost-Full Flag

and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT
Modes).

TABLE 1  FLAG PROGRAMMING

SPM FS1/SEN FS0/SD MRS1 MRS2 X1 AND Y1 REGlSTERS

HH H↑ X64 X
HH H
HH L
HH L
HL H
HL H
HL L
LH L
LH H
LL H
LL L

NOTES:

1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

2. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.

↑↑ 64 64
↑ X16 X
↑↑ 16 16
↑ X8 X
↑↑ 88
↑↑ Parallel programming via Port A Parallel programming via Port A
↑↑ Serial programming via SD Serial programming via SD
↑↑ Reserved Reserved
↑↑ Reserved Reserved
↑↑ Reserved Reserved

11

(1)

X2 AND Y2 REGlSTERS

(2)