Integrated Device Technology Inc IDT723622L15PF, IDT723622L15PQF, IDT723622L20PF, IDT723622L20PQF, IDT723622L30PF Datasheet

Integrated Device Technology, Inc.

CMOS SyncBiFIFO



256 x 36 x 2, 512 x 36 x 2,
1024 x 36 x 2

IDT723622
IDT723632
IDT723642

FEATURES:

• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)

• Two independent clocked FIFOs buffering data in oppo­site directions

• Memory storage capacity:

IDT723622–256 x 36 x 2
IDT723632–512 x 36 x 2
IDT723642–1024 x 36 x 2

• Mailbox bypass register for each FIFO

• Programmable Almost-Full and Almost-Empty flags

• Microprocessor Interface Control Logic

• IRA, ORA,

• IRB, ORB,

AEA
AEB

, and
, and

AFA

flags synchronized by CLKA

AFB

flags synchronized by CLKB

• Supports clock frequencies up to 67MHz

FUNCTIONAL BLOCK DIAGRAM

Mail 1

CLKA

CSA

W/RA

ENA

MBA

RST1

Port-A

Control

Logic

FIFO1,
Mail1
Reset
Logic

Input

Register

36

Pointer

Register

256 x 36
512 x 36

1024 x 36

SRAM

Write

• Fast access times of 11ns

• Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)

• Low-power 0.8-Micron Advanced CMOS technology

• Industrial temperature range (-40oC to +85oC) is avail­able, tested to military electrical specifications

DESCRIPTION:

The IDT723622/723632/723642 is a monolithic, high-speed,
low-power, CMOS Bidirectional SyncFIFO (clocked) memory
which supports clock frequencies up to 67MHz and have read
access times as fast as 11ns. Two independent 256/512/
1024x36 dual-port SRAM FIFOs on board each chip buffer
data in opposite directions. Each FIFO has flags to indicate
empty and full conditions and two programable flags (almost

MBF1

Output

Register

Read

Pointer

36

IRA

AFA

FS

0

FS1

A0 - A35

ORA

AEA

36

MBF2

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

FIFO 1

9

FIFO 2

Output

Status Flag

Logic

Programmable Flag

Offset Registers

Status Flag

Logic

Read

Pointer

256 x 36
512 x 36

1024 x 36

Register

SRAM

Mail 2

Register

Write

Pointer

Input

Register

36

FIFO2,
Mail2
Reset
Logic

Port-B

Control

Logic

ORB

AEB

B0 - B35

IRB

AFB

RST2

CLKB

CSB
W

/RB
ENB
MBB

3022 drw 01

COMMERCIAL TEMPERATURE RANGE DECEMBER 1996

1996 Integrated Device Technology, Inc. DSC-3022/3

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.22

IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

DESCRIPTION (CONTINUED)

Full and almost Empty) to indicate when a selected number of
words is stored in memory. Communication between each
port may bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has
been stored. Two or more devices may be used in parallel to
create wider data paths.

The IDT723622/723632/723642 is a synchronous (clocked)
FIFO, meaning each port employs a synchronous interface.
All data transfers through a port are gated to the LOW-to­HIGH transition of a port clock by enable signals. The clocks
for each port are independent of one another and can be

PIN CONFIGURATION

/RB

NC
B
B34
B33
B32

GND

B
B30
B29
B28
B27
B26

VCC

B25
B24

GND

B
B22
B21
B20
B19
B18

GND

B
B16

VCC

B15
B14
B13
B12

GND

NC

NC

CC

NC

V

ENB

CLKB

W

GND

IRB

CSB

987654321

10

NC

17161514131211

18

35

19
20
21
22
23

31

24
25
26
27
28
29
30
31
32
33

23

34
35
36
37
38
39
40

17

41
42
43
44
45
46
47
48
49
50

51525354555657

585960

ORB

AFB

61

CC

AEB

MBF1

V

626364

MBB

PQ132-1

65

asynchronous or coincident. The enables for each port are
arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.

The Input Ready (IRA, IRB) and Almost-Full (

AFA, AFB

flags of a FIFO are two-stage synchronized to the port clock
that writes data into its array. The Output Ready (ORA, ORB)
and Almost-Empty (

AEA, AEB

) flags of a FIFO are two-stage
synchronized to the port clock that reads data from its array.
Offset values for the Almost-Full and Almost-Empty flags of
both FIFOs can be programmed from Port A.

The IDT723622/723632/723642 is characterized for op-

eration from 0°C to 70°C.

A

RST2

GND

FS1

132

666768

FS0

131

69

MBA

RST1

130

129

70

71

AEA

MBF2

128

127

72

73

AFA

126

74

CC

V

125

75

ORA

IRA

CSA

124

123

122

121

76

7778798081

R

W/

ENA

120

CLKA

GND

119

118

116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

82

NC

117

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

83

NC
NC
A

35

A34
A33
A32
VCC
A31
A30
GND
A

29

A28
A27
A26
A25
A24
A23
GND
A

22

VCC
A21
A20
A19
A18
GND
A

17

A16
A15
A14
A13
VCC
A12
NC

)

11

NC

B

NOTES:

1. NC – no internal connection

2. Uses Yamaichi socket IC51-1324-828

VCC

B6

5

B

GND

B4B3B2B1B0

B9B7B8

B10

0

A1

A2

VCC

A3A4A5

A

GND

PQF Package

TOP VIEW

5.22 2

6

A

GND

A7A8A9

NC

NC

A10

A11

GND

3022 drw 02

IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

A

A35
A34
A33
A32

VCC

A31
A30

GND

A
A28
A27
A26
A25
A24
A23

GND

A

VCC

A21
A20
A19
A18

GND

A
A16
A15
A14
A13

VCC

A12

CLKA

GND

120

119

R

W/

ENA

118

117

IRA

CSA

116

115

CC

ORA

V

114

113

AFA

112

MBF2

AEA

111

110

MBA

RST1

109

108

FS0

107

GND

FS1

106

105

RST2

MBB

104

103

CC

V

MBF1

102

101

ORB

AEB

AFB

99

98979695949392

100

1
2
3
4
5
6
7
8
9

29

10
11
12
13
14

PN120-1
15
16
17

22

18
19
20
21
22
23
24

17

25
26
27
28
29
30

A4

40

41

A3

434445

42

A2A1A0

VCC

47

46

0

B

GND

49

48

515253

50

B1B2B3B4B5

GND

31

32333435363738

11

A9A8A7

A

A10

GND

A6

39

5

A

GND

/RB

W

CSB

CLKB

ENB

IRB

GND

54555657585960

6

B7B8B9

B

VCC

B10

B11

CC

V

91

90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61

35

B
B34
B33
B32
GND

31

B
B30
B29
B28
B27
B26
VCC
B25
B24
GND

23

B
B22
B21
B20
B19
B18
GND

17

B
B16
VCC
B15
B14
B13
B12
GND

3022 drw 03

TQFP

TOP VIEW

5.22 3

IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol Name I/O Description

A0-A35 Port-A Data I/0 36-bit bidirectional data port for side A.

AEA

AEB

AFA

AFB

B0 - B35 Port-B Data I/O 36-bit bidirectional data port for side B.
CLKA Port-A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A

CLKB Port-B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B

CSA

CSB

ENA Port-A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

ENB Port-B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

FS1, Flag Offset I The LOW-to-HIGH transition of a FlFO’s reset input latches the values of FSO
FS0 Selects and FS1. If either FSO or FS1 is HIGH when a reset input goes HIGH, one

IRA Input-Ready O IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is

IRB Input-Ready O IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is

MBA Port-A Mailbox I A HIGH level on MBA chooses a mailbox register for a port-A read or

Port-A Almost O Programmable almost-empty flag synchronized to CLKA. It is LOW

-Empty Flag (Port A) when the number of words in FIF02 is less than or equal to the value in the
almost-empty A offset register, X2.

Port-B Almost O Programmable almost-empty flag synchronzed to CLKB. It is LOW

-Empty Flag (Port B) when the number of words in FIF01 is less than or equal to the value in the
almost-empty B offset register, X1.

Port-A Almost O Programmable almost-full flag synchronized to CLKA. It is LOW when

-Full Flag (Port A) the number of empty locations in FIF01 is less than or equal to the value in
the almost-full A offset register, Y1.

Port-B Almost O Programmable almost-full flag synchronized to CLKB. It is LOW when

-Full Flag (Port B) the number of empty locations in FIF02 is less than or equal to the value in
the almost-full B offset register, Y2.

and can be asynchronous or coincident to CLKB. IRA, ORA,

AFA

, and

AEA

are all synchronized to the LOW-to-HIGH transition of CLKA.

and can be asynchronous or coincident to CLKA. IRB, ORB,

AFB

, and

AEB

are synchronized to the LOW-to-HIGH transition of CLKB.

Port-A Chip I

CSA

must be LOW to enable to LOW-to-HIGH transition of CLKA to read or

Select write on port A. The AO-A35 outputs are in the high-impedance state when

CSA

is HIGH.

Port-B Chip I

CSB

must be LOW to enable a LOW-to-HIGH transition of CLKB to read or

Select write data on port B. The BO- B35 outputs are in the high-impedance state

when

CSB

is HIGH.

write data on port A.

write data on port B.

of the three preset values is selected as the offset for the FlFOs almost-full
and almost-empty flags. If both FIFOs are reset simultaneously and both FSO
and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to
FIFO1 almost empty offsets for both FlFOs.

Flag (Port A) LOW, FIFO1 is full and writes to its array are disabled. IRA is set LOW

when FIFO1 is reset and is set HIGH on the second LOW-to-HIGH transition
of CLKA after reset.

Flag (Port B) LOW, FIFO2 is full and writes to its array are disabled. IRB is set LOW when

FIFO2 is reset and is set HIGH on the second LOW-to-HIGH transition of
CLKB after reset.

Select write operation. When the AO-A35 outputs are active, a HIGH level on MBA

selects data from the mail2 register for output and a LOW level selects FIF02
output-register data for output.

5.22 4

IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONT.)

Symbol Name I/O Description

MBB Port-B Mailbox I A HIGH level on MBB chooses a mailbox register for a port-B read or

Select write operation. When the B0-B35 outputs are active, a HIGH level on

MBB selects data from the mail1 register or output and a LOW level selects
FIFO1 output-register data for output.

MBF1

MBF2

ORA Output-Ready O ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is

ORB Output-Ready O ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB

RST1

RST2

W/RA Port-A Write/ I A HIGH selects a write operation and a LOW selects a read operation on port A

W

/RB Port-B Write/ I A LOW selects a write operation and a HIGH selects a read operation on port B

Mail1 Register O
Flag to the mail1 register. Writes to the mail1 register are inhibited while

Mail2 Register O
Flag mail2 register. Writes to the mail2 register are inhibited while

MBF1

is set LOW by a LOW-to-HIGH transition of CLKA that writes data

LOW.
read is selected and MBB is HIGH.

MBF2

MBF1

is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B

MBF1

is set HIGH when FIFO1 is reset.

is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the

MBF2

MBF2

is set HIGH by a LOW-to-HIGH transition of CLKA when a port-A read is

selected and MBA is HIGH.

MBF2

is also set HIGH when FIFO2 is reset.

MBF1

is

is LOW.

Flag (Port A) LOW, FIFO2 is empty and reads from its memory are disabled. Ready data

is present on the output register of FIFO2 when ORA is HIGH. ORA is
forced LOW when FlFO2 is reset and goes HIGH on the third LOW-to-HIGH
transition of CLKA after a word is loaded to empty memory.

Flag (Port B) is LOW, FlFO1 is empty and reads from its memory are disabled. Ready data

is present on the output register of FIFO1 when ORB is HIGH. ORB is forced LOW
when FIFO1 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKB
after a word is loaded to empty memory.

FIFO1 Reset I To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH

transitions of CLKB must occur while
of

RST1

latches the status of FSO and FS1 for

RST1

is LOW. The LOW-to-HIGH transition

AFA

and

AEB

offset selection.

FIFO1 must be reset upon power up before data is written to its RAM.

FIFO2 Reset I To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH

transitions of CLKB must occur while
of

RST2

latches the status of FSO and FS1 for

RST2

is LOW. The LOW-to-HIGH transition

AFB

and

AEA

offset selection.

FIFO2 must be reset upon power up before data is written to its RAM.

Read Select for a LOW-to-HIGH transition of CLKA. The AO-A35 outputs are in

the HIGH impedance state when W/RA is HIGH.

Read Select for a LOW-to-HIGH transition of CLKB. The BO-B35 outputs are in the HIGH

impedance state when W/RB is LOW.

5.22 5

IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UN­LESS OTHERWISE NOTED)

Symbol Rating Commercial Unit

CC Supply Voltage Range -0.5 to 7 V

V

(2)

V

I
O

V
I

IK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA

OK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA

I

OUT Continuous Output Current (VO = 0 to VCC) ±50 mA

I
I

CC Continuous Current Through VCC or GND ±400 mA

A Operating Free Air Temperature Range 0 to 70 °C

T
T

STG Storage Temperature Range -65 to 150 °C

NOTES:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

Input Voltage Range -0.5 to VCC+0.5 V

(2)

Output Voltage Range -0.5 to VCC+0.5 V

(1)

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Max. Unit

V

CC Supply Voltage 4.5 5.5 V

IH High-Level Input Voltage 2 V

V

IL Low-Level Input Voltage 0.8 V

V

I

OH High-Level Output Current -4 mA

OL Low-Level Output Current 8 mA

I

A Operating Free-Air 0 70 °C

T

Temperature

5.22 6

IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERA­TURE RANGE (UNLESS OTHERWISE NOTED)

IDT723622
IDT723632
IDT723642

Commerical

A = 15, 20, 30 ns

t

Parameter Test Conditions Min. Typ.

OH VCC = 4.5V, IOH = -4 mA 2.4 V

V

OL VCC = 4.5 V, IOL = 8 mA 0.5 V

V

I

LI VCC = 5.5 V, VI = VCC or 0 ±5 µA

LO VCC = 5.5 V, VO = VCC or 0 ±5 µA

I
I

CC VCC = 5.5 V, VI = VCC -0.2 V or 0 400 µA

(2)

∆I

CC

VCC = 5.5 V, One Input at 3.4 V,
Other Inputs at V

CC or GND

CSA

= VIH A0-A35 0 mA

CSB

= VIH B0-B35 0

CSA

= VIL A0-A35 1

CSB

= VIL B0-35 1

All Other Inputs 1

C

IN VI = 0, f = 1 MHz 4 pF

OUT VO = 0, f = 1 MHZ 8 pF

C

(1)

Max. Unit

NOTES:

1. All typical values are at V

2. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or V

CC = 5V, TA = 25°C.

CC.

5.22 7

IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPER­ATING FREE-AIR TEMPERATURE

723622-15 723622-20 723622-30
723632-15 723632-20 723632-30
723642-15 723642-20 723642-30

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

S Clock Frequency, CLKA or CLKB 66.7 50 33.4 MHz

f

t

CLK Clock Cycle Time, CLKA or CLKB 15 20 30 ns

CLKH Pulse Duration, CLKA or CLKB HIGH 6 8 10 ns

t

t

CLKL Pulse Duration, CLKA and CLKB LOW 6 8 10 ns

DS Setup Time, A0-A35 before CLKA↑ and B0-B35 4 5 6 ns

t

before CLKB↑

ENS Setup Time,

t

CLKA↑;

t

RSTS Setup Time,

or CLKB↑

tFSS Setup Time, FS0 and FS1 before

HIGH

t

DH Hold Time, A0-A35 after CLKA↑ and B0-B35 after 1 1 1 ns

CLKB↑

ENH Hold Time,

t

CSB, W

t

RSTH Hold Time,

CLKB↑

tFSH Hold Time, FS0 and FS1 after

(2)

SKEW1

t

Skew Time, between CLKA↑ and CLKB↑ for ORA, 7.5 9 11 ns
ORB, IRA, and IRB

(2)

t

SKEW2

Skew Time, between CLKA↑ and CLKB↑ for

AEB, AFA

CSA

, W/RA, ENA, and MBA before 4.5 5 6 ns

CSB, W

/RB, ENB, and MBB before CLKB↑

RST1

or

RST2

(1)

LOW before CLKA↑ 567ns

RST1

CSA

, W/RA, ENA, and MBA after CLKA↑;1 1 1 ns

/RB, ENB, and MBB after CLKB↑

RST1

or

RST2

(1)

, and

AFB

LOW after CLKA↑ or 4 4 5 ns

RST1

and

and

RST2

RST2

7.5 8.5 9.5 ns

HIGH 2 3 3 ns

AEA

,121620ns

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB
cycle.

5.22 8