Integrated Device Technology Inc IDT723614L15PF, IDT723614L15PQF, IDT723614L20PF, IDT723614L20PQF, IDT723614L30PF Datasheet
...
Integrated Device Technology, Inc.
CMOS SyncBiFIFO
WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
IDT723614
FEATURES:
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage
capacity each) buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Dynamic Port B bus sizing of 36-bits (long word), 18-bits
(word), and 9-bits (byte)
• Selection of Big- or Little-Endian format for word and
byte bus sizes
• Three modes of byte-order swapping on port B
• Programmable Almost-Full and Almost-Empty Flags
FUNCTIONAL BLOCK DIAGRAM
CLKA
RST
ODD/
EVEN
W/RA
Device
Control
CSA
ENA
MBA
Port-A
Control
Logic
Input
Register
64 x 36
SRAM
Write
Pointer
• Microprocessor interface control logic
•
EFA, FFA, AEA
•
EFB, FFB, AEB
, and
, and
AFA
flags synchronized by CLKA
AFB
flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
• Low-power advanced BiCMOS technology
• Supports clock frequencies up to 67 MHz
• Fast access times of 10 ns
• Available in 132-pin plastic quad flat package (PQF) or
space-saving 120-pin thin quad flat package (TQFP)
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
MBF1
Mail 1
Register
Read
Pointer
Parity
Generation
Parity
Gen/Check
Output
Register
Byte Swapping
Byte Matching &
PEFB
PGB
36
36
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
EFB
AEB
B0-B
FFB
AFB
3146 drw 01
35
FFA
AFA
FS0
FS1
A0 - A
35
EFA
AEA
PGA
PEFA
MBF2
The IDT logo is a registered trademark and SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
36
FIFO1
FIFO2
Output
Register
Parity
Gen/Check
Status Flag
Logic
Programmable Flag
Offset Register
64 x 36
Parity
Generation
Pointer
SRAM
Status Flag
Logic
Read
Mail 2
Register
Write
Pointer
Bus Matching &
Byte Swapping
Input
Register
Port-B
Control
Logic
COMMERCIAL TEMPERATURE RANGE MAY 1997
1997 Integrated Device Technology, Inc DSC-3146/4
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
1
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The IDT723614 is a monolithic, high-speed, low-power
BiCMOS bidirectional clocked FIFO memory. It supports
clock frequencies up to 67MHz and has read access times as
fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs
on board the chip buffer data in opposite directions. Each
FIFO has flags to indicate empty and full conditions and two
programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory.
FIFO data on port B can be input and output in 36-bit, 18-bit,
and 9-bit formats with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible
PIN CONFIGURATIONS
MBA
MBF2
1
FS
5
EVEN
0
ODD/
FS
432
GND
AEA
EFA
GND
VCC
GND
A
A11
VCC
A12
A13
A14
GND
A
A16
A17
A18
A19
A20
GND
A
A22
A23
A
R
CC
W/
GND
PEFA
V
PGA
9
876
10
CSA
AFA
ENA
CLKA
FFA
17161514131211
18
19
20
A
0
21
A1
22
A2
23
24
3
A
25
A4
26
A5
27
A6
28
29
A7
30
A8
31
A9
32
33
10
34
35
36
37
38
39
40
15
41
42
43
44
45
46
47
21
48
49
50
515253545556575859606162636465666768697071727374757677787980818283
with any bus size selection. Communication between each
port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has
been stored. Parity is checked passively on each port and may
be ignored if not desired. Parity generation can be selected for
data read from each port. Two or more devices can be used
in parallel to create wider data paths.
The IDT723614 is a clocked FIFO, which means each port
employs a synchronous interface. All data transfers through a
port are gated to the LOW-to-HIGH transition of a continuous
(free-running) port clock by enable signals. The clocks for
each port are independent of one another and can be asyn-
B
R
CC
RST
*
GND
BE
1
132
SW1
SW0
131
130
SIZ1
129
SIZ0
128
GND
MBF1
127
126
PEFB
PGB
125
124
V
123
W/
122
CLKB
ENB
121
120
CSB
119
FFB
118
AFB
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
GND
AEB
EFB
0
B
B1
B2
GND
B
3
B4
B5
B6
VCC
B7
B8
B9
GND
10
B
B11
VCC
B12
B13
B14
GND
15
B
B16
B17
B18
B19
B20
GND
B
21
B22
B23
28
A24
VCC
A
A25
A26
A27
A29
VCC
GND
33
A
A30
A31
A32
A34
GND
*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP (PQ132-1, order code: PQF)
NOTES:
1. NC - No internal connection.
2. Uses Yamaichi socket IC51-1324-828.
35
B
A35
B34
B33
GND
TOP VIEW
32
B
GND
26
CC
B31
B30
VCC
B
B29
B28
B27
B25
B24
V
GND
3146 drw 02
2
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
chronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous
interface.
The full flag (
FFA, FFB
) and almost-full flag (
AFA, AFB
) of
a FIFO are two-stage synchronized to the port clock that
PIN CONFIGURATIONS (CONT.)
A28
115
A29
114
30
GND
A
113
112
A31
111
A32
110
A33
109
A34
108
A
A
A
GND
A
A
A
A
A
A
A
A
A
A
A
GND
A
A
A
V
CC
A
A
A
A
GND
A
A
A
EFA
AEA
A24
VCC
A25
A26
A27
120
119
118
117
116
23
1
22
2
21
3
4
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13
12
12
13
11
14
10
15
16
9
17
8
18
7
19
20
6
21
5
22
4
23
3
24
25
2
26
1
27
0
28
29
30
writes data to its array. The empty flag (
empty (
AEA, AEB
) flag of a FIFO are two stage synchronized
EFA, EFB
to the port clock that reads data from its array.
The IDT723614 is characterized for operation from 0°C to
70°C.
A35
107
GND
B35
106
105
34
B
104
B33
103
B32
102
29
B30
B31
B
GND
99
98979695949392
101
100
VCC
B28
B27
23
B
B26
B25
B24
91
B
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
22
B
21
GND
20
B
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
9
B
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
2
B
B
1
B
0
EFB
AEB
AFB
) and almost-
313233
FFA
AFA
34
CSA
ENA
A
R
W/
CC
V
39
38
PGA
PEFA
40
41
4243444546
2
MBA
MBF
1
FS
FS0
RST
EVEN
353637
CLKA
ODD/
TQFP (PN120-1, order code: PF)
TOP VIEW
47
BE
GND
484950
SW1
SIZ1
SW0
51
52
53545556575859
1
PGB
SIZ0
PEFB
MBF
CC
V
B
R
W/
ENB
CLKB
60
FFB
CSB
3146 drw 03
3
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol Name I/O Description
A0-A35 Port A Data I/O 36-bit bidirectional data port for side A.
AEA
AEB
AFA
AFB
B0-B35 Port B Data. I/O 36-bit bidirectional data port for side B.
BE
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B
CSA
CSB
EFA
EFB
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
FFA
FFB
Port A Almost-Empty O Programmable almost-empty flag synchronized to CLKA. It is LOW when
Flag (Port A) the number of 36-bit words in FIFO2 is less than or equal to the value in
the offset register, X.
Port B Almost-Empty O Programmable almost-empty flag synchronized to CLKB. It is LOW when the
Flag (Port B) number of 36-bit words in FIFO1 is less than or equal to the value in the
offset register, X.
Port A Almost-Full O Programmable almost-full flag synchronized to CLKA. It is LOW when the
Flag (Port A) number of 36-bit empty locations in FIFO1 is less than or equal to the value
in the offset register, X.
Port B Almost-Full O Programmable almost-full flag synchronized to CLKB. It is LOW when the
Flag (Port B) number of 36-bit empty locations in FIFO2 is less than or equal to the value
in the offset register, X.
Big-endian select I Selects the bytes on port B used during byte or word data transfer. A LOW
on BE
selects the most significant bytes on B0-B35 for use, and a HIGH
selects the least significant bytes
and can be asynchronous or coincident to CLKB.
EFA, FFA, AFA
, and
AEA
are synchronized to the LOW-to-HIGH transition of CLKA.
and can be asynchronous or coincident to CLKA. Port B byte swapping and
data port sizing operations are also synchronous to the LOW-to-HIGH transition of CLKB.
EFB, FFB, AFB
, and
AEB
are synchronized to the LOW-to-HIGH
transition of CLKB.
Port A Chip Select I
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or
write data on port A. The A0-A35 outputs are in the high-impedance state
when
CSA
is HIGH.
Port B Chip Select I
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port B. The B0-B35 outputs are in the high-impedance state
when
CSB
is HIGH.
Port A Empty Flag O
EFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
EFA
(Port A) LOW, FIFO2 is empty, and reads from its memory are disabled. Data can
be read from FIFO2 to the output register when
EFA
is HIGH.
EFA
is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after data is loaded into empty FIFO2 memory.
Port B Empty Flag O
EFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
EFB
(Port B) LOW, the FIFO1 is empty, and reads from its memory are disabled. Data can
be read from FIFO1 to the output register when
EFB
is HIGH.
EFB
is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after data is loaded into empty FIFO1 memory.
write data on port A.
write data on port B.
Port A Full Flag O
(Port A) LOW, FIFO1 is full, and writes to its memory are disabled.
FFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
FFA
is forced LOW
FFA
when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset.
Port B Full Flag O
(Port B) LOW, FIFO2 is full, and writes to its memory are disabled.
FFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
FFB
is forced LOW
FFB
when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after reset.
is
is
is
is
4
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol Name I/O Description
`FS1, FS0 Flag-Offset Selects I The LOW-to-HIGH transition of
selects one of four preset values for the almost-full flag and almost-empty flag
offset.
MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a port A read or write
Select operation. When the A0-A35 outputs are active, a HIGH level on MBA selects
data from the mail2 register for output, and a LOW level selects FIFO2 output
register data for output.
MBF1
Mail1 Register Flag O
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the
mail1 register. Writes to the mail1 register are inhibited while
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is
selected and both SIZ1 and SIZ0 are HIGH.
is reset.
MBF2
Mail2 Register Flag O
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the
mail2 register. Writes to the mail2 register are inhibited while
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is
selected and MBA is HIGH.
ODD/ Odd/Even Parity I Odd parity is checked on each port when ODD/
EVEN
Select checked when ODD/
EVEN
generated for each port if parity generation is enabled for a readoperation.
PEFA
Port A Parity Error O When any byte applied to terminals A0-A35 fails parity,
Flag (Port A) organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant
bit of each byte serving as the parity bit. The type of parity checked is deter
mined by the state of the ODD/
The parity trees used to check the A0-A35 inputs are shared by the mail2 register
to generate parity if parity generation is selected by PGA. Therefore, if a mail2
read parity generation is setup by having W/RA LOW, MBA HIGH, and PGA
PEFB
HIGH, the
Port B Parity Error O When any valid byte applied to terminals B0-B35 fails parity,
PEFA
flag is forced HIGH regardless of the A0-A35 inputs.
Flag (Port B) are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit
of each byte serving as the parity bit. A byte is valid when it is used by the bus
size selected for Port B. The type of parity checked is determined by the state of
the ODD/
EVEN
input.
The parity trees used to check the B0-B35 inputs are sharedby the mail 1 register to
generate parity if parity generation isselected by PGB. Therefore, if a mail1 read
with parity generation is setup by having W/RB LOW, SIZ1 and SIZ0 HIGH, and
PGB HIGH, the
PEFB
flag is forced HIGH regardless of the state of the B0-B35
inputs.
PGA Port A Parity I Parity is generated for data reads from port A when PGA is HIGH. The type of
Generation parity generated is selected by the state of the ODD/
organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity
bits are output in the most significant bit of each byte.
PGB Port B Parity I Parity is generated for data reads from port B when PGB is HIGH. The type
Generation of parity generated is selected by the state of the ODD/
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
RST
Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while
AFB, MBF1
FFB
flags LOW. The LOW-to-HIGH transition of
, and
MBF2
flags HIGH and the
FS1 and FS0 inputs to select almost-full and almost-empty flag offsets
SIZ0, SIZ1 Port B bus size I A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and
selects (Port B) the following LOW-to-HIGH transition of CLKB implements the latched states as a
port B bus size. Port B bus sizes can be long word, word, or byte. A high on both
SIZ0 and SIZ1 accesses the mailbox reegisters for a port B 36-bit write or read.
RST
latches the values of FS0 and FS1, which
MBF2
is set HIGH when the device is reset.
is LOW. ODD/
EVEN
input.
MBF1
MBF1
is set HIGH when the device
MBF2
EVEN
is HIGH, and even parity is
EVEN
also selects the type of parity
PEFA
is LOW. Bytes are
PEFB
EVEN
input. Bytes are
EVEN
input. Bytes are
RST
is LOW. This sets the
EFA, EFB, AEA, AEB, FFA,
RST
latches the status of the
is set LOW.
is set LOW.
is LOW. Bytes
AFA
,
and
5
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol Name I/O Description
SW0, SW1 Port B byte swap I At the beginning of each long word transfer, one of four modes of byte-order
Select (Port B) swapping is selected by SW0 and SW1. The four modes are no swap, byte
swap, word swap, and byte-word swap. Byte-order swapping is possible with
any bus-size selection.
W/RA Port A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on
Select port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
W/RB Port B Write/Read I A HIGH selects a write operation and a LOW selects a read operation on
Select port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is HIGH.
SIGNAL DESCRIPTIONS
RESET
The IDT723614 is reset by taking the reset (
RST
) input
LOW for at least four port A clock (CLKA) and four port B clock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of each FIFO and forces the
full flags (
the almost-empty flags (
flags (
(
MBF1, MBF2
LOW-to-HIGH transitions of CLKA and
FFA, FFB
AFA, AFB
) HIGH. After a reset,
) LOW, the empty flags (
AEA, AEB
) LOW and the almost-full
EFA, EFB
) LOW,
) HIGH. A reset also forces the mailbox flags
FFA
is set HIGH after two
FFB
is set HIGH after
two LOW-to-HIGH transitions of CLKB. The device must be
reset after power up before data is written to its memory.
A LOW-to-HIGH transition on the
RST
input loads the
almost-full and almost-empty offset register (X) with the values selected by the flag-select (FS0, FS1) inputs. The values
that can be loaded into the registers are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of port A data A0-A35 outputs is controlled by
the port A chip select (
CSA
) and the port A write/read select
(W/RA). The A0-A35 outputs are in the high-impedance state
when either
active when both
CSA
or W/RA is HIGH. The A0-A35 outputs are
CSA
and W/RA are LOW. Data is loaded into
FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition
of CLKA when
MBA is LOW, and
CSA
is LOW, W/RA is HIGH, ENA is HIGH,
FFA
is HIGH. Data is read from FIFO2 to
the A0-A35 outputs by a LOW-to-HIGH transition of CLKA
when
CSA
is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW,
and
EFA
is HIGH (see Table 2).
The port B control signals are identical to those of port A.
The state of the port B data (B0-B35) outputs is controlled by
the port B chip select (
CSB
) and the port B write/read select
(W/RB). The B0-B35 outputs are in the high-impedance state
when either
active when both
CSB
or W/RB is HIGH. The B0-B35 outputs are
CSB
and W/RB are LOW. Data is loaded into
FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition
of CLKB when
CSB
is LOW, W/RB is HIGH, ENB is HIGH,
EFB
is HIGH, and either SIZ0 or SIZ1 is LOW. Data is read from
FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of
CLKB when
CSB
is LOW, W/RB is LOW, ENB is HIGH,
EFB
is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 3).
The setup and hold time constraints to the port clocks
for the port chip selects (CSA, CSB) and write/read selects (W/
RA, W/RB) are only for enabling write and read operations and
are not related to high-impedance control of the data outputs.
If a port enable is LOW during a clock cycle, the port chip select
and write/read select can change states during the setup and
hold time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two
flip-flop stages. This is done to improve flag reliability by
reducing the probability of metastable events on the output
when CLKA and CLKB operate asynchronously to one another.
EFA, AEA, FFA
EFB, AEB, FFB
, and
, and
AFA
are synchronized to CLKA.
AFB
are synchronized to CLKB. Tables
4 and 5 show the relationship of each port flag to FIFO1 and
FIFO2.
EMPTY FLAGS (
EFA
EFA
,
EFB
EFB
)
The empty flag of a FIFO is synchronized to the port clock
that reads data from its array. When the empty flag is HIGH,
new data can be read to the FIFO output register. When the
empty flag is LOW, the FIFO is empty and attempted FIFO
reads are ignored. When reading FIFO1 with a byte or word
size on port B,
EFB
is set LOW when the fourth byte or second
word of the last long word is read.
The read pointer of a FIFO is incremented each time a
new word is clocked to the output register. The state machine
that controls an empty flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. A word written to a
FIFO can be read to the FIFO output register in a minimum of
three cycles of the empty flag synchronizing clock. Therefore,
an empty flag is LOW if a word in memory is the next data to
be sent to the FIFO output register and two cycles of the port
6
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
clock that reads data from the FIFO have not elapsed since the
time the word was written. The empty flag of the FIFO is set
HIGH by the second LOW-to-HIGH transition of the synchronizing clock, and the new data word can be read to the FIFO
output register in the following cycle.
A LOW-to-HIGH transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the
clock transition occurs at time t
SKEW1 or greater after the write.
Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 13 and 14).
TABLE 1: FLAG PROGRAMMING
ALMOST-FULL AND
FS1 FS0
RST
RST
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
HH↑ 16
HL↑ 12
LH↑ 8
LL↑ 4
FULL FLAG (
FFA
FFA
,
FFB
FFB
)
The full flag of a FIFO is synchronized to the port clock
that writes data to its array. When the full flag is HIGH, a
memory location is free in the SRAM to receive new data. No
memory locations are free when the full flag is LOW and
attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is
incremented. The state machine that controls a full flag
monitors a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, the previous
memory location is ready to be written in a minimum of three
cycles of the full flag synchronizing clock. Therefore, a full flag
is LOW if less than two cycles of the full flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the full
flag synchronization clock after the read sets the full flag
HIGH and the data can be written in the following clock cycle.
A LOW-to-HIGH transition on a full flag synchronizing
clock begins the first synchronization cycle of a read if the
clock transition occurs at time t
SKEW1 or greater after the read.
Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 15 and 16).
TABLE 2: PORT-A ENABLE FUNCTION TABLE
CSA
CSA
W/
RRA ENA MBA CLKA A0-A35 Outputs Port Functions
H X X X X In High-Impedance State None
L H L X X In High-Impedance State None
LHHL↑ In High-Impedance State FIFO1 Write
LHHH↑ In High-Impedance State Mail1 Write
L L L L X Active, FIFO2 Output Register None
LLHL↑Active, FIFO2 Output Register FIFO2 Read
L L L H X Active, Mail2 Register None
LLHH↑ Active, Mail2 Register Mail2 Read (Set
TABLE 3: PORT-B ENABLE FUNCTION TABLE
CSB
CSB
W/
RRB ENB SIZ1, SIZ0 CLKB B0-B35 Outputs Port Functions
H X X X X In High-Impedance State None
L H L X X In High-Impedance State None
L H H One, both LOW ↑ In High-Impedance State FIFO2 Write
L H H Both HIGH ↑ In High-Impedance State Mail2 Write
L L L One, both LOW X Active, FIFO1 Output Register None
L L H One, both LOW ↑ Active, FIFO1 Output Register FIFO1 read
L L L Both HIGH X Active, Mail1 Register None
L L H Both HIGH ↑ Active, Mail1 Register Mail1 Read (Set
MBF2
MBF1
HIGH)
HIGH)
7
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ALMOST EMPTY FLAGS (
AEA
AEA
,
AEB
AEB
)
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array. The state machine
that controls an almost-empty flag monitors a write-pointer
and a read-pointer comparator that indicates when the FIFO
SRAM status is almost empty, almost empty+1, or almost
empty+2. The almost-empty state is defined by the value of
the almost-full and almost-empty offset register (X). This
register is loaded with one of four preset values during a
device reset (see Reset above). An almost-empty flag is LOW
when the FIFO contains X or less long words in memory and
is HIGH when the FIFO contains (X+1) or more long words.
Two LOW-to-HIGH transitions of the almost-empty flag
synchronizing clock are required after a FIFO write for the
almost-empty flag to reflect the new level of fill. Therefore, the
almost-empty flag of a FIFO containing (X+1) or more long
words remains LOW if two cycles of the synchronizing clock
have not elapsed since the write that filled the memory to the
(X+1) level. An almost-empty flag is set HIGH by the second
LOW-to-HIGH transition of the synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-toHIGH transition of an almost-empty flag synchronizing clock
begins the first synchronization cycle if it occurs at time t
SKEW2
or greater after the write that fills the FIFO to (X+1) long words.
Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figure 17 and 18).
ALMOST FULL FLAGS (
AFA
AFA
,
AFB
AFB
)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array. The state machine that
controls an almost-full flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almostempty offset register (X). This register is loaded with one of
four preset values during a device reset (see Reset above).
An almost-full flag is LOW when the FIFO contains (64-X) or
more long words in memory and is HIGH when the FIFO
contains [64-(X+1)] or less long words.
Two LOW-to-HIGH transitions of the almost-full flag
synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill. Therefore, the
almost-full flag of a FIFO containing [64-(X+1)] or less words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the read that reduced the number of long words
in memory to [64-(X+1)]. An almost-full flag is set HIGH by the
second LOW-to-HIGH transition of the synchronizing clock
after the FIFO read that reduces the number of long words in
memory to [64-(X+1)]. A LOW-to-HIGH transition of an
almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time t
SKEW2 or greater after the read
that reduces the number of long words in memory to [64(X+1)]. Otherwise, the subsequent synchronizing clock cycle
can be the first synchronization cycle (see Figure 19 and 20).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command
and control information between port A and port B without
putting it in queue. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on CLKA writes
A0-A35 data to the mail1 register when a port A write is
selected by
CSA
, W/RA, and ENA with MBA HIGH. A LOWto-HIGH transition on CLKB writes B0-B35 data to the mail2
register when a port B write is selected by
CSB
, W/RB, and
ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail
register sets the corresponding flag (
MBF1
or
MBF2
) LOW.
Attempted writes to a mail register are ignored while the mail
flag is LOW.
When the port A data outputs (A0-A35) are active, the
data on the bus comes from the FIFO2 output register when
MBA is LOW and from the mail2 register when MBA is HIGH.
When the port B data outputs (B0-B35) are active, the data on
the bus comes from the FIFO1 output register when either one
TABLE 4: FIFO1 FLAG OPERATION
Synchronized Synchronized
Number of 36-Bit to CLKB to CLKA
Words in the FIFO1
(1)
EFB
EFB
AEB
AEB
AFA
AFA
FFA
FFA
0LLHH
1 to X H L H H
(X+1) to [64-(X+1)] H H H H
(64-X) to 63 H H L H
64 H H L L
NOTE:
1. X is the value in the almost-empty flag and almost-full flag offset register.
TABLE 5: FIFO2 FLAG OPERATION
Synchronized Synchronized
Number of 36-Bit to CLKA to CLKB
Words in the FIFO2
(1)
EFA
EFA
AEA
AEA
AFB
AFB
0LLHH
1 to X H L H H
(X+1) to [64-(X+1)] H H H H
(64-X) to 63 H H L H
64 H H L L
FFB
FFB
8
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)
Symbol Rating Commercial Unit
V
CC Supply Voltage Range -0.5 to 7 V
(2)
I
V
O
V
I
IK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA
OK Output Clamp Current, (VO < 0 or VO > VCC) ±50 mA
I
I
OUT Continuous Output Current, (VO = 0 to VCC) ±50 mA
CC Continuous Current Through VCC or GND ±500 mA
I
A Operating Free Air Temperature Range 0 to 70 °C
T
T
STG Storage Temperature Range -65 to 150 °C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
Input Voltage Range -0.5 to VCC+0.5 V
(2)
Output Voltage Range -0.5 to VCC+0.5 V
(1)
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
VIH HIGH Level Input Voltage 2 – V
VIL LOW-Level Input Voltage – 0.8 V
IOH HIGH-Level Output Current – -4 mA
IOL LOW-Level Output Current – 8 mA
TA Operating Free-air 0 70 °C
Temperature
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter Test Conditions Min. Typ.
OH VCC = 4.5V, IOH = -4 mA 2.4 V
V
V
OL VCC = 4.5 V, IOL = 8 mA 0.5 V
I VCC = 5.5 V, VI = VCC or 0 ±50 µA
I
OZ VCC = 5.5 V, VO = VCC or 0 ±50 µA
I
I
CC VCC = 5.5 V, IO = 0 mA, VI = VCC or GND 1 mA
IN VI = 0, f = 1 MHz 4 pF
C
OUT VO = 0, f = 1 MHZ 8 pF
C
NOTE:
1 . All typical values are at VCC = 5 V, TA = 25°C.
(1)
Max. Unit
9
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE (See Figures 4 through 26)
IDT723614L15 IDT723614L20 IDT723614L30
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
S Clock Frequency, CLKA or CLKB – 66.7 – 50 – 33.4 MHz
f
t
CLK Clock Cycle Time, CLKA or CLKB 15 – 20 – 30 – ns
CLKH Pulse Duration, CLKA and CLKB HIGH 6 – 8 – 12 – ns
t
CLKL Pulse Duration, CLKA and CLKB LOW 6 – 8 – 12 – ns
t
t
DS Setup Time, A0-A35 before CLKA↑ and B0-B35 4 –5–6–ns
before CLKB↑
ENS Setup Time,
t
CLKA↑;
t
SZS Setup Time, SIZ0, SIZ1,and
SWS Setup Time, SW0 and SW1 before CLKB↑ 5–7–8–ns
t
t
PGS Setup Time, ODD/
CLKA↑; ODD/
tRSTS Setup Time,
or CLKB↑
tFSS Setup Time, FS0 and FS1 before
DH Hold Time, A0-A35 after CLKA↑ and B0-B35 1 –1–1–ns
t
after CLKB↑
t
ENH Hold Time,
CLKA↑;
SZH Hold Time, SIZ0, SIZ1, and
t
SWH Hold Time, SW0 and SW1 after CLKB↑ 0–0–0–ns
t
t
PGH Hold Time, ODD/
ODD/
EVEN
tRSTH Hold Time,
t
FSH Hold Time, FS0 and FS1 after
(3)
SKEW1
t
t
SKEW2
Skew Time, between CLKA↑ and CLKB↑ 8–8–10–ns
for
EFA, EFB, FFA
(3)
Skew Time, between CLKA↑ and CLKB↑ 9–16–20–ns
for
AEA, AEB, AFA
CSA
, W/RA, ENA and MBA before 5 –5–6–ns
CSB
,W/RB and ENB before CLKB↑
BE
before CLKB↑ 4–5–6–ns
EVEN
and PGA before 4 –5–6–ns
EVEN
and PGB before CLKB↑
RST
(2)
CSB, W/R
LOW before CLKA↑ 5–6–7–ns
CSA
, W/RA, ENA and MBA after 1 –1–1–ns
B, and ENB after CLKB↑
BE
after CLKB↑ 2–2–2–ns
EVEN
and PGA after CLKA↑;0–0–0–ns
and PGB after CLKB↑
RST
LOW after CLKA↑ or CLKB↑
RST
, and
FFB
, and
AFB
(1)
RST
HIGH 5 –6–7–ns
(1)
(2)
5–6–7–ns
HIGH 4 –4–4–ns
NOTES:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
10
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
A Access Time, CLKA↑ to A0-A35 and CLKB↑ 210212215ns
t
to B0-B35
t
WFF Propagation Delay Time, CLKA↑ to
CLKB↑ to
REF Propagation Delay Time, CLKA↑ to
t
and CLKB↑ to
PAE Propagation Delay Time, CLKA↑ to
t
CLKB↑ to
t
PAF Propagation Delay Time, CLKA↑ to
CLKB↑ to
PMF Propagation Delay Time, CLKA↑ to
t
or
MBF2
MBF1
t
PMR Propagation Delay Time, CLKA↑ to B0-B35
and CLKB↑ to A0-A35
(3)
tPPE
t
MDV Propagation Delay Time, MBA to A0-A35 valid 1 11 1 11. 5 1 12 ns
Propagation delay time, CLKB↑ to
FFB
EFB
AEB
AFB
HIGH and CLKB↑ to
HIGH
(2)
and SIZ1, SIZ0 to B0-B35 valid
PDPE Propagation Delay Time, A0-A35 valid to
t
valid; B0-B35 valid to
t
POPE Propagation Delay Time, ODD/
and
PEFB
(4)
POPB
t
Propagation Delay Time, ODD/
PEFB
valid
bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)
PEPE Propagation Delay Time,
t
t
PEPB
MBA, or PGA to
SIZ0, or PGB to
(4)
Propagation Delay Time,
PEFA; CSB
PEFB
CSA
, ENB, W/RB, SIZ1,
CSA
MBA, or PGA to parity bits (A8, A17, A26, A35);
CSB,
ENB, W/RB,SIZ1, SIZ0, or PGB to parity
bits (B8, B17, B26, B35)
t
RSF Propagation Delay Time,
RST
HIGH
EN Enable Time,
t
active and
CSA
and W/RA LOW to A0-A35 2 10 2 12 2 14 ns
CSB
LOW and W/RB HIGH to
B0-B35 active
DIS Disable Time,
t
at high impedance and
CSA
or W/RA HIGH to A0-A35 1819111ns
CSB
HIGH or W/RB
LOW to B0-B35 at high impedance
FFA
and 2 10 2 12 2 15 ns
EFA
and 2 10 2 12 2 15 ns
AEA
and 2 10 2 12 2 15 ns
AFA
and 2 10 2 12 2 15 ns
MBF1
LOW 1 9 1 12 1 15 ns
MBF2
LOW or
PEFB
PEFA
EVEN
to
PEFA
EVEN
to parity 2 11 2 12 2 14 ns
, ENA,W/RA, 1 11 1 12 1 14 ns
, ENA, W/RA, 3 12 3 13 3 14 ns
to (
MBF1, MBF2
L = 30pF (See Figures 4 through 26)
IDT723614L15 IDT723614L20 IDT723614L30
(1)
311313315ns
211212213ns
310311313ns
311312314ns
) 1 15 1 20 1 30 ns
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when a new port B bus size is implemented by the rising CLKB edge.
4. Only applies when reading data from a mail register.
11
IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
A35—A27 A26—A18 A17—A9 A8—A0
BYTE ORDER ON PORT A:
BE
SIZ1 SIZ0
BE
X L L
BEBE SIZ1 SIZ0
L L H
AB
B35—B27 B26—B18 B17—B9 B8—B0
A
B35—B27 B26—B18 B17—B9 B8—B0
A
B35—B27 B26—B18 B17—B9 B8—B0
C
B
(a) LONG WORD SIZE
B
D
(b) WORD SIZE — BIG ENDIAN
C
C
COMMERCIAL TEMPERATURE RANGE
D
D
Write to FIFO1/
Read From FIFO2
Read from FIFO1/
Write to FIFO2
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
BE
SIZ1 SIZ0
BE
H L H
BEBE SIZ1 SIZ0
L H L
B35—B27 B26—B18 B17—B9 B8—B0
CD
B35—B27 B26—B18 B17—B9 B8—B0
AB
(c) WORD SIZE — LITTLE ENDIAN
B35—B27 B26—B18 B17—B9 B8—B0
A
B35—B27 B26—B18 B17—B9 B8—B0
B
B35—B27 B26—B18 B17—B9 B8—B0
C
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
3rd: Read from FIFO1/
Write to FIFO2
B35—B27 B26—B18 B17—B9 B8—B0
D
(d) BYTE SIZE — BIG ENDIAN
Figure 1. Dynamic Bus Sizing
4th: Read from FIFO1/
Write to FIFO2
3146 drw fig 01
12
Loading...