Integrated Device Technology Inc IDT723612L15PF, IDT723612L15PQF, IDT723612L20PF, IDT723612L20PQF, IDT723612L30PF Datasheet

Integrated Device Technology, Inc.

BiCMOS SyncBiFIFO
64 x 36 x 2

IDT723612

FEATURES:

• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)

• Two independent clocked FIFOs (64 x 36 storage
capacity each) buffering data in opposite directions

• Mailbox bypass Register for each FIFO

• Programmable Almost-Full and Almost-Empty Flags

• Microprocessor interface control logic

•

EFA, FFA, AEA

•

EFB, FFB, AEB

, and
, and

AFA

flags synchronized by CLKA

AFB

flags synchronized by CLKB

• Passive parity checking on each port

• Parity generation can be selected for each port

FUNCTIONAL BLOCK DIAGRAM

CLKA

RST

ODD/

EVEN

W/RA

Device

Control

CSA

ENA

MBA

Port-A

Control

Logic

Input

Register

Pointer

• Low-power advanced BiCMOS technology

• Supports clock frequencies up to 67 MHz

• Fast access times of 10ns

• Available in 132-pin plastic quad flat package (PQF) or
space-saving 120-pin thin quad flat package (TQFP)

• Industrial temperature range (-40oC to +85oC) is avail­able, tested to military electrical specifications

DESCRIPTION:

The IDT723612 is a monolithic high-speed, low-power
BiCMOS bi-directional clocked FIFO memory. It supports
clock frequencies up to 67 MHz and has read access times as

MBF1

Write

Mail 1

Register

64 x 36

SRAM

Pointer

Read

Parity

Gen/Check

Parity

Output

Generation

Register

PEFB

PGB

36

36

CLKB

CSB

W/RB
ENB
MBB

3136 drw 01

EFB
AEB

B0 - B36

FFB
AFB

FIFO2

Output

Status Flag

Logic

Programmable Flag

Offset Register

Read

Pointer

Parity

Register

Generation

FFA

AFA

FS0

FS1

A0 - A35

EFA
AEA

PGA

PEFA

MBF2

The IDT logo is a registered trademark and Sync BiFIFO is a trademark of Integrated Device Technology Inc.

36

FIFO1

Parity

Gen/Check

Status Flag

Logic

Write

Pointer

64 x 36

SRAM

Mail 2

Register

Input

Register

Port-B

Control

Logic

COMMERCIAL TEMPERATURE RANGE MAY 1997

1997 Integrated Device Technology, Inc. DSC-3136/4

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

1

IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

fast as 10ns. Two independent 64 x 36 dual-port SRAM
FIFOs on board the chip buffer data in opposite directions.
Each FIFO has flags to indicate empty and full conditions and
two programmable flags (almost-full and almost-empty) to
indicate when a selected number of words is stored in
memory. Communication between each port can bypass the
FIFOs via two 36-bit mailbox registers. Each mailbox register
has a flag to signal when new mail has been stored. Parity is
checked passively on each port and may be ignored if not
desired. Parity generation can be selected for data read from
each port. Two or more devices can be used in parallel to
create wider data paths.

The IDT723612 is a clocked FIFO, which means each port

employs a synchronous interface. All data transfers through

PIN CONFIGURATIONS

A

CC

GND

GND

A0
A1
A2

GND

A3
A4
A5
A6

VCC

A7
A8
A9

GND

A10
A11

VCC

A12
A13
A14

GND

A
A16
A17
A18
A19
A20

GND

A21
A22
A23

V

ENA

CLKA

W/

17161514131211

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

15

41
42
43
44
45
46
47
48
49
50

515253545556575859606162636465666768697071727374757677787980818283

MBA

PGA

10

FS1

987654321

a port are gated to the LOW-to-HIGH transition of a port clock
by enable signals. The clocks for each port are independent
of one another and can be asynchronous or coincident. The
enables for each port are arranged to provide a simple bi­directional interface between microprocessors and/or buses
with synchronous control.

The full flag (

FFA, FFB

) and almost-full (

AFA, AFB

a FIFO are two-stage synchronized to the port clock that writes
data to its array. The empty flag (
(

AEA, AEB

) flag of a FIFO are two stage synchronized to the

EFA, EFB

) and almost-empty

port clock that reads data from its array.

The IDT723612 is characterized for operation from 0°C to
70°C.

130

129

MBB

128

127

GND

126

125

PGB

124

VCC

123

W/ B

122

CLKB

ENB

121

120

119

118

117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

GND

B0
B1
B2
GND
B3
B4
B5
B6
VCC
B7
B8
B9
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23

FS0

ODD/

GND

NC

132

NCNCNC

131

*

) flag of

28

A24

VCC

Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.

*

A

A25

A26

A27

A29

A30

A31

VCC

GND

PQFP (PQ132-1, order code: PQF)

Note:

1. NC - No internal connection

2. Uses Yamaichi socket IC51-1324-828

A32

A33

GND

B35

A34

A35

B34

GND

TOP VIEW

B33

B32

GND

CC

B31

B30

VCC

B26

B29

B28

B27

B25

B24

V

GND

3136 drw 02

2

IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2

PIN CONFIGURATIONS (CONT.)

COMMERCIAL TEMPERATURE RANGE

A23
A22
A21

GND

A
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10

GND

A9
A8
A7

VCC

A6
A5
A4
A3

GND

A2
A1
A0

A24

120

A25

119

A26

118

VCC

117

A27

116

A28

115

A29

114

GND

A30A31

113

112

111

A32

110

A33

109

A34

108

A35

107

B35

GND

106

105

B34

104

B33

103

B32

102

B31

101

B30

100

GND

99

29

B

B28

B27

VCC

98979695949392

1
2
3
4

20

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

23

B26

B25

B24

B

91

B22

90

B21

89

GND

88

B20

87

B19

86

B18

85

B17

84

B16

83

B15

82

B14

81

B13

80

B12

79

B11

78

B10

77

GND

76

B9

75

B8

74

B7

73

VCC

72

B6

71

B5

70

B4

69

B3

68

GND

67

B2

66

B1

65

B0

64
63
62
61

Note:

1. NC - No internal connection

313233

34

353637

ENA

CLKA

A
W/

CC

V

39

38

PGA

40

41

4243444546

MBA

1

FS

FS0

47

NCNCNC

GND

484950

ODD/

TQFP (PN120-1, order code: PF)

TOP VIEW

NC

51

52

MBB

53545556575859

CC

V

PGB

W/ B

ENB

CLKB

60

3136 drw 03

3

IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol Name I/O Description

A0-A35 Port-A Data I/O 36-bit bidirectional data port for side A.

AEA

AEB Port-B Almost-Empty O Programmable almost-full flag synchronized to CLKB. It is LOW when the

AFA

AFB

B0-B35 Port-B Data. I/O 36-bit bidirectional data port for side B.

CLKA Port-A Clock I CLKA is a continuous clock that synchronizes all data transfers through port-

CLKB Port-B Clock I CLKB is a continuous clock that synchronizes all data transfers through port-

CSA

CSB

EFA

EFB

ENA Port-A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

ENB Port-B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

FFA

FFB

FS1, FS0 Flag-Offset Selects I The LOW-to-HIGH transition of

MBA Port-A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a port-A read or write

Almost-Empty Flag O Programmable almost-empty flag synchronized to CLKA. It is LOW when

(Port A) the number of words in the FIFO2 is less than or equal to the value in the

offset register, X.

Flag (PortB) number of words in FIFO1 is less than or equal to the value in the

offset register, X.

Port-A Almost-Full O Programmable almost-full flag synchronized to CLKA. It is LOW when the

Flag (Port A) number of empty locations in FIFO1 is less than or equal to the value in the

offset register, X.

Port-B Almost-Empty O Programmable almost-full flag synchronized to CLKB. It is LOW when the

Flag (Port B) number of empty locations in FIFO2 is less than or equal to the value in the

offset register, X.

A and can be aynchronous or coincident to CLKB.

EFA, FFA, AFA

, and

are synchronized to the LOW-to-HIGH transition of CLKA.

Port-A Chip Select I

B and can be asynchronous or coincident to CLKA.

AEB

are synchronized to the LOW-to-HIGH transition of CLKB.

CSA

must be LOW to enable a LOW-to-HIGH transition of CLKA to read or

EFB, FFB, AFB

, and

write data on port-A. The A0-A35 outputs are in the high-impedance state
when

CSA

is HIGH.

Port-B Chip Select I

B

must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B. The B0-B35 outputs are in the high-impedance state
when

CSB

is HIGH.

Port-A Empty Flag O

EFA

is synchronized to the LOW-to-HIGH transition of CLKA. When

EFA

(Port A) LOW, FIFO2 is empty, and reads from its memory are disabled. Data can

be read from FIFO2 to the output register when

EFA

is HIGH.

EFA

is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after data is loaded into empty FIFO2 memory.

Port-B Empty Flag O

EFB

is synchronized to the LOW-to-HIGH transition of CLKB. When

EFB

(Port B) LOW, the FIFO1 is empty, and reads from its memory are disabled. Data

can be read from FIFO1 to the output register when

EFB

is HIGH.

EFB

forced LOW when the device is reset and is set HIGH by the second LOW­to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.

write data on port-A.

write data on port-B.

Port-A Full Flag O

(Port A) LOW, FIFO1 is full, and writes to its memory are disabled.

FFA

is synchronized to the LOW-to-HIGH transition of CLKA. When

FFA

FFA

is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after reset.

Port-B Full Flag O

(Port B) LOW, FIFO2 is full, and writes to its memory are disabled.

FFB

is synchronized to the LOW-to-HIGH transition of CLKB. When

FFB

FFB

is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after reset.

RST

latches the values of FS0 and FS1,
which selects one of four preset values for the almost-full flag and almost­empty flag.

operation. When the A0-A35 outputs are active, a HIGH level on MBA
selects data from the mail2 register for output, and a LOW level selects
FIFO2 output register data for output.

AEA

is

is

is

is

is

4

IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONTINUED)

SYMBOL NAME I/O DESCRIPTION

MBB Port-B Mailbox I A HIGH level on MBB chooses a mailbox register for a port-B read or write

Select operation. When the B0-B35 outputs are active, a HIGH level on MBB selects

data from the mail1 register for output, and a LOW level selects FIFO1
output register data for output.

MBF1

MBF2

ODD/ Odd/Even Parity I Odd parity is checked on each port when ODD/

EVEN

PEFA

PEFB

PGA Port-A Parity I Parity is generated for data reads from port A when PGA is HIGH. Genera-

PGB Port-B Parity I Parity is generated for data reads from port B when PGB s HIGH. The type of

RST

W/RA Port-A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on

W/RB Port-B Write/Read I A HIGH selects a write operation and a LOW selects a read operation on

Mail1 Register Flag O

MBF1

is set LOW by a LOW-to-HIGH transition of CLKA that writes data to
the mail1 register. Writes to the mail1 register are inhibited while
LOW.
B read is selected and MBB is HIGH.

MBF1

is set HIGH by a LOW-to-HIGH transition of CLKB when a port-

MBF1

is set HIGH when the device is

MBF1

reset.

Mail2 Register Flag O

MBF2

is set LOW by a LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while
LOW.
A read is selected and MBA is HIGH.

MBF2

is set HIGH by a LOW-to-HIGH transition of CLKA when a port-

MBF2

is set HIGH when the device is

MBF2

reset.

EVEN

is HIGH, and even

Select parity is checked when ODD/

EVEN

is LOW. ODD/

EVEN

also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.

Port-A Parity Error O When any byte applied to terminals A0-A35 fails parity,

PEFA

is LOW.

Flag (Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the

most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/

EVEN

input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read with
parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH,
the

PEFA

flag is forcedHIGH regardless of the A0-A35 inputs.

Port-B Parity Error O When any byte applied to terminals B0-B35 fails parity,

PEFB

is LOW.

Flag (Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most

significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/

EVEN

input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected by PGB. Therefore, if a mail1 read with
parity generation is setup by having W/RB LOW, MBB HIGH, and PGB HIGH,
the

PEFB

flag is forced HIGH regardless of the state of the B0-B35 inputs.

tion The type of parity generated is selected by the state of the ODD/

EVEN

input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.

Generation parity generated is selected by the state of the ODD/

EVEN

input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.

Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-

HIGH transitions of CLKB must occur while

AFB, MBF1
FFB

flags LOW. The LOW-to-HIGH transition of

, and

MBF2

flags HIGH and the

RST

is LOW. This sets the

EFA, EFB, AEA, AEB, FFA,

RST

latches the status of the

and

FS1 and FS0 inouts to select almost-full and almost-empty flag offset.

Select port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the

high-impedance state when W/RA is HIGH.

Select port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the

high-impedance state when W/RB is HIGH.

is set

is set

AFA

,

5

IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)

Symbol Rating Commercial Unit

V

CC Supply Voltage Range -0.5 to 7 V

(2)

I

V

O

V
I

IK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA

OK Output Clamp Current, (VO < 0 or VO > VCC) ±50 mA

I
I

OUT Continuous Output Current, (VO = 0 to VCC) ±50 mA
CC Continuous Current Through VCC or GND ±500 mA

I

A Operating Free Air Temperature Range 0 to 70 °C

T
T

STG Storage Temperature Range -65 to 150 °C

Notes:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated condi­tions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

Input Voltage Range -0.5 to VCC+0.5 V

(2)

Output Voltage Range -0.5 to VCC+0.5 V

(2)

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 4.5 5.5 V

VIH HIGH Level Input Voltage 2 – V

VIL LOW-Level Input Voltage – 0.8 V

IOH HIGH-Level Output Current – -4 mA

IOL LOW-Level Output Current – 8 mA

TA Operating Free-air 0 70 °C

Temperature

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)

Parameter Test Conditions Min. Typ.

V

OH VCC = 4.5V, IOH = -4 mA 2.4 V
OL VCC = 4.5 V, IOL = 8 mA 0.5 V

V

LI VCC = 5.5 V, VI = VCC or 0 ±50 µA

I

I

LO VCC = 5.5 V, VO = VCC or 0 ±50 µA

CC VCC 5.5 V, IO = 0 mA, VI = VCC or GND 1 mA

I
C

IN VI= 0, f = 1 MHz 4 pF

OUT VO = 0, f = 1 MHZ 8 pF

C

(1)

Max. Unit

Note:

1. All typical values are at VCC = 5 V, TA = 25°C.

6

IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE

IDT723612L15 IDT723612L20 IDT723612L30

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

S Clock Frequency, CLKA or CLKB – 66.7 – 50 – 33.4 MHz

f
t

CLK Clock Cycle Time, CLKA or CLKB 15 – 20 – 30 – ns
CLKH Pulse Duration, CLKA and CLKB HIGH 6–8–12–ns

t

CLKL Pulse Duration, CLKA and CLKB LOW 6–8–12–ns

t
t

DS Setup Time, A0-A35 before CLKA↑ and B0-B35 4–5–6–ns

before CLKB↑

ENS1 Setup Time,

t

W/RB before CLKB↑

t

ENS2 Setup Time, ENA, before CLKA↑; ENB before 4–5–6–ns

CLKB↑

ENS3 Setup Time, MBA before CLKA↑: MBB before 4–5–6–ns

t

CLKB↑

t

PGS Setup Time, ODD/

CLKA↑; ODD/

tRSTS Setup Time,

or CLKB↑

tFSS Setup Time, FS0/FS1 before

DH Hold Time, A0-A35 after CLKA↑ and B0-B35 2.5 – 2.5 – 2.5 – ns

t

after CLKB↑

ENH1 Hold Time,

t

W/RB after CLKB↑

t

ENH2 Hold Time, ENA, after CLKA↑; ENB after CLKB↑ 2.5 – 2.5 – 2.5 – ns
ENH3 Hold Time, MBA after CLKA↑; MBB after CLKB↑ 1–1–1–ns

t
t

PGH Hold Time, ODD/

ODD/

EVEN

tRSTH Hold Time,

FSH Hold Time, FS0 and FS1 after

t

SKEW1

SKEW2

(3)

Skew Time, between CLKA↑ and CLKB↑ 8–8–10–ns
for

EFA, EFB, FFA

(3)

Skew Time, between CLKA↑ and CLKB↑ 9–16–20–ns
For

AEA, AEB, AFA

t

t

CSA

, W/RA before CLKA↑;

EVEN

and PGA before 4–5–6–ns

EVEN

and PGB before CLKB↑

RST

(2)

LOW before CLKA↑ 5–6–7–ns

RST

CSA

W/RA after CLKA↑;

EVEN

and PGA after CLKA↑;1–1–1–ns

and PGB after CLKB↑

RST

LOW after CLKA↑ or CLKB↑

RST

, and

FFB

, and

AFB

CSB

,6–6–7–ns

(1)

HIGH 5–6–7–ns

CSB

, 2–2–2–ns

(1)

(2)

5–6–7–ns

HIGH 4–4–4–ns

Notes:

1. Only applies for a clock edge that does a FIFO read.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relation­ship between CLKA cycle and CLKB cycle.

7

IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, C

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

A Access Time, CLKA↑ to A0-A35 and CLKB↑ 210212215ns

t

to B0-B35

WFF Propagation Delay Time, CLKA↑ to

t

CLKB↑ to

t

REF Propagation Delay Time, CLKA↑ to

and CLKB↑ to

PAE Propagation Delay Time, CLKA↑ to

t

CLKB↑ to

t

PAF Propagation Delay Time, CLKA↑ to

CLKB↑ to

PMF Propagation Delay Time, CLKA↑ to

t

or

MBF2

MBF1

t

PMR Propagation Delay Time, CLKA↑ to B0-B35

and CLKB↑ to A0-A35

FFB

EFB

AEB

AFB

HIGH and CLKB↑ to

HIGH

(2)

tMDV Propagation Delay Time, MBA to A0-A35 valid 1 11 1 11.5 1 12 ns

and MBB to B0-B35 valid

PDPE Propagation Delay Time, A0-A35 valid to

t

valid; B0-B35 valid to

t

POPE Propagation Delay Time, ODD/

and

PEFB

(3)

POPB

t

Propagation Delay Time, ODD/

PEFB

valid

bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)

t

PEPE Propagation Delay Time, W/

PEPB

t

PGA to

(3)

Propagation Delay Time, W/RA,

PEFA

; W/RB,

R

A,

CSB

, ENB. MBB, PGB to

PGA to parity bits (A8, A17, A26, A35); W/RB,
ENB. MBB or PGB to parity bits (B8, B17, B26, B35)

t

RSF Propagation Delay Time,

LOW and (

EN Enable Time,

t

active and

AFA, AFB, MBF1, MBF2

CSA

and W/RA LOW to A0-A35 2 10 2 12 2 14 ns

CSB

LOW and W/RB HIGH to

RST

B0-B35 active

t

DIS Disable Time,

at high impedance and

CSA

or W/RA HIGH to A0-A35 1 819111ns

CSB

HIGH or W/RB

LOW to B0-B35 at high impedance

FFA

and 210212215ns

EFA

and 210212215ns

AEA

and 210212215ns

AFA

and 210212215ns

MBF1

LOW 1 9 1 12 1 15 ns

MBF2

LOW or

PEFA

EVEN

to

PEFA

EVEN

to parity 2 11 2 12 2 14 ns

CSA

, ENA, MBA or 1 11 1 12 1 14 ns

CSA

, ENA, MBA or 3 12 3 13 3 14 ns

CSB

to (

AEA, AEB

) HIGH

L = 30pF

IDT723612L15 IDT723612L20 IDT723612L30

(1)

311313315ns

310311313ns

311312314ns

PEFB

,

) 1 15 1 20 1 30 ns

Notes:

1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.

2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.

3. Only applies when reading data from a mail register.

8

IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

SIGNAL DESCRIPTIONS

RESET

The IDT723612 is reset by taking the reset (
LOW for at least four port-A clock (CLKA) and four port-B clock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of each FIFO and forces the
full flags (
the almost-empty flags (
flags (
(

MBF1, MBF2

LOW-to-HIGH transitions of CLKA and

FFA, FFB

AFA, AFB

) HIGH. After a reset,

) LOW, the empty flags (

AEA, AEB

) LOW and the almost-full

) HIGH. A reset also forces the mailbox flags

FFA

is set HIGH after two

FFB

two LOW-to-HIGH transitions of CLKB. The device must be
reset after power up before data is written to its memory.

ALMOST-FULL AND

FS1 FS0

RST

RST

ALMOST-EMPTY FLAG
OFFSET REGISTER (X)

HH↑ 16
HL↑ 12

LH↑ 8
LL↑ 4

Table 1. Flag Programming

RST

) input

EFA, EFB

) LOW,

is set HIGH after

A LOW-to-HIGH transition on the

RST

input loads the
almost-full and almost-empty registers (X) with the values
selected by the flag-select (FS0, FS1) inputs. The values that
can be loaded into the registers are shown in Table 1.

FIFO WRITE/READ OPERATION

The state of port-A data A0-A35 outputs is controlled by

the port-A chip select (

CSA

) and the port-A write/read select
(W/RA). The A0-A35 outputs are in the high-impedance state
when either
active when both

CSA

or W/RA is HIGH. The A0-A35 outputs are

CSA

and W/RA are LOW.

Data is loaded into FIFO1 from the A0-A35 inputs on a
LOW-to-HIGH transition of CLKA when
HIGH, ENA is HIGH, MBA is LOW, and

CSA

is LOW, W/RA is

FFA

is HIGH. Data is
read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH
transition of CLKA when
HIGH, MBA is LOW, and

CSA

is LOW, W/RA is LOW, ENA is

EFA

is HIGH (see Table 2).

The port-B control signals are identical to those of port A.
The state of the port-B data (B0-B35) outputs is controlled by
the port-B chip select (

CSB

) and the port-B write/read select
(W/RB). The B0-B35 outputs are in the high-impedance state
when either
active when both

CSB

or W/RB is HIGH. The B0-B35 outputs are

CSB

and W/RB are LOW.

Data is loaded into FIFO2 from the B0-B35 inputs on a
LOW-to-HIGH transition of CLKB when
HIGH, ENB is HIGH, MBB is LOW, and

CSB

is LOW, W/RB is

FFB

is HIGH. Data is

read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH

CSA

CSA

W/

RRA ENA MBA CLKA A0-A35 Outputs Port Functions

H X X X X In High-Impedance State None

L H L X X In High-Impedance State None
LHHL↑ In High-Impedance State FIFO1 Write
LHHH↑ In High-Impedance State Mail1 Write
L L L L X Active, FIFO2 Output Register None
LLHL↑Active, FIFO2 Output Register FIFO2 Read
L L L H X Active, Mail2 Register None
LLHH↑ Active, Mail2 Register Mail2 Read (Set

Table 2. Port-A Enable Function Table

CSB

CSB

W/

RRB ENB MBB CLKB B0-B35 Outputs Port Functions

H X X X X In High-Impedance State None

L H L X X In High-Impedance State None
LHHL↑ In High-Impedance State FIFO2 Write
LHHH↑ In High-Impedance State Mail2 Write
L L L L X Active, FIFO1 Output Register None
LLHL↑Active, FIFO1 Output Register FIFO1 read
L L L H X Active, Mail1 Register None
LLHH↑ Active, Mail1 Register Mail1 Read (Set

MBF2

MBF1

HIGH)

HIGH)

Table 3. Port-B Enable Function Table

9