Integrated Device Technology Inc IDT723611L15PF, IDT723611L15PQF, IDT723611L20PF, IDT723611L20PQF, IDT723611L30PF Datasheet
...
Integrated Device Technology, Inc.
FEATURES:
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
• 64 x 36 storage capacity
• Synchronous data buffering from Port A to Port B
• Mailbox bypass register in each direction
• Programmable Almost-Full (AF) and Almost-Empty (AE)
flags
• Microprocessor Interface Control Logic
• Full Flag (FF) and Almost-Full (AF) flags synchronized by
CLKA
• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
• Supports clock frequencies up to 67MHz
COMMERCIAL TEMPERATURE RANGE MAY 1997
1997 Integrated Device Technology, Inc. DSC-3024/4
IDT723611
CMOS SyncFIFO
64 x 36
• Fast access times of 10ns
• Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
• Low-power advanced CMOS technology
• Industrial temperature range (-40oC to +85oC) is available, tested to military elecrical specifications
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power,
CMOS Synchronous (clocked) FIFO memory which supports
clock frequencies up to 67MHz and has read access times as
fast as 10ns. The 64 x 36 dual-port FIFO buffers data from Port
A to Port B. The FIFO has flags to indicate empty and full
conditions, and two programmable flags, Almost-Full (AF) and
Almost-Empty (AE), to indicate when a selected number of
words is stored in memory. Communication between each
port can take place through two 36-bit mailbox registers. Each
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Reset
Logic
RST
PEFA
MBF2
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
EF
AE
36
B0 - B35
FF
AF
FS
0
FS1
3024 drw 01
Programmable
Flag Offset
Registers
A0 - A35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
PGA
Parity
Gen/Check
PGB
PEFB
36
64 x 36
SRAM
•
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
1
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
2
IDT723611 CMOS SyncFIFO
64 x 36 COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
chronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The Full-Flag (FF) and Almost-Full (AF) flag of the FIFO are
two-stage synchronized to the port clock that writes data into
its array (CLKA). The Empty Flag (EF) and Almost-Empty (AE)
flag of the FIFO are two-stage synchronized to the port clock
that reads data from its array.
The IDT723611 is characterized for operation from 0°C to
70°C.
mailbox register has a flag to signal when new mail has been
stored. Parity is checked passively on each port and may be
ignored if not desired. Parity generation can be selected for
data read from each port. Two or more devices may be used
in parallel to create wider data paths.
The IDT723611 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data
transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asyn-
Note:
1. NC = No internal connection
TQFP (PN120-1, order code: PF)
TOP VIEW
PIN CONFIGURATION
3024 drw 02
A23
A22
A21
GND
A
20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A
9
A8
A7
VCC
A6
A5
A4
A3
GND
A
2
A1
A0
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
22
B21
GND
B
20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B
9
B8
B7
VCC
B6
B5
B4
B3
GND
B
2
B1
B0
EF
AE
NC
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AF
FF
CSA
ENA
CLKA
W/
R
A
V
CC
PGA
PEFA
MBF2
MBA
FS
1FS0
ODD/
EVEN
RST
GND
NCNCNC
NC
MBB
MBF1
PEFB
PGB
V
CC
W/
R
B
CLKB
ENB
CSB
NC
31
32333435363738
39
40
41424344454647
48
495051
52
53545556575859
60
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99989796959493
92
B
23
A
24A25A26
VCCA27A28A29GND
A30A31A34A35B
35
GND
B
34B33
B32B30B31GND
B29B28B27VCCB26B25B
24
A32A
33
IDT723611 CMOS SyncFIFO
64 x 36 COMMERCIAL TEMPERATURE RANGES
3
PIN CONFIGURATION (CONTINUED)
PQFP (PQ132-1, order code: PQF)
TOP VIEW
*
*
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
GND
AE
EF
B
0
B1
B2
GND
B
3
B4
B5
B6
VCC
B7
B8
B9
GND
B
10
B11
VCC
B12
B13
B14
GND
B
15
B16
B17
B18
B19
B20
GND
B
21
B22
B23
GND
NC
NC
A
0
A1
A2
GND
A
3
A4
A5
A6
VCC
A7
A8
A9
GND
A
10
A11
VCC
A12
A13
A14
GND
A
15
A16
A17
A18
A19
A20
GND
A
21
A22
A23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3024 drw 03
117
17161514131211
10
987654321
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
V
CC
VCC
A24
A25
A26
A27
GND
A
28
A29
VCC
A30
A31
A32
GND
A
33
A34
A35
GND
B
35
B34
B33
GND
B
32
B31
B30
VCC
B29
B28
B27
GND
B
26
B25
B24
515253545556575859606162636465666768697071727374757677787980818283
NC
AF
FF
CSA
ENA
CLKA
W/
R
A
V
CC
PGA
FS0ODD/
EVEN
FS
1
PEFA
MBF2
RST
NC
GND
NCNCNC
MBF1
GND
PEFB
V
CC
W/
R
B
CLKB
ENB
CSB
NC
GND
MBA
MBB
PGB
4
IDT723611 CMOS SyncFIFO
64 x 36 COMMERCIAL TEMPERATURE RANGES
Symbol Name I/O Description
A0-A35 Port-A Data I/O 36-bit bidirectional data port for side A.
AE
Almost-Empty Flag O Programmable almost-empty flag synchronized to CLKB. It is LOW when
the number of words in the FIFO is less than or equal to the value in the offset
register, X.
AF
Almost-Full Flag. O Programmable almost-full flag synchronized to CLKA. It is LOW when the
number of empty locations in the FIFO is less than or equal to the value in the
offset register, X.
B0-B35 Port-B Data. I/O 36-bit bidirectional data port for side B.
CLKA Port-A Clock I CLKA is a continuous clock that synchronizes all data transfers through port-A
and can be aynchronous or coincident to CLKB. FF and AF are synchronized
to the LOW-to-HIGH transition of CLKA.
CLKB Port-B Clock I CLKB is a continuous clock that synchronizes all data transfers through port-B
and can be asynchronous or coincident to CLKA. EF and AE are synchronized
to the LOW-to-HIGH transition of CLKB.
CSA
Port-A Chip Select I
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A. The A0-A35 outputs are in the high-impedance state
when
CSA
is HIGH.
CSB
Port-B Chip Select I
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B. The B0-B35 outputs are in the high-impedance state
when
CSB
is HIGH.
EF
Empty Flag O
EF
is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW,
the FIFO is empty, and reads from its memory are disabled. Data can be read
from the FIFO to its output register when EF is HIGH. EF is forced LOW when
the device is reset and is set HIGH by the second LOW-to-HIGH transition of
CLKB after data is loaded into empty FIFO memory.
ENA Port-A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A.
ENB Port-B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B.
FF
Full Flag O
FF
is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW,
the FIFO is full, and writes to its memory are disabled. FF is forced LOW when
the device is reset and is set HIGH by the second LOW-to-HIGH transition of
CLKA after reset.
FS1, FS0 Flag-Offset Selects I The LOW-to-HIGH transition of
RST
latches the values of FS0 and FS1,
which loads one of four preset values into the almost-full and almost-empty
offset register (X).
MBA Port-A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a port-A read or write
operation.
MBB Port-B Mailbox Select I A HIGH level on MBB chooses a mailbox register for a port-B read or write
operation. When the B0-B35 outputs are active, a HIGH level on MBB selects
data from the mail1 register for output, and a LOW level selects the FIFO
output register data for output.
MBF1
Mail1 Register Flag O
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to
the mail1 register. Writes to the mail1 register are inhibited while
MBF1
is set
LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B
read is selected and MBB is HIGH.
MBF1
is set HIGH when the device is
reset.
PIN DESCRIPTION
IDT723611 CMOS SyncFIFO
64 x 36 COMMERCIAL TEMPERATURE RANGES
5
PIN DESCRIPTION (CONTINUED)
Symbol Name I/O Description
MBF2
Mail2 Register Flag O
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while
MBF2
is
LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA when a port-
A read is selected and MBA is HIGH.
MBF2
is set HIGH when the device is
reset.
ODD/ Odd/Even Parity I Odd parity is checked on each port when ODD/
EVEN
is HIGH, and even
EVEN
Select parity is checked when ODD/
EVEN
is LOW. ODD/
EVEN
also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
PEFA
Port-A Parity Error O When any byte applied to terminals A0-A35 fails parity,
PEFA
is LOW.
Flag (Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the
most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/
EVEN
input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read with
parity generation is setup by having
CSA
LOW, ENA HIGH, W/RA LOW, MBA
HIGH, and PGA HIGH, the
PEFA
flag is forced HIGH regardless of the state of
A0-A35 inputs.
PEFB
Port-B Parity Error O When any byte applied to terminals B0-B35 fails parity,
PEFB
is LOW.
Flag (Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35, with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/
EVEN
input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected by PGB. Therefore, if a mail1 read with
parity generation is setup by having
CSB
LOW, ENB HIGH, W/RB LOW,
MBB HIGH, and PGB HIGH, the
PEFB
flag is forced HIGH regardless of the
state of the B0-B35 inputs
PGA Port-A Parity I Parity is generated for mail2 register reads from port A when PGA is HIGH.
Generation The type of parity generated is selected by the state of the ODD/
EVEN
input.
Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte.
PGB Port-B Parity I Parity is generated for data reads from port B when PGB is HIGH. The type
Generation of parity generated is selected by the state of the ODD/
EVEN
input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
RST
Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while
RST
is LOW. This sets the AF,
MBF1
, and
MBF2
flags HIGH and the EF, AE, and FF flags LOW. The LOW-
to-HIGH transition of
RST
latches the status of the FS1 and FS0 inputs to
select almost-full and almost-empty flag offset.
W/RA Port-A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on
Select port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
W/RB Port-B Write/Read I A HIGH selects a write operation and a LOW selects a read operation on
Select port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is HIGH.
6
IDT723611 CMOS SyncFIFO
64 x 36 COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
(1)
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
Symbol Rating Commercial Unit
V
CC Supply Voltage Range -0.5 to 7 V
V
I
(2)
Input Voltage Range -0.5 to VCC+0.5 V
V
O
(2)
Output Voltage Range -0.5 to VCC+0.5 V
I
IK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA
I
OK Output Clamp Current, (VO = < 0 or VO > VCC) ±50 mA
I
OUT Continuous Output Current, (VO = 0 to VCC) ±50 mA
I
CC Continuous Current Through VCC or GND ±500 mA
T
A Operating Free Air Temperature Range 0 to 70 °C
T
STG Storage Temperature Range -65 to 150 °C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter Test Conditions Min. Typ.
(1)
Max. Unit
V
OH VCC = 4.5V, IOH = -4 mA 2.4 V
V
OL VCC = 4.5 V, IOL = 8 mA 0.5 V
I
LI VCC = 5.5 V, VI = VCC or 0 ±50 µA
I
LO VCC = 5.5 V, VO = VCC or 0 ±50 µA
I
CC VCC = 5.5 V, IO = 0 mA, VI = VCC or GND Outputs HIGH 60 mA
Outputs LOW 130
Outputs Disabled 60
CIN VI = 0, f = 1 MHz 4 pF
C
OUT VO = 0, f = 1 MHZ 8 pF
Notes:
1. All typical values are at VCC = 5 V, TA = 25°C.
Symbol Parameter Min. Max. Unit
V
CC Supply Voltage 4.5 5.5 V
V
IH High-Level Input Voltage 2 V
V
IL Low-Level Input Voltage 0.8 V
I
OH High-Level Output Current -4 mA
I
OL Low-Level Output Current 8 mA
T
A Operating Free-Air 0 70 °C
Temperature
RECOMMENDED OPERATING CONDITIONS
Loading...