Integrated Device Technology Inc IDT72265L15TF, IDT72265L15TFB, IDT72265L20G, IDT72265L20PF, IDT72265L20TF Datasheet

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1997

1997 Integrated Device Technology, Inc DSC-3037/7

1

Integrated Device Technology, Inc.

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

FUNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

8,192 x 18

16,384 x 18

•

•

•

•

FLAG

LOGIC

FF/IR

PAF

EF/OR

PAE

HF

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WEN

WCLK

D

0-D17

LD

MRS

REN

RCLK

OE

Q

0-Q17

•

•

•

•

TIMING

FS

OFFSET REGISTER

•

PRS

FWFT/SI

SEN

RT

3037 drw 01

IDT72255
IDT72265

CMOS SUPERSYNC FIFO
8,192 x 18, 16,384 x 18

FEATURES:

• 8,192 x 18-bit storage capacity (IDT72255)

• 16,384 x 18-bit storage capacity (IDT72265)

• 10ns read/write cycle time (8ns access time)

• Retransmit Capability

• Auto power down reduces power consumption

• Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings

• Empty, Full and Half-full flags signal FIFO status

• Programmable Almost Empty and Almost Full flags, each
flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or

First Word Fall Through timing (using OR and IR flags)

• Easily expandable in depth and width

• Independent read and write clocks (permit simultaneous
reading and writing with one clock signal)

• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64­pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)

• Output enable puts data outputs into high impedance

• High-performance submicron CMOS technology

• Industrial temperature range (-40

o

C to +85oC) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT72255/72265 are monolithic, CMOS, high capac­ity, high speed, low power First-In, First-Out (FIFO) memories
with clocked read and write controls. These FIFOs are appli­cable for a wide variety of data buffering needs, such as optical
disk controllers, local area networks (LANs), and inter-proces­sor communication.

Both FIFOs have an 18-bit input port (Dn) and an 18-bit
output port (Qn). The input port is controlled by a free-running
clock (WCLK) and a data input enable pin (

WEN

). Data is

written into the synchronous FIFO on every clock when

WEN

is asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (

REN

). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output enable
pin (OE) is provided on the read port for three-state control of
the outputs.

The IDT72255/72265 have two modes of operation: In the

IDT Standard Mode

, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the

First Word Fall Through Mode

(FWFT), the first word written to an empty FIFO appears

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

2

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18

automatically on the outputs, no read operation required. The
state of the FWFT/SI pin during Master Reset determines the
mode in use.

The IDT72255/72265 FIFOs have five flag functions, EF/

OR

(Empty Flag or Output Ready), FF/IR (Full Flag or Input
Ready), and HF (Half-full Flag). The EF and FF functions are
selected in the IDT Standard Mode.

The IR and OR functions are selected in the First Word Fall
Through Mode. IR indicates that the FIFO has free space to
receive data. OR indicates that data contained in the FIFO is
available for reading.

HF

is a flag whose threshold is fixed at the half-way point in

memory. This flag can always be used irrespective of mode.

PAE, PAF

can be programmed independantly to any point
in memory. They, also, can be used irrespective of mode.
Programmable offsets determine the flag threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, such that

PAE

can be set at

127 or 1023 locations from the empty boundary and the

PAF

threshold can be set at 127 or 1023 locations from the full
boundary. All these choices are made with LD during Master
Reset

.

In the serial method, SEN

together with LD are used to load
the offset registers via the Serial Input (SI). In the parallel
method,

WEN

together with LD can be used to load the offset

registers via Dn.

REN

together with LD can be used to read the
offsets in parallel from Qn regardless of whether serial or
parallel offset loading is selected.

During Master Reset (

MRS

), the read and write pointers are
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The LD pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.

The Partial Reset (

PRS

) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly.

PRS

is

useful for resetting a device in mid-operation, when repro-

TQFP (PN64-1, order code: PF)

STQFP (PP64-1, order code: TF)

TOP VIEW

PIN 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

FS

V

CC

GND

D17
D16
D15
D14
D13
D12
D11
D10

D9
D8
D7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q17
Q16
GND
Q15
Q14
V

CC

Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND

WCLK

FWFT/SI

GND

/

V

CC

/

RCLK

Q5

Q4

V

CC

Q3

Q2

GND

Q1

Q0

GND

D0

D1

D2

D3

D4

D5

D6

3037 drw 02

PIN CONFIGURATIONS

3

IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

gramming offset registers may not be convenient.

The Retransmit function allows the read pointer to be reset
to the first location in the RAM array. It is synchronized to
RCLK when RT is LOW. This feature is convenient for

sending the same data more than once.

If, at any time, the FIFO is not actively performing a function,
the chip will automatically power down. This occurs if neither
a read nor a write occurs within 10 cycles of the faster clock,
RCLK or WCLK. During the Power Down state, supply current
consumption (ICC2) is at a minimum. Initiating any operation
(by activating control inputs) will immediately take the device

out of the Power Down state.

The IDT72255/72265 are depth expandable. The addition

of external components is unnecessary. The IR and

OR

functions, together with

REN

and

WEN

, are used to extend the

total FIFO memory capacity.

The FS line ensures optimal data flow through the FIFO. It
is tied to GND if the RCLK frequency is higher than the WCLK
frequency or to Vcc if the RCLK frequency is lower than the
WCLK frequency

The IDT72255/72265 is fabricated using IDT’s high speed
submicron CMOS technology.

PGA (G68-1, order code: G)

TOP VIEW

NOTES:

1. DNC = Do not connect

D8

Pin 1 Designator

ABCDEFGHJ KL

Q0 D2

PAF

DNC

VCC

RCLK

RENOE

GND

DNC

MRS

LD

WCLK

PRS

V

CC

WEN

D

17

GND

D

15

D16

D11

D14

D12

D10

D9

D7D6

PAE

D

4

D3D1

D0

Q1

Q2

GND

Q

3Q4 GND

Q

8 Q7

Q10

DNC

GND

V

CC

Q17

Q16

Q15

Q14

Q13 Q12

Q9

HF

EF

/

OR

FF

/

IR

11

10

09

08

07

06

05

04

03

02

01

RT

FWFT/

SI

D13

D5GND

V

CC

GND

Q

11

Q6

Q5

3037 drw 03

SEN

FS

GND

PIN CONFIGURATIONS (CONT.)

4

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18

Symbol Name I/O Description

D

0–D17 Data Inputs I Data inputs for a 18-bit bus.

MRS

Master Reset I

MRS

initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard Mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.

PRS

Partial Reset I

PRS

initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.

RT

Retransmit I Allows data to be resent starting with the first location of FIFO memory.

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode.

Through/Serial In After Master Reset, this pin functions as a serial input for loading offset registers

WCLK Write Clock I When enabled by

WEN

, the rising edge of WCLK writes data into the FIFO and

offsets into the programmable registers.

WEN

Write Enable I

WEN

enables WCLK for writing data into the FIFO memory and offset registers.

RCLK Read Clock I When enabled by

REN

, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

REN

Read Enable I

REN

enables RCLK for reading data from the FIFO memory and offset registers.

OE

Output Enable I OE controls the output impedance of Q

n

SEN

Serial Enable I

SEN

enables serial loading of programmable flag offsets

LD

Load I During Master Reset, LD selects one of two partial flag default offsets (127 and

1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.

FS Frequency Select I The FS setting optimizes data flow through the FIFO.

FF/IR

Full Flag/ O In the IDT Standard Mode, the FF function is selected. FF indicates whether or
Input Ready not the FIFO memory is full. In the FWFT mode, the IR function is selected.

IR

indicates whether or not there is space available for writing to the FIFO memory.

EF/OR

Empty Flag/ O In the IDT Standard Mode, the EF function is selected.

EF

indicates whether or

Output Ready not the FIFO memory is empty. In FWFT mode, the OR function is selected.

OR

indicates whether or not there is valid data available at the outputs.

PAF

Programmable O

PAF

goes HIGH if the number of free locations in the FIFO memory is more than

Almost Full Flag offset m which is stored in the Full Offset register.

PAF

goes LOW if the num-

ber of free locations in the FIFO memory is less than m.

PAE

Programmable O

PAE

goes LOW if the number of words in the FIFO memory is less than offset n

Almost Empty which is stored in theEmpty Offset register.

PAE

goes HIGH if the number of

Flag words in the FIFO memory is greater than offset n.

HF

Half-full Flag O

HF

indicates whether the FIFO memory is more or less than half-full.

Q

0–Q17 Data Outputs O Data outputs for a 18-bit bus.

V

CC Power +5 volt power supply pins.

GND Ground Ground pins.

PIN DESCRIPTION

3037 tbl 01

5

IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC
OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CCM Military Supply 4.5 5.0 5.5 V

Voltage

V

CCC Commercial Supply 4.5 5.0 5.5 V

Voltage

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.0 — — V

Commercial

V

IH Input High Voltage 2.2 — — V

Military

V

IL

(1)

Input Low Voltage — — 0.8 V
Commercial & Military

NOTE: 3037 tbl 03

1. 1.5V undershoots are allowed for 10ns once per cycle.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

V

TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with respect to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature Under –55 to +125 –65 to +135 °C

Bias

T

STG Storage –55 to +125 –65 to +155 °C

Temperature

I

OUT DC Output Current 50 50 mA

NOTE: 3037 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maimum rating conditions for extended periods may
affect reliabilty.

DT72255L IDT72255L

IDT72265L IDT72265L

Commercial Military

t

CLK = 10, 12,15, 20ns tCLK = 15, 25ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

I

LI

(1)

Input Leakage Current (any input) –1 — 1 –10 — 10 µA

I

LO

(2)

Output Leakage Current –10 — 10 –10 — 10 µA

V

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V

V

OL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V

I

CC1

(3)

Active Power Supply Current — — 180 — — 250 mA

I

CC2

(3,4)

Power Down Current (All inputs = VCC - 0.2V or — — 15 — — 25 mA
GND + 0.2V, RCLK and WCLK are free-running)

NOTES:

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. OE = V

IH

3. Tested at f = 20 MHz with outputs unloaded.

4. No data written or read for more than 10 cycles

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

NOTES:

1. With output deselected, (OE=HIGH).

2. Characterized values, not currently tested.

Symbol Parameter

(1)

Conditions Max. Unit

C

IN

(2)

Input VIN = 0V 10 pF
Capacitance

C

OUT

(1,2)

Output VOUT = 0V 10 pF
Capacitance

3037 tbl 05

CAPACITANCE (TA = +25°C, f = 1.0MHz)

3037 tbl 04

6

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

3037 tbl 06

Commercial Com'l & Mil. Commercial Military

72255L10 72255L12 72255L15 72255L20 72255L25
72265L10 72265L12 72265L15 72265L20 72265L25

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

f

S Clock Cycle Frequency — 100 — 83.3 — 66.7 — 50 — 40 MHz

t

A Data Access Time 2 8 2 9 2 10 2 12 3 15 ns

t

CLK Clock Cycle Time 10 — 12 — 15 — 20 — 25 — ns

t

CLKH Clock High Time 4.5 — 5 — 6 — 8 — 10 — ns

t

CLKL Clock Low Time 4.5

(2)

—5

(2)

—6

(2)

—8 —10—ns

t

DS Data Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns

t

DH Data Hold Time 0 — 0 — 1 — 1 — 1 — ns

t

ENS Enable Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns

t

ENH Enable Hold Time 0 — 0 — 1 — 1 — 1 — ns

t

LDS Load Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns

t

LDH Load Hold Time 6.5 — 8.5 — 10 — 10 — 10 — ns

t

RS Reset Pulse Width

(3)

10 — 12 — 15 — 20 — 25 — ns

t

RSS Reset Set-up Time 10 — 12 — 15 — 20 — 25 — ns

t

RSR Reset Recovery Time 10 — 12 — 15 — 20 — 25 — ns

t

RSF Reset to Flag and Output Time — 10 — 12 — 15 — 20 — 25 ns

t

FWFT Mode Select Time 0 — 0 — 0 — 0 — 0 — ns

t

RTS Retransmit Set-Up Time 3.5 — 3.5 — 4 — 5 — 6 — ns

t

OLZ Output Enable to Output in Low Z

(4)

0—0—0—0 —0 —ns

t

OE Output Enable to Output Valid 3 7 3 7.5 3 8 3 10 3 13 ns

t

OHZ Output Enable to Output in High Z

(4)

3 7 3 7.5 3 8 3 10 3 13 ns

t

WFF Write Clock to

FF

or

IR

—8—9—10—12—15ns

t

REF Read Clock to

EF

or

OR

—8—9—10—12—15ns

t

PAF Write Clock to

PAF

– 8—9—10—12—15ns

t

PAE Read Clock to

PAE

—8—9—10—12—15ns

t

HF Clock to

HF

— 16 — 18 — 20 — 22 — 25 ns

t

SKEW1 Skew time between RCLK and WCLK 8 — 10 — 12 — 15 — 20 — ns

for FF and

IR

t

SKEW2 Skew time between RCLK and 15 — 18 — 21 — 25 — 35 — ns

WCLK for

PAE

and

PAF

NOTES:

1. All AC timings apply to both Standard IDT Mode and First Word Fall
Through Mode.

2. For the RCLK line: t

CLKL (min.) = 7 ns only when reading the offsets from

the programmable flag registers; otherwise, use the table value. For the
WCLK line, use the t

CLKL (min.) value given in the table.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

3037 tbl 08

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

See Figure 1

AC TEST CONDITIONS

Figure 1. Output Load

* Includes jig and scope capacitances.

3037 drw 04

1.1K

30pF*

680Ω

5V

D.U.T.

1.5V

1.5V

3ns

7

IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS:

INPUTS:
DATA IN (D

0 - D17)

Data inputs for 18-bit wide data.

CONTROLS:
MASTER RESET (

MRS

MRS

)

A Master Reset is accomplished whenever the Master

Reset (

MRS

) input is taken to a LOW state. This operation sets
the internal read and write pointers to the first location of the
RAM array.

PAE

will go LOW,

PAF

will go HIGH, and HF will

go HIGH.

If FWFT is LOW during Master Reset then the IDT Standard

Mode, along with EF and FF are selected. EF will go LOW and

FF

will go HIGH. If FWFT is HIGH, then the First Word Fall

through Mode (FWFT), along with IR and OR, are selected.

OR

will go HIGH and IR will go LOW.

If LD is LOW during Master Reset, then

PAE

is assigned a

threshold 127 words from the empty boundary and

PAF

is
assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.

If LD is HIGH during Master Reset, then

PAE

is assigned a

threshold 1023 words from the empty boundary and

PAF

is
assigned a threshold 1023 words from the full boundary;
1023 words corresponds to an offset value of 3FFH. Following
Master Reset, serial loading of the offsets is permitted, but not
parallel loading.

Regardless of whether serial or parallel offset loading has
been selected, parallel reading of the registers is always
permitted. (See section describing the LD line for further
details).

During a Master Reset, the output register is initialized to
all zeroes. A Master Reset is required after power up, before
a write operation can take place.

MRS

is asynchronous.

PARTIAL RESET (

PRS

PRS

)

A Partial Reset is accomplished whenever the Partial
Reset (

PRS

) input is taken to a LOW state. As in the case of
the Master Reset, the internal read and write pointers are set
to the first location of the RAM array,

PAE

goes LOW,

PAF

goes HIGH, and HF goes HIGH.

Whichever mode is active at the time of partial reset, IDT
Standard Mode or First Word Fall-through, that mode will
remain selected. If the IDT Standard Mode is active, then

FF

will go HIGH and EF will go LOW. If the First word Fall-through
Mode is active, then OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset regis­ters remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes.

PRS

is asynchronous.

A Partial Reset is useful for resetting the device during the
course of operation, when reprogramming flag settings may
not be convenient.

RETRANSMIT (

RTRT)

The Retransmit operation allows data that has already
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.

Retransmit Setup is initiated by holding RT LOW during a
rising RCLK edge.

REN

and

WEN

must be HIGH before
bringing RT LOW. At least one word, but no more than Full ­2 words should have been written into the FIFO between
Reset (Master or Partial) and the time of Retransmit Setup
(Full = 8,192 words for the 72255, 16,384 words for the

72265).

If IDT Standard mode is selected, the FIFO will mark the
beginning of the Retransmit Setup by setting EF LOW. The
change in level will only be noticeable if EF was HIGH before
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.

When

EF

goes HIGH, Retransmit Setup is complete and
read operations may begin starting with the first location in
memory. Since IDT Standard Mode is selected, every word
read including the first word following Retransmit Setup re­quires a LOW on

REN

to enable the rising edge of RCLK.
Writing operations can begin after one of two conditions have
been met: EF is HIGH or 14 cycles of the faster clock (RCLK
or WCLK) have elapsed since the RCLK rising edge enabled
by the RT pulse.

The deassertion time of EF during Retransmit Setup is

variable. The parameter t

RTF1, which is measured from the

rising RCLK edge enabled by RT to the rising edge of EF is
described by the following equation:

tRTF1 max. = 14*Tf + 3*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever is
shorter, and TRCLK is the RCLK period.

Regarding FF: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup, FF will
remain HIGH throughout the setup procedure.

For IDT Standard mode, updating the

PAE, HF

, and

PAF

flags begins with the "first"

REN

-enabled rising RCLK edge

following the end of Retransmit Setup (the point at which

EF

goes HIGH). This same RCLK rising edge is used to access
the "first" memory location. HF is updated on the first RCLK
rising edge.

PAE

is updated after two more rising RCLK

edges.

PAF

is updated after the "first" rising RCLK edge,

followed by the next two rising WCLK edges. (If the t

skew2

specification is not met, add one more WCLK cycle.)

If FWFT mode is selected, the FIFO will mark the beginning
of the Retransmit Setup by setting OR HIGH. The change in
level will only be noticeable if OR was LOW before setup.
During this period, the internal read pointer is set to the first
location of the RAM array.

8

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18

When

OR

goes LOW, Retransmit Setup is complete; at the
same time, the contents of the first location are automatically
displayed on the outputs. Since FWFT Mode is selected, the
first word appears on the outputs, no read request necessary.
Reading all subsequent words requires a LOW on

REN

to
enable the rising edge of RCLK. Writing operations can begin
after one of two conditions have been met: OR is LOW or 14
cycles of the faster clock (RCLK or WCLK) have elapsed since
the RCLK rising edge enabled by the RT pulse.

The assertion time of OR during Retransmit Setup is
variable. The parameter tRTF2, which is measured from the
rising RCLK edge enabled by RT to the falling edge of OR is
described by the following equation:

tRTF2 max. = 14*Tf + 4*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever
is shorter, and TRCLK is the RCLK period. Note that a
Retransmit Setup in FWFT mode requires one more RCLK
cycle than in IDT Standard mode.

Regarding IR: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup, IR will
remain LOW throughout the setup procedure.

For FWFT mode, updating the

PAE, HF

, and

PAF

flags
begins with the "last" rising edge of RCLK before the end of
Retransmit Setup. This is the same edge that asserts OR and
automatically accesses the first memory location. Note that,
in this case,

REN

is not required to initiate flag updating.

HF

is updated on the "last" RCLK rising edge.

PAE

is updated

after two more rising RCLK edges.

PAF

is updated after the
"last" rising RCLK edge, followed by the next two rising WCLK
edges. (If the t

skew2 specification is not met, add one more

WCLK cycle.)

RT

is synchronized to RCLK. The Retransmit operation is
useful in the event of a transmission error on a network, since
it allows a data packet to be resent.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state
of the FWFT/SI helps determine whether the device will
operate in IDT Standard mode or First Word Fall Through
(FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
present in the FIFO memory. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (

REN

) line.

If, at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there is valid data at the data
outputs (Q

n). It also uses Input Ready (

IR

) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to Qn, no read request necessary. Subsequent words
must be accessed using the Read Enable (

REN

) line.

After Master Reset, FWFT/SI acts as a serial input for

loading

PAE

and

PAF

offsets into the programmable registers.
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
FWFT/SI functions the same way in both IDT Standard and
FWFT modes.

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the write clock
(WCLK). Data set-up and hold times must be met with respect
to the LOW-to-HIGH transition of the WCLK. The write and
read clocks can either be asynchronous or coincident.

WRITE ENABLE (

WEN

WEN

)

When Write Enable (

WEN

) is LOW, data can be loaded into
the input register on the rising edge of every WCLK cycle.
Data is stored in the RAM array sequentially and indepen­dently of any on-going read operation.

When

WEN

is HIGH, the input register holds the previous

data and no new data is loaded into the FIFO.

To prevent data overflow in the IDT Standard Mode, FF will
go LOW , inhibiting further write operations. Upon the comple­tion of a valid read cycle, FF will go HIGH allowing a write to
occur.

WEN

is ignored when the FIFO is full.

To prevent data overflow in the FWFT mode, IR will go
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle, IR will go LOW allowing a write to occur.

WEN

is ignored when the FIFO is full.

READ CLOCK (RCLK)

Data can be read on the outputs, on the rising edge of the
read clock (RCLK), when Output Enable (OE) is set LOW. The
write and read clocks can be asynchronous or coincident.

READ ENABLE (

REN

REN

)

When Read Enable (

REN

) is LOW, data is loaded from the
RAM array into the output register on the rising edge of the
RCLK.

When

REN

is HIGH, the output register holds the previous

data and no new data is loaded into the output register.

In the IDT Standard Mode, every word accessed at Q

n,

including the first word written to an empty FIFO, must be
requested using

REN

. When all the data has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further
read operations.

REN

is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH after tFWL1 +tREF
and a read is permitted.

In the FWFT Mode, the first word written to an empty FIFO
automatically goes to the outputs Qn, no need for any read
request. In order to access all other words, a read must be
executed using

REN

. When all the data has been read from
the FIFO, Output Ready (OR) will go HIGH, inhibiting further
read operations.

REN

is ignored when the FIFO is empty.
Once a write is performed, OR will go LOW after tFWL2 +tREF,
when the first word appears at Qn ; if a second word is written
into the FIFO, then

REN

can be used to read it out.

9

IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL ENABLE (

SEN

SEN

)

Serial Enable is (

SEN

) is an enable used only for serial
programming of the offset registers. The serial programming
method must be selected during Master Reset.

SEN

is always
used in conjunction with LD. When these lines are both LOW,
data at the SI input can be loaded into the input register one
bit for each LOW-to-HIGH transition of WCLK.

When

SEN

is HIGH, the programmable registers retains

the previous settings and no offsets are loaded.

SEN

functions the same way in both IDT Standard and

FWFT modes.

OUTPUT ENABLE (

OEOE)

When Output Enable (OE) is enabled (LOW), the parallel

output buffers receive data from the output register. When

OE

is HIGH, the output data bus (Qn) goes into a high impedance
state.

LOAD (

LDLD)

This is a dual purpose pin. During Master Reset, the state
of the Load line (LD) determines one of two default values (127
or 1023) for the

PAE

and

PAF

flags, along with the method by

which these flags can be programmed, parallel or serial. After

Master Reset, LD enables write operations to and read
operations from the registers. Only the offset loading method
currently selected can be used to write to the registers. Aside
from Master Reset, there is no other way change the loading
method. Registers can be read only in parallel; this can be
accomplished regardless of whether serial or the parallel
loading has been selected.

Associated with each of the programmable flags,

PAE

and

PAF

, are registers which can either be written to or read from.
Offset values contained in these registers determine how
many words need to be in the FIFO memory to switch a partial
flag. A LOW on LD during Master Reset selects a default

PAE

offset value of 07FH ( a threshold 127 words from the empty
boundary), a default

PAF

offset value of 07FH (a threshold 127
words from the full boundary), and parallel loading of other
offset values. A HIGH on LD during Master Reset selects a
default

PAE

offset value of 3FFH (a threshold 1023 words from

the empty boundary), a default

PAF

offset value of 3FFH (a
threshold 1023 words form the full boundary), and serial
loading of other offset values.

The act of writing offsets (in parallel or serial) employs a
dedicated write offset register pointer. The act of reading
offsets employs a dedicated read offset register pointer. The

Figure 2. Partial Flag Programming Sequence

NOTES:

1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.

2. The programming method can only be selected at Master Reset.

3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

4. The programming sequence applies to both IDT Standard and FWFT modes.

Selection

Parallel write to registers:
Empty Offset
Full Offset

Parallel read from registers:

Empty Offset
Full Offset

No Operation

Write Memory

Read Memory

No Operation

3037 tbl 02

0

0

X

1

1

1

0

0

1

1

0

X

1

1

1

0

1

X

0

1

1

Serial shift into registers:
26 bits for the 72255
28 bits for the 72265

1

1

1

X

X

X

0

WCLK

X

X

X

X

RCLK

X

X

X

X

X

1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)