IDT IDT72261LA, IDT72271LA User Manual

查询IDT72261LA供应商

CMOS SuperSync FIFO
16,384 x 9
32,768 x 9

FEATURES:

••

•

Choose among the following memory organizations:

••

IDT72261LA 16,384 x 9
IDT72271LA 32,768 x 9

••

•

Pin-compatible with the IDT72281/72291 SuperSync FIFOs

••

••

10ns read/write cycle time (8ns access time)

•

••

••

• Fixed, low first word data latency time

••

••

• Auto power down minimizes standby power consumption

••

••

• Master Reset clears entire FIFO

••

••

• Partial Reset clears data, but retains programmable settings

••

••

• Retransmit operation with fixed, low first word data latency time

••

••

Empty, Full and Half-Full flags signal FIFO status

•

••

••

• Programmable Almost-Empty and Almost-Full flags, each flag

••

can default to one of two preselected offsets

••

• Program partial flags by either serial or parallel means

••

••

• Select IDT Standard timing (using EF and FF flags) or First

••

Word Fall Through timing (using OR and IR flags)

••

• Output enable puts data outputs into high impedance state

••

••

• Easily expandable in depth and width

••

••

• Independent Read and Write clocks (permit reading and writing

••

simultaneously)

™

IDT72261LA
IDT72271LA

••

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

••

pin Slim Thin Quad Flat Pack (STQFP)

••

•

High-performance submicron CMOS technology

••

••

•

Industrial temperature range (–40°C to +85°C) is available

••

DESCRIPTION:

The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:

••

• The limitation of the frequency of one clock input with respect to the other

••

has been removed. The Frequency Select pin (FS) has been removed,

thus it is no longer necessary to select which of the two clock inputs,

RCLK or WCLK, is running at the higher frequency.

••

• The period required by the retransmit operation is now fixed and short.

••

••

• The first word data latency period, from the time the first word is written

••

to an empty FIFO to the time it can be read, is now fixed and short. (The

variable clock cycle counting delay associated with the latency period found

on previous SuperSync devices has been eliminated on this SuperSync

family.)

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK

WRITE CONTROL

LOGIC

WRITE POINTER

MRS

PRS

RESET

LOGIC

0

-D

8

D

INPUT REGISTER

RAM ARRAY

16,384 x 9
32,768 x 9

OUTPUT REGISTER

LD

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ

CONTROL

LOGIC

SEN

RCLK

REN

FF/IR
PAF
EF/OR
PAE
HF

FWFT/SI

RT

0

-Q

8

Q

OE

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice

1

.

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IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

SuperSync FIFOs are particularly appropriate for network, video, telecom­munications, data communications and other applications that need to buffer
large amounts of data.

The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (REN) input. Data is read from the FIFO on every rising
edge of RCLK when REN is asserted. An Output Enable (OE) input is provided
for three-state control of the outputs.

PIN CONFIGURATIONS

FWFT/SI

PIN 1

WEN

SEN

DC

V

V

GND

GND

GND

GND

GND

GND

GND

GND

GND

CC

CC

D8

D7

MRS

PRS

WCLK

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

(1)

3

4
5

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

6

7
8

9
10
11

12
13

14
15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

LD

GND

The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the
frequency of one clock input with respect to the other.

There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and enabling
a rising RCLK edge, will shift the word from internal memory to the data output
lines.

CC

PAF

FF/IR

HF

EF/OR

V

PAE

REN

RCLK

RT

OE

48

47
46

45
44
43

42
41

40
39
38

37
36

35
34

33

DNC

DNC

GND

DNC

DNC

V

CC

DNC

DNC

DNC

GND

DNC

DNC

Q8

Q7

Q6

GND

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

NOTES:

1. DC = Don’t Care. Must be tied to GND or V

2. This pin may either be tied to ground or left open.

3. DNC = Do Not Connect.

CC, cannot be left open.

D6

D5

D4

D3

D2

D1

D0

TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)

TOP VIEW

2

GND

Q0

Q1

GND

Q2

Q3

CC

V

Q4

Q5

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COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for
access. The state of the FWFT/SI input during Master Reset determines
the timing mode in use.

For applications requiring more data storage capacity than a single
FIFO can provide, the FWFT timing mode permits depth expansion by
chaining FIFOs in series (i.e. the data outputs of one FIFO are connected
to the corresponding data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF
and FF functions are selected in IDT Standard mode. The IR and OR
functions are selected in FWFT mode. HF, PAE and PAF are always
available for use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point
in memory. (See Table I and Table II.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that PAE can be
set to switch at 127 or 1,023 locations from the empty boundary and the
PAF threshold can be set at 127 or 1,023 locations from the full boundary.
These choices are made with the LD pin during Master Reset.

For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,

are used to load the offset registers via Dn. REN together with LD on each rising
edge of RCLK can be used to read the offsets in parallel from Qn regardless
of whether serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur: The read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The LD pin selects either a partial flag default
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.

The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program­ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in
mid-operation, when reprogramming partial flags would be undesirable.

The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the
memory array.

If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.

The IDT72261LA/72271LA are fabricated using IDT’s high speed sub­micron CMOS technology.

PARTIAL RESET (PRS)

WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)

LOAD (LD)

DATA IN (D

0

- Dn)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO

MASTER RESET (MRS)

READ CLOCK (RCLK)
READ ENABLE (REN)

OUTPUT ENABLE (OE)

DATA OUT (Q0 - Qn)

IDT
72261LA
72271LA

RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)

HALF FULL FLAG (HF)

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IDT72261LA/72271LA SuperSync FIFO™
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COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION

Symbol Name I/O Description

D0–D8 Data Inputs I Data inputs for a 9-bit bus.
MRS Master Reset I MRS initializes the read and write pointers to zero and sets the output register to all zeroes.

During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of
two programmable flag default settings, and serial or parallel programming of the offset settings.

PRS Partial Reset I PRS initializes the read and write pointers to zero and sets the output method (serial or parallel),

and programmable flag settings are all retained.

RT Retransmit I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets

LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings. RT is useful to reread data from the
first physical location of the FIFO.

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial

In After Master Reset, this pin functions as a serial input for loading offset registers

WCLK Write Clock I When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into

the programmable registers for parallel programming, and when enabled by SEN, the rising

edge of WCLK writes one bit of data into the programmable register for serial programming.
WEN Write Enable I WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK Read Clock I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets

from the programmable registers.

REN Read Enable I REN enables RCLK for reading data from the FIFO memory and offset registers.
OE Output Enable I OE controls the output impedance of Qn.
SEN Serial Enable I SEN enables serial loading of programmable flag offsets.
LD Load I During Master Reset, LD selects one of two partial flag default offsets (127 or

the flag offset programming method, serial or parallel. After

Master Reset, this pin enables writing to

and reading from the offset registers.
DC Don't Care I This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory

Input Ready is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space

available for writing to the FIFO memory.
EF/OR Empty Flag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory

Output Ready is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data

available at the outputs.
PAF Programmable O PAF goes LOW if the number of words in the FIFO memory is more than word capacity of the FIFO

Almost-Full Flag minus the full offset value m, which is stored in the Full Offset register. There are two possible default

values for m: 127 or 1,023.
PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the

Almost-Empty Flag Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values for n

can be programmed into the device.
HF Half-Full Flag O HF indicates whether the FIFO memory is more or less than half-full.
Q0–Q8 Data Outputs O Data outputs for a 9-bus
VCC Power +5 Volt power supply pins.
GND Ground Ground pins.

the EF flag to

1,023) and determines

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IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Com’l & Ind’l Unit

VTERM Terminal Voltage –0.5 to +7 V

with respect to GND

STG Storage –55 to +125 °C

T

Temperature

OUT DC Output Current –50 to +50 mA

I

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4. 5 5.0 5.5 V
Commercial/Industrial
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.0 — — V

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

VIL

TA Operating Temperature 0 — +70 °C

Commercial/Industrial

(1)

Input Low Voltage — — 0.8 V
Commercial/Industrial

Commercial

TA Operating Temperature –40 — +85 ° C

Industrial

NOTE:

1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)

IDT72261LA
IDT72271LA

Commercial and Industrial

tCLK = 10, 15, 20 ns

Symbol Parameter Min. Max. Unit

(2)

I

LI

(3)

LO

I

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — V

V

OL Output Logic “0” Voltage, IOL = 8 mA — 0.4 V

V

(4,5,6)

CC1

I

(4,7)

CC2

I

Input Leakage Current –1 1 µA
Output Leakage Current –1 0 10 µA

Active Power Supply Current — 7 5 mA
Standby Current — 20 mA

(1)

NOTES:

1. Industrial temperature range product for the 15ns and 20ns speed grade are available as a standard device.

2. Measurements with 0.4 ≤ V

3. OE ≥ V

4. Tested with outputs disabled (I

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical I

7. All Inputs = V

IH, 0.4 ≤ VOUT ≤ VCC.

CC1 = 15 + 1.85*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f S/2,

L = capacitive load (in pF).

C

CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

IN ≤ VCC.

OUT = 0).

CAPACITANCE

(TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2)

IN

C

Input VIN = 0V 10 pF
Capacitance

(1,2)

OUT

C

Output VOUT = 0V 10 pF
Capacitance

NOTES:

1. With output deselected, (OE ≥ VIH).

2. Characterized values, not currently tested.

(1)

Conditions Max. Unit

5

IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)

Commercial Commercial & Industrial
IDT72261LA10 IDT72261LA15 IDT72261LA20
IDT72271LA10 IDT72271LA15 IDT72271LA20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

fS Clock Cycle Frequency — 100 — 66.7 — 50 MHz
tA Data Access Time 2 8 2 10 2 1 2 n s
tCLK Clock Cycle Time 10 — 15 — 20 — ns
tCLKH Clock High Time 4.5 — 6 — 8 — n s
tCLKL Clock Low Time 4.5 — 6 — 8 — n s
tDS Data Setup Time 3 — 4 — 5 — ns
tDH Data Hold Time 0 — 1 — 1 — ns
tENS Enable Setup Time 3 — 4 — 5 — ns
tENH Enable Hold Time 0 — 1 — 1 — ns
tLDS Load Setup Time 3 — 4 — 5 — ns
tLDH Load Hold Time 0 — 1 — 1 — ns
tRS Reset Pulse Width

(3)

10 — 15 — 20 — ns
tRSS Reset Setup Time 10 — 15 — 2 0 — ns
tRSR Reset Recovery Time 1 0 — 1 5 — 2 0 — ns
tRSF Reset to Flag and Output Time — 10 — 1 5 — 2 0 ns
tFWFT Mode Select Time 0 — 0 — 0 — ns
tRTS Retransmit Setup Time 3 — 4 — 5 — ns
tOLZ Output Enable to Output in Low Z

(4)

0 —0— 0—ns
tOE Output Enable to Output Valid 2 6 3 8 3 1 0 ns
tOHZ Output Enable to Output in High Z

(4)

2638310ns
tWFF Write Clock to FF or IR —8—10—12ns
tREF Read Clock to EF or OR —8—10—12ns
tPAF Write Clock to PAF —8—10—12ns
tPAE Read Clock to PAE —8—10—12ns
tHF Clock to HF —16—20—22ns
tSKEW1 Skew time between RCLK and WCLK for FF/IR 5—6—10—ns
tSKEW2 Skew time between RCLK and WCLK for PAE and PAF 12 — 15 — 20 — ns
t

SKEW3 Skew time between RCLK and WCLK for EF/OR 60 — 60 — 60 — ns

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

(2)

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1

D.U.T.

* Includes jig and scope capacitances.

6

5V

680Ω

Figure 2. Output Load

1.1K

30pF*

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IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH
(FWFT) MODE

The IDT72261LA/72271LA support two different timing modes of opera-

tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset,
by the state of the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard

mode will be selected. This mode uses the Empty Flag (EF) to indicate
whether or not there are any words present in the FIFO. It also uses the Full
Flag function (FF) to indicate whether or not the FIFO has any free space
for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using the Read Enable (REN) and
RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will

be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR)
to indicate whether or not the FIFO has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.

Various signals, both input and output signals operate differently de-

pending on which timing mode is in effect.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the

manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After
the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read

operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 8,193th word for IDT72261LA and 16,385th word for IDT72271LA
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.
Again, if no reads are performed, the PAF will go LOW after (16,384-m)
writes for the IDT72261LA and (32,768-m) writes for the IDT72271LA. The
offset “m” is the full offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.

When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further

write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 16,384 writes for the IDT72261LA and
32,768 for the IDT72271LA, respectively.

If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause
the FIFO to become empty. When the last word has been read from the
FIFO, the EF will go LOW inhibiting further read operations. REN is ignored
when the FIFO is empty.

When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program­mable. See section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the
8,194th word for the IDT72261LA and 16,386th word for the IDT72271LA,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAF will go LOW after (16,385-m) writes for the IDT72261LA and (32,769­m) writes for the IDT72271LA, where m is the full offset value. The default
setting for this value is stated in the footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 16,385 writes for the 72261LA and
32,769 writes for the IDT72271LA, respectively. Note that the additional
word in FWFT mode is due to the capacity of the memory plus output
register.

If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is
ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple register­buffered, and the IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.

7

IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The
IDT72261LA/72271LA has internal registers for these offsets. Default
settings are stated in the footnotes of Table 1 and Table 2. Offset values
can be programmed into the FIFO in one of two ways; serial or parallel
loading method. The selection of the loading method is done using the LD
(Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on
LD during Master Reset selects serial loading of offset values and in
addition, sets a default PAE offset value of 3FFH (a threshold 1,023 words
from the empty boundary), and a default PAF offset value of 3FFH (a
threshold 1,023 words from the full boundary). A LOW on LD during Master
Reset selects parallel loading of offset values, and in addition, sets a

default PAE offset value of 07FH (a threshold 127 words from the empty
boundary), and a default PAF offset value of 07FH (a threshold 127 words
from the full boundary). See Figure 3, Offset Register Location and Default
Values.

In addition to loading offset values into the FIFO, it also possible to read
the current offset values. It is only possible to read offset values via parallel
read.

Figure 4, Programmable Flag Offset Programming Sequence, summa­rizes the control pins and sequence for both serial and parallel program­ming modes. For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming
has been selected.

TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE

IDT72261LA IDT72271LA

Number of
Words in
FIFO

0

(1)

1 to n

(n+1) to 8,192

8,193 to (16,384-(m+1))

(2)

(16,384-m)

to 16,383

16,384

16,385 to (32,768-(m+1))

(32,768-m)

0

(1)

1 to n

(n+1) to 16,384

(2)

to 32,767

32,768

FF PAF HF PAE EF

HHHL L

HHHL H

HHHHH

HHLH H

HLLHH

LLLHH

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

TABLE 2 — STATUS FLAGS FOR IDT STANDARD MODE

IDT72261LA IDT72271LA

0

Number of
Words in

(1)

FIFO

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

8,194 to (16,385-(m+1))

(16,385-m)

1 to n+1

(n+2) to 8,193

16,385

(1)

to 16,384

(2)

16,386 to (32,769-(m+1))

(32,769-m)

0

1 to n+1

(n+2) to 16,385

32,769

(1)

to 32,768

(2)

IR PAF HF PAE OR

LHH LH

LHH LL

LHHHL

LHL HL

LLL HL

HL L H L

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8

IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

LD

IDT72261LA  16,384 x 9  BIT

8

85 0

8

85

WEN

7

EMPTY OFFSET (LSB) REG.

DEFAULT VALUE

07FH if LD is LOW at Master Reset

3FFH if LD is HIGH at Master Reset

EMPTY OFFSET (MSB) REG.

00H

7

FULL OFFSET (LSB) REG.

DEFAULT VALUE

07FH if LD is LOW at Master Reset

3FFH if LD is HIGH at Master Reset

FULL OFFSET (MSB) REG.

00H

Figure 3. Offset Register Location and Default Values

REN

SEN

0

8

86 0

0

8

0

86

WCLK RCLK Selection

IDT72271LA  32,768 x 9  BIT

7

EMPTY OFFSET (LSB) REG.

DEFAULT VALUE

07FH if LD is LOW at Master Reset

3FFH if LD is HIGH at Master Reset

EMPTY OFFSET (MSB) REG.

00H

7

FULL OFFSET (LSB) REG.

DEFAULT VALUE

07FH if LD is LOW at Master Reset

3FFH if LD is HIGH at Master Reset

FULL OFFSET (MSB) REG.

00H

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0

0

0

0

0

1

1

X Parallel write to registers:

Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)

0

1

0

1

X Parallel read from registers:

Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)

0

1

1

0

X

Serial shift into registers:
28 bits for the 72261LA
30 bits for the 72271LA

1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

X

1

1

1

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

1

0

X

1

1

X

0

1

1

X

X

X

X X No Operation

X Write Memory

X Read Memory

X X No Operation

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Figure 4. Programmable Flag Offset Programming Sequence

9