Integrated Device Technology Inc IDT72271L10G, IDT72271L10PF, IDT72271L10TF, IDT72261L12G, IDT72261L12PF Datasheet

Integrated Device Technology, Inc.

CMOS SUPERSYNC FIFO
16,384 x 9, 32,768 x 9

IDT72261
IDT72271

FEATURES:

• 16,384 x 9-bit storage capacity (IDT72261)

• 32,768 x 9-bit storage capacity (IDT72271)

• 10ns read/write cycle time (8ns access time)

• Retransmit Capability

• Auto power down reduces power consumption

• Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings

• Empty, Full and Half-full flags signal FIFO status

• Programmable Almost Empty and Almost Full flags, each
flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or

First Word Fall Through timing (using OR and IR flags)

• Easily expandable in depth and width

• Independent read and write clocks (permit simultaneous
reading and writing with one clock signal

• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64­pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)

• Output enable puts data outputs into high impedance

• High-performance submicron CMOS technology

• Industrial temperature range (-40
able, tested to military electrical specifications

O

C to +85OC) is avail-

DESCRIPTION:

The IDT72261/72271 are monolithic, CMOS, high capac­ity, high speed, low power first-in, first-out (FIFO) memories
with clocked read and write controls. These FIFOs are
applicable for a wide variety of data buffering needs, such as
optical disk controllers, local area networks (LANs), and inter­processor communication.

Both FIFOs have a 9-bit input port (D
port (Qn). The input port is controlled by a free-running clock
(WCLK) and a data input enable pin (
into the synchronous FIFO on every clock when
asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (

REN

). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output
enable pin (OE) is provided on the read port for three-state
control of the outputs.

The IDT72261/72271 have two modes of operation: In the

IDT Standard Mode

, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the

First Word Fall Through Mode

(FWFT), the first word written to an empty FIFO appears
automatically on the outputs, no read operation required. The

n) and a 9-bit output

WEN

). Data is written

WEN

is

FUNCTIONAL BLOCK DIAGRAM

MRS

PRS

FS

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

WEN

WRITE CONTROL

WRITE POINTER

RESET LOGIC

•

LOGIC

TIMING

WCLK

•

OUTPUT REGISTER

•

OE

D0-D8

INPUT REGISTER

•

•

RAM ARRAY

16,384 x 9
32,768 x 9

•

•

Q0-Q8

LD

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ

CONTROL

LOGIC

•

•

SEN

FF/IR
PAF
EF/OR
PAE
HF

FWFT/SI

RT

RCLK

REN

3036 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1997

1997 Integrated Device Technology, Inc DSC-3036/6

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

1

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

state of the FWFT/SI pin during Master Reset determines the
mode in use.

The IDT72261/72271 FIFOs have five flag functions, EF/

OR

(Empty Flag or Output Ready), FF/IR (Full Flag or Input
Ready), and HF (Half-full Flag). The EF and FF functions are
selected in the IDT Standard Mode.

The IR and OR functions are selected in the First Word Fall
Through Mode. IR indicates that the FIFO has free space to
receive data. OR indicates that data contained in the FIFO is
available for reading.

HF

is a flag whose threshold is fixed at the half-way point in

memory. This flag can always be used irrespective of mode.

PAE, PAF

can be programmed independantly to any point
in memory. They, also, can be used irrespective of mode.
Programmable offsets determine the flag threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, such that
127 or 1023 locations from the empty boundary and the

PAE

can be set at

PAF

threshold can be set at 127 or 1023 locations from the full

PIN CONFIGURATIONS

PRS

MRS

WCLK

LD

FWFT/SI

GND

boundary. All these choices are made with LD during Master
Reset

.

In the serial method, SEN

together with LD are used to load
the offset registers via the Serial Input (SI). In the parallel
method,
registers via Dn.

WEN

together with LD can be used to load the offset

REN

together with LD can be used to read the
offsets in parallel from Qn regardless of whether serial or
parallel offset loading is selected.

During Master Reset (

MRS

), the read and write pointers are
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The LD pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.

The Partial Reset (

PRS

) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly.
useful for resetting a device in mid-operation, when repro­gramming offset registers may not be convenient.

IR

/

FF

PAF

HF

CC

V

PAE

OR

/

EF

RCLK

REN

RT

OE

PRS

is

PIN 1

WEN

SEN

FS

CC

V
VCC

(2)

GND

(2)

GND

(2)

GND

(2)

GND

(2)

GND

(2)

GND

(2)

GND

(2)

GND

(2)

GND

D8
D7

NOTES:

1. DNC = Do not connect.

2. This pin may either be tied to ground or left open.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

D6

D5

D4

D3

D2

D1

D0

GND

Q0

Q1

GND

Q2

Q3

CC

V

Q4

TQFP (PN64-1, order code: PF)

STQFP (PP64-1, order code: TF)

TOP VIEW

Q5

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

DNC
DNC
GND
DNC
DNC

CC

V
DNC
DNC
DNC
GND
DNC
DNC
Q8
Q7
Q6
GND

3036 drw 02

2

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The Retransmit function allows the read pointer to be reset
to the first location in the RAM array. It is synchronized to
RCLK when RT is LOW. This feature is convenient for
sending the same data more than once.

If, at any time, the FIFO is not actively performing a function,
the chip will automatically power down. This occurs if neither
a read nor a write occurs within 10 cycles of the faster clock,
RCLK or WCLK. During the Power Down state, supply current
consumption (ICC2) is at a minimum. Initiating any operation
(by activating control inputs) will immediately take the device
out of the Power Down state.

PIN CONFIGURATIONS (CONT.)

V

11

10

09

08

6

Q

Q8Q

DNC

DNC

GND

7

DNC

Q

Q

CC

5

4

Q

3

Q

2

GND

The IDT72261/72271 are depth expandable. The addition
of external components is unnecessary. The IR and
functions, together with
total FIFO memory capacity.

The FS line ensures optimal data flow through the FIFO. It
is tied to GND if the RCLK frequency is higher than the WCLK
frequency or to Vcc if the RCLK frequency is lower than the
WCLK frequency

The IDT72261/72271 is fabricated using IDT’s high speed
submicron CMOS technology.

Q

1

GND

Q

0

D

0

D

1

D

2

D

D

REN

and

WEN

, are used to extend the

3

D

5

D

D

4

GND

GND

7

6

(2)

D

8

(2) (2)

GND

OR

LD

MRS

GND

GND

GND GND

V

CC

SEN

WCLK

PRS

DNC

07

DNC DNC

06

DNC

05

04

GND

DNC

03

DNC

02

01

GND

CC

V

DNC

DNC

RT

RENOE

RCLK

Pin 1 Designator

GND

EF

/

OR

PAE

V

CC

HF

PAF

FF

/

IR

GND

DNC

FWFT/

SI

ABCDEFGHJKL

PGA (G68-1, order code: G)

TOP VIEW

(2)

(2)

(2) (2)

GND

GND

V

(2)

(2)

CC

FS

WEN

3036 drw 03

NOTES:

1. DNC = Do not connect.

2. This pin may either be tied to ground or left open.

3

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Symbol Name I/O Description

0–D8 Data Inputs I Data inputs for a 9-bit bus.

D

MRS

PRS

RT

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode.

WCLK Write Clock I When enabled by

WEN

RCLK Read Clock I When enabled by

REN
OE
SEN
LD

FS Frequency Select I The FS setting optimizes data flow through the FIFO.

FF/IR

EF/OR

PAF

PAE

HF

Q

0–Q8 Data Outputs O Data outputs for a 9-bit bus.

CC Power +5 volt power supply pins.

V
GND Ground Ground pins.

Master Reset I

MRS

initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard Mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.

Partial Reset I

PRS

initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.

Retransmit I Allows data to be resent starting with the first location of FIFO memory.

Through/Serial In After Master Reset, this pin functions as a serial input for loading offset registers

WEN

, the rising edge of WCLK writes data into the FIFO and

offsets into the programmable registers.

Write Enable I

WEN

enables WCLK for writing data into the FIFO memory and offset registers.

REN

, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

Read Enable I
Output Enable I OE controls the output impedance of Q
Serial Enable I

REN

enables RCLK for reading data from the FIFO memory and offset registers.

n

SEN

enables serial loading of programmable flag offsets

Load I During Master Reset, LD selects one of two partial flag default offsets (127 and

1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.

Full Flag/ O In the IDT Standard Mode, the FF function is selected. FF indicates whether or
Input Ready not the FIFO memory is full. In the FWFT mode, the IR function is selected.

indicates whether or not there is space available for writing to the FIFO memory.

Empty Flag/ O In the IDT Standard Mode, the EF function is selected.

EF

indicates whether or

Output Ready not the FIFO memory is empty. In FWFT mode, the OR function is selected.

OR

indicates whether or not there is valid data available at the outputs.

Programmable O

PAF

goes HIGH if the number of free locations in the FIFO memory is more than

Almost Full Flag offset m which is store in Almost Full which is stored in the Full Offset register.

goes LOW if the number of free locations in the FIFO memory is less than m.

Programmable O
Almost Empty Flag which is stored in theEmpty Offset register.

PAE

goes LOW if the number of words in the FIFO memory is less than offset n

PAE

goes HIGH if the number of

words in the FIFO memory is greater than offset n.

Half-full Flag O

HF

indicates whether the FIFO memory is more or less than half-full.

IR

PAF

3097 tbl 01

4

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial MIilitary Unit

V

TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with respect to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature Under –55 to +125 –65 to +135 °C

Bias

STG Storage –55 to +125 –65 to +155 °C

T

Temperature

I

OUT DC Output Current 50 50 mA

NOTE: 3097 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maimum rating conditions for extended periods may
affect reliabilty.

RECOMMENDED DC
OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CCM Military Supply 4.5 5.0 5.5 V

Voltage

V

CCC Commercial Supply 4.5 5.0 5.5 V

Voltage

GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — — V

V

Commercial

V

IH Input High Voltage 2.2 — — V

Military

(1)

V

IL

NOTE: 3097 tbl 03

1. 1.5V undershoots are allowed for 10ns once per cycle.

Input Low Voltage — — 0.8 V
Commercial & Military

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

DT72261L IDT72261L

IDT72271L IDT72271L

Commercial Military

CLK = 10, 12,15, 20ns tCLK = 15, 25ns

t

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

(1)

LI

I
I

LO

V

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V
OL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V

V
I

CC1

I

CC2

NOTES:

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. OE = V

3. Tested at f = 20 MHz with outputs unloaded.

4. No data written or read for more than 10 cycles

Input Leakage Current (any input) –1 — 1 –10 — 10 µA

(2)

Output Leakage Current –10 — 10 –10 — 10 µA

(3)

Active Power Supply Current — — 150 — — 200 mA

(3,4)

Power Down Current (All inputs = VCC - 0.2V or — — 15 — — 25 mA
GND + 0.2V, RCLK and WCLK are free-running)

IH

3097 tbl 04

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2)

C

IN

Input VIN = 0V 10 pF
Capacitance

(1,2)

C

OUT

Output VOUT = 0V 10 pF
Capacitance

NOTES:

1. With output deselected, (OE=HIGH).

2. Characterized values, not currently tested.

(1)

Conditions Max. Unit

3097 tbl 05

5

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Commercial Com'l & Mil. Commercial Military

72261L10 72261L12 72261L15 72261L20 72261L25
72271L10 72271L12 72271L15 72271L20 72271L25

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

f

S Clock Cycle Frequency — 100 — 83.3 — 66.7 — 50 — 40 MHz
A Data Access Time 2 8 2 9 2 10 2 12 3 15 ns

t

t

CLK Clock Cycle Time 10 — 12 — 15 — 20 — 25 — ns

CLKH Clock High Time 4.5 — 5 — 6 — 8 — 10 — ns

t

CLKL Clock Low Time 4.5

t

DS Data Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns

t
t

DH Data Hold Time 0 — 0 — 1 — 1 — 1 — ns

ENS Enable Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns

t

ENH Enable Hold Time 0 — 0 — 1 — 1 — 1 — ns

t
t

LDS Load Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns
LDH Load Hold Time 6.5 — 8.5 — 10 — 10 — 10 — ns

t

IR

FF

EF

PAF

PAE

and

or

or

(3)

(4)

(4)

IR

OR

PAF

RS Reset Pulse Width

t

t

RSS Reset Set-up Time 10 — 12 — 15 — 20 — 25 — ns
RSR Reset Recovery Time 10 — 12 — 15 — 20 — 25 — ns

t

RSF Reset to Flag and Output Time — 10 — 12 — 15 — 20 — 25 ns

t

t

FWFT Mode Select Time 0 — 0 — 0 — 0 — 0 — ns

RTS Retransmit Set-Up Time 3.5 — 3.5 — 4 — 5 — 6 — ns

t

OLZ Output Enable to Output in Low Z

t

OE Output Enable to Output Valid 3 7 3 7.5 3 8 3 10 3 13 ns

t

t

OHZ Output Enable to Output in High Z
WFF Write Clock to

t

REF Read Clock to

t

t

PAF Write Clock to

t

PAE Read Clock to

t

HF Clock to

SKEW1 Skew time between RCLK and WCLK 8 — 10 — 12 — 15 — 20 — ns

t

HF

for FF and

t

SKEW2 Skew time between RCLK and 15 — 18 — 21 — 25 — 35 — ns

WCLK for

NOTES:

1. All AC timings apply to both Standard IDT Mode and First Word Fall
Through Mode.

2. For the RCLK line: t
the programmable flag registers; otherwise, use the table value. For the
WCLK line, use the t

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

PAE

CLKL (min.) = 7 ns only when reading the offsets from

CLKL (min.) value given in the table.

(2)

—5

10 — 12 — 15 — 20 — 25 — ns

0—0—0—0 —0—ns

3 7 3 7.5 3 8 3 10 3 13 ns
—8—9—10—12—15ns
—8—9—10—12—15ns

– 8—9—10—12—15ns
—8—9—10—12—15ns
— 16 — 18 — 20 — 22 — 25 ns

AC TEST CONDITIONS

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

3ns

1.5V

1.5V

See Figure 1

3097 tbl 08

(2)

—6

(2)

D.U.T.

* Includes jig and scope capacitances.

—8 —10—ns

3097 tbl 06

5V

1.1K

680

Ω

Figure 1. Output Load

30pF*

3036 drw 04

6

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS:

INPUTS:
DATA IN (D

Data inputs for 9-bit wide data.

CONTROLS:
MASTER RESET (

A Master Reset is accomplished whenever the Master
Reset (
the internal read and write pointers to the first location of the
RAM array.
go HIGH.

If FWFT is LOW during Master Reset then the IDT Standard

Mode, along with EF and FF are selected. EF will go LOW and

FF

will go HIGH. If FWFT is HIGH, then the First Word Fall

through Mode (FWFT), along with IR and OR, are selected.

OR

will go HIGH and IR will go LOW.

If LD is LOW during Master Reset, then
threshold 127 words from the empty boundary and
assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.

If LD is HIGH during Master Reset, then
threshold 1023 words from the empty boundary and
assigned a threshold 1023 words from the full boundary;
1023 words corresponds to an offset value of 3FFH. Following
Master Reset, serial loading of the offsets is permitted, but not
parallel loading.

Regardless of whether serial or parallel offset loading has
been selected, parallel reading of the registers is always
permitted. (See section describing the LD line for further
details).

During a Master Reset, the output register is initialized to
all zeroes. A Master Reset is required after power up, before
a write operation can take place.

PARTIAL RESET (

A Partial Reset is accomplished whenever the Partial
Reset (
the Master Reset, the internal read and write pointers are set
to the first location of the RAM array,
goes HIGH, and HF goes HIGH.

Whichever mode is active at the time of partial reset, IDT
Standard Mode or First Word Fall-through, that mode will
remain selected. If the IDT Standard Mode is active, then
will go HIGH and EF will go LOW. If the First word Fall-through
Mode is active, then OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset regis­ters remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes.
is asynchronous.

0 - D8)

MRS

)

MRS

MRS

) input is taken to a LOW state. This operation sets

PAE

will go LOW,

PRS

)

PRS

PRS

) input is taken to a LOW state. As in the case of

PAF

will go HIGH, and HF will

PAE

is assigned a

PAE

is assigned a

MRS

is asynchronous.

PAE

goes LOW,

PAF

PAF

is

is

PAF

FF

PRS

A Partial Reset is useful for resetting the device during the
course of operation, when reprogramming flag settings may
not be convenient.

RETRANSMIT (

RTRT)

The Retransmit operation allows data that has already
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.

Retransmit Setup is initiated by holding RT LOW during a
rising RCLK edge.

REN

and

WEN

must be HIGH before
bringing RT LOW. At least one word, but no more than Full ­2 words should have been written into the FIFO between
Reset (Master or Partial) and the time of Retransmit Setup
(Full = 16,384 words for the 72261, 32,768 words for the

72271).

If IDT Standard mode is selected, the FIFO will mark the
beginning of the Retransmit Setup by setting EF LOW. The
change in level will only be noticeable if EF was HIGH before
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.

When

EF

goes HIGH, Retransmit Setup is complete and
read operations may begin starting with the first location in
memory. Since IDT Standard Mode is selected, every word
read including the first word following Retransmit Setup re­quires a LOW on

REN

to enable the rising edge of RCLK.
Writing operations can begin after one of two conditions have
been met: EF is HIGH or 14 cycles of the faster clock (RCLK
or WCLK) have elapsed since the RCLK rising edge enabled
by the RT pulse.

The deassertion time of EF during Retransmit Setup is

variable. The parameter t

RTF1, which is measured from the

rising RCLK edge enabled by RT to the rising edge of EF is
described by the following equation:

t

RTF1 max. = 14*Tf + 3*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever is
shorter, and TRCLK is the RCLK period.

Regarding FF: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup, FF will
remain HIGH throughout the setup procedure.

For IDT Standard mode, updating the

flags begins with the "first"

REN

-enabled rising RCLK edge

following the end of Retransmit Setup (the point at which

PAE, HF

, and

PAF

EF

goes HIGH). This same RCLK rising edge is used to access
the "first" memory location. HF is updated on the first RCLK
rising edge.
edges.

PAE

is updated after two more rising RCLK

PAF

is updated after the "first" rising RCLK edge,
followed by the next two rising WCLK edges. (If the tskew2
specification is not met, add one more WCLK cycle.)

If FWFT mode is selected, the FIFO will mark the beginning
of the Retransmit Setup by setting OR HIGH. The change in
level will only be noticeable if OR was LOW before setup.
During this period, the internal read pointer is set to the first
location of the RAM array.

7

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9

When

OR

goes LOW, Retransmit Setup is complete; at the
same time, the contents of the first location are automatically
displayed on the outputs. Since FWFT Mode is selected, the
first word appears on the outputs, no read request necessary.
Reading all subsequent words requires a LOW on

REN

to
enable the rising edge of RCLK. Writing operations can begin
after one of two conditions have been met:

OR

is LOW or 14
cycles of the faster clock (RCLK or WCLK) have elapsed since
the RCLK rising edge enabled by the RT pulse.

The assertion time of OR during Retransmit Setup is
variable. The parameter tRTF2, which is measured from the
rising RCLK edge enabled by RT to the falling edge of OR is
described by the following equation:

tRTF2 max. = 14*Tf + 4*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever
is shorter, and TRCLK is the RCLK period. Note that a
Retransmit Setup in FWFT mode requires one more RCLK
cycle than in IDT Standard mode.

Regarding IR: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup, IR will
remain LOW throughout the setup procedure.

For FWFT mode, updating the

PAE, HF

, and

PAF

flags
begins with the "last" rising edge of RCLK before the end of
Retransmit Setup. This is the same edge that asserts OR and
automatically accesses the first memory location. Note that,
in this case,
is updated on the "last" RCLK rising edge.
after two more rising RCLK edges.

REN

is not required to initiate flag updating.

PAE

PAF

is updated after the

HF

is updated

"last" rising RCLK edge, followed by the next two rising WCLK
edges. (If the t

skew2 specification is not met, add one more

WCLK cycle.)

RT

is synchronized to RCLK. The Retransmit operation is
useful in the event of a transmission error on a network, since
it allows a data packet to be resent.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state
of the FWFT/SI helps determine whether the device will
operate in IDT Standard mode or First Word Fall Through
(FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
present in the FIFO memory. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (

REN

) line.

If, at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there is valid data at the data
outputs (Q

n). It also uses Input Ready (

IR

) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to Qn, no read request necessary. Subsequent words
must be accessed using the Read Enable (

REN

) line.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

After Master Reset, FWFT/SI acts as a serial input for

loading

PAE

and

PAF

offsets into the programmable registers.
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
FWFT/SI functions the same way in both IDT Standard and
FWFT modes.

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the write clock
(WCLK). Data set-up and hold times must be met with respect
to the LOW-to-HIGH transition of the WCLK. The write and
read clocks lines can either be asynchronous or coincident.

WRITE ENABLE (

When Write Enable (

WEN

WEN

)

WEN

) is LOW, data can be loaded into
the input register on the rising edge of every WCLK cycle.
Data is stored in the RAM array sequentially and indepen­dently of any on-going read operation.

When

WEN

is HIGH, the input register holds the previous

data and no new data is loaded into the FIFO.

To prevent data overflow in the IDT Standard Mode, FF will
go LOW , inhibiting further write operations. Upon the comple­tion of a valid read cycle, FF will go HIGH allowing a write to
occur.

WEN

is ignored when the FIFO is full.

To prevent data overflow in the FWFT mode, IR will go
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle, IR will go LOW allowing a write to occur.

WEN

is ignored when the FIFO is full.

READ CLOCK (RCLK)

Data can be read on the outputs, on the rising edge of the
read clock (RCLK), when Output Enable (OE) is set LOW. The
write and read clocks can be asynchronous or coincident.

READ ENABLE (

When Read Enable (

REN

REN

)

REN

) is LOW, data is loaded from the
RAM array into the output register on the rising edge of the
RCLK.

When

REN

is HIGH, the output register holds the previous

data and no new data is loaded into the output register.

In the IDT Standard Mode, every word accessed at Q
including the first word written to an empty FIFO, must be
requested using

REN

. When all the data has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further
read operations.

REN

is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH after tFWL1 +tREF
and a read is permitted.

In the FWFT Mode, the first word written to an empty FIFO
automatically goes to the outputs Qn, no need for any read
request. In order to access all other words, a read must be
executed using

REN

. When all the data has been read from
the FIFO, Output Ready (OR) will go HIGH, inhibiting further
read operations.

REN

is ignored when the FIFO is empty.
Once a write is performed, OR will go LOW after tFWL2 +tREF,
when the first word appears at Qn ; if a second word is written
into the FIFO, then

REN

can be used to read it out.

n,

8

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL ENABLE (

Serial Enable is (

SEN

)

SEN

SEN

) is an enable used only for serial
programming of the offset registers. The serial programming
method must be selected during Master Reset.

SEN

is always
used in conjunction with LD. When these lines are both LOW,
data at the SI input can be loaded into the input register one
bit for each LOW-to-HIGH transition of WCLK.

When

SEN

is HIGH, the programmable registers retains

the previous settings and no offsets are loaded.

SEN

functions the same way in both IDT Standard and

FWFT modes.

OUTPUT ENABLE (

OEOE)

When Output Enable (OE) is enabled (LOW), the parallel

output buffers receive data from the output register. When

OE

is HIGH, the output data bus (Qn) goes into a high impedance
state.

LOAD (

LDLD)

This is a dual purpose pin. During Master Reset, the state
of the Load line (LD) determines one of two default values (127
or 1023) for the

PAE

and

PAF

flags, along with the method by

which these flags can be programmed, parallel or serial. After

LD

WEN

REN

SEN

WCLK RCLK Selection

Master Reset, LD enables write operations to and read
operations from the registers. Only the offset loading method
currently selected can be used to write to the registers. Aside
from Master Reset, there is no other way change the loading
method. Registers can be read only in parallel; this can be
accomplished regardless of whether serial or the parallel
loading has been selected.

Associated with each of the programmable flags,

PAF

, are two registers which can either be written to or read

PAE

and

from. Offset values contained in these registers determine
how many words need to be in the FIFO memory to switch a
partial flag. A LOW on LD during Master Reset selects a
default

PAE

offset value of 07FH ( a threshold 127 words from

the empty boundary), a default

PAF

offset value of 07FH (a
threshold 127 words from the full boundary), and parallel
loading of other offset values. A HIGH on LD during Master
Reset selects a default
1023 words from the empty boundary), a default

PAE

offset value of 3FFH (a threshold

PAF

offset
value of 3FFH (a threshold 1023 words form the full bound­ary), and serial loading of other offset values.

The act of writing offsets (in parallel or serial) employs a
dedicated write offset register pointer. The act of reading
offsets employs a dedicated read offset register pointer. The

0

0

0

X

1

1

1

NOTES:

1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.

2. The programming method can only be selected at Master Reset.

3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

4. The programming sequence applies to both IDT Standard and FWFT modes.

0

1

1

1

0

X

1

1

0

1

1

X

0

1

1

1

0

1

X

X

X

X Parallel read from registers:

X X No Operation

X Read Memory

X X No Operation

X Parallel write to registers:

X Serial shift into registers:

X Write Memory

Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)

Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)

28 bits for the 72261
30 bits for the 72271
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

3097 tbl 01

Figure 2. Partial Flag Programming Sequence

9