Integrated Device Technology Inc IDT72251L15J, IDT72251L20J, IDT72251L25J, IDT72251L35J Datasheet

Integrated Device Technology, Inc.

CMOS SyncFIFO
8192 X 9

ADVANCED

INFORMATION

IDT72251

FEATURES:

• 8192 x 9-bit organization

• Pin/function compatible with IDT72421/722x1 family

• 15 ns read/write cycle time

• Read and write clocks can be independent

• Dual-Ported zero fall-through time architecture

• Empty and Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags can
be set to any depth

• Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively

• Output enable puts output data bus in high-impedance
state

• Advanced submicron CMOS technology

• Available in 32-pin plastic leaded chip carrier (PLCC)

o

• Industrial temperature range (-40

C to +85oC) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT72251 SyncFIFO is a very high-speed, low­power First-In, First-Out (FIFO) memory with clocked read
and write controls. The IDT72251 has a 8192 x 9-bit memory
array. This FIFO is applicable for a wide variety of data
buffering needs such as graphics, local area networks and

interprocessor communication.

This FIFO has a 9-bit input and output port. The input port
is controlled by a free-running clock (WCLK), and two write
enable pins (

WEN1

, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (

REN2

). The read clock can be tied to the write clock for single

REN1

clock operation or the two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.

The Synchronous FIFO has two fixed flags, Empty (EF) and
Full (FF). Two programmable flags, Almost-Empty (
Almost-Full (

PAF

), are provided for improved system control.

PAE

) and

The programmable flags default to Empty+7 and Full-7 for

PAE

and

PAF

, respectively. The programmable flag offset
loading is controlled by a simple state machine and is initiated
by asserting the load pin (LD).

The IDT72251 is fabricated using IDT’s high-speed

submicron CMOS technology.

,

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN2

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

D

0

- D

8

INPUT REGISTER

RAM ARRAY

8192 x 9

OUTPUT REGISTER

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ CONTROL

LOGIC

RCLK

Q0 - Q

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

8

3545 drw 01

COMMERCIAL TEMPERATURE RANGES DECEMBER 1996

1996 Integrated Device Technology, Inc DSC-3545/-

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.14 1

IDT72251 CMOS SyncFIFO
8192 x 9 COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

2

3

4

5

6

7

INDEX

D

D
PAF
PAE

GND
REN1
RCLK
REN2

OE

DDDDD

432132 31 30

5

1

6

0

7
8
9
10
11
12
13

14 15 16 17 18 19 20

EF

FF

J32-1

Q

PLCC

TOP VIEW

8

D

D

RS

29

WEN1

28

WCLK

27

WEN2/LD

26

CC

V

25

8

Q

24

7

Q

23

6

Q

22

5

Q

21

3

2Q1Q0

Q4Q

2655 drw 02b

PIN DESCRIPTIONS

Symbol Name I/O Description

0-D8 Data Inputs I Data inputs for a 9-bit bus.

D

RS

WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write

WEN1

WEN2/

Q

0-Q8 Data Outputs O Data outputs for a 9-bit bus.

RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when

REN1

REN2

OE

EF

PAE

PAF

FF

V

CC Power One +5 volt power supply pin.

GND Ground One 0 volt ground pin.

Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,

FF

and

PAF

go HIGH, and

PAE

and EF go LOW. A reset is required before an initial WRITE after

power-up.

Enable(s) are asserted.

Write Enable 1 I If the FIFO is configured to have programmable flags,

When

WEN1

is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If

the FIFO is configured to have two write enables,

WEN1

is the only write enable pin.

WEN1

must be LOW and WEN2 must be

HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW.

LD

Write Enable 2/ I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
Load

LD

is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables,

WEN1

must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is config­ured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag
offsets.

REN1

and

REN2

asserted.

Read Enable 1 I When

REN1

and

REN2

are LOW, data is read from the FIFO on every LOW-to-HIGH transition

of RCLK. Data will not be read from the FIFO if the EF is LOW.

Read Enable 2 I When

REN1

and

REN2

are LOW, data is read from the FIFO on every LOW-to-HIGH transition

of RCLK. Data will not be read from the FIFO if the EF is LOW.

Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a

high-impedance state.

Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When

EF

is HIGH, the FIFO is not empty. EF is synchronized to RCLK.

Programmable O When
Almost-Empty The default offset at reset is Empty+7.

PAE

is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.

PAE

is synchronized to RCLK.

Flag
Programmable O When

Almost-Full Flag default offset at reset is Full-7.

PAF

is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The

PAF

is synchronized to WCLK.

Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is

HIGH, the FIFO is not full. FF is synchronized to WCLK.

are

2655 tbl 01

5.14 2

IDT72251 CMOS SyncFIFO
8192 x 9 COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Unit

TERM Terminal Voltage –0.5 to +7.0 V

V

with Respect to
GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

STG Storage –55 to +125 °C

T

Temperature

OUT DC Output 50 mA

I

Current

2655 tbl 02

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C)

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CCC Commercial 4.5 5.0 5.5 V

Supply Voltage

GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — — V

V

Commercial

IL Input Low Voltage — — 0.8 V

V

Commercial

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter Conditions Max. Unit

(2)

C

IN
OUT

C

NOTES:

1. With output deselected (OE = HIGH).

2. Characterized values, not currently tested.

Input Capacitance VIN = 0V 10 pF

(1,2)

Output Capacitance VOUT = 0V 10 pF

IDT72251

Commercial

tCLK = 15, 20, 25, 35

Symbol Parameter Min. Typ. Max. Unit

(1)

LI

I

(2)

I

LO

V

OH Output Logic “1” Voltage, IOH = –2mA 2.4 — — V
OL Output Logic “0” Voltage, IOL = 8mA — — 0.4 V

V

(4)

I

CC1

NOTES:

1. Measurements with 0.4 ≤ V

2.

3 & 4. Measurements are made with outputs unloaded. Tested at f

IH, 0.4 ≤ VOUT ≤ VCC.

OE

≥ V

(3) Typical I
(4) Typical I

CLK = 1/tCLK.

f

CL = external capacitive load (30pF typical)

Input Leakage Current (Any Input) -1 — 1 µA
Output Leakage Current -10 — 10 µA

Active Power Supply Current — — 80 mA

IN ≤ VCC.

CLK = 20MHz.

CC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA
CC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA

5.14 3

IDT72251 CMOS SyncFIFO
8192 x 9 COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C

Commercial

72251L15 72251L20 72251L25 72251L35

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

f

S Clock Cycle Frequency — 66.7 — 50 — 40 — 28.6 MHz

t

A Data Access Time 2 10 2 12 3 15 3 20 ns

t

CLK Clock Cycle Time 15 — 20 — 25 — 35 — ns

t

CLKH Clock HIGH Time 6 — 8 — 10 — 14 — ns

t

CLKL Clock LOW Time 6 — 8 — 10 — 14 — ns

t

DS Data Set-up Time 4 — 5 — 6 — 8 — ns

t

DH Data Hold Time 1 — 1 — 1 — 2 — ns

t

ENS Enable Set-up Time 4 — 5 — 6 — 8 — ns

t

ENH Enable Hold Time 1 — 1 — 1 — 2 — ns

t

RS Reset Pulse Width

t

RSS Reset Set-up Time 15 — 20 — 25 — 35 — ns

t

RSR Reset Recovery Time 15 — 20 — 25 — 35 — ns

t

RSF Reset to Flag Time and Output Time — 15 — 20 — 25 — 35 ns

t

OLZ Output Enable to Output in Low-Z

t

OE Output Enable to Output Valid 3 8 3 10 3 13 3 15 ns

t

OHZ Output Enable to Output in High-Z

t

WFF Write Clock to Full Flag — 10 — 12 — 15 — 20 ns

t

REF Read Clock to Empty Flag — 10 — 12 — 15 — 20 ns

t

PAF Write Clock to Programmable Almost-Full Flag — 10 — 12 — 15 — 20 ns

t

PAE Read Clock to Programmable Almost-Empty Flag — 10 — 12 — 15 — 20 ns

t

SKEW1 Skew Time Between Read Clock and Write Clock 6 — 8 — 10 — 12 — ns

for Empty Flag and Full Flag

SKEW2 Skew Time Between Read Clock and Write Clock 28 — 35 — 40 — 42 — ns

t

for Programmable Almost-Empty Flag and
Programmable Almost-Full Flag

NOTES:

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

(1)

(2)

(2)

15 — 20 — 25 — 35 — ns

0— 0— 0 — 0— ns

3 8 310 3 13 315ns

AC TEST CONDITIONS

In Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1

5V

1.1K

D.U.T.

680

Ω

30pF*

or equivalent circuit

Figure 1. Output Load

2655 tbl 09

5.14 4

*Includes jig and scope capacitances.

2655 drw 03

IDT72251 CMOS SyncFIFO
8192 x 9 COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS

INPUTS:

Data In (D

CONTROLS:

Reset (

(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full Flag
(

PAF

) will be reset to HIGH after t
Programmable Almost-Empty Flag (
after tRSF. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.

Write Clock (WCLK) — A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data set­up and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Programmable Almost-Full Flag (
respect to the LOW-to-HIGH transition of the write clock
(WCLK).

The write and read clocks can be asynchronous or
coincident.

Write Enable 1 (

programmable flags, Write Enable 1 (
enable control pin. In this configuration, when Write Enable 1
(

WEN1

RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.

In this configuration, when Write Enable 1 (
the input register holds the previous data and no new data is
allowed to be loaded into the register.

If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.

To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after t
allowing a valid write to begin. Write Enable 1 (
ignored when the FIFO is full.

Read Clock (RCLK) — Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (EF) and Programmable Almost-Empty Flag (
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).

The write and read clocks can be asynchronous or
coincident.

0 - D8) — Data inputs for 9-bit wide data.

RSRS) — Reset is accomplished whenever the Reset

RSF. The Empty Flag (

PAE

) will be reset to LOW

PAF

) are synchronized with

WEN1

) — If the FIFO is configured for

WEN1

WEN1

EF

) and

) is the only

) is low, data can be loaded into the input register and

WEN1

) is HIGH,

WFF,

WEN1

) is

PAE

Read Enables (

(

REN1, REN2

REN1

,

REN2

REN1

) — When both Read Enables

REN2

) are LOW, data is read from the RAM array to
the output register on the LOW-to-HIGH transition of the read
clock (RCLK).

When either Read Enable (

REN1, REN2

) is HIGH, the
output register holds the previous data and no new data is
allowed to be loaded into the register.

When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
The Read Enables (

REN1, REN2

) are ignored when the FIFO

is empty.

Output Enable (

OEOE) — When Output Enable (OE) is

enabled (LOW), the parallel output buffers receive data from
the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.

Write Enable 2/Load (WEN2/

LLDD) — This is a dual-purpose

pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows depth
expansion. If Write Enable 2/Load (WEN2/LD) is set high at
Reset (

RS

= LOW), this pin operates as a second write enable

pin.

If the FIFO is configured to have two write enables, when
Write Enable (

LD

) is HIGH, data can be loaded into the input register and

WEN1

) is LOW and Write Enable 2/Load (WEN2/

RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.

In this configuration, when Write Enable (

WEN1

) is HIGH
and/or Write Enable 2/Load (WEN2/LD) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.

To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after t
allowing a valid write to begin. Write Enable 1 (

WEN1

) and Write

Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.

The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/LD) is set LOW at Reset
(RS=low). The IDT7225 device contain four 8-bit offset
registers which can be loaded with data on the inputs, or read
on the outputs. See Figure 3 for details of the size of the
registers and the default values.

If the FIFO is configured to have programmable flags when
the Write Enable 1 (

LD

) are set low, data on the inputs D is written into the Empty

WEN1

) and Write Enable 2/Load (WEN2/

(Least Significant Bit) offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). Data is written into the
Empty (Most Significant Bit) offset register on the second
LOW-to-HIGH transition of the write clock (WCLK), into the

)

Full (Least Significant Bit) offset register on the third transition,
and into the Full (Most Significant Bit) offset register on the
fourth transition. The fifth transition of the write clock (WCLK)
again writes to the Empty (Least Significant Bit) offset register.

WFF,

5.14 5

IDT72251 CMOS SyncFIFO
8192 x 9 COMMERCIAL TEMPERATURE RANGES

However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing the Write Enable 2/Load (WEN2/LD) pin HIGH, the
FIFO is returned to normal read/write operation. When the
Write Enable 2/Load (WEN2/LD) pin is set LOW, and Write
Enable 1 (

WEN1

) is LOW, the next offset register in sequence

is written.

The contents of the offset registers can be read on the
output lines when the Write Enable 2/Load (WEN2/LD) pin is
set low and both Read Enables (

REN1, REN2

) are set LOW.
Data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).

A read and write should not be performed simultaneously

to the offset registers.

OUTPUTS:

Full Flag (

FFFF) — The Full Flag (FF) will go LOW, inhibiting

further write operation, when the device is full. If no reads are
performed after Reset (RS), the Full Flag (FF) will go LOW
after 8192 writes for the IDT72251.

The Full Flag (FF) is synchronized with respect to the LOW-

to-HIGH transition of the write clock (WCLK).

Empty Flag (

EFEF) — The Empty Flag (EF) will go LOW,

inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.

The Empty Flag (EF) is synchronized with respect to the

LOW-to-HIGH transition of the read clock (RCLK).

Programmable Almost-Full Flag (

Programmable Almost-Full Flag (

PAF

) will go LOW when the

PAF

PAF

) — The

FIFO reaches the Almost-Full condition. If no reads are
performed after Reset (RS), the Programmable Almost-Full
Flag (

PAF

) will go LOW after 8192 writes for the IDT72251.

The offset “m” is defined in the Full offset registers.

If there is no Full offset specified, the Programmable

Almost-Full Flag (

The Programmable Almost-Full Flag (

PAF

) will go LOW at Full-7 words.

PAF

) is synchronized
with respect to the LOW-to-HIGH transition of the write clock
(WCLK).

LD WEN1 WCLK

0 0 Empty Offset (LSB)

0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation

NOTE:

1. The same selection sequence applies to reading from the registers.
and

REN2

transition of RCLK.

87 0

84 0

87 0

84 0

are enabled and read is performed on the LOW-to-HIGH

Figure 2. Write Offset Register

Figure 3. Offset Register Location and Default Values

(1)

Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)

72251 — 8192 x 9-BIT

Empty Offset (LSB)

Default Value 007H

Full Offset (LSB)

Default Value 007H

Selection

REN1

(MSB)
00000

(MSB)
00000

Programmable Almost-Empty Flag (

Programmable Almost-Empty Flag (

PAE

PAE

) — The

PAE

) will go LOW when
the read pointer is "n+1" locations less than the write pointer.
The offset "n" is defined in the Empty offset registers. If no
reads are performed after Reset the Programmable Almost­Empty Flag (

PAE

) will go HIGH after "n+1" for the IDT72251.

If there is no Empty offset specified, the Programmable

Almost-Empty Flag (

The Programmable Almost-Empty Flag (

PAE

) will go LOW at Empty+7 words.

PAE

) is
synchronized with respect to the LOW-to-HIGH transition of
the read clock (RCLK).

Data Outputs (Q0 - Q8) — Data outputs for a 9-bit wide

data.

TABLE 1: STATUS FLAGS

NUMBER OF WORDS

IN FIFO

FF PAF PAE EF

0HHLL

(1)

1 to n

(n+1) to (8192-(m+1) H H H H

(8192-m)

NOTES:

1. n = Empty Offset (n = 7 default value)

2. m = Full Offset (m = 7 default value)

5.14 6

(2)

to 8191 H L H H

8192 L L H H

HHL H