Integrated Device Technology Inc IDT72205LB25TFB, IDT72205LB35G, IDT72205LB35GB, IDT72205LB35J, IDT72205LB35JB Datasheet
...
Integrated Device Technology, Inc.
CMOS SyncFIFO
256 x 18, 512 x 18, 1024 x 18, 2048 x
18 and 4096 x 18
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
FEATURES:
• 256 x 18-bit organization array (72205LB)
• 512 x 18-bit organization array (72215LB)
• 1024 x 18-bit organization array (72225LB)
• 2048 x 18-bit organization array (72235LB)
• 4096 x 18-bit organization array (72245LB)
• 15 ns read/write cycle time
• Easily expandable in depth and width
• Read and write clocks can be asynchronous or coincident
• Dual-Port zero fall-through time architecture
• Programmable almost-empty and almost-full flags
• Empty and Full flags signal FIFO status
• Half-Full flag capability in a single device configuration
• Output enable puts output data bus in high-impedance
state
• High-performance submicron CMOS technology
• Available in a 64-lead thin quad flatpack (TQFP/STQFP),
pin grid array (PGA), and plastic leaded chip carrier
(PLCC)
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40
O
C to +85OC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs
are applicable for a wide variety of data buffering needs, such
as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
Both FIFOs have 18-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a data
input enable pin (
FIFO on every clock when
WEN
). Data is read into the synchronous
WEN
is asserted. The output port
is controlled by another clock pin (RCLK) and another enable
pin (
REN
). The read clock can be tied to the write clock for
single clock operation or the two clocks can run asynchronous
of one another for dual-clock operation. An Output Enable pin
(OE) is provided on the read port for three-state control of the
output.
The synchronous FIFOs have two fixed flags, Empty (EF)
and Full (FF), and two programmable flags, Almost-Empty
(
PAE
) and Almost-Full (
PAF
). The offset loading of the programmable flags is controlled by a simple state machine, and
is initiated by asserting the Load pin (LD). A Half-Full flag (HF)
is available when the FIFO is used in a single device configuration.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
are depth expandable using a daisy-chain technique. The XI
and XO pins are used to expand the FIFOs. In depth expansion configuration, FL is grounded on the first device and set
to HIGH for all other devices in the daisy chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is
fabricated using IDT’s high-speed submicron CMOS technology. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WEN
WRITE CONTROL
WRITE POINTER
FL
WXI
(HF)/
WXO
RXI
RXO
RS
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc
EXPANSION LOGIC
RESET LOGIC
WCLK D0-D17
INPUT REGISTER
LOGIC
256 x 18, 512 x 18
1024 x 18, 2048 x 18
OUTPUT REGISTER
OE
•
•
RAM ARRAY
4096 x 18
•
•
Q0-Q17
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
RCLK
MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1996
1996 Integrated Device Technology, Inc. DSC-2766/7
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.16 1
REN
LD
FF
PAF
EF
PAE
HF/(WXO
2766 drw 01
)
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
WXO
11
VCC
Q
3
GND
Q
0
HF
/
VCC
WEN
FLRXI
FF WXI
G68-1
RSEFLD
OE
PAF
RCLK
REN
Q1Q2
10
09
08
07
06
05
04
03
02
Q4
GND
Q6 Q5
Q7
VCC
GND
Q10 Q9
VCC
Q11
Q12
GND
Q14 Q13
V
CC
Q8
Q16Q15
01 GND GND
RXO
Pin 1 Designator
GND
VCC
VCCQ17
PAE
WCLK
GND
VCC
D17 D14
D16
D2
D6
D10
D12
D15
ABCDEFGHJKL
PGA
TOP VIEW
D0
D1
D3D4
D5
D7
D8
D9
D11
D13
2766 drw 02
D14
D13
D12
D11
D10
D9
VCC
D8
GND
D
D6
D5
D4
D3
D2
D1
D0
D16
GND
D17
RCLK
D15
98765432
10
RENLDOE
RS
GND
EF
VCC
6867666564636261
1
11
12
13
14
15
16
17
18
7
19
J68-1
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39404142 43
PAE
FL
WEN
WCLK
WXI
CC
V
PAF
RXI
FF
HF
/
RXO
0
Q
WXO
CC
V
Q1
Q17
Q16
2
Q
GND
15
GND
Q
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Q3
VCC
VCC
Q14
Q13
GND
Q
12
Q11
VCC
Q10
Q9
GND
8
Q
Q7
VCC
Q6
Q5
GND
Q
4
2766 drw 03
PLCC
TOP VIEW
5.16 2
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
PIN 1
15
D
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16
D
17
D
GND
REN
RCLK
LDOERS
VCCGND
EF
17Q16
Q
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
PN 64-1
PP64-1
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
15
Q
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CC
V
Q14
Q13
GND
12
Q
Q11
VCC
Q10
Q9
GND
Q
8
Q7
Q6
Q5
GND
4
Q
VCC
FL
PAE
NOTE:
1. For information on the flatpack (F68-1), contact factory.
WEN
WCLK
CC
V
WXI
TQFP/STQFP
TOP VIEW
PAF
RXI
FF
HF
/
WXO
RXO
0Q1
Q
GND
3
2
Q
Q
2766 drw 04
5.16 3
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol Name I/O Description
D0–D17 Data Inputs I Data inputs for a 18-bit bus.
RS
WCLK Write Clock I When
WEN
RCLK Read Clock I When
REN
OE
LD
FL
WXI
RXI
EF
PAE
PAF
FF
WXO/HF
RXO
Q0–Q17 Data Outputs O Data outputs for a 18-bit bus.
VCC Power Eight +5V power supply pins for the PLCC and PGA, five pins for the TQFP.
GND Ground Eight ground pins for the PLCC and PGA, seven pins for the TQFP.
Reset I When RS is set LOW, internal read and write pointers are set to the first location of the
RAM array, FF and
PAF
go HIGH, and
PAE
and EF go LOW. A reset is required before an
initial WRITE after power-up.
WEN
is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,
if the FIFO is not full.
Write Enable I When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of
WCLK. When
WEN
is HIGH, the FIFO holds the previous data. Data will not be written
into the FIFO if the FF is LOW.
REN
is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if
the FIFO is not empty.
Read Enable I When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of
RCLK. When
REN
is HIGH, the output register holds the previous data. Data will not be
read from the FIFO if the EF is LOW.
Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will
be in a high-impedance state.
Load I When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers
on the LOW-to-HIGH transition of the WCLK, when
WEN
is LOW. When LD is LOW,
data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-toHIGH transition of the RCLK, when
REN
is LOW.
First Load I In the single device or width expansion configuration, FL is grounded. In the depth
expansion configuration, FL is grounded on the first device (first load device) and set to
HIGH for all other devices in the daisy chain.
Write Expansion I In the single device or width expansion configuration,
Input expansion configuration,
WXI
is connected to
WXO
WXI
is grounded. In the depth
(Write Expansion Out) of the
previous device.
Read Expansion I In the single device or width expansion configuration, RXI is grounded. In the depth
Input expansion configuration,
RXI
is connected to
RXO
(Read Expansion Out) of the previous
device.
Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited.
When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
Programmable O When
PAE
is LOW, the FIFO is almost empty based on the offset programmed into the
Almost-Empty Flag FIFO. The default offset at reset is 31 from empty for 72205LB, 63 from empty for
72215LB, and 127 from empty for 72225LB/72235LB/72245LB.
Programmable O When
PAF
is LOW, the FIFO is almost full based on the offset programmed into the FIFO.
The default offset at reset is 31 from full for 72205LB, 63 from full for 72215LB, and
127 from full for 72225LB/72235LB/72245LB.
Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited.
When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK.
Write Expansion O In the single device or width expansion configuration, the device is more than half full
Out/Half-Full Flag when HF is LOW. In the depth expansion configuration, a pulse is sent from
WXI
of the next device when the last location in the FIFO is written.
Read Expansion O In the depth expansion configuration, a pulse is sent from
RXO
to
RXI
WXO
to
of the next device
Out when the last location in the FIFO is read.
2766 tbl 01
5.16 4
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Commercial MIilitary Unit
V
TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with respect to GND
T
A Operating 0 to +70 –55 to +125 °C
Temperature
T
BIAS Temperature Under –55 to +125 –65 to +135 °C
Bias
STG Storage –55 to +125 –65 to +155 °C
T
Temperature
I
OUT DC Output Current 50 50 mA
NOTE: 2766 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maimum rating conditions for extended
(1)
RECOMMENDED DC
OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
CCM Military Supply 4.5 5.0 5.5 V
V
Voltage
V
CCC Commercial Supply 4.5 5.0 5.5 V
Voltage
GND Supply Voltage 0 0 0 V
V
IH Input High Voltage 2.0 — — V
Commercial
V
IH Input High Voltage 2.2 — — V
Military
(1)
IL
V
NOTE: 2766 tbl 03
1. 1.5V undershoots are allowed for 10ns once per cycle.
Input Low Voltage — — 0.8 V
Commercial & Military
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
IDT72205LB IDT72205LB
IDT72215LB IDT72215LB
IDT72225LB IDT72225LB
Commercial Military
CLK = 15, 20, 25, 35, 50ns tCLK = 25, 35, 50ns
t
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
(1)
ILI
ILO
VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V
VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V
ICC1
ICC2
Input Leakage Current (any input) –1 — 1 –10 — 10 µA
(2)
Output Leakage Current –10 — 10 –10 — 10 µA
(3)
Active Power Supply Current — — 200 — — 250 mA
(3)
Average Standby Current (All Input = VCC – 0.2V, — — 70 — — 85 mA
except RCLK and WCLK which are free-running)
IDT72235LB IDT72235LB
IDT72245LB IDT72245LB
Commercial Military
CLK = 15, 20, 25, 35, 50ns tCLK = 25, 35, 50ns
t
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
(1)
I
LI
(2)
LO
I
OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V
V
OL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V
V
I
CC1
CC2
I
Input Leakage Current (any input) –1 — 1 –10 — 10 µA
Output Leakage Current –10 — 10 –10 — 10 µA
(4)
Active Power Supply Current — — 200 — — 250 mA
(4)
Average Standby Current (All Input = VCC – 0.2V, — — 70 — — 85 mA
except RCLK and WCLK which are free-running)
NOTES: 2766 tbl 04
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ V
3 & 4. Tested at f = 20MHz with outputs unloaded.
IH, 0.4 ≤ VOUT ≤ VCC.
(3) Typical Icc
(4 ) Typical Icc
CLK = 1/tCLK, CL = external capacitive load (30 pF typical)
f
1 = 60 + (fCLK*0.57/MHz) + (fCLK*CL*0.02/MHz-pF) mA
1 = 80 + (fCLK + 0.73/MHz) + (fCLK*CL*0.02/MHz-pF) mA
5.16 5
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
(2)
C
IN
Input VIN = 0V 10 pF
Capacitance
(1,2)
C
OUT
Output VOUT = 0V 10 pF
Capacitance
NOTES: 2766 tbl 05
1. With output deselected, (
2. Characterized values, not currently tested.
(1)
Conditions Max. Unit
OE
= HIGH).
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial Commercial and Military
72205LB15 72205LB20 72205LB25 72205LB35 72205LB50
72215LB15 72215LB20 72215LB25 72215LB35 72215LB50
72225LB15 72225LB20 72225LB25 72225LB35 72225LB50
72235LB15 72235LB20 72235LB25 72235LB35 72235LB50
72245LB15 72245LB20 72245LB25 72245LB35 72245LB50
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
f
S Clock Cycle Frequency — 66.7 — 50 — 40 — 28.6 — 20 MHz
t
A Data Access Time 2 10 2 12 3 15 3 20 3 25 ns
t
CLK Clock Cycle Time 15 — 20 — 25 — 35 — 50 — ns
t
CLKH Clock HIGH Time 6.5 — 8 — 10 — 14 — 20 — ns
t
CLKL Clock LOW Time 6.5 — 8 — 10 — 14 — 20 — ns
t
DS Data Set-up Time 4 — 5 — 6 — 7 — 10 — ns
t
DH Data Hold Time 1 — 1 — 1 — 2 — 2 — ns
t
ENS Enable Set-up Time 4 — 5 — 6 — 7 — 10 — ns
t
ENH Enable Hold Time 1 — 1 — 1 — 2 — 2 — ns
t
RS Reset Pulse Width
t
RSS Reset Set-up Time 10 — 12 — 15 — 20 — 30 — ns
t
RSR Reset Recovery Time 10 — 12 — 15 — 20 — 30 — ns
t
RSF Reset to Flag and Output Time — 35 — 35 — 40 — 45 — 50 ns
t
OLZ Output Enable to Output in Low-Z
t
OE Output Enable to Output Valid — 8 — 9 — 12 — 15 — 20 ns
t
OHZ Output Enable to Output in High-Z
t
WFF Write Clock to Full Flag — 10 — 12 — 15 — 20 — 30 ns
t
REF Read Clock to Empty Flag — 10 — 12 — 15 — 20 — 30 ns
t
PAF Clock to Programmable — 28 — 30 — 35 — 40 — 40 ns
Almost-Full Flag
t
PAE Clock to Programmable — 28 — 30 — 35 — 40 — 40 ns
Almost-Empty Flag
t
HF Clock to Half-Full Flag — 28 — 30 — 35 — 40 — 40 ns
t
XO Clock to Expansion Out — 10 — 12 — 15 — 20 — 30 ns
t
XI Expansion In Pulse Width 6.5 — 8 — 10 — 14 — 20 — ns
t
XIS Expansion In Set-Up Time 5 — 8 — 10 — 15 — 20 — ns
t
SKEW1 Skew time between Read Clock & 10 — 14 — 16 — 18 — 20 — ns
Write Clock for Full Flag
SKEW2 Skew time between Read Clock & 10 — 14 — 16 — 18 — 20 — ns
t
Write Clock for Empty Flag
NOTES: 2766 tbl 06
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
(1)
15 — 20 — 25 — 35 — 50 — ns
(2)
0—0—0— 0—0—ns
(2)
1 8 1 9 1 12 1 15 1 20 ns
5.16 6
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
2766 tbl 07
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D
Data inputs for 18-bit wide data.
CONTROLS:
RESET (
Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and
write pointers are set to the first location. A reset is required
after power-up before a write operation can take place. The
Full Flag (FF), Half-Full Flag (HF), and Programmable AlmostFull Flag (
Flag (EF) and Programmable Almost-Empty Flag (
reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to
their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of
the write clock (WCLK). Data set-up and hold times must be
met with respect to the LOW-to-HIGH transition of the write
clock (WCLK).
The write and read clocks can be asynchronous or
coincident.
0 - D17)
RSRS)
PAF
) will be reset to HIGH after t
RSF. The Empty
PAE
) will be
5V
1.1K
D.U.T.
680Ω
Figure 1. Output Load
* Includes jig and scope capacitances.
30pF*
2766 drw 05
The write and read clocks can be asynchronous or
coincident.
READ ENABLE (
When Read Enable (
REN
REN
)
REN
) is LOW, data is loaded from the
RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK).
When
REN
is HIGH, the output register holds the previous
data and no new data is loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
a write is performed, the EF will go HIGH after t
can begin.
OUTPUT ENABLE (
REN
is ignored when the FIFO is empty.
OEOE)
REF and a read
When Output Enable (OE) is enabled (LOW), the parallel
output buffers receive data from the output register. When
OE
is disabled (HIGH), the Q output data bus is in a highimpedance state.
LOAD (
LDLD)
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
devices contain two 12-bit offset registers with data on the
inputs, or read on the outputs. When the Load (LD) pin is set
LOW and
WEN
is set LOW, data on the inputs D0-D11 is
written into the Empty offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). When the LD pin and
WRITE ENABLE (
When Write Enable (
WEN
WEN
)
WEN
) is LOW, data can be loaded into
the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM
array sequentially and independently of any on-going read
operation.
When
WEN
is HIGH, the input register holds the previous
data and no new data is loaded into the FIFO.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the FF will go HIGH after t
to begin.
WEN
is ignored when the FIFO is full.
WFF allowing a write
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH
transition of the read clock (RCLK), when Output Enable (OE)
is set LOW.
LD WEN WCLK
0 0 Writing to offset registers:
0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation
NOTE: 2766 tbl 08
1. The same selection sequence applies to reading from the registers.
is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
5.16 7
(1)
Empty Offset
Full Offset
Figure 2. Write Offset Register
Selection
REN
Loading...