Integrated Device Technology Inc. IDT72021, IDT72031, IDT72041 User Manual

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Integrated Device Technology, Inc.

CMOS SUPERSYNC FIFO™
8,192 x 18
16,384 x 18

IDT72255LA
IDT72265LA

FEATURES:

• Choose among the following memory organizations:
IDT72255LA 8,192 x 18
IDT72265LA 16,384 x 18

• Pin-compatible with the IDT72275/72285 SuperSync FIFOs

• 10ns read/write cycle time (8ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each

flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

•

Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

FUNCTIONAL BLOCK DIAGRAM

WCLK

D0 -D

• Independent Read and Write clocks (permit reading and
writing simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the
64-pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT72255LA/72265LA are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with clocked
read and write controls. These FIFOs offer numerous improve­ments over previous SuperSync FIFOs, including the following:

• The limitation of the frequency of one clock input with

respect to the other has been removed. The Frequency
Select pin (FS) has been removed, thus it is no longer
necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed

and short.

17

INPUT REGISTER

WRITE CONTROL

LOGIC

RAM ARRAY

8,192 x 18

WRITE POINTER

RESET

LOGIC

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

16,384 x 18

OUTPUT REGISTER

Q0 -Q

17

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ

CONTROL

LOGIC

/
/

FWFT/SI

RCLK

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DESCRIPTION (Continued)

• The first word data latency period, from the time the first
word is written to an empty FIFO to the time it can be read,
is now fixed and short. (The variable clock cycle counting
delay associated with the latency period found on previous
SuperSync devices has been eliminated on this SuperSync
family.)

SuperSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other
applications that need to buffer large amounts of data.

The input port is controlled by a Write Clock (WCLK) input
and a Write Enable (
on every rising edge of WCLK when

WEN

) input. Data is written into the FIFO

WEN

is asserted. The
output port is controlled by a Read Clock (RCLK) input and
Read Enable (
rising edge of RCLK when

REN

) input. Data is read from the FIFO on every

REN

is asserted. An Output Enable

(OE) input is provided for three-state control of the outputs.

PIN CONFIGURATIONS

WCLK

FWFT/SI

GND

The frequencies of both the RCLK and the WCLK signals
may vary from 0 to fMAX with complete independence. There
are no restrictions on the frequency of one clock input with
respect to the other.

There are two possible timing modes of operation with
these devices: IDT Standard mode and First Word Fall Through
(FWFT) mode.

In

IDT Standard mode,

the first word written to an empty
FIFO will not appear on the data output lines unless a specific
read operation is performed. A read operation, which consists
of activating

REN

and enabling a rising RCLK edge, will shift

the word from internal memory to the data output lines.

In

FWFT mode,

the first word written to an empty FIFO is
clocked directly to the data output lines after three transitions
of the RCLK signal. A

REN

does not have to be asserted for
accessing the first word. However, subsequent words written
to the FIFO do require a LOW on

/

VCC

/

RCLK

REN

for access. The state

PIN 1

DC

V

CC

GND

D17
D16
D15
D14
D13
D12
D11
D10

D9
D8
D7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

Q17
Q16
GND
Q15
Q14
V

CC

Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND

D6

D5

D4

D3

D2

D1

D0

GND

Q0

Q1

TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)

TOP VIEW

GND

Q2

Q3

CC

V

Q4

Q5

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DESCRIPTION (Continued)

of the FWFT/SI input during Master Reset determines the
timing mode in use.

For applications requiring more data storage capacity than
a single FIFO can provide, the FWFT timing mode permits
depth expansion by chaining FIFOs in series (i.e. the data
outputs of one FIFO are connected to the corresponding data
inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or
Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full
Flag),

PAE

(Programmable Almost-Empty flag) and
grammable Almost-Full flag). The EF and FF functions are
selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF,
available for use, irrespective of timing mode.

PAE

and

PAF

can be programmed independently to switch
at any point in memory. (See Table I and Table II.) Program­mable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, so that
switch at 127 or 1,023 locations from the empty boundary and
the

PAF

threshold can be set at 127 or 1,023 locations from the
full boundary. These choices are made with the LD pin during
Master Reset.

For serial programming,
rising edge of WCLK, are used to load the offset registers via
the Serial Input (SI). For parallel programming,
with LD on each rising edge of WCLK, are used to load the
offset registers via Dn.
edge of RCLK can be used to read the offsets in parallel from

REN

PAE

and

PAF

PAE

SEN

together with LD on each

together with LD on each rising

PAF

(Pro-

are always

can be set to

WEN

together

Qn regardless of whether serial or parallel offset loading has
been selected.

During Master Reset (
The read and write pointers are set to the first location of the
FIFO. The FWFT pin selects IDT Standard mode or FWFT
mode. The LD pin selects either a partial flag default setting
of 127 with parallel programming or a partial flag default
setting of 1,023 with serial programming. The flags are
updated according to the timing mode and default offsets
selected.

The Partial Reset (
pointers to the first location of the memory. However, the
timing mode, partial flag programming method, and default or
programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the
timing mode and offsets in effect.
a device in mid-operation, when reprogramming partial flags
would be undesirable.

The Retransmit function allows data to be reread from the
FIFO more than once. A LOW on the RT input during a rising
RCLK edge initiates a retransmit operation by setting the read
pointer to the first location of the memory array.

If, at any time, the FIFO is not actively performing an
operation, the chip will automatically power down. Once in the
power down state, the standby supply current consumption is
minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down
state.

The IDT72255LA/72265LA are fabricated using IDT’s high
speed submicron CMOS technology.

MRS

) the following events occur:

PRS

) also sets the read and write

PRS

is useful for resetting

PARTIAL RESET ( )

WRITE CLOCK (WCLK)

WRITE ENABLE (

LOAD (

DATA IN (D

0

- Dn)

SERIAL ENABLE( )

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

FULL FLAG/INPUT READY (

/ )

PROGRAMMABLE ALMOST-FULL (

Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO

)

)

)

MASTER RESET ( )

READ CLOCK (RCLK)
READ ENABLE (

OUTPUT ENABLE (

DATA OUT (Q0 - Qn)

IDT
72255LA
72265LA

RETRANSMIT ( )
EMPTY FLAG/OUTPUT READY (
PROGRAMMABLE ALMOST-EMPTY (

HALF FULL FLAG ( )

)

)

/ )

)

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol Name I/O Description

D0–D17 Data Inputs I Data inputs for a 18-bit bus.

MRS

PRS

RT

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode.

WCLK Write Clock I When enabled by

WEN

RCLK Read Clock I When enabled by

REN
OE
SEN
LD

DC Don't Care I This pin must be tied to either VCC or GND and must not toggle after Master

FF/IR

EF/OR

PAF

PAE

HF

Q0–Q17 Data Outputs O Data outputs for an 18-bit bus.
VCC Power +5 Volt power supply pins.
GND Ground Ground pins.

Master Reset I

MRS

initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.

Partial Reset I

PRS

initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.

Retransmit I

RT

asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.

Through/Serial In After Master Reset, this pin functions as a serial input for loading offset registers

WEN

, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by

SEN

, the rising edge of WCLK writes one bit of data into the

programmable register for serial programming.

Write Enable I

WEN

enables WCLK for writing data into the FIFO memory and offset registers.

REN

, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

Read Enable I

REN

enables RCLK for reading data from the FIFO memory and offset registers.
Output Enable I OE controls the output impedance of Qn.
Serial Enable I

SEN

enables serial loading of programmable flag offsets.

Load I During Master Reset, LD selects one of two partial flag default offsets (127 or

1,023) and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers.

Reset.

Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or
Input Ready not the FIFO memory is full. In the FWFT mode, the IR function is selected.

indicates whether or not there is space available for writing to the FIFO memory.

Empty Flag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or
Output Ready not the FIFO memory is empty. In FWFT mode, the OR function is selected.

OR

indicates whether or not there is valid data available at the outputs.

Programmable O

PAF

goes LOW if the number of words in the FIFO memory is more than

Almost-Full Flag total word capacity of the FIFO minus the full offset value m, which is stored in the

Full Offset register. There are two possible default values for m: 127 or 1,023.

Programmable O

PAE

goes LOW if the number of words in the FIFO memory is less than offset n,

Almost-Empty Flag which is stored in the Empty Offset register. There are two possible default values

for n: 127 or 1,023. Other values for n can be programmed into the device.

Half-Full Flag O

HF

indicates whether the FIFO memory is more or less than half-full.

IR

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IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Com’l & Ind’l Unit

V

TERM Terminal Voltage –0.5 to +7.0 V

with respect to GND

STG Storage –55 to +125 °C

T

Temperature

OUT DC Output Current –50 to +50 mA

I

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex­tended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

Commercial/Industrial
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.0 — — V

Commercial/Industrial

(1)

V

IL

Input Low Voltage — — 0.8 V

Commercial/Industrial

A Operating Temperature 0 — 70 °C

T

Commercial
T

A Operating Temperature –40 — 85 °C

Industrial

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C )

IDT72255LA
IDT72265LA

Commercial & Industrial

tCLK = 10, 15, 20 ns

(1)

Symbol Parameter Min. Max. Unit

(2)

ILI
I

LO

(3)

Input Leakage Current –1 1 µA

Output Leakage Current –10 10 µA
VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — V
V

OL Output Logic “0” Voltage, IOL = 8 mA — 0.4 V

(4,5,6)

I

CC1

(4,7)

CC2

I

NOTES:

1. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.

2. Measurements with 0.4 ≤ VIN ≤ VCC.

3.OE

≥ VIH, 0.4 ≤ VOUT ≤ VCC.

4. Tested with outputs disabled (IOUT = 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical I
data switching at f

7. All Inputs = V

Active Power Supply Current — 80 mA
Standby Current — 20 mA

CC1 = 15 + 2.1*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels),

S/2, CL = capacitive load (in pF).

CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2)

C

IN

Input VIN = 0V 10 pF
Capacitance

(1,2)

C

OUT

Output VOUT = 0V 10 pF
Capacitance

NOTES:

1. With output deselected, (OE ≥ V

2. Characterized values, not currently tested.

(1)

Conditions Max. Unit

IH).

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IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C )

Commercial Com’l & Ind’l

IDT72255LA10 IDT72255LA15 IDT72255LA20
IDT72265LA10 IDT72265LA15 IDT72265LA20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

S Clock Cycle Frequency — 100 — 66.7 — 50 MHz

f

A Data Access Time 2 8 2 10 2 12 ns

t

CLK Clock Cycle Time 10 — 15 — 20 — ns

t

CLKH Clock High Time 4.5 — 6 — 8 — ns

t

CLKL Clock Low Time 4.5 — 6 — 8 — ns

t

DS Data Setup Time 3 — 4 — 5 — ns

t

DH Data Hold Time 0 — 1 — 1 — ns

t

ENS Enable Setup Time 3 — 4 — 5 — ns

t

ENH Enable Hold Time 0 — 1 — 1 — ns

t

LDS Load Setup Time 3 — 4 — 5 — ns

t

LDH Load Hold Time 0 — 1 — 1 — ns

t

PAF

FF

EF

PAF

PAE

or

or

(3)

(4)

(4)

IR

OR

10 — 15 — 20 — ns

0—0—0—ns

26 3 8 310ns
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
—16 — 20 — 22ns

RS Reset Pulse Width

t

RSS Reset Setup Time 10 — 15 — 20 — ns

t

RSR Reset Recovery Time 10 — 15 — 20 — ns

t

RSF Reset to Flag and Output Time — 10 — 15 — 20 ns

t

FWFT Mode Select Time 0 — 0 — 0 — ns

t

RTS Retransmit Setup Time 3 — 4 — 5 — ns

t

OLZ Output Enable to Output in Low Z

t

OE Output Enable to Output Valid 2 6 3 8 3 10 ns

t

OHZ Output Enable to Output in High Z

t

WFF Write Clock to

t

REF Read Clock to

t

PAF Write Clock to

t

PAE Read Clock to

t

HF Clock to

t

SKEW1 Skew time between RCLK and WCLK 5 — 6 — 10 — ns

t

for FF/

SKEW2 Skew time between RCLK and WCLK 12 — 15 — 20 — ns

t

for

t

SKEW3 Skew time between RCLK and WCLK 60 — 60 — 60 — ns

for EF/

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2.

Industrial temperature range product for 15ns and 20ns speed grade are available as a
standard device.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

PAE

HF

IR

and

OR

(1)

5V

1.1K

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1

D.U.T.

680Ω

Figure 2. Output Load

* Includes jig and scope capacitances.

30pF*

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL
THROUGH (FWFT) MODE

The IDT72255LA/72265LA support two different timing
modes of operation: IDT Standard mode or First Word Fall
Through (FWFT) mode. The selection of which mode will
operate is determined during Master Reset, by the state of the

FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
present in the FIFO. It also uses the Full Flag function (FF) to
indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read
Enable (

FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there is valid data at the data
outputs (Qn). It also uses Input Ready (IR) to indicate whether
or not the FIFO has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to
Qn after three RCLK rising edges,
sary. Subsequent words must be accessed using the Read
Enable (

differently depending on which timing mode is in effect.

IDT STANDARD MODE

operate in the manner outlined in Table 1. To write data into to
the FIFO, Write Enable (
the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable
Almost-Empty flag (
been loaded into the FIFO, where n is the empty offset value.
The default setting for this value is stated in the footnote of Table

1. This parameter is also user programmable. See section on
Programmable Flag Offset Loading.

assumed no read operations were taking place, the Half-Full
flag (HF) would toggle to LOW once the 4,097th word for
IDT72255LA and 8,193th word for IDT72265LA respectively
was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (
go LOW. Again, if no reads are performed, the
LOW after (8,192-m) writes for the IDT72255LA and (16,384-m)
writes for the IDT72265LA. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote
of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.

inhibiting further write operations. If no reads are performed

REN

) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then

REN

= LOW is not neces-

REN

) and RCLK.

Various signals, both input and output signals operate

In this mode, the status flags, FF,

WEN

) must be LOW. Data presented to

PAE

) will go HIGH after n + 1 words have

PAF, HF, PAE

, and

EF

If one continued to write data into the FIFO, and we

PAF

) to

PAF

will go

When the FIFO is full, the Full Flag (FF) will go LOW,

after a reset, FF will go LOW after D writes to the FIFO.
D = 8,192 writes for the IDT72255LA and 16,384 for the
IDT72265LA, respectively.

If the FIFO is full, the first read operation will cause FF to go

HIGH. Subsequent read operations will cause

PAF

and HF to
go HIGH at the conditions described in Table 1. If further read
operations occur, without write operations,

PAE

will go LOW
when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO
to become empty. When the last word has been read from the
FIFO, the EF will go LOW inhibiting further read operations.

REN

is ignored when the FIFO is empty.

When configured in IDT Standard mode, the EF and

FF

outputs are double register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be

found in Figure 7, 8 and 11.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR,

PAF, HF, PAE

, and

OR

operate in the manner outlined in Table 2. To write data into
to the FIFO,

WEN

must be LOW. Data presented to the DATA
IN lines will be clocked into the FIFO on subsequent transi­tions of WCLK. After the first write is performed, the Output
Ready (OR) flag will go LOW. Subsequent writes will continue
to fill up the FIFO.

PAE

will go HIGH after n + 2 words have
been loaded into the FIFO, where n is the empty offset value.
The default setting for this value is stated in the footnote of
Table 2. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we
assumed no read operations were taking place, the HF would
toggle to LOW once the 4,098th word for the IDT72255LA and
8,194th word for the IDT72265LA, respectively was written
into the FIFO. Continuing to write data into the FIFO will cause
the

PAF

to go LOW. Again, if no reads are performed, the

PAF

will go LOW after (8,193-m) writes for the IDT72255LA and
(16,385-m) writes for the IDT72265LA, where m is the full
offset value. The default setting for this value is stated in the
footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH,
inhibiting further write operations. If no reads are performed after
a reset, IR will go HIGH after D writes to the FIFO. D = 8,193
writes for the IDT72255LA and 16,385 writes for the IDT72265LA,
respectively. Note that the additional word in FWFT mode is due
to the capacity of the memory plus output register.

If the FIFO is full, the first read operation will cause the

IR

flag to go LOW. Subsequent read operations will cause the

PAF

and HF to go HIGH at the conditions described in Table

2. If further read operations occur, without write operations,
the

PAE

will go LOW when there are n + 1 words in the FIFO,
where n is the empty offset value. Continuing read operations
will cause the FIFO to become empty. When the last word has
been read from the FIFO, OR will go HIGH inhibiting further
read operations.

REN

is ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple
register-buffered, and the IR flag output is double register­buffered.

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IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

Relevant timing diagrams for FWFT mode can be found in

Figure 9, 10 and 12.

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable.
The IDT72255LA/72265LA has internal registers for these
offsets. Default settings are stated in the footnotes of Table 1
and Table 2. Offset values can be programmed into the FIFO
in one of two ways; serial or parallel loading method. The
selection of the loading method is done using the LD (Load)
pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled.
A HIGH on LD during Master Reset selects serial loading of
offset values and in addition, sets a default

PAE

offset value
of 3FFH (a threshold 1,023 words from the empty boundary),
and a default

PAF

offset value of 3FFH (a threshold 1,023

words from the full boundary). A LOW on LD during Master
Reset selects parallel loading of offset values, and in addition,
sets a default
from the empty boundary), and a default

PAE

offset value of 07FH (a threshold 127 words

PAF

offset value of
07FH (a threshold 127 words from the full boundary). See
Figure 3,

Offset Register Location and Default Values

.

In addition to loading offset values into the FIFO, it also

possible to read the current offset values. It is only possible to
read offset values via parallel read.

Figure 4,

quence

Programmable Flag Offset Programming Se-

, summarizes the control pins and sequence for both
serial and parallel programming modes. For a more detailed
description, see discussion that follows.

The offset registers may be programmed (and repro­grammed) any time after Master Reset, regardless of whether
serial or parallel programming has been selected.

TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE

72255LA 72265LA

0

(1)

Number of
Words in
FIFO

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

4,097 to (8,192-(m+1))

(8,192-m)

1 to n

(n+1) to 4,096

(2)

to 8,191

8,192

8,193 to (16,384-(m+1))
(16,384-m)

0

(1)

1 to n

(n+1) to 8,192

(2)

to 16,383

16,384

HHHL L
HHHLH
HHHH H
HHLHH

HLLHH

LLLHH

TABLE II –– STATUS FLAGS FOR FWFT MODE

72255LA 72265LA

0

Number of
Words in

(

1)

FIFO

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

4,098 to (8,193-(m+1))

(8,193-m)

1 to n+1

(n+2) to 4,097

8,193

(1)

to 8,192

(2)

8,194 to (16,385-(m+1))

(16,385-m)

0

1 to n+1

(n+2) to 8,193

to 16,384

16,385

LHHLH

(1)

(2)

LHHLL
LHHHL

LHLHL
LLLHL
HLL HL

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IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

72255LA – 8,192 x 18–BIT

17 0

17 0

12

EMPTY OFFSET REGISTER

07FH if is LOW at Master Reset,

3FFH if

12

07FH if

3FFH if

DEFAULT VALUE

is HIGH at Master Reset

FULL OFFSET REGISTER

DEFAULT VALUE

is LOW at Master Reset,

is HIGH at Master Reset

Figure 3. Offset Register Location and Default Values

72265LA – 16,384 x 18–BIT

17 0

17 0

13

EMPTY OFFSET REGISTER

07FH if is LOW at Master Reset,

13

07FH if

DEFAULT VALUE

3FFH if

FULL OFFSET REGISTER

3FFH if

is HIGH at Master Reset

DEFAULT VALUE

is LOW at Master Reset,
is HIGH at Master Reset

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WCLK

0

0

1

1

RCLK

X

Parallel write to registers:

Selection

Empty Offset
Full Offset

0

1

0

1

X

Parallel read from registers:

Empty Offset
Full Offset

0

1

1

0

X

Serial shift into registers:
26 bits for the 72255LA
28 bits for the 72265LA

1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

X

1

1

1

1

0

X

1

1

X

0

1

1

X

X

X

X

X

X

X

X

X

No Operation

Write Memory

Read Memory

No Operation

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

Figure 4. Programmable Flag Offset Programming Sequence

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