IDT IDT71V67603, IDT71V67803 User Manual
256K X 36, 512K X 18
A0-A18Address Inputs
Input
Synchronous
Chip Enable
Input
Synchronous
CS0,
1
Chip Selec ts
Input
Synchronous
Output Enable
Input
Asynchronous
Global Write Enable
Input
Synchronous
Byte Write Enable
Input
Synchronous
1
,
2
,
3
,
4
(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
Burst Address Advance
Input
Synchronous
Add res s S tatus (Cache Controlle r)
Input
Synchronous
Address Status (Processor)
Input
Synchronous
Li ne ar / Inte rl e av e d Bu rs t Ord e r
Input
DCZZSleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4Data In p u t / Output
I/O
Synchronous
VDD, V
DD Q
Co re Po we r, I/ O P o we r
Su ppl y
N/A
VSSGround
Su ppl y
N/A
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
IDT71V67603
IDT71V67803
Features
◆◆
◆
◆◆
256K x 36, 512K x 18 memory configurations
◆◆
◆
◆◆
Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
◆◆
◆
◆◆
LBOLBO
LBO input selects interleaved or linear burst mode
LBOLBO
◆◆
◆
◆◆
Self-timed write cycle with global write control (
write enable (
◆◆
◆
◆◆
3.3V core power supply
◆◆
◆
◆◆
Power down controlled by ZZ input
◆◆
◆
◆◆
3.3V I/O supply (VDDQ)
◆◆
◆
◆◆
Packaged in a JEDEC Standard 100-pin thin plastic quad
BWEBWE
BWE), and byte writes (
BWEBWE
BWBW
BWx)
BWBW
GWGW
GW), byte
GWGW
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V67603/7803 are high-speed SRAMs organized as
Pin Description Summary
CE
CS
256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67603/7803 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
OE
GW
BWE
BW
BW
BW
BW
ADV
ADSC
ADSP
LBO
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
5310 tbl 01
©2004 Integrated Device Technology, Inc.
SEPTEMBER 2004
1
DSC-5310/06
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
Symbol
Pin Function
I/O
Acti ve
Description
18
1
4
1
4
1
0-7
2
8-15
1
0
1
1
1
31
P4
DD
DDQ
SS
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
A0-A
ADSC
ADSP
ADV
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the
Address Status
(Cache Contro lle r)
Address Status
(Process or)
Burst Address
Advance
rising edge of CLK and
ADSC
Low o r
I LOW Synchronous Address Status from Cache Controller.
used to load the address registers with new addresses.
I LOW Synchronous Address Status from Processor.
load the address registers with new addresses.
I LOW Synchronous Address Advance.
ADV
internal burst counter, controlling burst access after the initial address is loaded. When the
Low and CE Low.
ADSP
is an active LOW input that is
ADSC
is an ac tiv e LO W inp u t that is us e d to
ADSP
is gated by CE.
ADSP
is an ac tiv e LO W inp u t that is us e d to ad v anc e the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
BW
BWE
-
CE
BW
Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs
rising edge of CLK then
x inputs are passed to the next stage in the circuit. If
BW
HIGH then the byte write inputs are blocked and only
Individual Byte
Write Enables
Chip Enable I LOW Synchronous chip e nable. CE is us e d wi th CS0 and
I LOW Synchronous byte write enables.
Any active byte write causes all outputs to be disabled.
also g ates
CE
ADSP
.
controls I/O
BW
, I/OP1,
CS
-
. If
BW
BW
c an initiate a write cycle.
GW
controls I/O
BW
is LOW at the
BWE
, I/OP2, etc.
to e nable the IDT71V 67603/7803.
CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this
input.
CS
CS
GW
I/O0-I/O
I/OP1-I/O
Chip Select 0 I HIGH Synchrono us active HIGH chip select. CS0 is used with CE and
Chip Select 1 I LOW Synchronous active LOW chip select.
Global Write
Enab le
I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK.
supersedes individual byte write enables.
GW
is used with CE and CS0 to e nab le th e ch ip .
CS
Data Input/Output I/O N/A Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
to e nab le th e ch ip .
CS
BWE
is
LBO
Linear Burst Order I LOW Asynchronous burst order selection input. When
sequence is selected. When
is LOW the Linear burst sequence is selected.
LBO
is HIGH, the interleaved burst
LBO
static input and must not change state while the device is operating.
OE
Output Enabl e I LOW Asynchro nous o utput enab le . When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When
is HIGH the I/O pins are in a high-
OE
impe d ance s tate.
V
V
V
Power Supply N/A N/A 3.3V core power supply.
Power Supply N/A N/A 3.3V I/O Supply.
Ground N/A N/A Ground.
NC No Connect N/A N/A NC pins are not electrically connected to the device.
ZZ Sleep Mode I HIGH Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67603/7803 to its lo wes t po we r consu mp tio n lev el. Data retention i s g uaranteed in
Sleep Mode.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
LBO
5310 tbl 02
is a
6.42
2
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CLK
ADSC
AD SP
CEN
CLR
Binary
Counter
Burst
Sequence
2
Burst
Logic
Q0
Q1
A0*
A1*
INTERNAL
ADDRESS
18/19
256K x 36/
512K x18-
BIT
MEMORY
ARRAY
A0–A
17/18
BW E
BW
BW
BW
BW
I/O0–I/O
I/OP1–I/O
GW
CE
CS
CS
ZZ
OE
CLK EN
ADDRESS
REGISTER
Byte 1
Write Register
1
Byte 2
Write Register
2
3
4
0
1
Powerdown
31
P4
36/18
Byte 3
Write Register
Byte 4
Write Register
D
Enable
Register
CLK EN
DQ
Enable
Delay
Register
18/19
Q
2
A0,A
1
A
2–A18
9
9
9
9
DATA INPUT
REGISTER
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
36/18
OE
OUTPUT
REGISTER
OUTPUT
BUFFER
36/18
,
5301 drw01
6.42
3
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
Symbol
Rati ng
Commercial
Uni t
TERM
TERM
DD
TERM
TERM
DDQ
A
BIAS
STG
T
OUT
Grade
Temperature
(1)
VSSVDDV
DDQ
Symbol
Parameter
Min.
Typ.
Max.
Uni t
DD
DDQ
SS
IH
DD
IH
DDQ
IL
Symbol
Parameter
(1)
Conditions
Max.
Unit
CINInp ut Cap ac itanc e
VIN = 3dV
5pFC
I/O
I/O Cap acitanc e
V
OUT
= 3dV
7
pF
5310 tbl 07
Symbol
Par a me t e r
(1)
Conditions
Max .
Unit
CINInput Cap aci tance
VIN = 3dV
7pFC
I/O
I/O Cap aci tance
V
OUT
= 3dV
7
pF
5310 tbl 07 a
Symbol
Parameter
(1)
Conditions
Max.
Uni t
CINInp ut Capa ci tanc e
VIN = 3dV
7pFC
I/O
I/O Cap aci tance
V
OUT
= 3dV
7
pF
5310 tbl 07b
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
(2)
V
(3,6)
V
(4,6)
V
(5,6)
V
(7)
T
T
T
P
I
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Terminal Voltage with
-0.5 to +4.6 V
Re sp e c t to GND
Terminal Voltage with
-0.5 to V
V
Re sp e c t to GND
Terminal Voltage with
-0.5 to VDD +0.5 V
Re sp e c t to GND
Terminal Voltage with
-0.5 to V
+0.5 V
Re sp e c t to GND
Operating Temperature
Temperatur e
-0 to + 70
-55 to +125
o
o
Under Bias
Storage
-55 to +125
o
Temperatur e
Power Dis sipation 2.0 W
DC Outp ut Cu rre nt 50 mA
5310 tbl 03
Comm erc ial 0°C to +70° C 0V 3.3V± 5% 3.3V± 5%
Industrial -40° C to + 85°C 0V 3.3V± 5% 3.3V ± 5%
NOTE:
1. TA is the "instant on" case temperature.
Recommended DC Operating
Conditions
C
V
Core S upp l y Vol tage 3.135 3.3 3.465 V
C
C
V
I/O Supp ly Vol tage 3.135 3.3 3.465 V
V
Supply Voltage 0 0 0 V
V
Input High Voltage - Inputs 2.0
V
I n put High Vol tage - I/O 2.0
V
Input Low Voltag e -0.3
NOTE:
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
(1)
____
____
____
V
+0.3 V
V
+0.3 V
0.8 V
5310 tbl 04
5310 tbl 05
100 Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 100-Pin TQFP
C
4
3
2
0
7
A6A
10099989796959493929190 8786858483828189 88
W
S
E
B
C
C
1
1
D
S
LK
D
W
W
W
B
B
B
S
S
C
C
V
V
E
W
W
B
G
P
S
V
S
D
E
A
O
8A9
D
D
A
A
A
I/O
I/O
I/O
V
DDQ
V
I/O
I/O
I/O
I/O
V
V
DDQ
I/O
I/O
VDD/NC
V
V
I/O
I/O
V
DDQ
V
I/O
I/O
I/O
I/O
V
V
DDQ
I/O
I/O
I/O
SS
SS
DD
NC
SS
SS
SS
1
P3
2
16
3
17
4
5
6
18
7
19
8
20
9
21
10
11
12
22
13
23
(1)
14
15
16
17
18
24
19
25
20
21
22
26
23
27
24
28
25
29
26
27
28
30
29
31
30
P4
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
O
LB
5
A0A1A2A3A4A
S
D
C
C
N
N
C
S
V
17
D
N
A
V
80
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
V
NC
V
ZZ
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
5301 drw 02
15
DDQ
SS
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
P2
14
13
12
11
10
9
8
(2)
7
6
5
4
3
2
1
,
0
P1
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
14A13A12A11A10
16
A
A15A
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 512K x 18, 100-Pin TQFP
C
2
0
7
A6A
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
C
S
E
N
C
C
1
1
D
S
C
W
W
S
N
B
B
C
LK
D
S
C
V
V
E
W
W
B
G
P
S
V
S
E
D
A
O
8A9
D
D
A
A
A
V
DDQ
V
I/O
I/O
V
V
DDQ
I/O
I/O
VDD/NC
V
V
I/O
I/O
V
DDQ
V
I/O
I/O
I/O
V
V
DDQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DD
1
2
3
4
5
SS
6
7
8
8
9
9
10
SS
11
12
10
13
11
(1)
14
15
16
17
SS
18
12
19
13
20
21
SS
22
14
23
15
24
P2
25
26
SS
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
O
LB
5
A0A1A2A3A4A
S
D
C
C
N
C
S
N
V
18
D
N
A
V
80
A
10
79
NC
78
NC
77
V
DDQ
76
V
SS
75
NC
74
I/O
I/O
I/O
V
V
I/O
I/O
V
NC
V
ZZ
I/O
I/O
V
V
I/O
I/O
NC
NC
V
V
NC
NC
NC
5310 drw 03
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
P1
7
6
5
4
(2)
3
2
1
0
,
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
15A14A13A12A11
17
A
A16A
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 119 BGA
1234567
DDQ
A V
B NC CS
NC
C
16
I/O
D
17
I/O
E
DDQ
F V
20
I/O
G
22
H I/O
DDQ
V
J
24
K I/O
25
I/O
L
DDQ
M V
29
I/O
N
31
P I/O
NC A
R
T NC NC A
DDQ
U V
A
A
I/O
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
I/O
DNU
6
(4)
0
7
P3
18
19
21
23
DD
26
27
28
30
P4
5
(3)
4
A
3
A
2
A
SS
V
SS
V
SS
V
3
BW
SS
V
NC V
SS
V
4
BW
SS
V
SS
V
SS
V
LBO
10
(3)
DNU
ADSP
ADSC
DD
V
NC V
CE
OE
ADV BW
GW
DD
CLK V
NC
BWE
1
A
0
A
DD
V
VDD/NC
11
A
(3)
DNU
DNU
8
A
9
A
12
A
SS
SS
V
SS
V
2
SS
V
NC V
SS
1
BW
SS
V
SS
V
SS
V
(1)
14
A
(3)
16
A
A
17
15
A
P2
I/O
13
I/O
12
I/O
11
I/O
9
I/O
DD
6
I/O
4
I/O
3
I/O
2
I/O
P1
I/O
13
A
NC ZZ
(3)
DNU
DDQ
V
NC
NC
15
I/O
14
I/O
DDQ
V
10
I/O
8
I/O
DDQ
V
7
I/O
5
I/O
DDQ
V
1
I/O
0
I/O
NC
(2)
DDQ
V
5310 drw 04
,
Top View
Pin Configuration 512K x 18, 119 BGA
1234567
DDQ
V
A
B NC CS
C A
NC
8
D I/O
NC I/O
E
DDQ
V
F
G NC I/O
11
I/O
H
DDQ
V
J
NC I/O
K
13
L I/O
DDQ
M V
15
N I/O
P NC I/O
R NC A
T NC A
DDQ
V
U
6
A
(4)
0
7
NC V
9
NC V
10
NC V
DD
V
12
NC NC
14
I/O
NC V
P2
5
10
(3)
DNU
A
A
A
SS
SS
V
SS
BW
SS
NC
SS
V
SS
V
SS
V
SS
SS
V
LBO
A
DNU
4
3
2
2
15
(3)
ADSP
ADSC
DD
V
NC V
CE
OE
ADV
GW
DD
V
CLK V
BWE
1
A
0
A
DD
V
NC A
(3)
DNU
V
8
A
9
A
13
A
SS
SS
V
SS
V
SS
V
SS
V
NC V
SS
1
BW
SS
V
SS
V
SS
V
/NC NC
DD
14
DNU
(1)
(3)
16
A
A
18
17
A
P1
I/O
NC I/O
6
I/O
NC I/O
4
I/O
DD
NC I/O
2
I/O
NC V
1
I/O
NC I/O
12
A
11
A
(3)
DNU
DDQ
V
NC
NC
NC
7
DDQ
V
5
NC
DDQ
V
3
NC
DDQ
NC
0
(2)
ZZ
DDQ
V
5310 drw 05
,
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. T7 can be left unconnected and the device will always remain in active mode.
3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
4. On future 18M device CS0 will be removed, B2 will be used for address expansion.
6.42
7
Loading...