Integrated Device Technology Inc IDT71V509S50Y, IDT71V509S66Y Datasheet
Integrated Device Technology, Inc.
128K x 8 3.3V SYNCHRONOUS SRAM
WITH ZBT AND FLOW-THROUGH
OUTPUT
ADVANCE
INFORMATION
IDT71V509
FEATURES:
• 128K x 8 memory configuration
• High speed - 66 MHz (9 ns Clock-to-Data Access)
• Flow-Through Output
• No dead cycles between Write and Read Cycles
• Low power deselect mode
• Single 3.3V power supply (±5%)
• Packaged in 44-lead SOJ
DESCRIPTION:
The IDT71V509 is a 3.3V high-speed 1,024,576-bit synchronous SRAM organized as 128K x 8. It is designed to
eliminate dead cycles when turning the bus around between
reads and writes, or writes and reads. Thus, it has been given
the name ZBT, or Zero Bus Turnaround.
Addresses and control signals are applied to the SRAM
FUNCTIONAL BLOCK DIAGRAM
Address
DQ
during one clock cycle, and one clock cycle later its associated
data cycle occurs, be it read or write.
The IDT71V509 contains data, address, and control signal
registers. Output Enable is the only asynchronous signal, and
can be used to disable the output at any time.
A Clock Enable (
CEN
) pin allows operation of the IDT71V509
to be suspended as long as necessary. All synchronous
inputs are ignored when
CEN
is high. A Chip Select (CS) pin
allows the user to deselect the device when desired. If CS is
high, no new memory operation is initiated, but any pending
data transfers (reads and writes) will still be completed.
The IDT71V509 utilizes IDT's high-performance 3.3V CMOS
process, and is packaged in a JEDEC Standard 400-mil 44lead small outline J-lead plastic package (SOJ) for high board
density.
Address
Control
(WE, CS,
Clock
CEN
SRAM
DQ
)
Input Register
DQ
Clk
Control Logic
OE
Control
Gate
DI DO
Mux
Data
Sel
3618 drw 01
The IDT logo is a registered trademark and CacheRAM, Zero Bus Turnaround and ZBTare trademarks of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. 11.3 DSC-3618/1
1
IDT71V509
128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBT AND FLOW-THROUGH OUTPUT COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC
A16
A15
A14
A13
A12
A11
WE
VDD
CLK
VSS
VDD
NC
CS
CEN
A10
A9
A8
A7
A6
A5
NCA4
(4)
(5)
(1)
(3)
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
SO44-1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
VSS
I/O7
I/O6
VDD
I/O5
I/O4
OE
VDD
VSS
VSS
I/O3
I/O2
VDD
I/O1
I/O0
VSS
(2)
NC
A3
Notes:
1. Pin 32: Future control input
2. Pin 20: Future I/O8
3. Pin 23: Future A17
4. Pin 44: Future A18
5. Pin 36 does not need to be connected directly to VDD, as long as it is ≥ VIH.
3618 drw 02
PIN DEFINITIONS
TOP VIEW
(1)
Symbol Pin Function I/O Active Description
A
0-A16 Address Inputs I N/A Synchronous Address inputs. The address is registered on every rising edge
of CLK if
CEN
and CS are both low.
CLK Clock I N/A The clock input. Except for OE, all input and output timing references for the
device are with respect to the rising edge of CLK.
CEN
Clock Enable I LOW Synchronous clock enable input. When
CEN
is sampled high, the other
synchronous inputs are ignored, and outputs remain unchanged. When
is sampled low, the IDT71V509 operates normally.
CS
Chip Select I LOW Synchronous chip select input. When CS is sampled low, the device operates
normally. When CS is sampled high, no read or write operation is initiated,
and the I/O bus is tri-stated the next cycle. CS is ignored if
CEN
is high at
the same rising edge of CLK.
WE
Write Enable I LOW Synchronous write enable. If WE is sampled low, a write is initiated at the
address that is registered at that time. If WE is sampled high, a read is initiated
at the address that is registered at that time. WE is ignored when either
or CS is sampled high.
OE
Output Enable I LOW Asynchronous output enable. When OE is high, the I/O bus goes high
impedance. OE must be low to read data from the IDT71V509.
I/O
0-I/O7 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
DD Power Supply N/A N/A 3.3V power supply pins.
V
V
SS Ground N/A N/A Ground pins.
CEN
CEN
11.3 2
IDT71V509
128K X 8 3.3V SYNCHRONOUS SRAM WITH ZBT AND FLOW-THROUGH OUTPUT COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL TIMING DIAGRAM
CYCLE
CLOCK
ADDRESS
(A0 - A16)
CONTROL
(CS,
CEN, WE
DATA
(I/O0 - I/O7)
n+29
A29
C29
)
D28
TYPICAL OPERATION -
n+30
A30
C30
D29
CSCS AND
n+31
A31
C31
D30
CEN
ARE LOW
CEN
n+32
A32
C32
D31
n+33
A33
C33
D32
n+34
A34
C34
D33
n+35
A35
C35
D34
n+36
A36
C36
D35
n+37
A37
C37
D36
3618 drw 03
Cycle Address
WE
WE
CSCSCEN
CENOEOE
I/O Comments
n A0 H L L ? D-1 ?
n+1 A1 L L L L D0 Data Out
n+2 A2 H L L X D1 Data In
n+3 A3 L L L L D2 Data Out
n+4 A4 H L L X D3 Data In
n+5 A5 L L L L D4 Data Out
n+6 A6 H L L X D5 Data In
n+7 A7 L L L L D6 Data Out
n+8 A8 H L L X D7 Data In
n+9 A9 L L L L D8 Data Out
n+10 A10 H L L X D9 Data In
n+11 A11 H L L L D10 Data Out
n+12 A12 L L L L D11 Data Out
n+13 A13 L L L X D12 Data In
n+14 A14 H L L X D13 Data In
n+15 A15 H L L L D14 Data Out
n+16 A16 H L L L D15 Data Out
n+17 A17 L L L L D16 Data Out
n+18 A18 L L L X D17 Data In
n+19 A19 L L L X D18 Data In
n+20 A20 H L L X D19 Data In
n+21 A21 H L L L D20 Data Out
11.3 3
Loading...