Integrated Device Technology Inc IDT71V35761S183BQ, IDT71V35761S183BQI, IDT71V35761S183PF, IDT71V35761S183PFI, IDT71V35761S200BG Datasheet

128K x 36, 256K x 18

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect

IDT71V35761S

IDT71V35781S
IDT71V35761SA
IDT71V35781SA

Features

◆◆

◆

◆◆

128K x 36, 256K x 18 memory configurations

◆◆

◆

◆◆

Supports high system speed:

Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time

◆◆

◆

◆◆

LBO input selects interleaved or linear burst mode

◆◆

◆

◆◆

Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)

◆◆

◆

◆◆

3.3V core power supply

◆◆

◆

◆◆

Power down controlled by ZZ input

◆◆

◆

◆◆

3.3V I/O

◆◆

◆

◆◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)

◆◆

◆

◆◆

Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array

Description

The IDT71V35761/781 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.

The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761/81 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.

The IDT71V35761/781 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.

Pin Description Summary

17

A0-A

CE

0

1

, CS

CS

OE

GW

BWE

BW

BW

1

2

,

,

CLK Clock Input N/A

ADV

ADSC

ADSP

LBO

TMS Test Mode Select Input Synchronous
TDI Test Data Inp ut Inp ut Sy nc hro no u s
TCK Test Clock Input N/A
TDO Tes t Data O utp ut Outp ut Syn ch ro no us

TRST

ZZ Sleep Mode Input Asynchronous

0

-I/O31, I/OP1-I/O

I/O

DD

DDQ

, V

V

SS

V

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V35781.

©2003 Integrated Device Technology, Inc.

BW

(1)

BW

3

4

,

P4

Ad d re s s Inp uts Inp ut Sy nc hro no u s
Chip Enable Input Synchronous
Chip Se le c ts Input Synchro no us
Outp ut E na b le Inp ut As y nc hrono u s
Glob al Write Enab le Input Synch rono us
Byte Write Enab le Input Synchro no us
Individual Byte Write Selects Input Synchronous

Burst Address Advance Input Synchronous
Add re ss Status (Cache Co ntroll er) Input Sync hrono us
Address Status (Processor) Input Synchronous
Linear / Interleaved Burst Order Input DC

JTAG Reset (Optional) Input Asynchronous

Data Inp ut / Ou tp ut I/O Sy nc hro no u s
Core Power, I/O Power Supply N/A
Ground Supply N/A

JUNE 2003

1

5301 tbl 01

DSC-5301/03

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Symbol

Pin Function

I/O

Active

Descri ption

11

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Definitions

17

A0-A

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK

(1)

and ADSC Low or ADSP Low and CE Low.

ADSC

ADSP

ADV

Address Status

(Cache Co ntrol le r)

Address Status

(Processor)

Burst Address

Ad v ance

I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the

address registers with new addresses.

I LOW Synchronous Address Status from Processor. ADSP is an activ e LOW i nput that is use d to lo ad the add re ss

registers with new addresses. ADSP is gated by CE.

I LOW Synchronous Address Advance.

ADV

is an activ e LOW i nput that is use d to adv ance the i nternal b urs t
counter, controlling burst access after the initial address is lo aded . When the input is HIGH the burst counter is
not incremented; that is, there is no address advance.

BWE

Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW

1

-BW4. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BW E is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle .

BW

1

CE

-BW

4

Individual Byte
Write E nab le s

I LOW Synchronous byte write enables. BW1 controls I/O

write causes all outputs to be disabled.

0-7

, I/OP1, BW2 controls I/O

Chip Enable I LOW Sy nchronous chip enable. CE is us ed with CS0 and CS1 to e nabl e the IDT71V35761/781. CE also g ate s

8-15

, I/OP2, etc. Any active b yte

ADSP.

CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input.
CS

CS

GW

0

I/O

-I/O

I/OP1-I/O

LBO

0

1

Chip Select 0 I HIGH Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
Chip Select 1 I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to e n ab le th e c hip .

Global Write

Enabl e

31

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and

P4

I LOW Sy nchronous glob al write enable. This input will write all four 9-bit data bytes when LOW o n the rising edge of

CLK. GW supersedes individual byte write enables.

triggered by the rising edge of CLK.

Linear Burst Order I LOW Asynchronous b urst order selection input. When LBO is HIGH, the interleaved burst sequence is selected.

When LBO is LOW the Line ar burst sequence is selected. LBO is a s tatic inp ut and must no t chang e s tate
while the device is operating.

OE

Output Enab le I LO W A sy nchro no us o utput e nabl e . Whe n OE is LOW the data output drivers are enabled on the I/O pins if the chip

is also selected. When OE is HIGH the I/O pins are in a high-impedance state.

TMS Test ModeSelect I N/A Gives input command for TAP contro ller. Sampled on rising edge of TDK. This pin has an internal pullup.

TDI Test Da ta Inp ut I N/ A

TCK Test Clock I N/A

TDO Test Da taOu tp ut O N/ A

TRST

JTAG Reset

(Optional)

ILOW

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are c aptured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP co ntroller.

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
oc curs autom atical ly at p o wer up and also res e ts usi ng TMS and TCK p er IE EE 1149.1. If not use d TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.

Asynchronous sleep mode input. ZZ HIGH will gate th e CLK internally and po wer down the IDT71V35761/35781

ZZ Sleep Mode I HIGH

to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal
pull down.

DD

V

DDQ

V

SS

V

Power Supply N/A N/A 3.3V core power supply.
Power Supply N/A N/A 3.3V I/O Supply.

Ground N/A N/A Ground.

NC No Connect N/A N/A NC pins are not electrically connected to the device.

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

5301tbl 02

6.42

2

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

ADV

CLK

ADSC

ADSP

CEN

CLR

Binary

Counter

Burst

Sequence

2

Burst
Logic

Q0
Q1

A0*
A1*

INTERNAL
ADDRESS

17/18

128K x 36/
256K x 18-

BIT

MEMORY

ARRAY

A0-A

BWE

BW

BW

BW

BW

I/O0—I/O

I/OP1— I/O

16/17

GW

CE

CS

CS

ZZ

OE

CLK EN

ADDRESS

REGISTER

Byte 1

Write Register

1

Byte 2

Write Register

2

3

4

0

1

Powerdown

31

P4

36/18

Byte 3

Write Register

Byte 4

Write Register

D

Enable
Register

CLK EN

DQ

Enable
Delay
Register

17/18

Q

2

A0,A

1

2–A17

A

Byte1
Write Driver

9

Byte2
Write Driver

9

Byte3
Write Driver

9

Byte4
Write Driver

9

DATA INPUT

REGISTER

36/18

OE

OUTPUT

REGISTER

OUTPUT
BUFFER

36/18

,

5301 drw 01

TMS

TDI

TCK

JTAG

(SA Version)

TDO

TRST

(Optional)

6.42

3

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

(2)

(3,6)

(4,6)

(5,6)

(7)

o

o

o

o

5301 t bl 03

Grade

Temperature

(1)

VSSVDDV

DDQ

Symbol

Parameter

Min.

Typ.

Max.

Unit

(1)

(1)

(1)

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

Commercial &

Symbol Rating

V

TERM

Termi nal Vol tage wi th
Re s p e c t to G ND

V

TERM

Termi nal Vol tage wi th
Re s p e c t to G ND

V

TERM

Termi nal Vol tage wi th

Industrial Unit

-0.5 to +4.6 V

-0.5 to V

-0.5 to VDD +0.5 V

(1)

DD

Recommended Operating
Temperature and Supply Voltage

Com me rci al 0° C to +70 ° C 0V 3.3V ± 5% 3.3V ± 5%

Industrial -40° C to +85° C 0V 3.3V± 5% 3.3V± 5%

V

NOTES:

1. TA is the "instant on" case temperature.

5301 t b l 04

Re s p e c t to G ND

V

TERM

Termi nal Vol tage wi th
Re s p e c t to G ND

Commercial

A

T

Operating Temperature

Industrial

Operating Temperature

T

BIAS

T emperature
Under Bias

T

STG

Storage
T emperature

P

T

OUT

I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

Po we r Di s si p atio n 2.0 W
DC Output Curre nt 50 mA

-0.5 to V

-0 to +7 0

-40 to + 85

-55 to +125

-55 to +125

DDQ

+0.5 V

Recommended DC Operating
Conditions

C

DD

V

C

C

C

NOTES:

1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

Core Supply Voltage 3.135 3.3 3.465 V

DDQ

V

I/O Sup pl y Vo ltage 3.135 3.3 3.465 V

SS

V

Supply Voltage 0 0 0 V
VIHInput High Voltage - Inputs 2.0
VIHI n pu t High Voltage - I / O 2.0
VILInput Low Voltage -0. 3

____

____

(2)

____

DD

V

+0.3 V

DDQ

V

+0.3

0.8 V

(1)

5301 tbl 06

V

100 Pin TQFP Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol P arameter

Inp ut Cap ac i tanc e VIN = 3dV 5 p F

C

IN

I/O Cap ac ita nce V

C

I/O

Conditions Max. Unit

= 3dV 7 p F

OUT

5301 tbl 07

165 fBGA Capacitance

(TA = +25°C, f = 1.0MHz)

Symbo l Para me t e r

Inp ut Cap a ci tanc e VIN = 3dV 7 pF

C

IN

I/O Cap aci tance V

C

I/O

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

Conditions Max . Unit

= 3dV 7 pF

OUT

5301 tb l 07b

6.42

4

119 BGA Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol Parame te r

Input Capacitance VIN = 3dV 7 p F

C

IN

I/O Cap acitanc e V

C

I/O

Con dit ion s Max. Un it

= 3dV 7 p F

OUT

5301 tbl 07a

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36

C

4

3

2

0

7

A6A

10099989796959493929190 8786858483828189 88

W

S

E

B

C

C

1

1

D

S

LK

D

W

W

W

B

B

B

S

S
C

C

V

V

E

W

W
B

G

P

S

S

V

D

E

A

O

8A9

D

D

A

A

A

I/O
I/O
I/O

DDQ

V

V
I/O
I/O
I/O
I/O

V

DDQ

V

I/O
I/O

VDD/NC

V

V
I/O
I/O

DDQ

V

V
I/O
I/O
I/O
I/O

V

DDQ

V

I/O
I/O
I/O

DD

NC

1

P3

2

16

3

17

4
5

SS

6

18

7

19

8

20

9

21

10

SS

11
12

22

13

23

(1)

14
15
16
17

SS

18

24

19

25

20
21

SS

22

26

23

27

24

28

25

29

26

SS

27
28

30

29

31

30

P4

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

O
LB

5

A0A1A2A3A4A

S

D

C

C

S

N

N

V

C

C

D

N

N

V

80
79
78
77
76
75
74
73
72

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

14A13A12A11A10

16

A

A15A

I/O

I/O

I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
V

NC
V

ZZ
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O

I/O

5301drw 02

15
14

DDQ

SS

13
12
11

10
SS
DDQ

9

8
SS

DD

(2)

DDQ
SS

5

4

3

2
SS
DDQ

P2

7
6

1

,

0
P1

100 TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 18

C

2

0

7

A6A

10099989796959493929190 8786858483828189 88

C

S

E

N

C

C

1

1

D

S

C

W

W

S

B

N

B

C

LK

D

S

C

V

V

E

W

W
B

G

P

S

V

S

E

D
A

O

8A9

D

D

A

A

A

DDQ

V

V

I/O
I/O
V

DDQ

V

I/O
I/O

VDD/NC

V

V
I/O
I/O

DDQ

V

V
I/O
I/O
I/O

V

DDQ

V

NC
NC
NC

NC
NC

NC

NC

NC
NC
NC

1
2
3
4
5

SS

6
7
8

8

9

9

10

SS

11
12

10

13

11

(1)

14
15

DD

16
17

SS

18

12

19

13

20
21

SS

22

14

23

15

24

P2

25
26

SS

27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

O
LB

5

A0A1A2A3A4A

S

D

C

C

C

S

N

N

V

C

D

N

N

V

80

10

A

79

NC

78

NC

77

DDQ

V

76

SS

V

75

NC

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

15A14A13A12A11

17

A

A16A

I/O
I/O
I/O
V
V
I/O
I/O
V

NC
V

ZZ
I/O
I/O
V
V
I/O
I/O
NC
NC
V
V
NC
NC

NC

5301 drw 03

SS
DDQ

SS

DD

DDQ
SS

SS
DDQ

P1
7
6

5
4

(2)

3
2

1
0

,

100 TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

6

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 119 BGA

1234567

DDQ

V

A

NC CS

B

NC

C A

16

I/O

D

17

I/O

E

DDQ

V

F

20

I/O

G

22

I/O

H

DDQ

V

J

24

I/O

K

25

I/O

L

DDQ

M V

29

I/O

N

31

I/O

P

NC A

R

NC NC A

T

DDQ

U V

A

I/O
I/O
I/O
I/O
I/O

DD

V
I/O
I/O
I/O
I/O
I/O

NC/TMS

6

0

7

P3

18

19

21

23

26

27

28

30

P4

5

(2)

4

A

3

A

2

A

SS

V

SS

V

SS

V

BW

SS

V
NC V

SS

V

BW

SS

V

SS

V

SS

V

LBO

10

NC/TDI

3

4

(2)

ADSP
ADSC

DD

V

NC V
CE

OE
ADV BW
GW

DD

CLK V

NC

BWE

1

A

0

A

DD

V

11

A

NC/TCK

(2)

A
A

A

SS

SS

V

SS

V

SS

V
NC V

SS

BW

SS

V

SS

V

SS

V

DD

V

A

NC/TDO

8

9

12

2

1

/NC

14

(1)

(2)

16

A

1

CS

15

A

P2

I/O

13

I/O

12

I/O

11

I/O

9

I/O

DD

6

I/O

4

I/O

3

I/O

2

I/O

0

I/O

13

A
NC

NC/TRST

(2,4)

DDQ

V

NC
NC

15

I/O

14

I/O

DDQ

V

10

I/O

8

I/O

DDQ

V

7

I/O

5

I/O

DDQ

V

1

I/O

P1

I/O

NC

(3)

ZZ

DDQ

V

5301 drw 04

,

Top View

Pin Configuration  256K x 18, 119 BGA

1234567

DDQ

V

A

NC CS

B

NC

C

8

I/O

D

NC I/O

E

DDQ

V

F

NC I/O

G

11

I/O

H

DDQ

V

J

NC I/O

K

13

I/O

L

DDQ

V

M

15

I/O

N

NC I/O

P

NC A

R

NC A

T

DDQ

V

U

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. T7 can be left unconnected and the device will always remain in active mode.

4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6

A

0

7

A

NC V

9

NC V

10

NC V

DD

V

12

NC NC

14

I/O

NC V

P2

5

10

NC/TMS

(2)

4

A

3

A

2

A

SS

SS

V

SS

BW

SS

NC V

SS

V

SS

V

SS

V

SS

SS

V
LBO

15

A

NC/TDI

2

(2)

ADSP

ADSC

DD

V

A
A

A

NC V

CE
OE

ADV

GW

V
V
V
V

DD

NC V

CLK V

BW

BWE

A
A

V

V

1

V

0

V

DD

V

DD

NC A

(2)

NC/TCK

NC/TDO

Top View

8

9

13

SS

SS

SS

SS

SS

SS

SS

SS

SS

/NC

14

1

(1)

(2)

16

A

1

CS

17

A

7

I/O
NC I/O

5

I/O
NC I/O

3

I/O

DD

NC I/O

1

I/O
NC V

0

I/O
NC I/O

12

A

11

A

NC/TRST

(2,4)

DDQ

V

NC
NC
NC

6

DDQ

V

4

NC

DDQ

V

2

NC

DDQ

NC

P1

NC

(3)

ZZ

DDQ

V

5301 drw 05

,

6.42

7