IDT IDT71V3577S, IDT71V3579S, IDT71V3577SA, IDT71V3579SA User Manual

查询IDT71V3577S75BGG供应商

128K X 36, 256K X 18

3.3V Synchronous SRAMs

3.3V I/O, Flow-Through Outputs Burst Counter , Single Cycle Deselect

Features

◆

128K x 36, 256K x 18 memory configurations

◆◆

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Supports fast access times:

Commercial: – 7.5ns up to 117MHz clock frequency Commercial and Industrial: – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency

◆

LBOLBO

LBO input selects interleaved or linear burst mode

LBOLBO

◆◆

◆

◆◆

Self-timed write cycle with global write control ( enable (

◆◆

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3.3V core power supply

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Power down controlled by ZZ input

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3.3V I/O

◆◆

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Optional - Boundary Scan JTAG Interface (IEEE 1149.1

BWEBWE

BWE), and byte writes (

BWEBWE

BWBW

BWx)

BWBW

compliant)

◆◆

◆

◆◆

Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array

GWGW

GW), byte write

GWGW

IDT71V3577S

IDT71V3579S IDT71V3577SA IDT71V3579SA

Description

The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.

The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3577/79 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin.

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).

Pin Description Summary

A0-A

BWE

(1)

CLK Clo ck Inpu t N/A

ADV

ADSC

ADSP

LBO

TMS Test Mode Select Input Synchronous TDI Test Data Inp ut Inpu t Sy nchr ono us TCK Test Clock Input N/A TDO Test Data Outp ut Outp ut S y nchr ono us

TRST

ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/O VDD, V

DDQ

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V3579.

Address Inputs Input Synchronous Chip Enable Input Sy nchronous Chip S e l e c ts Input Sy nc hr o no us Output Enable Input Asynchronous Global Write Enable Input Synchronous Byte Write Enable Input Sy nchronous Indi v idua l By te Wri te S e l e c ts Inpu t Sy nc hr o no us

Burs t A d d r e s s A d v anc e Inpu t Sy nc hr o no us Ad d r e ss S tatus (Cac he Contro l l e r) Inpu t Sy nc hr o no us Ad d re ss Status (Pr oc e ss o r) Inpu t Sy nchr ono us Linear / Interleaved Burst Order Input DC

JTAG Reset (Optional) Input Asynchronous

Data Inp ut / Outp ut I/O Sy nc hrono us Co re P owe r, I/O P o we r Supp l y N/A Ground Supply N/A

FEBRUARY 2005

5280 tb l 01

DSC-5280/08

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Symbol

Pin Function

I/O

Active

Descrip tion

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Definitions

A0-A

ADSC

ADSP

ADV

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK

Address Status

(Cache Co ntrol le r)

Address Status

(Processor)

Burst Address

Ad vance

(1)

and

ADSC

Low or

ADSP

Low and CE Low.

I LOW Synchronous Address Status from Cache Controller.

address registers with new addresses.

I LOW Synchronous Address Status from Processor.

registers with new addresses.

ADSP

I LOW Synchronous Address Advance.

controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not

ADSC

is an ac tive LOW inp ut that is used to lo ad the

ADSP

is an active LOW inp ut that is used to l oad the add res s

is gated by CE.

ADV

is an active LOW input that is used to advance the internal burst counter,

incremented; that is, there is no address advance.

BWE

Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs

then BWx inputs are passed to the next stage in the circuit. If

BWE

. If

BWE

is LOW at the rising edge of CLK

is HIGH then the byte write inputs are

blocked and only GW can initiate a write cycle .

Individual Byte Write E nabl e s

I LOW Synchronous byte write enables.

write causes all outputs to be disabled.

Chip Enable I LOW Sy nchronous chip enable. CE is used with CS0 and

controls I/O

0-7

, I/OP1,

controls I/O

to enabl e the IDT71V3577/79. CE also gate s

8-15

, I/OP2, etc. Any active byte

ADSP

CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input. CS

I/O0-I/O

I/OP1-I/O

LBO

Chip Select 0 I HIGH Synchronous active HIGH chip select. CS0 is used with CE and

Chip S el ec t 1 I LOW Sync hro no us active LOW chip s el ec t.

Global Write

Enab l e

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of

I LOW Sy nchronous global write enable. This input will write all fo ur 9-bit data b ytes when LOW on the rising edge of

CLK. GW supersedes individual byte write enables.

CLK. The data o utput path is flow-through (no output register).

Linear Burst Order I LOW Asynchronous burst order selection input. When

LBO

When

is LOW the Linear burst sequence is selected.

is used with CE and CS0 to e nab le th e c hip .

LBO

is HIGH, the inter-leaved burst sequence is selected.

to enable the chip.

LBO

is a static inp ut and must no t chang e s tate

while the device is operating.

Output Enabl e I LOW A sy nchro nous o utput enab le . Whe n OE is LOW the data output drivers are enabled on the I/O pins if the chip

is also selected. When

is HIGH the I/O pins are in a high-impedance state.

TMS Test ModeSelect I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

TDI Test Da ta Inp ut I N/ A

TCK Test Clock I N/A

TDO Test Data Outp ut O N/ A

TRST

JTAG Reset

(Optional)

ILOW

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed be tween TDI and TDO. This output is active depending on the state of the TAP controller.

Optional Asynchronous JTAG reset. Can be used to reset the TAP contro ller, but not required. JTAG reset occurs automatically at p ower up and also resets using TMS and TCK pe r IEEE 1149.1. If not us ed

TRST

be left floating. This pin has an internal pullup. Only available in BGA package. Asynchronous sleep mode input. ZZ HIGH will g ate the CLK inte rnally and po wer down the IDT71V3577/79 to

ZZ Sleep Mode I HIGH

its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down.

DDQ

Power Supply N/A N/A 3.3V core power supply. Power Supply N/A N/A 3.3V I/O Supply.

Ground N/A N /A Ground.

NC No Connect N/A N/A NC pins are not electrically connected to the device.

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

can

5280 tbl 02

6.422

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

ADV

CLK

ADSC

ADSP

CEN

CLR

Binary

Counter

Burst

Sequence

Burst

Logic

A0*

A1*

INTERNAL ADDRESS

17/18

128K x 36/ 256K x 18-

BIT

MEMORY

ARRAY

A0-A

BWE

I/O0-I/O

I/OP1- I/O

16/17

CLK EN

ADDRESS

Byte 1

Write Register

Byte 2

Write Register

Byte 3

Write Register

Byte 4

WriteRegister

Powerdown

Enable Register

CLK EN

17/18

A0,A

2-A17

DATA INPUT

Byte 1 Write Driver

Byte 2 Write Driver

Byte 3 Write Driver

Byte 4 Write Driver

36/18

OUTPUT BUFFER

36/18

TMS

TDI

TCK

TRST

(Optional)

JTAG

(SA Version)

5280 drw 01

TDO

6.42

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Symbol

Rati ng

Commercial &

Industrial Values

Uni t

TERM

DDQ

Commercial

Industrial

BIAS

STG

OUT

Grade

Temperature

(1)

VSSVDDV

DDQ

Symbol

Parameter

Min.

Typ.

Max.

Unit

DDQ

Symbol

Parameter

(1)

Conditions

Max.

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

5pFC

I/O

I/O Cap acitanc e

OUT

= 3dV

5280 tbl 07

Symb ol

Par a me t er

(1)

Con dit io ns

Max .

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

7pFC

I/O

I/O Cap aci tance

OUT

= 3dV

5280 tbl 07a

Symbo l

Par a me t er

(1)

Con dit io ns

Max .

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

7pFC

I/O

I/O Cap acitanc e

OUT

= 3dV

5280 tb l 07b

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

(1)

Recommended Operating

Temperature Supply Voltage

(2)

(3,6)

(4,6)

(5,6)

(7)

P I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have ramped up. Power supply sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

Terminal Voltage with

-0.5 to +4.6 V

Re sp e c t to GND Terminal Voltage with

-0.5 to V

Re sp e c t to GND Terminal Voltage with

-0.5 to VDD +0.5 V

Re sp e c t to GND Terminal Voltage with

-0.5 to V

+0.5 V

Re sp e c t to GND

-0 to + 70

Operating Temperature

-40 to + 85

Operating Temperature Temperature

-55 to +125

Under Bias Storage

-55 to +125

Temperature Power Dis sipation 2.0 W DC Outp ut Cu rre nt 50 mA

5280 tbl 03

Comm ercial 0° C to +70°C 0V 3.3V± 5% 3. 3V± 5%

Ind us tria l -40° C to + 8 5° C 0 V 3.3V ±5% 3. 3V ±5%

NOTES:

1. TA is the "instant on" case temperature.

Recommended DC Operating

Conditions

NOTES:

1. V IH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

Core Supply Voltage 3. 135 3.3 3.465 V

I/O Supply Voltage 3.135 3.3 3.465 V

Supply Voltage 0 0 0 V

Input High Voltage - Input s 2. 0

Input H igh Voltage - I /O 2. 0

Input Low Voltage -0.3

5280 tbl 04

____

+0.3 V

____

(2)

____

(1)

+0.3

0.8 V

5280 tbl 06

100 Pin TQFP Capacitance

(TA = +25° C, f = 1.0mhz)

165 fBGA Capacitance

(TA = +25° C, f = 1.0mhz)

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.424

119 BGA Capacitance

(TA = +25° C, f = 1.0mhz)

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36

A6A7C

10099989796959493929190 8786858483828189 88

W G

D A

8A9

I/O

I/O I/O

I/O I/O I/O I/O

I/O I/O

I/O I/O I/O I/O

I/O I/O

DDQ

4 5

11 12

(1)

15 16 17

20 21

27 28

313233 34 35 363738 39 40 41 42 43 44 45 46 47 48 49 50

O LB

A4A

I/O I/O I/O V

DDQ SS

V I/O I/O I/O I/O V

DDQ

I/O I/O V

NC V

ZZ I/O I/O V

DDQ

I/O I/O

I/O I/O V

DDQ

I/O I/O

I/O

5280 drw 02a

P2 15 14

13 12 11 10

9 8

(2)

7 6

5 4

3 2

1 0

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

100 TQFP

Top View

NOTES:

1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 18

A6A7C

100 99 98 97 96 95 94 93 92 91 9 0 87 86 8 5 84 83 82 8189 88

W B

LK C

W B

D A

8A9

I/O

I/O I/O

NC NC NC

DDQ

NC I/O I/O V

DDQ

NC V

DDQ

NC V

DDQ

1 2 3 4 5 6 7 8

10 11 12

(1)

14 15 16 17 18

20 21 22

25 26 27 28 29 30

313233 34 35 363738 39 40 41 42 43 44 45 46 47 48 49 50

O LB

A4A

C N

79 78 77 76 75 74 73

68 67 66 65 64

63 62 61 60

59 58 57 56

55 54 53 52

NC NC V

DDQ

NC I/O I/O I/O V

DDQ

I/O I/O V

NC V

ZZ I/O I/O V

DDQ

I/O I/O

NC NC V

DDQ

NC NC NC

5280 drw 02b

P1 7 6

5 4

(2)

3 2

1 0

100 TQFP

Top View

NOTES:

1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.426

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 119 BGA

1234567

DDQ

NC CS

B C

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

NC A

NC NC A

DDQ

I/O

NC/TMS

(2)

NC V

V LBO

(2)

NC/TDI

ADSP ADSC

NC V

CE OE

ADV BW

CLK V

BWE

(2)

NC/TCK

NC V

NC/TDO

(2)

I/O

NC/TRST

I/O I/O

I/O

(2,4)

5280 drw02c

DDQ

NC NC

DDQ

I/O

DDQ

I/O I/O

DDQ

I/O I/O

NCA

DDQ

(3)

Top View

Pin Configuration  256K x 18, 119 BGA

1234567

DDQ

A V B NC CS

D I/ O

NC I/O

DDQ

F V

NC I/O

H I/O

DDQ

K NC I/O

L I/O

DDQ

M V

I/O

NC I/O

P R NC A T NC A

DDQ

U V

NOTES:

1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. T7 can be left unconnected and the device will always remain in active mode.

4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to V DD.

NC V

I/O

NC V

NC/TMS

A A

NC V

V LBO

(2)

NC/TDI

(2)

ADSP ADSC

NC V

CE OE

ADVBW

CLK V

BWE

A A

NC A

NC/TCK

(2)

A A

V V V V

NC V

BW V V V

NC/TDO

(2)

I/O

NC I/O

I/O

NC I/O

I/O

NC I/O

I/O

NC V

I/O

NC I/O

NC/TRST

(2,4)

5280 drw 02d

DDQ

NC NC NC

DDQ

NCA

DDQ

(3)

Top View

6.42

+ 15 hidden pages

IDT IDT71V3577S, IDT71V3579S, IDT71V3577SA, IDT71V3579SA User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual