IDT IDT71V3556S, IDT71V3558S, IDT71V3556SA User Manual
128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs
IDT71V3556S
IDT71V3558S
IDT71V3556SA
IDT71V3558SA
Features
◆◆
◆
◆◆
128K x 36, 256K x 18 memory configurations
◆◆
◆
◆◆
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
◆◆
◆
◆◆
ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆
◆◆
Internally synchronized output buffer enable eliminates the
need to control
◆◆
◆
◆◆
Single R/
◆◆
◆
◆◆
Positive clock-edge triggered address, data, and control
OEOE
OE
OEOE
WW
W (READ/WRITE) control pin
WW
signal registers for fully pipelined applications
◆◆
◆
◆◆
4-word burst capability (interleaved or linear)
◆◆
◆
◆◆
Individual byte write (
◆◆
◆
◆◆
Three chip enables for simple depth expansion
◆◆
◆
◆◆
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
◆◆
◆
◆◆
Optional- Boundary Scan JTAG Interface (IEEE 1149.1
BWBW
BWBW
BW1 -
BW4) control (May tie active)
BWBW
BWBW
compliant)
◆◆
◆
◆◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Pin Description Summary
Description
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
17
A0-A
1
CE
OE
W
R/
CEN
BW
CLK Clock Input N/A
ADV/
LBO
TMS Test Mode Select Input Synchronous
TDI Test Data Input Input Synchronous
TCK Test Clock Input N/A
TDO Tes t Data Ou tp ut Outp ut Sync hr on o us
TRST
ZZ Sleep Mode Input Synchronous
0
I/O
VDD, V
SS
V
2
CE
, CE2,
1
2
3
BW
BW
,
,
LD
-I/O31, I/OP1-I/O
DDQ
4
BW
,
P4
Address Inputs Input Synchronous
Chip E nabl es Input Sync hrono us
Output Enable Input Asynchronous
Read /Write Si gnal Input Sy nchro nous
Clock Enable Input Synchronous
Individual Byte Write Selects Input Synchronous
Ad vance b urst add re ss / Lo ad ne w ad dre ss Input Sync hrono us
Linear / Interleaved Burst Order Input Static
JTAG Reset (Optional) Input Asynchronous
Data Inp ut / Ou tp ut I/O Sy nc hr ono u s
Core P owe r, I/ O Po we r Sup p ly Static
Ground Supply Static
SEPTEMBER 2004
5281 tbl 01
©2004 Integrated Device Technology, Inc.
1
DSC-5281/08
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
Symbo l
Pin Function
I/O
Active
Description
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Description continued
The IDT71V3556/58 has an on-chip burst counter. In the burst
mode, the IDT71V3556/58 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
Pin Definition
(1)
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V3556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
17
A0-A
ADV/
LD
R/
W
CEN
1
-
BW
BW
1
,
CE
CE
2
CE
CLK Clock I N/A
I/O
-I/O
0
I/OP1-I/O
LBO
OE
TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI Test Data Inp ut I N/A
TCK Te st Cloc k I N/A
TDO Tes t Data O utp ut O N/A
TRST
ZZ Sleep Mode I HIGH
DD
V
DDQ
V
SS
V
Address Inputs I N/A
Adv ance / Load I N/A
Read / Write I N/A
Clock Enable I LOW
Ind iv id ua l By te
4
Write Enable s
Chip Enab les I LOW
2
Chip Enab le I HIGH
31
Data Inp ut/ Ou tp ut I/O N/A
P4
Linear Burst O rde r I LOW
Output Enable I LOW
JTAG Reset
(Optional)
Powe r Sup p ly N/A N/A 3.3V c ore p owe r sup p ly.
Power Supply N/A N/A 3.3V I/O Supply.
Ground N/A N/A Ground.
ILOW
ILOW
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
low,
ADV/
LD
ADV/
LD
is sampled low at the rising edge of clock with the chip selected. When ADV/
deselected, any burst in progress is terminated. When ADV/
is advanced for any burst that was in progress. The external addresses are ignored when ADV/
high.
signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
R/
W
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
Synchronous Clock Enable Input. When
ignored and outputs remain unchanged. The effect of
to high clock transition did not occur. For normal operation,
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(When R/
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/
sampled high. The appropriate byte(s) of data are written into the device two cycles later.
tied low if always doing write to the entire 36-bit word.
Synchronous active low chip e nable.
2
sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
CE
The ZBT
Sync hrono us active high chi p e nable . CE
polarity but otherwise id entical to
This is the cl o ck i np ut to the IDT71V 3556 /58 . E x ce p t fo r
respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
Burst order se lection input. When
the Linear burst sequence is selected.
Asynchronous output enable.
are in a high-impe danc e state.
operation,
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are d riven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Optional Asynchronous JTAG reset. Can be used to reset the TAP co ntroller, but not required. JTAG reset
oc curs automatically at powe r up and als o rese ts using TMS and TCK per IEEE 1149.1. If not used
be le ft floating. This pin has an internal pullup. Only available in BGA package.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to
its lowest power consumption level. Data retention is guaranteed in Sleep M ode . This pin has an internal
pulldown.
low, and true chip enab les .
CEN
is a sync hrono us input that is used to l oad the internal reg isters with new addre s s and co ntrol when it
is s a mp le d hi gh then th e i nte rna l b urs t c ou nter
LD
is sampled high, all other synchronous inputs, including clock are
CEN
and ADV/LD are sampled low) the appropriate byte write signal (
W
1
and
CE
CE
TM
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
2
is used with
1
2
and
.
CE
is high the Interleaved burst sequence is selected. When
is a static input and it must no t change d uring d ev ice op e ration.
LBO
can be tied low.
OE
CE
LBO
must be low to re ad d ata from the 71V3556/58. When OE is high the I/O pins
OE
does not need to be actively controlled for read and write cycles. In normal
OE
sampled high on the device outputs is as if the low
CEN
2
are used with CE2 to enable the IDT71V3556/58. (
must be sampled low at rising edge of clock.
CEN
1
2
and
CE
OE
to enable the chip. CE2 has inverted
CE
, all timing references for the device are made with
is low with the chip
LD
1
4
-
) must be valid. The b y te
BW
BW
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422
BW
LD
1
-
BW
is sampled
is
W
4
can all be
1
or
CE
is low
LBO
can
TRST
5281 tbl 02
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
Address A [0:16]
CE1, CE2, CE2
R/
CEN
ADV/LD
BW x
Clock
128Kx36 BIT
MEMORY ARRAY
DQ
W
DQ
egist er
Input R
DQ
Clk
Control Logic
Address
Control
Clk
Output Register
DI DO
Mux
D
Q
Sel
OE
TMS
TDI
TCK
TRST
(optional)
JTAG
(SA Version)
TDO
Gate
Data I/O [0:31],
I/O P[1:4]
5281 drw 01a
,
6.42
3
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
(2)
(1)
52 81 tbl 04
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram
Address A [0:17]
CE1, CE2, CE2
ADV/LD
Clock
LBO
R/W
CEN
BW x
DQ
DQ
egiste r
Input R
DQ
Clk
Control Logic
Clk
256x18 BIT
MEMORY ARRAY
Address
Control
DI DO
Mux
D
Output Register
Q
Sel
OE
TMS
TDI
TCK
TRST
(optional)
JTAG
(SA Version)
Recommended DC Operating
Conditions
Symbol Parameter Min. Typ. Max. Unit
Core Sup p ly Voltag e 3.135 3.3 3.465 V
V
DD
I/O S up p ly Vo lta ge 3. 135 3.3 3.465 V
V
DDQ
Supply Voltage 0 0 0 V
V
SS
Inp ut Hig h Vo l tag e - Inputs 2.0
V
IH
Input High Voltage - I/O 2.0
V
IH
Input Lo w Vol tage -0.3
V
IL
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
____
V
+0.3 V
DD
____
V
+0.3
DDQ
____
0.8 V
Gate
5281drw 01b
,
Data I/O [0:15],
TDO
V
I/O P[ 1:2]
6.424
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
Grade
Temperature
(1)
VSSVDDV
DDQ
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Comm ercial 0°C to +70°C 0V 3.3V± 5% 3.3V± 5%
Ind us tria l - 40° C to + 85°C 0 V 3.3V ±5% 3. 3V ± 5%
NOTES:
5281 tbl 05
1. TA is the "instant on" case temperature.
Pin Configuration - 128K x 36
D
L
4
3
2
A6A
100 99 9 8 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
B
C
C
2
1
7
E
W
E
1
2
D
S
LK
D
W
W
W
B
B
B
S
E
C
C
V
V
W
/
R
/
(2)
(2)
V
N
E
C
C
D
E
A
N
O
C
9
A8A
N
DDQ
V
SS
V
SS
DDQ
DD
V
SS
V
DDQ
V
SS
SS
V
DDQ
1
P3
2
16
3
17
4
5
6
18
7
19
8
20
9
21
10
11
12
22
13
23
(1)
14
15
(1)
16
17
18
24
19
25
20
21
22
26
23
27
24
28
25
29
26
27
28
30
29
31
30
P4
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
O
LB
5
A0A1A2A3A4A
S
C
N
D
C
N
C
S
V
C
D
N
N
V
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
V
I/O
I/O
V
DD
V
DD
I/O
I/O
V
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
80
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
V
V
V
VSS/ZZ
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
5281 drw 02
15
14
DDQ
SS
13
12
11
10
SS
DDQ
9
8
SS
DD
DD
7
6
DDQ
SS
5
4
3
2
SS
DDQ
1
0
P2
(1)
(3)
,
P1
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
14A13A12A11A10
16
A15A
A
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
6.42
5
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
Symbol
Rati ng
Commercial &
Industrial Values
Uni t
TERM
TERM
DD
TERM
TERM
DDQ
A
Commercial
Industrial
BIAS
STG
T
OUT
Symbol
Parameter
(1)
Conditions
Max.
Unit
CINInp ut Cap ac itanc e
VIN = 3dV
5pFC
I/O
I/O Cap aci tanc e
V
OUT
= 3dV
7
pF
5281 tbl 07
Symbol
Par a me t e r
(1)
Conditions
Max .
Unit
CINInput Cap aci tance
VIN = 3dV
7pFC
I/O
I/O Cap aci tance
V
OUT
= 3dV
7
pF
5281 tbl 07 a
Symb ol
Par a me t e r
(1)
Con dit ions
Max .
Unit
CINInp ut Cap ac itanc e
VIN = 3dV
TBDpFC
I/O
I/O Cap ac itance
V
OUT
= 3dV
TBD
pF
5281 tb l 07b
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18
LD
2
2
1
7
E
E
A6A
C
C
10099989796959493929190 8786858483828189 88
1
NC
2
NC
3
NC
4
DDQ
V
5
SS
V
6
NC
7
NC
8
8
I/O
9
9
I/O
10
SS
V
11
DDQ
V
12
10
I/O
13
11
I/O
(1)
14
DD
V
15
DD
V
(1)
16
DD
V
17
SS
V
18
12
I/O
19
13
I/O
20
DDQ
V
21
SS
V
22
14
I/O
23
15
I/O
24
P2
I/O
25
NC
26
V
SS
27
DDQ
V
28
NC
29
NC
30
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5
O
LB
1
2
D
S
C
C
W
W
B
B
N
N
C
A0A1A2A3A4A
N
LK
D
S
E
C
V
V
C
S
C
D
C
S
D
N
N
V
V
/
(2)
(2)
V
N
W
E
C
D
E
/
A
O
C
R
C
N
9
C
A8A
N
N
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
5281 drw 02a
15A14A13A12A11
17
A
A16A
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
Absolute Maximum Ratings
(2)
V
10
A
NC
NC
V
V
NC
I/O
I/O
I/O
V
V
I/O
I/O
V
V
V
VSS/ZZ
I/O
I/O
V
V
I/O
I/O
NC
NC
V
V
NC
NC
NC
DDQ
SS
SS
DDQ
SS
DD
DD
DDQ
SS
SS
DDQ
V
V
P1
7
6
V
5
4
(1)
(7)
T
(3)
3
2
T
1
0
T
,
P
I
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
Termi nal Voltage with
-0.5 to +4.6 V
Re sp e c t to GN D
(3,6)
Termi nal Voltage with
-0.5 to V
Re sp e c t to GN D
(4,6)
Termi nal Voltage with
-0.5 to VDD +0.5 V
Re sp e c t to GN D
(5,6)
Termi nal Voltage with
-0.5 to V
Re sp e c t to GN D
-0 to + 70
Operating Temperature
-40 to +85
Operating Temperature
Temperature
-55 to +125
Under Bias
Storage
-55 to +125
Temperature
Po we r Dis s ip a tio n 2. 0 W
DC Outp u t Curre nt 50 mA
+0.5 V
supply ramp up.
7. TA is the "instant on" case temperature.
(1)
V
o
C
o
C
o
C
o
C
5281 tbl 06
100 Pin TQFP Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
165 fBGA Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.426
119 BGA Capacitance
(TA = +25° C, f = 1.0MHz)
(1)
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 119 BGA
1234567
DDQ
A V
NC CE
B
NC
C
16
I/O
D
17
I/O
E
DDQ
V
F
20
I/O
G
22
H I/O
DDQ
J V
24
I/O
K
25
L I/O
DDQ
M V
29
N I/O
31
P I/O
R NC A
T NC NC A
DDQ
V
U
A
A
I/O
I/O
I/O
I/O
I/O
DD
V
I/O
I/O
I/O
I/O
I/O
NC/TMS
6
2
7
P3
18
19
21
23
26
27
28
30
P4
5
(3)
A
A
A
V
V
V
BW
V
V
V
BW
V
V
V
LBO
NC/TDI
4
3
2
SS
SS
SS
3
SS
DD(1)
SS
4
SS
SS
SS
10
(3)
NC(2)
LD
ADV/
DD
V
NC V
1
CE
OE
NC(2)
R/W
DD
V
CLK V
NC
CEN
1
A
0
A
DD
V
11
A
NC/TCK
(3)
8
A
9
A
12
A
SS
SS
V
SS
V
BW
SS
V
DD(1)
V
SS
BW
SS
V
SS
V
SS
V
V
14
A
NC/TDO
2
1
DD(1)
(3)
16
A
2
CE
15
A
P2
I/O
13
I/O
12
I/O
11
I/O
9
I/O
DD
V
6
I/O
4
I/O
3
I/O
2
I/O
P1
I/O
13
A
NC NC/ZZ
(3,4)
NC/TRST
DDQ
V
NC
NC
15
I/O
14
I/O
DDQ
V
10
I/O
8
I/O
DDQ
V
7
I/O
5
I/O
DDQ
V
1
I/O
0
I/O
NC
DDQ
V
5281 drw 13A
,
(5)
Top View
Pin Configuration - 256K x 18, 119 BGA
1234567
DDQ
V
A
NC CE2 A
B
NC
C
8
I/O
D
NC I/O
E
DDQ
V
F
NC I/O
G
11
I/O
H
DDQ
V
J
NC I/O
K
13
I/O
L
DDQ
V
M
15
I/O
N
NC I/O
P
NC A
R
NC A
T
DDQ
V
U
6
A
7
A
NC V
9
NC V
10
NC V
DD
V
12
NC NC
14
I/O
NC V
P2
5
10
NC/TMS
(3)
A
A
SS
SS
V
SS
BW
SS
DD(1)
V
SS
V
SS
V
SS
V
SS
SS
V
LBO
15
A
NC/TDI
4
3
2
2
(3)
NC(2)
ADV/LD
DD
V
NC V
CE
1
OE
NC(2)
R/
W
DD
V
CLK V
CEN
1
A
0
A
DD
V
NC A
NC/TCK
(3)
Top View
8
A
9
A
13
A
SS
SS
V
SS
V
SS
V
SS
V
DD(1)
V
SS
BW
SS
V
SS
V
SS
V
V
DD(1)
14
NC/TDO
1
(3)
16
A
2
CE
17
A
P1
I/O
NC I/O
6
I/O
NC I/O
4
I/O
DD
V
NC I/O
2
I/O
NC V
1
I/O
NC I/O
12
A
11
A
(3,4)
NC/TRST
DDQ
V
NC
NC
NC
7
DDQ
V
5
NC
DDQ
V
3
NC
DDQ
NC
0
NC
NC/ZZ
DDQ
V
5281drw13B
(5)
,
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.42
7
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
7
3BW2CE2
8
6CE2BW4BW1
9
DDQVSSVSSVSSVSSVSSVDDQ
P2
16VDDQVDDVSSVSSVSSVDDVDDQ
15
14
18VDDQVDDVSSVSSVSSVDDVDDQ
13
12
20VDDQVDDVSSVSSVSSVDDVDDQ
11
10
22VDDQVDDVSSVSSVSSVDDVDDQ
9
8
DD
DD
DDVSSVSSVSSVDD
24VDDQVDDVSSVSSVSSVDDVDDQ
7
6
26VDDQVDDVSSVSSVSSVDDVDDQ
5
4
28VDDQVDDVSSVSSVSSVDDVDDQ
3
2
30VDDQVDDVSSVSSVSSVDDVDDQ
1
0
DDQVSS
NC/
DD
SSVDDQ
P1
5A2
1
10A13A14
4A3
0
11A12A15A16
5281 tbl 25
7CE1BW2
2
8A10
2
1
9
DDQVSSVSSVSSVSSVSSVDDQ
P1
DDQVDDVSSVSSVSSVDDVDDQ
7
DDQVDDVSSVSSVSSVDDVDDQ
6
DDQVDDVSSVSSVSSVDDVDDQ
5
DDQVDDVSSVSSVSSVDDVDDQ
4
DD
DD
DDVSSVSSVSSVDD
DDQVDDVSSVSSVSSVDDVDDQ
3
DDQVDDVSSVSSVSSVDDVDDQ
2
DDQVDDVSSVSSVSSVDDVDDQ
1
DDQVDDVSSVSSVSSVDDVDDQ
0
DDQVSS
NC/
DD
SSVDDQ
5A2
1
11A14A15
4A3
0
12A13A16A17
5281 tbl 25a
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 165 fBGA
1234567891011
ANC
(2)
A
BNC A
CI/OP3NC V
DI/O17I/O
EI/O19I/O
FI/O21I/O
GI/O23I/O
HV
(1)
(1)
V
JI/O25I/O
KI/O27I/O
LI/O29I/O
MI/O31I/O
NI/OP4NC V
NC
(2)
(2)
PNCNC
R
LBO
CE1 BW
NC V
A
A
TRST
NC/TDI
NC/TMS
(3, 4)
(3)
(3)
CLK R/
NC V
A
NC/TDO
A
NC/TCK
CEN
LD
ADV/
W
OE
(1)
V
(3)
A
(3)
A
(2)
NC
NC
(2)
A
A
NC
NC I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC NC NC/ZZ
I/O
I/O
I/O
I/O
NC I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
(2)
(5)
Pin Configuration - 256K x 18, 165 fBGA
1234567891011
ANC
(2)
BNC A6CE
CNC NCV
DNC I/O8V
ENC I/O9V
FNCI/O10V
GNC I/O11V
HV
(1)
JI/O12NC V
KI/O13NC V
LI/O14NC V
MI/O15NC V
NI/OP2NC V
PNC NC
R
LBO
A
NC
(1)
V
(2)
(2)
NC
NC V
A
A
NC
BW
TRST
NC/TDI
NC/TMS
(3, 4)
(3)
(3)
CE
CLK R/
NC V
A
A
CEN
W
NC/TDO
NC/TCK
ADV
/LD
OE
NC
NC
(2)
(2)
A
A
NC
(2)
NC I/O
NC I/O
NC I/O
NC I/O
NC I/O
NC NC NC/ZZ
I/O
I/O
I/O
I/O
(1)
V
(3)
A
(3)
A
NC NC
(5)
NC
NC
NC
NC
NC
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.428
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
R/WChip
(5)
Enable
ADV/
x
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(2 cycles l ater)
OP E RATIO N
R/
1BW2BW3
(3)
4
(3)
P3
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Synchronous Truth Table
CEN
LD
(1)
BW
D
Q
HiZ
(7)
(7)
(7)
(7)
L L S ele ct L Valid Ex ternal X LOAD WRITE D
L H Se lect L X External X LOAD READ Q
L X X H Va lid Internal LOA D WRITE /
BURS T WRITE
L X X H X Inte rna l LOAD RE AD /
BURST READ
L X Deselect L X X X DESELECT or STOP
BURS T WRITE
(Advance burst counter)
BURST READ
(Advance burst counter)
(2)
(2)
(3)
L X X H X X DESELECT / NOOP NOOP HiZ
H X X X X X X SUSP E ND
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
(4)
Previous Value
5281 tbl 08
Partial Truth Table for Writes
(1)
W
BW
BW
READ HXXXX
WRITE ALL BYTES LLLL L
WRITE BYTE 1 (I/O[0:7], I/OP1)
WRITE BYTE 2 (I/O[8:15], I/OP2)
WRITE BY TE 3 (I/O[16:23], I/ O
WRITE BY TE 4 (I/O[24:31], I/ OP4)
(2)
(2)
(2,3)
)
(2,3)
LLHHH
LHLHH
LHHLH
LHHHL
NO WRITE L HHHH
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
5281 tbl 09
6.42
9
Loading...