Integrated Device Technology Inc IDT71V321S55PF, IDT71V321L25J, IDT71V321L25PF, IDT71V321L35PF, IDT71V321L55J Datasheet

I/O

Control

Address
Decoder

MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address
Decoder

I/O

Control

R/

W

L

CE

L

OE

L

BUSY

L

A

10L

A

0L

3026 drw 01

I/O0L- I/O

7L

CE

L

OE

L

R/

W

L

INT

L

BUSY

R

I/O0R-I/O

7R

A

10R

A

0R

INT

R

CE

R

OE

R

(2)

(1,2) (1,2)

(2)

R/

W

R

CE

R

OE

R

R/

W

R

11

11

Integrated Device Technology, Inc.

HIGH-SPEED 3.3V
2K x 8 DUAL-PORT
STATIC RAM WITH INTERRUPT

IDT71V321S/L

FEATURES:

• High-speed access
—Commercial: 25/35/55ns (max.)

• Low-power operation
—IDT71V321S

—Active: 250mW (typ.)
—Standby: 3.3mW (typ.)

—IDT71V321L

—Active: 250mW (typ.)
—Standby: 660µW (typ.)

• Two

INT

flags for port-to-port communications

• On-chip port arbitration logic

•

BUSY

output flag

• Fully asynchronous operation from either port

• Battery backup operation—2V data retention

• TTL-compatible, single 3.3V ±0.3V power supply

• Available in popular plastic packages

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT71V321 is a high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor com­munications. The IDT71V321 is designed to be used as a
stand-alone 8-bit Dual-Port RAM.

The device provides two independent ports with sepa­rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by

CE

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance technol­ogy, these devices typically operate on only 250mW of
power. Low-power (L) versions offer battery backup data
retention capability, with each Dual-Port typically consum­ing 200µW from a 2V battery.

The IDT71V321 devices are packaged in a 52-pin PLCC
and a 64-pin TQFP (thin plastic quad flatpack).

NOTE:

1.

BUSY

are totem-pole
outputs.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

and

INT

COMMERCIAL TEMPERATURE RANGE OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-3026/2

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.34

1

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

NDEX

A
A
A
A
A
A
A
A

A
I/O
I/O
I/O
I/O

1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L

(1,2)

8
9
10
11
12
13
14
15
16
17
18
19

20

0L

A

4L

I/O

L

OE

5L

I/O

10L

A

6L

I/O

L

L

INT

BUSY

234567474849505152

IDT71V321

TOP VIEW

7L

NC

I/O

L

R/W

CELVCCCE

R

R

R/W

1

J52-1

PLCC

(3)

27262524232221 333231302928

0R1R2R3R4R6R5R

GND

I/O

I/O

I/O

I/O

R

R

INT

BUSY

I/O

I/O

46
45

44
43
42
41
40
39
38
37
36
35

34

10R

A

I/O

OE
A
A
A
A
A
A
A
A
A
A
NC
I/O

R
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R

7R

3026 drw 02

INDEX

OE

L

A

0L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

N/C

A

7L

A

8L

A

9L

N/C

I/O

0L

I/O

1L
2L

I/O

10
11
12

13
14
15

16

L

L

INT

W

BUSY

R/

10L

N/C

N/C

A

636261605958575655

64

1
2
3

4
5
6

7
8
9

18

19

17

4L

3L

N/C

I/O5LI/O6LI/O7LI/O

I/O

64-PIN TQFP

TOP VIEW

22

21

20

L

L

CC

CC

V

V

CE

IDT71V321

PN64-1

25

24

23

N/C

GND

GND

R

R

W

R/

54

R

INT

BUSY

52

53

10R

A

51

N/C

50

N/C

49

48

R

CE

47

46
45

44
43

42
41

(3)

40
39

38
37

36
35
34

33

31

30

28

27

26

29

I/O0RI/O1RI/O2RI/O3RI/O4RI/O

N/C

32

5R

OE

0R

A
A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

N/C
A

7R

A

8R

A

9R

N/C
N/C
I/O
I/O

3026 drw 03

R

7R
6R

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

6.34 2

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Unit

(2)

TERM

V

Terminal Voltage –0.5 to +4.6 V

with Respect to

GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

T

STG Storage –55 to +125 °C

Temperature

I

OUT DC Output 50 mA

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to
+ 0.5V.

< 20mA for the period of VTERM > Vcc

3026 tbl 01

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

CC

Commercial 0°C to +70°C 0V 3.3V ± 0.3V

3026 tbl 02

RECOMMENDED
DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 3.0 3.3 3.6 V

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.0 — Vcc+0.3 V

V

IL Input Low Voltage –0.3

NOTES:

IL (min.) = -1.5V for pulse width less than 20ns.

1. V

TERM must not exceed VCC + 0.5V.

2. V

CAPACITANCE

(1)

(TA = +25°C, f = 1.0MHz) TQFP ONLY

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output Capacitance VIN = 3dV 10 pF

NOTES:

1. This parameter is determined by device characterization but is not
production tested.

2. 3dv references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

(1)

— 0.8 V

(2)

3026 tbl 03

Max. Unit

3026 tbl 04

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

Ll| Input Leakage VCC = 3.6V — 10 — 5 µA

|l

|lLO| Output Leakage

VOL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

V

OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

NOTE:

1. At Vcc < 2.0V input leakages are undefined. Supply CurrentVIN > VCC -0.2V or < 0.2V

Current

(1)

VIN = 0V to VCCVIN = GND to VCC

CE

Current V

(l/O

0-l/O7) lOL= 16mA

= VIH, VOUT = 0V to VCC —10 — 5µA

CC = 3.6V, VOUT = GND to VCC

(VCC = 3.3V ± 0.3V)

lDT71V321LIDT71V321S

3026 tbl 05

6.34 3

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Test

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

ISB1 Standby Current

(Both Ports — TTL
Level Inputs) f = f

ISB2 Standby Current

(One Port — TTL Active Port Outputs Open, L 30 75 30 70 30 60
Level Inputs) f = f

ISB3 Full Standby Current Both Ports

(Both Ports — All
CMOS Level Inputs) V

SB4 Full Standby Current

I

(One Port — All
CMOS Level Inputs)

NOTES: 3026 tbl 06

1. "X" in part numbers indicates power rating (S or L).

CC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.)

2. V

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”

of input levels of GND to 3V.

CE

= VIL, Outputs Open COM’L. S 75 150 75 145 75 135 mA

SEM

= V

IH L 75 120 75 115 75 105

(3)

MAX

CE

R = CEL = VIH COM’L. S 20 50 20 50 20 50 mA

SEM

R =

SEM

L = VIH L20 35 20 35 20 35

(3)

MAX

CE

"A" = VIL and CE"B" = VIH

(3)

MAX

SEM

R =

SEM

L = VIH

CE

L and COM’L. S 1.0 5.0 1.0 5.0 1.0 5.0 mA

CE

R > VCC - 0.2V L 0.2 3.0 0.2 3.0 0.2 3.0

IN > VCC - 0.2V or

V

IN < 0.2V, f = 0

SEM

R =

SEM

CE

"A" < 0.2V and COM’L. S 30 90 30 85 30 75 mA

CE

"B" > VCC - 0.2V

R =

SEM

V

SEM

IN > VCC - 0.2V or VIN < 0.2V

(4)

L > VCC - 0.2V

(5)

L > VCC - 0.2V

(5)

COM’L. S 30 105 30 100 30 90 mA

L30 75 30 70 30 60

Active Port Outputs Open

(3)

MAX

f = f

(1)

(VCC = 3.3V ± 0.3V)

71V321X25 71V321X35 71V321X55

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

DATA RETENTION CHARACTERISTICS (L Version Only)

71V321L

(1)

Symbol Parameter Test Conditions Min. Typ.

DR VCC for Data Retention 2.0 — 0 V

V

CCDR Data Retention Current VCC = 2.0V,

I

(3)

t

CDR

Chip Deselect to Data VIN > VCC - 0.2V or VIN< 0.2V 0 — — ns

CE

> VCC - 0.2V COM'L. — 100 1500 µA

Retention Time

(3)

t

R

Operation Recovery tRC

(2)

—— ns

Time

NOTES:

1. VCC = 2V, TA = +25°C, and is not production tested.

RC = Read Cycle Time.

2. t

3. This parameter is guaranteed by device characterization but not production tested.

6.34 4

Max. Unit

3026 tbl 07