IDT IDT71V2577S, IDT71V2579S User Manual
查询IDT71V2577S75BG供应商
128K x 36, 256K x 18
3.3V Synchronous SRAMs
2.5V I/O, Flow-Through Outputs
Burst Counter , Single Cycle Deselect
Features
◆
128K x 36, 256K x 18 memory configurations
◆◆
◆
◆◆
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
Commercial and Industrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
◆
LBO input selects interleaved or linear burst mode
◆◆
◆
◆◆
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
◆◆
◆
◆◆
3.3V core power supply
◆◆
◆
◆◆
Power down controlled by ZZ input
◆◆
◆
◆◆
2.5V I/O
◆◆
◆
◆◆
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆◆
◆
◆◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA)
Description
The IDT71V2577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V2577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
IDT71V2577S
IDT71V2579S
IDT71V2577SA
IDT71V2579SA
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Pin Description Summary
17
A0-A
CE
1
CS0, CS
OE
GW
BWE
1
BW
, BW2, BW3, BW
CLK Cloc k Input N/A
ADV
ADSC
ADSP
LBO
TMS Test Mode Select Input Synchronous
TDI Test Data Input Input Sync hronous
TCK Test Cloc k Input N/A
TDO Tes t Data Output Output Sync hrono us
TRST
ZZ Sleep Mode Input Asynchronous
0
I/O
-I/O31, I/OP1-I/O
DDQ
VDD, V
SS
V
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V2579.
© 2003 ntegrated Device Technology, Inc.
(1)
4
P4
Address Inputs Input Synchronous
Chip E nab le Input Sync hro nou s
Chip Sel ec ts Input Sync hronous
Output Enab le Input Asy nc hrono us
Global Write Enable Input Synchronous
Byte Write Enab le Input Sync hro nou s
Indiv id ual B yte Write Se le cts Input Sync hro nou s
Burst A dd re ss Ad v ance Input Sync hro nou s
Ad dre s s S tatus (Cache Co ntrol le r) Input Sync hro nou s
Ad dre s s S tatus (Pro ce s so r) Input Sync hro nou s
Line ar / Interl eav e d B urst Ord e r Input DC
JTAG Res e t (Op tio nal) Input Asy nc hro no us
Data Inp u t / Outp ut I/O Sy nc hro n o us
Core P o we r, I/O P o wer Sup p ly N/A
Ground Supply N/A
JUNE 2003
1
48 77 tb l 01
DSC-4877/08
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
Symbol
Pin Function
I/O
Active
Descrip tion
A0-A17Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of
CLK and
Low or
Low and
Low.
Address Status
(Cache Co ntrolle r)
I
LOW
Synchronous Address Status from Cache Controller.
is an active LOW inp ut that is used to lo ad the
address registers with new addresses.
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor.
is an active LOW inp ut that is used to lo ad the
address registers with new addresses.
is gated by
.
Burst Address
Advance
I
LOW
Synchronous Address Advance.
is an active LOW inp ut that is used to adv ance the i nternal b urst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst
counter is not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs
-
. If
is LOW at the rising edge of
CLK the n
x inputs are passed to the next stage in the circuit. If
is HIGH the n the b y te wri te inp uts
are blocked and only
can initiate a write cyc le.
-
Individual Byte
Write E nab le s
I
LOW
Synchronous byte write enables.
controls I/O
, I/OP1,
controls I/O
, I/OP2, etc. Any active
byte write causes all outputs to be disabled.
Chip Enab le
I
LOW
Sync hrono us c hip enab le .
is used with CS
and
to enable the IDT71V2577/79.
also gates
.
CLK
ClockIN/A
This is the clock input. All timing references for the device are made with respect to this input.
CS0Chip Se le c t 0
I
HIGH
Synchronous active HIGH chip select. CS
is used with
and
to enable the c hip.
Chip Se le c t 1
I
LOW
Synchronous active LOW chip select.
is used with
and CS
to enable the c hip.
Glob al Write
Enable
I
LOW
Synchronous glo bal write enable . This input will write all four 9-bit data bytes when LOW on the rising
edge of CLK.
supersedes individual byte write enables.
I/O0-I/O31I/OP1-I/OP4Data In p ut/ Outp ut
I/O
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge
of CLK. The data output path is flow-through (no output register).
Linear Burs t Orde r
I
LOW
Asynchronous burst order selection input. When
is HIGH, the inter-leaved burst sequence is
selected. When
is LOW the Linear burst sequence is selected.
is a static input and must not
change state while the device is operating.
Output Enable
I
LOW
Asynchronous output enable. When
is LOW the data output drivers are enabled on the I/O pins if the
chip is also selected. When
is HIGH the I/O pins are in a high-im pe dance state.
TMS
Test ModeSelect
I
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Te s t Data Inp u t
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling e dg e o f TCK. This pin has an internal pullup.
TDO
Test D ataO utp u t
O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
JTAG Reset
(Optional)
I
LOW
Optional Asynchronous JTAG reset. Can be used to re set the TAP controller, but not req uire d. JTAG reset
oc c ur s auto mati cal ly at p o wer up and al so re s e ts usi ng TMS and TCK p e r IEE E 1149. 1. If not use d
can be le ft floating. This pin has an internal pullup. Only available in BGA package .
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK inte rnally and power down the IDT71V2577/79
to its lo we st p owe r cons umpti o n leve l. Data retentio n is g uarantee d i n Sle ep Mode . This pin has an internal
pull down.
VDDPower Supply
N/A
N/A
3.3V core power supply.
V
Power Supply
N/A
N/A
2.5V I/O Sup ply.
VSSGround
N/A
N/A
Ground.
NC
No Co nne c t
N/A
N/A
NC pins are not electrically connected to the device.
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Definition
(1)
ADSC
ADSP
BW
ADV
BWE
1
CE
CS
GW
LBO
BW
ADSC
ADSP
CE
ADSC
ADSP
ADSP
CE
ADV
1
4
BW
BW
BW
BWE
BWE
GW
1
4
BW
CE
0-7
0
CS
2
BW
1
8-15
CE
ADSP
0
1
1
CS
CE
CE
CS
1
0
GW
LBO
LBO
LBO
OE
TRST
DDQ
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
OE
OE
TRST
4877 t bl 02
6.42
2
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CLK
ADSC
ADSP
CEN
CLR
Binary
Counter
Burst
Sequence
2
Burst
Logic
Q0
Q1
A0*
A1*
INTERNAL
ADDRESS
17/18
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
A0-A
BWE
BW
BW
BW
BW
I/O0-I/O
I/OP1- I/O
16/17
GW
CE
CS
CS
ZZ
OE
CLK EN
ADDRESS
REGISTER
Byte1
Write Register
1
Byte 2
WriteRegister
2
Byte3
Write Register
3
Byte 4
WriteRegister
4
0
1
Powerdown
31
P4
36/18
D
Enable
Register
CLK EN
17/18
Q
2
1
A0,A
2-A17
A
9
9
9
9
DATA INPUT
REGISTER
Byte 1
WriteDriver
Byte 2
WriteDriver
Byte 3
WriteDriver
Byte 4
WriteDriver
36/18
OE
OUTPUT
BUFFER
36/18
,
4877 drw 01
TMS
TDI
TCK
JTAG
(SA Version)
TDO
TRST
(Optional)
6.42
3
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
Symbol
Rati ng
Commerical &
Industrial Values
Uni t
Commercial
Industrial
Grade
Temperature
(1)
VSSVDDV
DDQ
Symbol
Parameter
Min.
Typ.
Max.
Uni t
VDDCore Supply Voltage
3.135
3.3
3.465VV
I/O Supply Voltage
2.375
2.5
2.625VVSSSupply Voltage
000VVIHInput High Voltage - Inputs
1.7
V
+ 0.3VVIHInp ut Hig h Vo l tag e
-
I/O
1.7
V
+ 0.3
V
VILInp ut Lo w Vo l tag e
-0.3
0.7
V
(1)
(1)
(1)
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
(2)
TERM
V
TERM
V
TERM
V
TERM
V
(7)
A
T
BIAS
T
STG
T
T
P
OUT
I
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the “instant on” case temperature.
Term inal Vo l tage with
-0.5 to +4.6 V
Re s p e c t to G ND
(3,6)
Term inal Vo l tage with
-0.5 to V
Re s p e c t to G ND
(4,6)
Term inal Vo l tage with
-0.5 to VDD +0.5 V
Re s p e c t to G ND
(5,6)
Term inal Vo l tage with
-0.5 to V
Re s p e c t to G ND
-0 to +7 0
Operating Temperature
-40 to + 85
Operating Temperature
T emperature
-55 to +125
Under Bias
Storage
-55 to +125
T emperature
Po we r Di ss ip ati o n 2.0 W
DC Output Curre nt 50 mA
DD
DDQ
+0.5 V
V
o
C
o
C
o
C
o
C
4877 t b l 03
Com me rc ial 0°C to + 70° C 0V 3.3V ± 5% 2.5V ± 5%
Industrial -40°C to + 85°C 0V 3.3V± 5% 2.5V± 5%
NOTES:
4877 t b l 04
1. TA is the “instant on” case temperature.
Recommended DC Operating
Conditions
DDQ
____
DD
DDQ
(1)
____
(2)
____
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
4877 t bl 05
100 Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
C
C
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
C
C
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Conditions Max. Unit
Inp ut Cap a ci tanc e VIN = 3dV 5 pF
IN
I/O Cap ac ita nce V
I/O
= 3dV 7 p F
OUT
Conditions Max . Unit
Inp ut Cap ac i tanc e VIN = 3dV 7 pF
IN
I/O Cap ac ita nce V
I/O
= 3dV 7 p F
OUT
4877 tbl 07
4877 tb l 07b
6.42
4
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol Pa ra met e r
C
Inp ut Cap ac ita nce VIN = 3dV 7 p F
IN
C
I/O Cap ac i tanc e V
I/O
Conditions Ma x . Unit
= 3dV 7 p F
OUT
4877 tbl 07a
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36
P
4
3
2
1
0
E
W
W
A6A7C
10099989796959493929190 8786858483828189 88
S
B
B
C
W
B
W
B
1
D
S
S
C
LK
D
S
V
C
V
W
G
E
W
B
C
S
V
S
E
D
O
A
8A9
D
D
A
A
A
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDQ
V
V
DDQ
SS
V
NC
V
DDQ
V
V
DDQ
SS
SS
DD
SS
SS
SS
1
P3
2
16
3
17
4
5
6
18
7
19
8
20
9
21
10
11
12
22
13
23
(1)
14
15
16
17
18
24
19
25
20
21
22
26
23
27
24
28
25
29
26
27
28
30
29
31
30
P4
313233 34 35 363738 39 40 41 42 43 44 45 46 47 48 49 50
80
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
V
NC
V
ZZ
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
P2
15
14
DDQ
SS
13
12
11
10
SS
DDQ
9
8
SS
DD
(2)
7
6
DDQ
SS
5
4
3
2
SS
DDQ
1
0
P1
,
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
O
LB
3
5
A
A4A
0
2
A
A
A
S
D
C
C
C
N
N
C
S
D
N
N
V
V
1
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
10
A
13
11
A
A
15
A
A
A
A
4877drw 02a
16
14
12
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 18
P
C
2
1
0
C
E
A6A7C
10099989796959493929190 8786858483828189 88
C
S
N
N
C
1
D
S
S
W
B
D
W
B
S
C
V
V
LK
C
E
E
W
W
B
O
G
V
S
S
D
8A9
D
D
A
A
A
A
V
V
V
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
V
NC
NC
NC
DDQ
V
NC
NC
I/O
I/O
V
DDQ
SS
V
NC
V
DDQ
V
NC
V
DDQ
NC
NC
NC
DD
SS
SS
SS
SS
P2
SS
1
2
3
4
5
6
7
8
8
9
9
10
11
12
10
13
11
(1)
14
15
16
17
18
12
19
13
20
21
22
14
23
15
24
25
26
27
28
29
30
313233 34 35 363738 39 40 41 42 43 44 45 46 47 48 49 50
80
A
NC
NC
V
V
NC
I/O
I/O
I/O
V
V
I/O
I/O
V
NC
V
ZZ
I/O
I/O
V
V
I/O
I/O
NC
NC
V
V
NC
NC
NC
10
DDQ
SS
P1
7
6
SS
DDQ
5
4
SS
DD
(2)
3
2
DDQ
SS
1
0
SS
DDQ
,
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
0
O
LB
5
2
1
3
A
A4A
A
C
A
A
N
D
S
C
N
C
S
V
C
D
N
N
V
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
14
12
13
11
A
A
A
16
15
A
A
A
4877 drw 02b
17
A
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 119 BGA
1234567
DDQ
V
A
NC
B
C
NC
16
I/O
D
17
I/O
E
DDQ
V
F
20
I/O
G
22
I/O
H
DDQ
V
J
24
I/O
K
25
I/O
L
DDQ
V
M
29
I/O
N
31
I/O
P
NC A
R
NC NC A
T
DDQ
V
U
A
CS
A
I/O
I/O
I/O
I/O
I/O
DD
V
I/O
I/O
I/O
I/O
I/O
NC/TMS
6
0
7
P3
18
19
21
23
26
27
28
30
P4
5
(2)
4
A
3
A
2
A
SS
V
SS
V
SS
V
BW
SS
V
NC V
SS
V
BW
SS
V
SS
V
SS
V
LBO
10
NC/TDI
3
4
(2)
NC/TCK
ADSP
ADSC
DD
V
NC V
CE
OE
ADV BW
GW
DD
CLK V
NC BW
BWE
1
A
0
A
DD
V
11
A
(2)
NC/TDO
8
A
9
A
12
A
SS
SS
V
SS
V
2
SS
V
NC V
SS
1
SS
V
SS
V
SS
V
SS
V
14
A
(2)
NC/
16
A
CS
15
A
P2
I/O
I/O
I/O
I/O
I/O
DD
I/O
I/O
I/O
I/O
I/O
13
NC
TRST
1
13
12
11
9
6
4
3
2
0
(2,4)
4877 drw 02c
DDQ
V
NC
NC
15
I/O
14
I/O
DDQ
V
10
I/O
8
I/O
DDQ
V
7
I/O
5
I/O
DDQ
V
1
I/O
P1
I/O
NCA
(3)
ZZ
DDQ
V
,
Top View
Pin Configuration 256K x 18, 119 BGA
1234567
DDQ
A V
NC
B
NC
C
8
I/O
D
NC I/O
E
DDQ
V
F
NC I/O
G
11
I/O
H
DDQ
V
J
NC I/O
K
13
I/O
L
DDQ
V
M
15
I/O
N
NC I/O
P
NC A
R
NC A
T
DDQ
V
U
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6
A
CS
0
7
A
NC V
9
NC V
10
NC V
DD
V
12
NC
14
I/O
NC V
P2
5
10
NC/TMS
(2)
4
A
3
A
2
A
SS
SS
V
SS
2
SS
NC V
SS
V
SS
V
SS
V
SS
SS
V
LBO
15
A
(2)
NC/TDI
Top View
ADSP
ADSC
DD
V
NC V
CE
OE
ADVBW
GW
DD
CLK V
NC BW
BWE
1
A
0
A
DD
V
NC A
NC/TCK
(2)
8
A
9
A
13
A
SS
SS
V
SS
V
SS
V
SS
V
NC V
SS
SS
V
SS
V
SS
V
SS
V
14
NC/TDO
1
(2)
16
A
1
CS
17
A
7
I/O
NC I/O
5
I/O
NC I/O
3
I/O
DD
NC I/O
1
I/O
NC V
0
I/O
NC I/O
12
11
A
NC/TRST
V
V
V
(2,4)
V
4877 drw 02d
DDQ
NC
NC
NC
DDQ
NC
DDQ
NC
DDQ
NC
NCA
ZZ
DDQ
6
4
2
P1
(3)
,
6.42
7
Loading...