IDT IDT71V2556S, IDT71V2558S, IDT71V2556SA, IDT71V2558SA User Manual

A0-A17Address Inputs

Input

Synchronous

1

, CE2,

2

Chip Enables

Input

Synchronous

Output E nabl e

Input

Asynchronous

R/WRead / Write Si g nal

Input

Synchronous

Clock Enable

Input

Synchronous

1

,

2

,

3

,

4

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV/LDAd vanc e b urs t addr e s s / Load ne w ad d re ss

Input

Synchronous

Linear / Interleaved Burst Order

Input

Static

TMS

Test Mode Select

Input

Synchronous

TDI

Tes t D ata In p u t

Input

Synchronous

TCK

Test C lo c k

Input

N/A

TDO

Test D at a O ut p u t

Output

Synchronous

JTAG Reset (Optional)

Input

Asynchronous

ZZ

Sleep Mode

Input

Synchronous

I/O0-I/O31, I/OP1-I/OP4Data In p u t / O utp u t

I/O

Synchronous

VDD, V

DDQ

Core P o we r, I/O P o wer

Supply

Static

VSSGround

Supply

Static

4875 tbl 01

查询IDT71V2556S供应商

128K x 36, 256K x 18

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter
Pipelined Outputs

Features

◆◆

◆

◆◆

128K x 36, 256K x 18 memory configurations

◆◆

◆

◆◆

Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)

◆◆

◆

◆◆

ZBTTM Feature - No dead cycles between write and read
cycles

◆◆

◆

◆◆

Internally synchronized output buffer enable eliminates the
need to control

◆◆

◆

◆◆

Single R/

◆◆

◆

◆◆

Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications

◆◆

◆

◆◆

4-word burst capability (interleaved or linear)

◆◆

◆

◆◆

Individual byte write (

◆◆

◆

◆◆

Three chip enables for simple depth expansion

◆◆

◆

◆◆

3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)

◆◆

◆

◆◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1
complaint)

◆◆

◆

◆◆

Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)

Description

The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega­bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus
Turnaround.

Address and control signals are applied to the SRAM during one clock

Pin Description Summary

OEOE

OE

OEOE

WW

W (READ/WRITE) control pin

WW

BWBW

BWBW

BW1 -

BW4) control (May tie active)

BWBW

BWBW

IDT71V2556S

IDT71V2558S
IDT71V2556SA
IDT71V2558SA

cycle, and two cycles later the associated data cycle occurs, be it read
or write.

The IDT71V2556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V2556/58 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.

There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.

The IDT71V2556/58 has an on-chip burst counter. In the burst mode,
the IDT71V2556/58 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. The LBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).

The IDT71V2556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).

CE

CE

OE

CEN

BW

BW

BW

BW

LBO

TRST

©2004 Integrated Device Technology, Inc.

1

OCTOBER 2004

DSC-4875/08

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

4875 tbl 02

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

Symbol Pin Function I/O Active Description

A0-A

17

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of

CLK, ADV/LD low, CEN low, and true chip e nables .

ADV/LD Advance / Lo ad I N/A ADV/LD is a s ync hro n o us inp ut that is used to lo ad the i nte rnal reg is te rs with ne w ad d re s s and c o ntro l

when it is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the
chip d e selected, any burst in p rog ress is terminated. When ADV/LD is sampled high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored
when ADV/LD is sample d high.

R/ W Re ad / Wri te I N/ A R/W signal is a synchronous input that identifies whether the current load cyc le initiated is a Read or

Write access to the memory array. The data bus activity for the current cycle takes place two clock
cycles later.

CEN

Clock Enable I LOW Synchro nous Clock Enable Input. When CE N is sam p led high, all other synchronous inputs, including

clock are i g nored and outputs remain unchanged. The e ffect of CE N sampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.

BW

1

-BW

4

Ind iv id ua l By te

Write Enables

I LOW Synchronous byte write enables. Each 9-bit byte has its own active low b yte write enable. On load

wri te c y cl es (Wh e n R/ W and ADV/LD are sampled low) the appropriate byte write signal (BW
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write
signals are ig n ore d whe n R/ W is sampled high. The appropriate byte(s) of data are written into the

CE

1

, CE

device two cycles later. BW

2

Chip Enables I LOW Sy nchronous active low chip enable. CE1 and CE2 are used with CE2 to e n abl e the IDT71V2556 /58.

(CE

or CE2 sampled high or CE2 sample d lo w) and ADV/LD low at the rising edge of c lock, initiates a

1

desele ct cycle. The ZBT

-BW4 can all be tied low if always doing write to the entire 36-bit word.

1

TM

has a two cy cle de se lect, i.e ., the data bus will tri-state two cloc k cy cle s

after des ele ct is initiated.

CE

2

Chip Enable I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has

inverted p olarity but otherwise ide ntical to CE

and CE2.

1

CLK Clock I N/A This is the clock input to the IDT71V2556/58. Exce p t for OE, all timing references for the de vice are

made with respect to the rising edge of CLK.

I/O

-I/O

0

I/OP1-I/O

LBO

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered

31

P4

and triggered by the rising edge of CLK.

Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO

is low the Linear burst se quence is selected. LBO i s a s tatic input and it mus t no t ch ang e d uri ng
device operation.

OE

Output Enab l e I LOW As ync hro n ous o utp ut e nab le . OE m ust b e l o w to re ad d ata from the 71V255 6/58 . W he n OE is high the

I/O pins are in a high-impedance state. OE d oes not need to be actively controll ed for read and write
cy c le s . In no rmal o p er atio n, OE can be tied low.

TMS Test Mode Se lect I N/A

TDI Te st Data In pu t I N/ A

TCK Test C l oc k I N/ A

TDO Tes t Data Ou tp ut O N/A

TRST

JTAG Reset

(Op tional)

ILOW

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an inte rnal
pullup.

Serial input of registers placed betwee n TDI and TDO. Sampled on rising edge of TCK. This pin has
an inte rnal p ull up .

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed between TDI and TDO. This output is active depending on the state of
the TAP c ontroller.

Optional Asynchronous JTAG reset. Can be used to re set the TAP controller, but not required. JTAG
re set occurs a utomaticall y at p owe r up and also re sets using TMS and TCK per IE EE 1149.1. If not
used TRST can be l e ft fl o ati ng. Thi s p i n ha s a n i nte r nal p u ll up .

Synchronous s leep mode input. ZZ HIGH will gate the CLK internally and p ower do wn the

ZZ Sleep Mode I HIGH

IDT71V2556/ 2558 to i ts l o we st p o we r c o ns ump ti on le v e l. Data rete n tio n is g uar ante ed i n Sl e e p Mod e .
This p in has an i nte rnal p ull d o wn

V

DD

V

DDQ

V

SS

Power Supply N/A N/A 3.3V core power supply.
Power Supp ly N/A N/A 2.5V I/O Supp ly.

Ground N/A N/A Ground.

-BW4)

1

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.422

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

Address A [0:16]

CE

1, CE2,CE2

R/W

CEN

ADV/LD

BWx

Clock

DQ

DQ

egister

Input R

DQ

Clk

Address

Control

Control Logic

Clk

128Kx36 BIT

MEMORY ARRAY

DI DO

Mux

D

Output Register

Q

Sel

OE

TMS

TDI

TCK

TRST

(optional)

JTAG

(SA Version)

TDO

Gate

Data I/O [0:31],

I/O P[1:4]

4875 drw 01a

,

6.42

3

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

(2)

(1)

4875 tbl 03

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

Address A [0:17]

CE

1, CE2,CE2

ADV/

Clock

LBO

R/

CEN

LD

BW

W

256x18 BIT

MEMOR YARRAY

DQ

DQ

egister

Address

Control

DI DO

x

Inpu t R

DQ

Clk

Control Logic

Clk

Mux

D

Output Register

Q

Sel

OE

TMS

TDI

TCK

TRST

(optional)

JTAG

(SA Version)

Recommended DC Operating

Conditions

Symbol Parameter Min. Typ. Max. Unit

Core S up p ly Vo ltag e 3.135 3.3 3. 465 V

V

DD

I/O S up p ly Vol tag e 2.3 75 2.5 2. 625 V

V

DDQ

Supply Voltage 0 0 0 V

V

SS

Input High Voltage - Inputs 1.7

V

IH

I nput Hi gh Volta g e - I/O 1. 7

V

IH

Input Lo w Vo ltag e -0.3

V

IL

NOTES:

1. V IL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

____

V

+0.3 V

DD

____

V

+0.3

DDQ

____

0.7 V

Gate

4875 drw 01b

Data I/O [0:15],

TDO

V

I/O P[1:2]

6.424

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Grade

Temperature

(1)

VSSVDDV

DDQ

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

Comm ercial 0° C to +70°C 0V 3.3V± 5% 2.5V± 5%

Ind us tria l -40°C to + 85°C 0 V 3. 3V±5% 2. 5V ± 5%

NOTES:

4875 tbl 05

1. TA is the "instant on" case temperature.

Pin Configuration  128K x 36

LD

4

3

2

A6A

100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88

B

C

C

2

1

7

E

W

E

1

2

D

S

LK

D

W

W

W

B

B

B

S

E
C

C

V

V

W

/
R

/

(2)

(2)

V

N

E

C

D

E

A

N

O

C

9

C

A8A

N

DDQ

V

SS

V

SS

DDQ

V

DD

V

SS

DDQ

V

SS

V

SS

DDQ

1

P3

2

16

3

17

4
5
6

18

7

19

8

20

9

21

10
11
12

22

13

23

(1)

14
15

(1)

16
17
18

24

19

25

20
21
22

26

23

27

24

28

25

29

26
27
28

30

29

31

30

P4

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

O
LB

5

C

A0A1A2A3A4A

N

D

S

C

S

N

V

C

C

D

N

N

V

I/O
I/O
I/O

V

I/O
I/O
I/O
I/O

V

I/O
I/O

V

DD

V

DD

I/O
I/O

V

I/O
I/O
I/O
I/O

V

I/O
I/O
I/O

80

I/O
I/O
I/O
V
V

SS

I/O
I/O
I/O
I/O
V
V

I/O
I/O
V
V

DD

V

DD

V
I/O
I/O
V

DDQ

V

SS

I/O
I/O
I/O
I/O
V
V
I/O
I/O

I/O

4875 drw 02

P2

15

14

DDQ

13
12
11

10
SS
DDQ

9

8
SS

(1)

SS/ZZ

7

6

5

4

3

2
SS
DDQ

1

0

P1

(3)

,

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

14A13A12A11A10

16

A15A

A

Top View

TQFP

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).

6.42

5

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Symbol

Ratin g

Commercial &

In dus tri al Va l ues

Uni t

TERM

TERM

DD

TERM

TERM

DDQ

A

Commerical

Industrial

BIAS

STG

T

OUT

Symbol

Parameter

(1)

Conditions

Max.

Unit

CINInp ut Capa ci tanc e

VIN = 3dV

5pFC

I/O

I/O Cap aci tance

V

OUT

= 3dV

7

pF

4875 tbl 07

Symbol

Par a me ter

(1)

Conditions

Max .

Unit

CINInput Cap aci tance

VIN = 3dV

7pFC

I/O

I/O Cap aci tance

V

OUT

= 3dV

7

pF

4875 tbl 07 a

Symbo l

Par a me t e r

(1)

Conditions

Max .

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

TBDpFC

I/O

I/O Cap aci tanc e

V

OUT

= 3dV

TBD

pF

4875 tb l 07b

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 18

LD

2

2

1

7

E

E

A6A

C

C

10099989796959493929190 8786858483828189 88

1

NC

2

NC

3

NC

4

DDQ

V

5

SS

V

6

NC

7

NC

8

8

I/O

9

9

I/O

10

SS

V

11

DDQ

V

12

10

I/O

13

11

I/O

(1)

14

DD

V

15

DD

V

(1)

16

DD

V

17

SS

V

18

12

I/O

19

13

I/O

20

DDQ

V

21

SS

V

22

14

I/O

23

15

I/O

24

P2

I/O

25

NC

26

SS

V

27

DDQ

V

28

NC

29

NC

30

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5

O
LB

1

2

D

S

C

C

W

W
B

N

B

N

C

A0A1A2A3A4A

N

LK

D

S

E

C

V

V

C

D

S

C

C

S

D

N

N

V

V

/

(2)

(2)

V

N

W

E

C

D

C

E

/

C

R

C
N

N

A8A

A

N

O

15A14A13A12A11

A16A

A

9

17

80
79
78
77
76
75
74
73
72

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

4875 drw 02a

Absolute Maximum Ratings

(2)

V

10

NC
NC

V
NC
I/O
I/O
I/O

I/O
I/O

V
V

V
V
I/O
I/O
NC
NC

A

V

V
V

V

V
I/O
I/O

V
V
NC
NC
NC

DDQ
SS

P1
7

6
SS
DDQ

5

4
SS
DD
DD
SS/ZZ

3

2
DDQ
SS

1

0

SS
DDQ

V

V

V

(1)

(7)

T

(3)

T

T

P

,

I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional

Te rminal Vo ltage with

Respect to GND

(3,6)

Te rminal Vo ltage with
Respect to GND

(4,6)

Te rminal Vo ltage with

-0.5 to VDD +0.5 V

Respect to GND

(5,6)

Te rminal Vo ltage with

-0.5 to V

Respect to GND

Operating Temperature

Operating Temperature
Temperature

Under B ia s
Storage

Temperature
Po we r Di ss i p atio n 2. 0 W
DC Output Current 50 mA

(1)

-0.5 to +4. 6 V

-0.5 to V

+0.5 V

-0 to + 70

-40 to + 85

-55 to + 125

-55 to + 125

4875 tbl 06

operation of the device at these or any other conditions above those indicated

Top View

TQFP

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long
as the input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).

in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.

7. TA is the "instant on" case temperature.

100 TQFP Capacitance

(1)

(TA = +25° C, f = 1.0MHz)

119 BGA Capacitance

(1)

(TA = +25° C, f = 1.0MHz)

V

o

C

o

C

o

C

o

C

165 fBGA Capacitance

(1)

(TA = +25° C, f = 1.0MHz)

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.426

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 119 BGA

1234567

DDQ

V

A

NC CE

B

NC

C

16

I/O

D

17

I/O

E

DDQ

V

F

20

I/O

G

22

I/O

H

DDQ

V

J

24

I/O

K

25

I/O

L

DDQ

V

M

29

I/O

N

31

I/O

P

NC A

R

NC NC A

T

DDQ

V

U

6

A

2

7

A

P3

I/O

18

I/O

19

I/O

21

I/O

23

I/O

DD

V

26

I/O

27

I/O

28

I/O

30

I/O

P4

I/O

5

NC/TMS

(3)

4

A

3

A

2

A

SS

V

SS

V

SS

V

BW

SS

V

DD(1)

V

SS

V

BW

SS

V

SS

V

SS

V

LBO

10

NC/TDI

3

4

(3)

NC(2)

ADV/LD

DD

V

NC V

1

CE

OE

NC(2)

R/W

DD

V
CLK V

NC

CEN

1

A

0

A

DD

V

11

A

(3)

NC/TCK

8

A

9

A

12

A

SS

SS

V

SS

V

2

BW

SS

V

DD(1)

V

SS

1

BW

SS

V

SS

V

SS

V

V

DD(1)

14

A

NC/TDO

16

A

2

CE

15

A

P2

I/O

13

I/O

12

I/O

11

I/O

9

I/O

DD

V

6

I/O

4

I/O

3

I/O

2

I/O

I/O

P1

13

A

NC NC/ZZ

(3)

TRST

NC/

(3,4)

DDQ

V

NC
NC

15

I/O

14

I/O

DDQ

V

10

I/O

8

I/O

DDQ

V

7

I/O

5

I/O

DDQ

V

1

I/O

0

I/O

NC

DDQ

V

4875 drw 13a

,

(5)

Top View

Pin Configuration  256K x 18, 119 BGA

1234567

DDQ

V

A

NC CE2 A

B

NC

C

8

I/O

D

NC I/O

E

DDQ

V

F

NC I/O

G

11

I/O

H

DDQ

V

J

NC I/O

K

13

I/O

L

DDQ

V

M

15

I/O

N

NC I/O

P

NC A

R

NC A

T

DDQ

V

U

NOTES:

1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. G4 and A4 are reserved for future 8M and 16M respectively.

3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin T7 supports ZZ (sleep mode) on the latest die revision.

6

A

7

A

NC V

9

NC V

10

NC V

DD

V

12

NC NC

14

I/O

NC V

P2

5

10

NC/TMS

(3)

4

A

3

2

A

SS

SS

V

SS

BW

SS

DD(1)

V

SS

V

SS

V

SS

V

SS

SS

V

LBO

15

A

NC/TDI

2

(3)

Top View

NC(2)

ADV/LD

DD

V

NC V

1

CE

OE

NC(2)

R/W

DD

V

CLK V

CEN

1

A

0

A

DD

V

NC A

(3)

NC/TCK

8

A

9

A

13

A

SS

SS

V

SS

V

SS

V

SS

V

DD(1)

V

SS

BW

1

SS

V

SS

V

SS

V

V

DD(1)

14

NC/TDO

16

A

CE

17

A

I/O

NC I/O
I/O
NC I/O
I/O

DD

V

NC I/O
I/O
NC V
I/O
NC I/O

12

A

11

A

(3)

NC/

2

P1

6

4

2

1

TRST

(3,4)

DDQ

V

NC
NC
NC

7

DDQ

V

5

NC

DDQ

V

3

NC

DDQ

NC

0

NC
NC/ZZ

DDQ

V

4875 drw 13b

,

(5)

6.42

7

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

7

3BW2CE2

8

6CE2BW4BW1

9

DDQVSSVSSVSSVSSVSSVDDQ

P2

16VDDQVDDVSSVSSVSSVDDVDDQ

15

14

18VDDQVDDVSSVSSVSSVDDVDDQ

13

12

20VDDQVDDVSSVSSVSSVDDVDDQ

11

10

22VDDQVDDVSSVSSVSSVDDVDDQ

9

8

DD

DD

DDVSSVSSVSSVDD

24VDDQVDDVSSVSSVSSVDDVDDQ

7

6

26VDDQVDDVSSVSSVSSVDDVDDQ

5

4

28VDDQVDDVSSVSSVSSVDDVDDQ

3

2

30VDDQVDDVSSVSSVSSVDDVDDQ

1

0

DDQVSS

NC/

DD

SSVDDQ

P1

5A2

1

10A13A14

4A3

0

11A12A15A16

4875 tb l 25

7CE1BW2

2

8A10

2

1

9

DDQVSSVSSVSSVSSVSSVDDQ

P1

DDQVDDVSSVSSVSSVDDVDDQ

7

DDQVDDVSSVSSVSSVDDVDDQ

6

DDQVDDVSSVSSVSSVDDVDDQ

5

DDQVDDVSSVSSVSSVDDVDDQ

4

DD

DD

DDVSSVSSVSSVDD

DDQVDDVSSVSSVSSVDDVDDQ

3

DDQVDDVSSVSSVSSVDDVDDQ

2

DDQVDDVSSVSSVSSVDDVDDQ

1

DDQVDDVSSVSSVSSVDDVDDQ

0

P2

DDQVSS

NC/

DD

SSVDDQ

5A2

1

11A14A15

4A3

0

12A13A16A17

4875 tb l 25a

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 165 fBGA

1234567891011

ANC

(2)

A
BNC A
CI/OP3NC V
DI/O17I/O
EI/O19I/O

FI/O21I/O
GI/O23I/O
HV

(1)

(1)

V

JI/O25I/O
KI/O27I/O

LI/O29I/O
MI/O31I/O
NI/OP4NC V

NC

(2)

(2)

PNCNC
R

LBO

CE1 BW

NC V

A
A

TRST

NC/TDI

NC/TMS

(3,4)

(3)

(3)

CEN

CLK R/W

NC V

A

NC/TDO

A

NC/TCK

(1)

(3)

(3)

ADV/LD NC

OE

V
A

A

NC

(2)

(2)

A
A

NC

NC I/O
I/O
I/O
I/O

I/O

I/O
I/O
I/O

I/O

NC NC NC/Z Z

I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O

NC I/O

NC

(2)

(5)

NC

Pin Configuration  256K x 18, 165 fBGA

1234567891011
ANC
BNC A6CE

(2)

A

NC

NC

BW

CE

CEN

CLK R/W

ADV/LD NC

OE

CNC NCV
DNC I/O8V
ENC I/O9V

FNCI/O10V
GNC I/O11V
HV

(1)

(1)

V

NC V

JI/O12NC V
KI/O13NC V

LI/O14NC V
MI/O15NC V

NC/TDO
NC/TCK

(1)

V

(3)

A

(3)

A

NI/O
PNC NC
R

LBO

NC V

(2)

(2)

NC

(3,4)

TRST

A
A

NC/TDI

NC/TMS

(3)

(3)

NC V

A
A

NOTES:

1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively respectively.

3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin H11 supports ZZ (sleep mode) on the latest die revision.

6.428

NC

(2)

(2)

A

A
NC I/O
NC I/O
NC I/O
NC I/O
NC I/O

NC NC NC /ZZ

I/O
I/O
I/O
I/O

NC NC

NC

(2)

(5)

NC
NC
NC
NC

NC

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

R/WChip

(5)

Enable

ADV/

x

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(2 cycles l ater)

OP E RATION

R/

1BW2BW3

(3)

4

(3)

P3

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Synchronous Truth Table

CEN

LD

(1)

BW

D

Q

HiZ

(7)

(7)

(7)

(7)

L L Sele ct L Valid Ex ternal X LOAD WRITE D
L H Sele ct L X External X LOAD READ Q
L X X H Valid Inte rnal LOAD WRITE /

BURS T WRITE

L X X H X Interna l LOA D RE A D /

BURST READ

L X Deselect L X X X DESELECT or STOP

BURS T WRITE

(Advance burst counter)

BURST READ

(Advance burst counter)

(2)

(2)

(3)

L X X H X X DESELECT / NOOP NOOP HiZ
H X X X X X X SUS PEND

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/ W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.

5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

(4)

Previous Value

4875 tbl 08

Partial Truth Table for Writes

(1)

W

BW

BW

READ HXXXX

WRITE ALL BYTES LLLLL
WRITE BYTE 1 (I/O[0:7], I/OP1)
WRITE BYTE 2 (I/O[8:15], I/OP2)
WRITE BYTE 3 (I/O[16:23] , I/O
WRITE BYTE 4 (I/O[24:31] , I/OP4)

(2)

(2)

(2,3)

)

(2,3)

LLHHH
LHLHH
LHHLH
LHHHL

NO WRITE L HHHH

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for X18 configuration.

4875 tbl 09

6.42

9