IDT IDT71T75702, IDT71T75902 User Manual

A0-A19Address Inputs

Input

Synchronous

, CE2,

Chip Enab le s

Input

Synchronous

Output Enable

Input

Asynchronous

R/WRead/ Write Sig nal

Input

Synchronous

Clo ck Enable

Input

Synchronous

,

,

,

Individ ual B y te Write S el e c ts

Input

Synchronous

CLK

Clock

Input

N/A

ADV/LDAdv ance B urst Ad dr ess /Lo a d Ne w Ad d res s

Input

Synchronous

Linear/Interleav e d B urst Orde r

Input

Static

TMS

Te st Mo de S e l e c t

Input

N/A

TDI

Te st Data Input

Input

N/A

TCK

Tes t C loc k

Input

N/A

TDO

Tes t D a t a Out p ut

Output

N/A

JTAG Re s e t (Optional)

Input

Asynchronous

ZZ

Slee p Mo d e

Input

Synchronous

I/O0-I/O31, I/OP1-I/OP4Data Input/Output

I/O

Synchronous

VDD, V

Co re Po we r, I/ O P o wer

Supply

Static

VSSGround

Supply

Static

查询IDT71T75702供应商

512K x 36, 1M x 18

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter
Flow-Through Outputs

Features

◆◆

◆

◆◆

512K x 36, 1M x 18 memory configurations

◆◆

◆

◆◆

Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)

◆◆

◆

◆◆

ZBTTM Feature - No dead cycles between write and read cycles

◆◆

◆

◆◆

Internally synchronized output buffer enable eliminates the
need to control OE

◆◆

◆

◆◆

Single R/W (READ/WRITE) control pin

◆◆

◆

◆◆

4-word burst capability (Interleaved or linear)

◆◆

◆

◆◆

Individual byte write (BW1 - BW4) control (May tie active)

◆◆

◆

◆◆

Three chip enables for simple depth expansion

◆◆

◆

◆◆

2.5V power supply (±5%)

◆◆

◆

◆◆

2.5V (±5%) I/O Supply (VDDQ)

◆◆

◆

◆◆

Power down controlled by ZZ input

◆◆

◆

◆◆

Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

◆◆

◆

◆◆

Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)

Description

The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBTTM, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.

IDT71T75702
IDT71T75902

The IDT71T75702/902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71T75702/902
to be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold their
previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.

The IDT71T75702/902 have an on-chip burst counter. In the burst
mode, the IDT71T75702/902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).

The IDT71T75702/902 SRAMs utilize IDT’s high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).

Pin Description Summary

1

CE

OE

CEN

BW

LBO

TRST

©2002 Integrated Device Technology, Inc.

2

CE

1

2

3

BW

BW

4

BW

DDQ

5319 tbl 01

MAY 2003

1

DSC-5319/07

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

Symbol

Pin Fu nction

I/O

Active

Description

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

19

A0-A

ADV/

Address Inputs I N/A Synchronous Address inputs. The address registe r is trigge red by a combination of the rising edge of

LD

Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control

(1)

CLK, ADV/LD low,

CEN

lo w, and true c hip e nab le s .

when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the
chip deselected, any burst in progress is terminated. When ADV/LD is samp led high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored when
ADV/LD is sampled high.

W

R/

Read / Write I N/ A R/W signal is a synchronous input that identifie s whethe r the current load c ycle initiated is a Read or

Write access to the memory array. The data bus activity fo r the current cycle takes place one clock
cycle late r.

CEN

Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including

clock are ignored and outputs remain unchanged. The effect of CEN samp led high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.

BW

1

-BW

Individual Byte

4

Write Enab le s

I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write

cycles (Whe n R/W and ADV/LD are sampled low) the appropriate byte write signal (BW

1

-BW4) mus t be
valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle

1

-BW4 can all be tied low if always doing write to the entire 36-bit word.

later. BW

CE

1

, CE

Chip Enables I LOW Synchronous active low c hip enable. CE1 and CE2 are used with CE2 to e nab le the IDT71T75702/902

2

1

or CE2 sampled high or CE2 samp led low) and ADV/LD low at the rising ed ge of clock, initiates a

(CE
desele ct cycle. The ZBT

TM

has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after

des elect is initiated .

2

CE

Chip E nab l e I HIGH Synchronous active high chip enable . CE2 is used with CE1 and CE2 to enab le the chip. CE2 has

1

inverted polarity but otherwise identical to CE

and CE2.

CLK Clock I N/A This is the clock input to the IDT71T75702/902. Exc ept for OE, al l ti ming references for the dev i ce are

made with respect to the rising edge of CLK.

0

31

I/O

-I/O

Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The

P4

I/OP1-I/O

LBO

Linear Burst Orde r I LOW Burst orde r sele ctio n inp ut. When LBO is high the Interleaved burst sequence is selected. When LBO is

d ata o utp ut p ath is flo w-th ro ug h (no o utp ut r eg i s te r).

low the Linear burst sequence is selected. LBO is a static input, and it must not change during d e vic e
op e rati o n.

OE

Output E nab le I LOW A sy nc hro nous o utp ut ena bl e . OE mus t b e lo w to re ad d ata from the ID T71T75702/ 90 2. Wh e n OE is HIGH

the I/O pins are in a high-im pe d ance s tate. OE does not need to be actively controlled for read and
write cycles. In normal operation, OE can be tied low.

TMS Test Mode Select I N/A Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.

TDI Tes t Data Inp ut I N/ A

TCK Te s t Clo ck I N/ A

TDO Te s t Data O utp ut O N/ A

TRST

JTAG Reset

(Optional)

ILOW

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven fro m falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed between TDI and TDO. This output is active d epending on the state of
the TAP contro ller.

Op tio nal as y nc hro no us J TAG re s e t. Can be us e d to re se t the TAP c o ntro l le r, b u t not re q ui re d . J TAG
reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not
used TRST can be left floating. This pin has an internal pullup. Only available in BGA package.

Synchronous sleep mode inp ut. ZZ HIGH will gate the CLK internally and power down the

ZZ Sleep Mod e I HIGH

IDT71T75702/902 to its lo wes t po wer co nsump tion le v el. Data retention is guaranteed in Sle e p Mo d e.
This pin has an internal pulld own.

DD

Power Supply N/A N/A 2.5V core power supply.
Power Supply N/A N/A 2.5V I/O Supp ly.

SS

Ground N/A N/A Ground.

5319 tbl 02

NOTE:

V

DDQ

V

V

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

2

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram  512K x 36

LBO

Address A [0:18]

,CE

1

CE

2CE2

R/

W

CEN

ADV/

LD

BW

Clock

512K x 36 BIT

MEMORY ARRAY

DQ

DQ

egister

Address

Control

DI DO

x

Input R

DQ

Clk

Control Logic

Mux

Sel

TMS

TDI

TCK

TRST

(optional)

OE

JTAG

TDO

Gate

Data I/O [0:31] , I/O P[1:4 ]

5319 drw 01

,

6.42

3

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

5319 tbl 03

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram  1M x 18

LBO

Address A [0:19]

CE

,CE

1

2CE2

R/W

CEN

ADV/LD

BWx

Clock

DQ

DQ

egister

Input R

DQ

Clk

Address

Control

Control Logic

1M x 18 BIT

MEMORY ARRAY

DI DO

Mux

Sel

OE

TMS

TDI

JTAG

TCK

TRST

(optional)

Recommended DC Operating
Conditions

Symb ol P arameter Min . Typ. Max. Un it

V

Core Sup p ly Vol tage 2.375 2.5 2.625 V

DD

V

I/O Sup p ly Vo ltage 2.375 2.5 2.625 V

DDQ

V

Ground 0 0 0 V

SS

____

____

____

DD

V

DDQ

V

+0.3

0.7 V

+0.3 V

(2)

VIHInp ut High Vo l tag e — Inp uts 1.7
VIHInp ut High Vo lta g e — I/ O 1. 7
VILInput Lo w Vo ltag e -0.3

NOTE:

1. V IL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.

(1)

TDO

V

Gate

Data I/O [0:15], I/O P[1:2]

5319 drw 01a

,

6.42

4

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

Grade

Temperature

(1)

VSSVDDV

DDQ

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Recommended Operating
Temperature Supply Voltage

Com me rc ial 0°C to + 70° C 0V 2. 5V ± 5% 2.5V ± 5%

Industrial -40°C to + 85°C 0V 2. 5V± 5% 2.5V± 5%

NOTES:

5319 tb l 05

1. TA is the “instant on” case temperature.

Pin Configuration  512K x 36

LD

4

3

2

A6A

10099989796959493929190 8786858483828189 88

B

C

C

2

1

7

E

W

E

1

2

D

S

LK

D

W

W

W

B

B

B

S

E
C

C

V

V

W

/
R

/
V

N

E

D

E
C

18

A

A

O

9

17

A8A

A

I/O
I/O
I/O

V

I/O
I/O
I/O
I/O

V

I/O
I/O

V

V

I/O
I/O

V

I/O
I/O
I/O
I/O

V

I/O
I/O
I/O

DDQ

V

V

DDQ

SS

V

DD

V

DDQ

V

V

DDQ

2

16

3

17

4
5

SS

6

18

7

19

8

20

9

21

10

SS

11
12

22

13

23

(1)

14
15

DD

(2)

16
17

SS

18

24

19

25

20
21

SS

22

26

23

27

24

28

25

29

26

SS

27
28

30

29

31

30

P4

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5

O
LB

A0A1A2A3A4A

S

(3)

S
M

/T
C

N

D

I
D

/T
C

N

(3)

S

D

(3,4)

O

V

V

K

D

C

/T

/T

C

C

N

N

(3)

1

P3

80
79
78
77
76
75
74
73
72

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

14A13A12A11A10

16

A

A15A

I/O
I/O
I/O

V
V
I/O
I/O
I/O
I/O

V

V
I/O
I/O

V
V

V

ZZ

I/O

I/O
V
V
I/O
I/O
I/O
I/O

V

V

I/O

I/O

I/O

5319 drw 02

DDQ
SS

SS
DDQ

SS
SS

DD

DDQ
SS

SS
DDQ

P2
15
14

13
12
11
10

9
8

(1)

7
6

5
4
3
2

1

,

0

P1

Top View

100 TQFP

NOTES:

1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is ≤ VIL.

2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is ≥ VIH.

3. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation,
several settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS,
TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.

4. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.

6.42

5

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

Symbol

Ratin g

Commer cial

Indu strial

Unit

(1)

(1)

(1)

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Pin Configuration  1M x 18

LD

2

2

1

7

E

E

A6A

C

C

100 99 98 97 96 95 94 93 9 2 91 90 87 86 85 84 83 82 8189 88

1

NC

2

NC

3

NC

4

V

DDQ

5

V

SS

6

NC

7

NC

8

I/O

8

9

I/O

9

10

V

SS

11

V

DDQ

12

I/O

10

13

I/O

11

(1)

14

V

SS

15

V

DD

(2)

16

V

DD

17

V

SS

18

I/O

12

19

I/O

13

20

V

DDQ

21

V

SS

22

I/O

14

23

I/O

15

24

I/O

P2

25

NC

26

V

SS

27

V

DDQ

28

NC

29

NC

30

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5

O
LB

1

2

D

S

C

C

W

W

N

B

B

N

(3)

A0A1A2A3A4A

S
M

/T
C

N

LK

D

S

E

C

V

V

C

S

D

(3)

(3)

S

I

D

O

V

D

V

D

/T

/T

C

C

N

N

/
V

N

W

E

D

19

E

/

A

A

O

C

R

11

(3,4)

K
C

/T
C

N

Top View

Absolute Maximum Ratings

18

9

A

A8A

80

A

10

79

NC

78

NC

77

V

DDQ

76

V

SS

75

NC

74

I/O

P1

73

I/O

7

72

I/O

6

71

V

SS

70

V

DDQ

69

I/O

5

68

I/O

4

67

V

SS

(1)

66

V

SS

65

V

DD

64

ZZ

63

I/O

3

62

I/O

2

61

V

DDQ

60

V

SS

59

I/O

1

58

I/O

0

57

NC

56

NC

55

V

SS

54

V

DDQ

53

NC

52

NC

51

NC

5319 drw 02a

17

A15A14A13A12A

A16A

(2)

TERM

V

TERM

V

TERM

V

TERM

V

(7)

A

T

BIAS

T

STG

T

T

P

OUT

I

(3,6)

(4,6)

(5,6)

Terminal Vo ltag e with

Respect to GND
Terminal Vo ltag e with

Respect to GND
Terminal Vo ltag e with

Respect to GND
Terminal Vo ltag e with

Respect to GND

-0.5 to +3.6 -0.5 to +3.6

DD

-0.5 to V

DD

-0.5 to V

+0.5 -0.5 to VDD +0.5

DDQ

-0.5 to V

+0.5 -0.5 to V

Ope rating Temp e rature 0 to + 70 -40 to + 85
Te mp e rature Und er B ias -55 to +125 -55 to +125
Storag e Temp e rature -55 to + 125 -55 to + 125
Po we r Dis s ip atio n 2.0 2.0 W
DC Output Curre nt 50 50 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

,

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.

7. TA is the “instant on” case temperature.

(1)

-0.5 to V

DDQ

DD

+0.5

100 TQFP

NOTES:

1. Pins 14 and 66 do not have to be connected directly to VSS as long as the
input voltage is < VIL.

2. Pin 16 does not have to be connected directly to VDD as long as the input voltage
is > VIH.

3. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and
pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)
pins38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will
remain disabled from power up.

4. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.

TQFP Capacitance

(TA = +25

Symbol Parameter

C

°°

°C, f = 1.0MHz)

°°

Conditions Max. Unit

Inp ut Cap ac i tanc e VIN = 3dV 5 p F

IN

fBGA Capacitance

(TA = +25

Symbo l Parame ter

C

C

°°

°C, f = 1.0MHz)

°°

Input Capacitance VIN = 3dV 7 pF

IN

I/O Cap ac ita nc e V

I/O

Conditions Max. Unit

= 3dV 7 p F

OUT

5319 tb l 07b

V

V

V

V

o

C

o

C

o

C

53 19 tb l 06

C

I/O Ca pa ci tanc e V

I/O

= 3dV 7 p F

OUT

5319 tbl 0 7

BGA Capacitance

(TA = +25

Symbol Para met e r

C

C

I/O

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

°°

°C, f = 1.0MHz)

°°

Conditions Max. Unit

Inp ut Cap ac ita nc e VIN = 3dV 7 pF

IN

I/O Cap ac itanc e V

= 3dV 7 p F

OUT

5319 tbl 07a

6.42

6

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

(3)

(3)

(3)

(3)

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

A

18

DD

NC V

CE

1

OE

A

17

DD

NC

A

1

A

0

DD

A

11

NC/TDO

(1,2,3,4)

A

8

9

A

12

SS
SS

V

SS

V

BW

2

SS

(1)

SS

V

SS

BW

1

SS

V

SS

V

SS

V

(1)

SS

V

A

14

(3)

NC/

A

16

CE

2

A

15

I/O

P2

I/O

13

I/O

12

I/O

11

I/O

9

DD

V

I/O

6

I/O

4

I/O3V
I/O

2

I/O

0

A

13

(4)

NC

(3, 5)

TRST

DDQ

V

NC
NC

I/O

15

I/O

14

DDQ

V

I/O

10

I/O

8

DDQ

V

I/O

7

I/O

5

DDQ

I/O

1

I/O

P1

NC
ZZ

DDQ

V

53 19 t b l 25

Pin Configuration  512K x 36, 119 BGA

1234567

DDQ

AV
BNCCE2A3ADV/LD A
CNCA
DI/O
EI/O17I/O

FV
GI/O20I/O
HI/O22I/O

JV
KI/O24I/O

LI/O25I/O
MV
NI/O29I/O

PI/O31I/O
RNCA
T NCNCA
UV

DDQ

DDQ

DDQ

DDQ

A

A

6

4

A
V
V
V

BW

V

V

BW

V
V
V

LBO

V

2

SS
SS
SS

3

SS

R/W V

(2)

DD

V

SS

CLK V

4

SS

CEN

SS
SS

V

10

(3)

NC/TCK

7

I/O

16

P3

18

I/O

19

21

23

DD

V

V

26

27

I/O

28

30

P4

5

NC/TMS

NC/TDI

Top View

Pin Configurations  1M x 18, 119 BGA

1234567

DDQ

AV
BNCCE2A3ADV/LD A
CNCA
DI/O8NC V
ENCI/O
FV
GNCI/O
HI/O11NC V

JV
KNCI/O12V
LI/O13NC V
MV
NI/O15NC V
PNCI/OP2V
RNCA
TNCA
UV

DDQ

DDQ

DDQ

DDQ

A

6

7

9

NC V

10

DD

V

I/O

14

5

10

NC/TMS

A

A

SS
SS

V

SS

BW

SS

DD

V

SS
SS
SS

V

SS
SS

LBO

A

NC/TDI

4

2

15

2

(2)

(3)

A

19

DD

V

NC V

CE

1

OE

A

18

R/W V

DDVSS

V
CLK V

NC

CEN

A

1

A

0

V

DDVSS

(4)

NC

NC/TCK

(1,2,3,4)

A

8

9

A

13

SS
SS

V
V

SS
SS

V

SS

(1)

SS

1

BW

SS

V

SS

V

SS

V

(1)

A

14

(3)

NC/TDO

A

16

CE

2

A

17

I/O

7

NC I/O
I/O5V
NC I/O
I/O

3

DD

V

NC I/O

1

I/O
NC V
I/O

0

NC I/O
A

12

A

11

(3, 5)

NC/

TRST

DDQ

V

NC
NC
NC

DDQ

NC

DDQ

V

NC

DDQ

NC

P1

NC
ZZ

DDQ

V

531 9 t b l 25a

6

4

2

NOTES:

Top View

1. Pins R5 and J5 do not have to be connected directly to VSS as long as the input voltage is < VIL.

2. Pin J3 does not have to be connected directly to VDD as long as the input voltage is > VIH.

3. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several
settings are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST)
U2, U3, U4 and U6 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.

4. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device).

5. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6.42

7

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

R/

1

,

2

(5)

ADV/

x

ADDRES S

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(One cycle l ater)

OPERATION

R/

1BW2BW3

(3)

4

(3)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1A0A1A0A1A0A1

A0

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Synchronous Truth Table

CEN

W

CE

CE

LD

(1)

BW

D

Q

HIZ

(7)

(7)

(7)

(7)

L L L L Valid Ex ternal X LOAD WRITE D
L H L L X Exte rnal X LOAD REA D Q
L X X H Va li d In te rna l LO AD WRITE /

BURS T WRITE

L X X H X Internal LOAD READ /

BURS T READ

L X H L X X X DESELECT or STOP

BURS T WRITE

(Ad vanc e bu rst co unte r)

BURS T READ

(Ad vanc e bu rst co unte r)

(2)

(2)

(3)

L X X H X X DESELECT / NOOP NOOP HIZ

H X X X X X X SUSPEND

NOTES:

(4)

Prev ious Value

5319 tbl 08

1. L = VIL , H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.

5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z during device power-up.

7. Q - data read from the device, D - data written to the device.

Partial Truth Table for Writes

(1)

W

BW

BW

READ HXXXX

WRITE ALL BYTES L L L L L

(2)

WRITE BYTE 1 (I/O[0:7], I/O
WRITE BYTE 2 (I/O[8:15], I/O
WRITE BYTE 3 (I/O[16:23], I/O
WRITE BYTE 4 (I/O[24:31], I/O

P1

)

(2)

P2

)

(2,3)

P3

)

(2,3)

P4

)

LLHHH
LHLHH
LHHLH
LHHHL

NO WRITE L HHHH

NOTES:

5319 t b l 09

1. L = VIL , H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for x18 configuration.

Interleaved Burst Sequence Table (LBO=VDD)

First Address 000 11011
Seco nd Address 0 1 0 0 1 1 1 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

(1)

11100100

5319 t b l 10

6.42

8