IDT IDT7132SA-LA, IDT7142SA-LA User Manual
m
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Features
◆◆
◆
◆◆
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35/55/100ns (max.)
◆◆
◆
◆◆
Low-power operation
– IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
Functional Block Diagram
OE
L
CE
L
R/W
L
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
◆◆
◆
◆◆
MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
◆◆
◆
◆◆
On-chip port arbitration logic (IDT7132 only)
◆◆
◆
◆◆
BUSY output flag on IDT7132; BUSY input on IDT7142
◆◆
◆
◆◆
Battery backup operation —2V data retention (LA only)
◆◆
◆
◆◆
TTL-compatible, single 5V ±10% power supply
◆◆
◆
◆◆
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
◆◆
◆
◆◆
Military product compliant to MIL-PRF-38535 QML
◆◆
◆
◆◆
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
IDT7132SA/LA
IDT7142SA/LA
OE
R
CE
R
R/W
R
I/O
OL-
I/O
7L
I/O
Control
(1,2)
BUSY
L
A
10L
A
0L
NOTES:
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
Address
Decoder
CE
OE
R/W
MEMORY
ARRAY
11
L
L
L
ARBITRATION
LOGIC
I/O
Control
I/O
OR-
I/O
7R
(1,2)
BUSY
R
A
Address
Decoder
11
CE
R
OE
R
R/W
R
2692 drw 01
10R
A
0R
©2004 Integrated Device Technology, Inc.
JUNE 2004
1
DSC-2692/16
IDT7132SA/LA and IDT 7142SA/LA
,
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Description
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port Static RAMs.
The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM
or as a “MASTER” Dual-Port RAM together with the IDT7142 “SLAVE”
Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
Both devices provide two independent ports with separate control,
address, and l/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature, controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin sidebraze or
plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks.
Military grade product is manufactured in compliance with the latest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(1,2,3)
V
CC
CE
R/W
BUSY
A
10R
OE
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2692 drw 02
R
R
7R
6R
5R
4R
3R
2R
1R
0R
INDEX
R
R
,
Pin Configurations
CE
L
148
R/W
L
2
BUSY
NOTES:
1. All V
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x 2.43 in x .18 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
L
A
OE
A
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
3
10L
4
L
5
0L
6
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L
4L
5L
6L
7L
IDT7132/
7
7142
8
PorC
9
10
11
P48-1
12
13
C48-2
14
15
48-Pin
16
17
18
View
19
20
21
22
23
&
DIP
Top
(4)
(4)
(5)
24
CC pins must be connected to the power supply.
I/O
I/O
I/O
L
Y
L
L
0
L
1
E
0
A
O
A
L
L
S
W
E
/
U
C
B
R
R
C
E
C
C
V
R
W
/
R
R
Y
R
R
S
0
1
E
U
A
O
B
65432148 47 46 45 44 43
A
A
A
A
A
A
A
A
A
A
I/O
I/O
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
7R
6R
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
7
8
9
10
11
12
13
14
15
16
17
18
IDT7132/42L48 or F
48-Pin LCC/ Flatpack
Top View
L48-1
&
F48-1
(4)
(4)
(5)
A
A
A
A
A
A
A
A
A
42
41
40
39
38
37
36
35
34
33
32
31
19 20 21 22 23 25 26 27 28 29 3024
L
L
3
4
O
O
/
/
I
I
Capacitance
Symbol Parameter Conditions
IN
C
OUT
C
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 3V to 0V.
L
L
L
7
6
5
O
O
O
/
/
/
I
I
I
(1)
Input Cap ac itance VIN = 3dV 11 pF
Output Capacitance V
D
N
G
R
0
O
/
I
R
1
O
/
I
R
2
O
/
I
R
3
O
/
I
R
4
O
/
I
(TA = +25°C,f = 1.0MHz)
OUT
= 3dV 11 pF
R
5
O
/
I
(2 )
2692drw03
Max. Unit
2692 tb l 00
2
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
INDEX
(1,2,3)
(con't.)
L
L
E
0
A
O
L
Y
L
0
1
A
L
S
L
W
/
R
C
E
C
C
V
C
U
/
B
N
R
Y
R
R
W
E
/
C
R
R
S
0
C
/
U
1
A
B
N
Pin Configurations
8
A
1L
9
A
2L
10
A
3L
11
A
4L
12
A
5L
13
A
6L
14
A
7L
15
A
8L
16
A
9L
I/O
I/O
I/O
I/O
NOTES:
CC pins must be connected to the power supply.
1. All V
2. All GND pins must be connected to the ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
17
0L
18
1L
19
2L
20
3L
L
4
O
/
I
234567
1
IDT7132/42J
52-Pin PLCC
L
L
L
6
5
7
O
O
O
/
/
/
I
I
I
J52-1
Top View
R
C
D
/
0
N
N
O
/
G
I
(4)
(5)
R
R
2
1
O
O
/
/
I
I
474849505152
46
OE
R
45
A
0R
44
A
1R
43
A
2R
42
A
3R
41
A
4R
40
A
5R
39
A
6R
38
A
7R
37
A
8R
36
A
9R
35
N/C
34
33323130292827262524232221
R
R
R
R
3
O
/
I
6
5
4
O
O
O
/
/
/
I
I
I
7R
I/O
2692 drw 04
Absolute Maximum Ratings
Symbol Rating
(2)
V
TER M
Terminal Voltage
Commercial
& Industrial
-0.5 to +7.0 -0.5 to +7.0 V
(1)
Military Unit
with Respect
to GND
T
BIAS
Te mperature
-55 to +125 -65 to +135
o
C
Unde r Bias
T
STG
Storage
-65 to +150 -65 to +150
o
C
Te mperature
OUT
I
DC Output
50 50 mA
Current
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
2. V
maximum, and is limited to
< 20mA for the period of VTERM > Vcc + 10%.
2692 tbl 01
6.42
Recommended Operating
Temperature and Supply Voltage
Grade
Military -55
Comme rcial 0
Industrial -40
NOTES:
1. This is the parameter T
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Ambient
Temperature GND Vcc
O
C to+125OC0V5.0V + 10%
O
C to +70OC0V5.0V
O
C to +85OC0V5.0V + 10%
A. This is the "instant on" case temperature.
+
Recommended DC Operating
Conditions
Symbol Parameter Min. Typ. Max. Unit
CC
Supply Voltag e 4.5 5.0 5.5 V
V
GND Ground 0 0 0 V
IH
Input High Voltage 2.2
V
IL
Input Lo w Voltage -0.5
V
NOTES:
IL (min.) = -1.5V for pulse width less than 10ns.
1. V
TERM must not exceed Vcc + 10%.
2. V
3
____
(1)
____
(2)
6.0
0.8 V
(1,2)
10%
26 92 tb l 02
V
2692 tbl 03
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
(1,5,8)
Temperature and Supply Voltage Range
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit
CC
Dynamic Ope rating Current
I
(Bo th Ports A ctive)
SB1
Standby Current
I
(Bo th Ports - TTL
Level Inp uts)
SB2
Standby Current
I
(One Port - TTL
Level Inp uts)
I
SB3
Full Standby Current (Both
Ports - All
CMOS Le vel Inp uts )
I
SB4
Full Standby Current
(One Port - All
CMOS Le vel Inp uts )
L
= CER = VIL,
CE
Outputs Disabled
(3)
f = f
MAX
CE
L
= CER = VIH,
(3)
f = f
MAX
CE
"A"
= VIL and CE
Active Port Outputs Disabled
(3)
MAX
f=f
L
and CER > VCC -0.2V
CE
IN
> VCC -0.2V o r VIN < 0.2V, f = 0
V
CE
"A"
< 0.2V andCE
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3)
f = f
MAX
"B"
= V
"B"
> VCC -0.2V
IH
(6)
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit
CC
Dynamic Operating
I
I
I
I
I
SB1
SB2
SB3
SB4
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Lev el Inp uts)
Standby Current
(One Port - TTL
Lev el Inp uts)
Full Standby Current
(Both Ports - All
CMOS Le vel Inputs)
Full Standby Current
(One Port - All
CMOS Le vel Inputs)
L
= CER = VIL,
CE
Outputs Disabled
(3 )
MAX
f = f
L
= CER = VIH,
CE
(3 )
MAX
f = f
"A"
= VIL and CE
CE
Active Port Outputs Disabled
(3)
MAX
f=f
L
and CER > VCC -0.2V
CE
IN
> VCC -0.2V or VIN < 0.2V, f = 0
V
"A"
< 0.2V and CE
CE
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3 )
MAX
f = f
"B"
= V
"B"
> VCC -0.2V
IH
(6)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC Package only
3. At f = f
Max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, T
A=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
7. Not available in DIP packages.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
COM'L SALA110
MIL &
IND
COM'L SALA30
MIL &
IND
COM'L SALA6565165
MIL &
IND
COM'L SALA1.0
(4)
MIL &
IND
(6)
COM'L SALA6060155
MIL &
IND
(4)
(6 )
4
(VCC = 5.0V ± 10%)
(2)
7132X20
(2)
7142X20
Com'l Only
250
110
200
____
SA
LA
SA
LA
____
____
____
65
30
45
____
____
____
____
125
____
SA
LA
SA
LA
____
____
____
15
0.2
____
____
____
____
1156060
____
SA
LA
____
____
____
COM'L SALA6565155
MIL &
IND
COM'L SALA20
MIL &
IND
COM'L SALA40
MIL &
IND
COM'L SALA1.0
MIL &
IND
COM'L SALA4040100
MIL &
IND
7132X25
7142X25
Com'l, Ind
& Military
110
110
110
110
30
30
30
30
65
65
65
65
1.0
5
0.2
1.0
0.2
60
60
SALA6565190
20
SALA20
20
40
SALA4040125
0.2
SALA1.0
0.2
SALA40
40
7132X55
7142X55
Com'l &
Mili tary
(7)
(7)
220
170
280
220
150
115
160
125
145
105
155
115
110
140
110
110
7132X35
7142X35
Com'l &
Military
80
165
80
120
80
230
80
170
65
25
45
25
80
25
60
25
50
12590mA
50
50
150
50
115
15
1.0
5
0.2
30
1.0
10
0.2
45
11085mA
45
45
145
45
105
7132X100
7142X100
Com'l &
Military
65
155
65
110
65
190
65
140
65
20
35
20
65
20
45
20
40
40
40
40
1.0
0.2
1.0
0.2
40
40
40
40
11075mA
125
110
75
90
15
4
30
10
70
85
mA
6545mA
80
60
154mA
30
10
2692 tbl 04a
mA
5535mA
65
45
90
154mA
30
10
9570mA
80
2692 tb l 04b
IDT7132SA/LA and IDT 7142SA/LA
,
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(VCC = 5.0V ± 10%)
7132SA
7142SA
7132LA
7142LA
Symbol Parameter Test Conditions
|I
LO
|I
V
V
Input Leak ag e Curre nt
LI
|
| Output Leak ag e Current
OL
Output Low Voltag e IOL = 4mA
Ope n Drain Output
OL
(1)
VCC = 5.5V,
IN
= 0V to V
V
V
CC
= 5.5V,
IH
CE = V
, V
CC
OUT
= 0V to V
CC
IOL = 16mA
___
___
___
___
10
10
0.4
0.5
Low Voltage (BUSY)
V
NOTE:
1. At Vcc
OH
Output High Voltage IOH = -4mA 2.4
< 2.0V leakages are undefined.
___
Data Retention Characteristics (LA Version Only)
Symbol Parameter Test Condition Min. Typ.
V
DR
I
CCDR
(3)
t
CD R
(3)
t
R
NOTES:
CC = 2V, TA = +25°C, and is not production tested.
1. V
RC = Read Cycle Time
2. t
3. This parameter is guaranteed but not production tested.
V
CC
for Data Retention VCC = 2.0V 2.0
Data Retention Current
Chip Des elect to Data Retention Time
CE >
V
CC
V
IN
> VCC -0.2V o r
IN
< 0.2V
V
-0.2V
Mil. & Ind.
Com'l.
Operation Recove ry Time t
___
___
0
(2)
RC
UnitMin. Max. Min. Max.
___
___
___
___
2.4
(1)
___ ___
100 4000
5µA
5
0.4 V
0.5
___
2692 tb l 0 5
Max. Unit
µA
100 1500 µA
___ ___
___ ___
2692 tb l 06
µA
V
V
V
ns
ns
Data Retention Waveform
V
CC
CE
DATA RETENTION MODE
V
DR
2.0V
4.5V 4.5V
t
CDR
V
IH
6.42
≥
V
DR
5
t
R
V
IH
2692 drw 05
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