• IDT7006 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
•M/S = H for
M/S = L for
BUSY
output flag on Master,
BUSY
input on Slave
• Busy and Interrupt Flags
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
R/
W
L
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in a 68-pin PGA, a 68-pin quad flatpack, a 68pin PLCC, and a 64-pin TQFP
• Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7006 is a high-speed 16K x 8 Dual-Port Static
RAM. The IDT7006 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
OE
R
CE
R
R/
W
R
I/O0L- I/O
NOTES:
1. (MASTER):
BUSY
is
output;
(SLAVE):
BUSY
2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
is input.
BUSY
outputs
and
INT
outputs are
non-tri-stated
push-pull.
BUSY
(1,2)
L
A
A
SEM
INT
13L
7L
Address
0L
L
(2)
L
Decoder
CE
OE
R/
W
L
L
L
14
I/O
Control
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/
S
I/O
Control
Address
Decoder
14
CE
R
OE
R
R/
W
R
I/O0R-I/O
BUSY
A
13R
A
0R
SEM
R
(2)
INT
R
2739 drw 01
7R
(1,2)
R
MILITARY AND COMMERCIAL TEMPERATURE RANGESOCTOBER 1996
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.07
1
IDT7006S/L
INDEX
IDT7006
PN-64
TQFP
TOP VIEW
(3)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
I/O
2L
V
CC
GND
GND
A
4R
BUSY
L
BUSY
R
INT
R
INT
L
GND
M/
S
OE
L
A
5L
I/O
1L
R/
W
L
CE
L
SEM
L
V
CC
OE
R
CE
R
R/
W
R
SEM
R
A
12R
GND
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
I/O
0L
2739 drw 03
A
13R
A
13L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAMMILITARY AND COMMERCIAL TEMPERATURE RANGES
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power.
L
L
L
W
SEM
CE
R/
IDT7006
J68-1
F68-1
TOP VIEW
R
N/C
CE
(1,2)
13R
A
N/C
GND
13L
A
(3)
12R
A
CC
V
11R
A
12L
A
10R
A
10L
11L
A
A
64 63 62 61
40 41 42 43
9R
8R
A
A
7R
A
6L
7L
8L
A
A
A
60
A
5L
59
4L
A
58
A
3L
57
A
2L
56
A
1L
55
A
0L
54
INT
53
BUSY
52
GND
51
M/
50
BUSY
49
INT
48
A
0R
47
A
1R
46
A
2R
45
A
3R
44
A
4R
2739 drw 02
5R
6R
A
A
9L
A
PIN CONFIGURATIONS
N/C
L
0L
OE
N/C
I/O
PLCC / FLATPACK
R
R
R
W
OE
R/
SEM
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
1L
I/O
98765432168676665
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39
7R
I/O
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500µW from a 2V
battery.
The IDT7006 is packaged in a ceramic 68-pin PGA, a 68pin quad flatpack, a 68-pin PLCC, and a 64-pin TQFP (thin
plastic quad flatpack) . Military grade product is manufactured
in compliance with the latest revision of MIL-STD-883, Class
B, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
L
L
S
R
R
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the the actual part-marking.
6.072
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAMMILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)
11
10
09
08
07
06
05
04
03
02
01
515048464442403836
A
A
5L
5254493937
53
A
7L
A
A
6L
55
A
9L
A
8L
56
57
A
11L
A
10L
58
59
V
CC
A
12L
60
61
N/C
A
13L
62
63
SEM
L
CE
L
64
65
OE
L
R/
W
L
676866
I/O
0L
N/C
13579
I/O
1L
I/O
I/O
2L
246810121416
I/O
I/O
3L
(1,2)
INT
A
1R
R
M/
4L
A
2L
A
0L
BUSY
S
L
4745434134
GND
BUSY
R
A
2R
A
0R
INT
3L
A
1L
L
IDT7006
G68-1
68-PIN PGA
(3)
111315
V
1R
CC
I/O
I/O
I/O2RI/O3RI/O
4R
5R
GNDGND
4L
5L
I/O
6L
TOP VIEW
I/O
7L
I/O
V
CC
0R
A
3R
35
A
4R
33
32
A
7R
31
30
A
9R
29
28
A
11R
27
26
GND
25
24
N/C
23
22
SEM
R
21
20
R
OE
1819
I/O
7R
17
I/O
6R
A
A
A
CE
R/
A
5R
A
6R
A
8R
10R
12R
13R
W
N/C
R
R
INDEX
ABCDEFGH JKL
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left PortRight PortNames
CE
L
R/
W
LR/WRRead/Write Enable
OE
L
A
0L – A13LA0R – A13RAddress
I/O
0L – I/O7LI/O0R – I/O7RData Input/Output
SEM
L
INT
L
BUSY
L
CE
RChip Enable
OE
ROutput Enable
SEM
RSemaphore Enable
INT
RInterrupt Flag
BUSY
RBusy Flag
M/
S
V
CCPower
Master or Slave Select
GNDGround
2739 drw 04
2739 tbl 01
6.073
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAMMILITARY AND COMMERCIAL TEMPERATURE RANGES
1. There are eight semaphore flags written to via I/O
ABSOLUTE MAXIMUM RATINGS
SymbolRatingCommercialMilitaryUnit
V
TERM
T
AOperating0 to +70–55 to +125°C
T
BIASTemperature–55 to +125–65 to +135°C
STGStorage–55 to +125 –65 to +150°C
T
I
OUTDC Output5050mA
NOTES:2739 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
2. V
or 10ns maximum, and is limited to
+ 0.5V.
WW
R/
W
WW
u
(2)
Terminal Voltage –0.5 to +7.0–0.5 to +7.0V
OEOE
SEMSEM
OE
OEOE
SEM
SEMSEM
I/O
XLDATA
0-7 Mode
OUTRead Data in Semaphore Flag Data Out
INWrite I/O0 into Semaphore Flag
0 and read from I/O0 - I/O15. These eight semaphores are addressed by A0 - A2.
(1)
with Respect
to GND
Temperature
Under Bias
Temperature
Current
< 20mA for the period of VTERM < Vcc
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GradeTemperatureGNDV
Military–55°C to +125°C0V5.0V ± 10%
Commercial0°C to +70°C0V5.0V ± 10%
RECOMMENDED DC OPERATING
CONDITIONS
SymbolParameterMin.Typ.Max. Unit
CCSupply Voltage4.55.05.5V
V
GNDSupply Voltage000V
IHInput High Voltage2.2—6.0
V
V
ILInput Low Voltage–0.5
NOTES:2739 tbl 06
1. VIL≥ -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 0.5V.
2. V
CAPACITANCE
(TA = +25°C, f = 1.0MHz)TQFP PACKAGE
SymbolParameterConditions
INInput CapacitanceVIN = 3dV9pF
C
OUTOutputVOUT = 3dV10pF
C
NOTES:2739 tbl 07
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
(1)
Capacitance
Ambient
(1)
(1)
—0.8V
(2)
2739 tbl 03
CC
2739 tbl 05
(2)
V
Max.Unit
6.074
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAMMILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
1. "X" in part numbers indicates power rating (S or L).
2. V
CC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (typ.).
3. At f = f
4. f = 0 means no address or control lines change.
5. Port "A"may be either left or right port. Port "B" is the port opposite port "A".
MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
(3)
MAX
SEM
R =
SEM
L > VIHL95160951608515080140
CE
R > VCC - 0.2VL————0.2100.210
IN > VCC - 0.2V or
V
IN < 0.2V, f = 0
SEM
R =
SEM
CE
"B" > VCC - 0.2V
SEM
R =
SEM
IN > VCC - 0.2V or
V
V
IN < 0.2v
(3)
f = f
MAX
(4)
L > VCC-0.2V
(5)
L > VCC-0.2VL————8020075170
COM.
COM.
COM
Com'l. OnlyCom'l. Only
(2)
Typ.
S 170310170310160290155265
L 160260160260150240145220
S2060 206020601660
L1050 105010501050
L—— ——8521080180
S 1051901051909518090170
S 1.0151.0151.0151.015
L 0.250.250.250.25
.S100170 1001709015585145
L90140901408013075120
Max.
(1)
(VCC = 5.0V ± 10%)
(2)
Typ.
Max.Typ.
(2)
Max. Typ.
(2)
Max.
Unit
6.075
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAMMILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
TestMil Only
SymbolParameterConditionVersionTyp.
CCDynamic Operating
I
Current
(Both Ports Active)f = f
SB1Standby Current
I
(Both Ports — TTL
Level Inputs)f = f
I
SB2Standby Current
(One Port — TTLActive Port Outputs Open,L751607516070160
Level Inputs)f = f
I
SB3Full Standby CurrentBoth Ports CEL andMIL.S1.0301.0301.030mA
(Both Ports — All
CMOS Level Inputs)V
SEM
R =
SEM
L≥ VCC-0.2V
I
SB4Full Standby CurrentCE"A" < 0.2V andMIL.S801758017575175 mA
(One Port — All
CMOS Level Inputs)
NOTES:2739 tbl 10
1. "X" in part numbers indicates power rating (S or L).
CC = 5V, TA = +25°C, and are not production tested. ICC DC =120mA (typ).
2. V
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B"is the opposite from port "A".
CE
= VIL, Outputs OpenMIL.S150300150300140300mA
SEM
= V
IHL140250140250130250
(3)
MAX
COM’L.S150250150250——
L140210140210——
CE
L = CER = VIHMIL.S138013801080mA
SEM
R =
SEM
L = VIHL10 65 10 65 8 65
(3)
MAX
COM’L.S13601360——
L10 50 10 50 — —
(5)
(5)
MIL.S851908519080190mA
COM’L.S8515585155——
L0.250.25——
CE
"A"=VIL and CEL"B"=VIH
(3)
MAX
SEM
R =
SEM
L = VIHL7513075130——
CE
R > VCC - 0.2VL0.2100.2100.210
IN > VCC - 0.2V orCOM’L.S1.0151.015——
V
IN < 0.2V, f = 0
CE
"B" > VCC - 0.2V
SEM
R =
SEM
IN > VCC - 0.2V orCOM’L.S8013580135——
V
V
IN < 0.2V
Active Port Outputs Open,L7011070110——
(3)
f = f
MAX
(4)
L≥ VCC - 0.2VL701507015065150
(1)
(Cont'd.)(VCC = 5.0V ± 10%)
7006X357006X557006X70
(2)
Max.Typ.
(2)
Max. Typ.
(2)
Max. Unit
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLC = 0.2V, VHC = VCC - 0.2V)
SymbolParameterTest ConditionMin.Typ.
DRVCC for Data RetentionVCC = 2V2.0——V
V
CCDRData Retention Current
I
(3)
CDR
t
(3)
R
t
NOTES:2739 tbl 11
1. TA = +25°C, VCC = 2V, and are not production tested.
2. t
RC = Read Cycle Time
3. This parameter is guaranteed by characterization, but are not production tested.
4. At Vcc = 2V input leakages are undefined
Chip Deselect to Data Retention Time
Operation Recovery TimetRC
(4)
(1)
Max.Unit
CE
≥ VHCMIL.—1004000µA
IN≥ VHC or ≤ VLCCOM’L.—1001500
V
SEM
≥ VHC0——ns
(2)
——ns
DATA RETENTION WAVEFORM
DATA RETENTION MODE
≥
V
V
CC
CE
4.5V
t
CDR
V
IH
DR
2V
V
DR
6.076
4.5V
t
R
V
IH
2739 drw 05
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