IDT IDT54FCT377T, IDT74FCT377T User Manual

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FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE

Integrated Device Technology, Inc.

FEATURES:

• Std., A, C and D speed grades

• Low input and output leakage ≤1µA (max.)

• CMOS power levels

• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– V

OL = 0.3V (typ.)

• High drive outputs (-15mA IOH, 48mA IOL)

• Power off disable outputs permit “live insertion”

• Meets or exceeds JEDEC standard 18 specifications

• Product available in Radiation Tolerant and Radiation

Enhanced versions

• Military product compliant to MIL-STD-883, Class B

and DESC listed (dual marked)

• Available in DIP, SOIC, QSOP, CERPACK and LCC

packages

IDT54/74FCT377T/AT/CT/DT

DESCRIPTION:

The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip­flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW. The register is fully

edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop’s O output. The CE input must be
stable only one set-up time prior to the LOW-to-HIGH transi­tion for predictable operation.

FUNCTIONAL BLOCK DIAGRAM

D0

CE

DCPQ

CP

D1

DCPQ

0

O

1

O

D2

DCPQ

D3

DCPQ

2

O

D4

DCPQ

3

O

D5

DCPQ

4

O

D6

DCPQ

5

O

D7

DCPQ

6

O

2630 drw 01

7

O

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES APRIL 1995

1995 Integrated Device Technology, Inc. 6.14 DSC-4200/3

1

IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

O0
D0
D1
O1
O2
D2
D3
O3

1
2
3
4

5
6
7
8
9

10

P20-1

D20-1
SO20-2
SO20-8

E20-1

CE

GND

DIP/SOIC/QSOP/CERPACK

TOP VIEW

20

Vcc

19

O7

18

D

7

17
16
15

&

14
13
12
11

6

D
O6
O5
D5
D4

4

O
CP

2630 drw 02

PIN DESCRIPTION

Pin Names Description

0 – D7 Data Inputs

D

CE

0 – O7 Data Outputs

O
CP Clock Pulse Input

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Military Unit

(2)

VTERM

VTERM

TA Operating

TBIAS Temperature

TSTG Storage

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not
extended periods may affect reliability. No terminal voltage may exceed
V

2. Input and V

3. Outputs and I/O terminals only.

Terminal Voltage
with Respect to
GND

(3)

Terminal Voltage
with Respect to
GND

Temperature

Under Bias

Temperature

Current

implied. Exposure to absolute maximum rating conditions for

CC by +0.5V unless otherwise noted.

Clock Enable (Active LOW)

CC terminals only.

2630 tbl 01

(1)

–0.5 to +7.0 –0.5 to +7.0 V

–0.5 to

CC +0.5

V

–0.5 to

VCC +0.5

V

0 to +70 –55 to +125 °C

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +150 °C

–60 to +120 –60 to +120 mA

2630 lnk 03

INDEX

D

1

O

1

O

2

D

2

D

3

D

32

4
5
6
7
8

10 11 12 13

9

3

O

0

O

L20-2

GND

1

CE

20 19

CP

Vcc

4

O

7

O

18
17
16
15
14

4

D

2630 drw 03

D

7

D

6

O

6

O

5

D

5

0

LCC

TOP VIEW

FUNCTION TABLE

(1)

Inputs Outputs

Operating Mode CP

CE

CE

DO

Load “1” ↑ lh H
Load “0” ↑ ll L
Hold ↑ h X No Change

H H X No Change

NOTE: 2630 tbl 02

1. H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH

Clock Transition
L = LOW Voltage Level
l = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock

Transition
X = Don't Care
↑ = LOW-to-HIGH Clock Transition

CAPACITANCE

Symbol Parameter

CIN Input

(TA = +25°C, f = 1.0MHz)

(1)

Conditions Typ. Max. Unit

VIN = 0V 6 10 pF

Capacitance

COUT Output

VOUT = 0V 8 12 pF

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

2630 lnk 04

6.14 2

IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

V

IH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
IL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

V

(4)

(4)

(4)

VCC = Max. VI = 2.7V — — ±1 µA
VCC = Max. VI = 0.5V — — ±1 µA
VCC = Max., VI = VCC (Max.) — — ±1 µA

(3)

, VO = GND –60 –120 –225 mA

IN = VIH or VIL IOH = –8mA COM’L.

V

IN = VIH or VIL IOL = 48mA COM’L.

V

IN = GND or VCC

A = -55°C.

IH Input HIGH Current

I

IL Input LOW Current

I

I Input HIGH Current

I

IK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V

V

OS Short Circuit Current VCC = Max.

I

OH Output HIGH Voltage VCC = Min. IOH = –6mA MIL. 2.4 3.3 — V

V

OL Output LOW Voltage VCC = Min. IOL = 32mA MIL. — 0.3 0.5 V

V

OFF Input/Output Power Off VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA

I

Leakage

(5)

VH Input Hysteresis — — 200 — mV

CC Quiescent Power VCC = Max. — 0.01 1 mA

I

Supply Current V

NOTES: 2630 tbl 05

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. The test limit for this parameter is ±5µA at T

5. This parameter is guaranted but not tested.

CC = 5.0V, +25°C ambient.

(1)

OH = –12mA MIL. 2.0 3.0 — V

I

OH = –15mA COM’L.

I

Min. Typ.

(2)

Max. Unit

6.14 3

IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

CC Quiescent Power Supply VCC = Max. — 0.5 2.0 mA

∆I

Current TTL Inputs HIGH V

ICCD Dynamic Power Supply VCC = Max., Outputs Open VIN = VCC — 0.15 0.25 mA/

Current

(4)

IN = 3.4V

CE

(3)

= GND VIN = GND MHz

(1)

Min. Typ.

One Input Toggling
50% Duty Cycle

I

C Total Power Supply VCC = Max., Outputs Open VIN = VCC — 1.5 3.5 mA

Current

(6)

fCP = 10MHz VIN = GND

CE

= GND V
One Bit Toggling V
f

i = 5MHz

IN = 3.4V — 2.0 5.5
IN = GND

50% Duty Cycle
V

CC = Max., Outputs Open VIN = VCC — 3.8 7.3

fCP = 10MHz, 50% Duty Cycle VIN = GND

CE

= GND V

IN = 3.4V — 6.0 16.3

Eight Bits Toggling VIN = GND
f

i = 2.5MHz

50% Duty Cycle

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)

CC = Quiescent Current

I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I

H = Duty Cycle for TTL Inputs High

D

T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

i = Input Frequency

f

i = Number of Inputs at fi

N
All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V). All other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

(5)

(5)

2639 tbl 05

6.14 4

IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

IDT54/74FCT377T FCT54/74FCT377AT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Condition

tPLH

Propagation Delay
CP to On

tPHL

CL = 50pF

R

(1)

L = 500Ω

tSU Set-Up Time HIGH or LOW

Dn to CP

tH Hold Time HIGH or LOW

Dn to CP

tSU Set-Up Time HIGH or LOW

CE

to CP

tH Hold Time HIGH or LOW

CE

to CP

tW Clock Pulse Width,

HIGH or LOW

Symbol Parameter Condition

tPLH

Propagation Delay
CP to On

tPHL

CL = 50pF

R

(1)

L = 500Ω

tSU Set-Up Time HIGH or LOW

Dn to CP

tH Hold Time HIGH or LOW

Dn to CP

tSU Set-Up Time HIGH or LOW

CE

to CP

tH Hold Time HIGH or LOW

CE

to CP

tW Clock Pulse Width,

HIGH or LOW

NOTES: 2630 tbl 07

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 ns

2.5 — 3.0 — 2.0 — 2.0 — ns

2.0 — 2.5 — 1.5 — 1.5 — ns

4.0 — 4.0 — 3.5 — 3.5 — ns

1.5 — 1.5 — 1.5 — 1.5 — ns

7.0 — 7.0 — 6.0 — 7.0 — ns

2630 tbl 06

IDT54/74FCT377CT FCT54/74FCT377DT

Com'l. Mil. Com'l. Mil.

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

2.0 5.2 2.0 5.5 2.0 4.4 — — ns

2.0 — 2.0 — 2.0 — — — ns

1.5 — 1.5 — 1.0 — — — ns

3.5 — 3.5 — 3.0 — — — ns

1.5 — 1.5 — 0.0 — — — ns

6.0 — 7.0 — 3.0 — — — ns

6.14 5

IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

V

CC

V

OUT

50pF

C L

Pulse

Generator

V

IN

D.U.T.

T

R

7.0V

500Ω

500Ω

2630 drw 04

SWITCH POSITION

Test

Open Drain
Disable Low

Enable Low

All Other Tests

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C
R

T = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

tSU

tSU

tH

tREM

tH

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

2630 drw 05

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

Switch

Closed

Open

2630 lnk 08

1.5V

tW

1.5V

2630 drw 06

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

tPLH

tPHL

tPLH tPHL

3V

1.5V
0V

OH

V

1.5V

VOL

3V

1.5V
0V

2630 drw 07

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

t

PLZtPZL

OUTPUT

NORMALLY

LOW

SWITCH
CLOSED

3.5V

1.5V

tPZH tPHZ

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

SWITCH
OPEN

1.5V
0V

F ≤ 2.5ns; tR ≤ 2.5ns

0.3V

0.3V

1.5V
0V

3.5V

VOL

VOH

0V

2630 drw 08

6.14 6

IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

Temperature

Range

XX

FCT

X

Family

XXXX

Device Type

X

Package

X

Process

Blank
B

P
D
SO
L
E
Q

377T

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Quarter-size Small Outline Package

Octal D Flip-Flop w/Clock Enable
377AT
377CT
377DT

Blank High Drive

°

54
74

C to +125°C

–55

0

°

C to +70°C

2630 drw 09

6.14 7