IDT IDT29FCT52AT, IDT29FCT52BT, IDT29FCT52CT, IDT29FCT52DT, IDT29FCT2052AT User Manual

查询5429FCT2052ATD供应商

FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS

Integrated Device Technology, Inc.

FEATURES:

• Common features:

– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility

– VOH = 3.3V (typ.)
– V

OL = 0.3V (typ.)

– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation

Enhanced versions

– Military product compliant to MIL-STD-883, Class B

and DESC listed (dual marked)

– Available in DIP, SOIC, SSOP, QSOP, CERPACK

and LCC packages

• Features for 29FCT52/29FCT53T:

– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”

• Features for 29FCT2052T:

– A, B and C speed grades
– Resistor outputs (-15mA IOH, 12mA IOL Com.)

(-12mA IOH, 12mA IOL Mil.)

– Reduced system switching noise

FUNCTIONAL BLOCK DIAGRAM

CPA
CEA

A

0
1

A
A

2

A

3

A

4

A

5

A

6

A

7

(1)

IDT29FCT52AT/BT/CT/DT

IDT29FCT2052AT/BT/CT

IDT29FCT53AT/BT/CT

DESCRIPTION:

The IDT29FCT52AT/BT/CT/DT and IDT29FCT53AT/BT/
CT are 8-bit registered transceivers built using an advanced
dual metal CMOS technology. Two 8-bit back-to-back regis­ters store data flowing in both directions between two bidirec­tional buses. Separate clock, clock enable and 3-state output
enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64mA.

The IDT29FCT52AT/BT/CT/DT and IDT29FCT2052AT/BT/
CT are non-inverting options of the IDT29FCT53AT/BT/CT.

The IDT29FCT2052AT/BT/CT has balanced drive outputs
with current limiting resistors. This offers low ground bounce,
minimal undershoot and controlled output fall times-reducing
the need for external series terminating resistors. The
IDT29FCT2052T part is a plug-in replacement for
IDT29FCT52T part.

OEB

D
D
D
D
D
D
D
D

CE CP

0
1
2
3
4
5
6
7

A

Reg.

Q

0

Q

1

Q

2

Q

3

Q

4

Q

5

Q

6

Q

7

B

0

B

1

B

2

B

3

B

4

B

5

B

6

B

7

D

0

D

1

D

2

D

3

B

D

4

D

5

D

6

D

7

CPB
CEB

2629 drw 01

NOTE:

1. IDT29FCT52T/IDT29FCT2052T function is shown. IDT29FCT53T is
the inverting option.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

OEA

Q
Q
Q
Q
Q
Q
Q
Q

0
1
2
3
4
5
6
7

CE CP

Reg.

MILITARY AND COMMERCIAL TEMPERATURE RANGES JUNE 1995

1995 Integrated Device Technology, Inc. 6.1 DSC-4224/5

1

IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

B
B
B5
B4
B
B
B1

B
OEB
CPA
CEA CPB

GND

1

7

2

6

3

P24-1

4

D24-1

5

3
2

0

6
7
8
9
10
11
12

SO24-2
SO24-7*
SO24-8*

E24-1

24

Vcc

23

A

22
21
20
19
18
17

&

16
15
14
13

7

A

6

A5
A4
A

3

A

2

A1
A0

OEA

CEB

2629 drw 02

5

6

INDEX

B
B
B2

NC NC

B1
B

5

4

6

3

7
8
9
10

0

11

12 13 14 15 16 17 18

7

B

432128 27 26

NC

B

B

L28-1

NC

CEA

CPA

GND

Vcc

CEB

6

A

A 7

CPB

OEA

25
24
23
22
21
20
19

A

5

A

4

A3
A

2

A

1

A0OEB

2629 drw 03

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

* For 29FCT52/29FCT2052AT/BT/CT only

PIN DESCRIPTION

Name I/O Description

0-7 I/O Eight bidirectional lines carrying the A Register inputs or B Register outputs.

A

0-7 I/O Eight bidirectional lines carrying the B Register inputs or A Register outputs.

B
CPA I Clock for the A Register. When

the CPA signal.

CEA

I Clock Enable for the A Register. When

of the CPA signal. When

OEB

I Output Enable for the A Register. When

OEB

is HIGH, the B

0-7 outputs are in the high-impedance state.

CPB I Clock for the B Register. When

the CPB signal.

CEB

I Clock Enable for the B Register. When

of the CPB signal. When

OEA

I Output Enable for the B Register. When

OEA

is HIGH, the A

0-7 outputs are in the high-impedance state.

CEA

is LOW, data is entered into the A Register on the LOW-to-HIGH transition of

CEA

is LOW, data is entered into the A Register on the LOW-to-HIGH transition

CEA

is HIGH, the A Register holds its contents, regardless of CPA signal transitions.

OEB

is LOW, the A Register outputs are enabled onto the B

CEB

is LOW, data is entered into the B Register on the LOW-to-HIGH transition of

CEB

is LOW, data is entered into the B Register on the LOW-to-HIGH transition

CEB

is HIGH, the B Register holds its contents, regardless of CPB signal transitions.

OEA

is LOW, the B Register outputs are enabled onto the A

LCC

TOP VIEW

0-7 lines. When

0-7 lines. When

2629 tbl 01

6.1 2

IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

REGISTER FUNCTION TABLE

(1)

(Applies to A or B Register)

Inputs Internal

DCP

X X H NC Hold Data

L ↑ L L Load Data

H ↑ LH

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition

Symbol Rating Commercial Military Unit

(2)

VTERM

Terminal Voltage
with Respect to
GND

(3)

VTERM

Terminal Voltage
with Respect to
GND

TA Operating

Temperature

TBIAS Temperature

Under Bias

TSTG Storage

Temperature

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi­tions above those indicated in the operational sections of this specifica­tion is not
extended periods may affect reliability. No terminal voltage may exceed
V

2. Input and V

3. Outputs and I/O terminals only.

implied. Exposure to absolute maximum rating conditions for

CC by +0.5V unless otherwise noted.

CC terminals only.

CE

CE

Q Function

2629 tbl 02

(1)

–0.5 to +7.0 –0.5 to +7.0 V

–0.5 to

CC +0.5

V

–0.5 to

VCC +0.5

0 to +70 –55 to +125 °C

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +150 °C

–60 to +120 –60 to +120 mA

2529 lnk 04

V

OUTPUT CONTROL

(1)

Internal Y-Outputs

OE

OE

Q 52/2052 53 Function

H X Z Z Disable Outputs

L L L H Enable Outputs
LHHL

NOTE: 2629 tbl 03

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance

CAPACITANCE (TA = +25°C, f = 1.0MHz)ABSOLUTE MAXIMUM RATINGS

Symbol Parameter

CIN Input

Capacitance

COUT Output

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 6 10 pF

VOUT = 0V 8 12 pF

2640 lnk 05

6.1 3

IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current
II L Input LOW Current

(4)

(4)

VI = 0.5V — — ±1

VCC = Max. VI = 2.7V — — ±1 µA

IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA

(4)

(4)

VO = 0.5V — — ±1

VCC = Max., VI = VCC (Max.) — — ±1 µA

IOZL (3-State Output pins)
II Input HIGH Current
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis — — 200 — mV
ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 mA

(2)

Max. Unit

2629 tbl 06

OUTPUT DRIVE CHARACTERISTICS FOR 29FCT52T/29FCT53T

Symbol Parameter Test Conditions

VOH Output HIGH Voltage VCC = Min.

IN = VIH or VIL

V

IOH = –6mA MIL.

OH = –8mA COM'L.

I
IOH = –12mA MIL.

OH = –15mA COM'L.

I

VOL Output LOW Voltage VCC = Min.

IN = VIH or VIL

V

IOS Short Circuit Current VCC = Max., VO = GND
IOFF Input/Output Power Off Leakage

(5)

VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA

IOL = 48mA MIL.

OL = 64mA COM'L.

I

(3)

(1)

Min. Typ.

2.4 3.3 — V

2.0 3.0 — V

— 0.3 0.55 V

–60 –120 –225 mA

(2)

Max. Unit

2629 tbl 07

OUTPUT DRIVE CHARACTERISTICS FOR 29FCT2052T

Symbol Parameter Test Conditions

I

ODL

I

ODH

V

OH

V

OL

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. The test limit for this parameter is ±5µA at T

5. This parameter is guaranteed but not tested.

Output LOW Current VCC = 5V, V
Output HIGH Current VCC = 5V, V
Output HIGH Voltage VCC = Min.

IN

= V

IH

V

or V

Output LOW Voltage VCC = Min.

IN

= V

IH

V

A = –55°C.

or V

IN

= V

IH or VIL, VOUT

IN

= V

IH

IL

IL

or V

IL,VOUT

(1)

(3)

= 1.5V

(3)

= 1.5V

IOH = –12mA MIL.

OH

= –15mA COM'L.

I

Min. Typ.

16 48 — mA

–16 –48 — mA

2.4 3.3 — V

IOL = 12mA — 0.3 0.50 V

(2)

Max. Unit

2629 tbl 08

6.1 4

IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

ICCD Dynamic Power Supply Current

(4)

VCC = Max.
V

IN = 3.4V

VCC = Max.

(3)

Outputs Open

OE

A or OEB = GND

One Input Toggling

(1)

IN = VCC

V
VIN = GND

Min. Typ.

— 0.5 2.0 mA

FCTxxxT — 0.15 0.25 mA/

FCT2xxxT — 0.06 0.12

50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open

fCP = 10MHz

VIN = VCC
VIN = GND

FCTxxxT — 1.5 3.5 mA

FCT2xxxT — 0.6 2.2

50% Duty Cycle

OE

A or OEB = GND VIN = 3.4V FCTxxxT — 2.0 5.5

One Bit Toggling

VIN = GND FCT2xxxT 1.1 4.2
at fi = 5MHz
50% Duty Cycle

VCC = Max.
Outputs Open
fCP = 10MHz

VIN = VCC

VIN = GND

FCTxxxT — 3.8 7.3

FCT2xxxT — 1.5 4.0

50% Duty Cycle

OE

A or OEB = GND VIN = 3.4V FCTxxxT — 6.0 16.3

Eight Bits Toggling

VIN = GND FCT2xxxT — 3.8 13.0
at fi = 2.5MHz
50% Duty Cycle

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)

CC = Quiescent Current

I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I
D

H = Duty Cycle for TTL Inputs High
T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f
f

i = Input Frequency

i = Number of Inputs at fi

N
All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V). All other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)

(5)

(5)

(5)

2629 tbl 09

6.1 5

IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol Parameter Condition

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

SU

Propagation Delay
CPA, CPB to An, Bn

Output Enable Time

OEA

or

OEB

to An, Bn

Output Disable Time

OEA

or

OEB

to An, Bn

Set-up Time, HIGH or LOW

CL = 50pF

R

L

= 500

An, Bn to CPA, CPB

t

H

Hold Time, HIGH or LOW
An, Bn to CPA, CPB

t

SU

t

H

t

W

Set-up Time, HIGH or LOW

CEA, CEB

to CPA, CPB

Hold Time, HIGH or LOW

CEA, CEB

to CPA, CPB

Clock Pulse Width HIGH or

(3)

LOW

29FCT52AT/53AT

29FCT2052AT

Com'l. Mil. Com'l. Mil.

(1)

Ω

Min

(2)

.

Max. Min

(2)

.

Max. Min

2.0 10.0 2.0 11.0 2.0 7.5 2.0 8.0 ns

1.5 10.5 1.5 13.0 1.5 8.0 1.5 8.5 ns

1.5 10.0 1.5 10.0 1.5 7.5 1.5 8.0 ns

2.5 — 2.5 — 2.5 — 2.5 — ns

2.0 — 2.0 — 1.5 — 1.5 — ns

3.0 — 3.0 — 3.0 — 3.0 — ns

2.0 — 2.0 — 2.0 — 2.0 — ns

3.0 — 3.0 — 3.0 — 3.0 — ns

29FCT52BT/53BT

29FCT2052BT

(2)

.

Max. Min

(2)

.

Max. Unit

2629 tbl 10

29FCT52CT/53CT

29FCT2052CT 29FCT52DT

Com'l. Mil. Com'l. Mil.

= 500

(1)

Ω

Symbol Parameter Condition

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

SU

Propagation Delay
CPA, CPB to An, Bn

Output Enable Time

OEA

or

OEB

to An, Bn

Output Disable Time

OEA

or

OEB

to An, Bn

Set-up Time, HIGH or LOW

CL = 50pF

R

L

An, Bn to CPA, CPB

t

H

Hold Time, HIGH or LOW
An, Bn to CPA, CPB

t

SU

t

H

t

W

NOTES: 2629 tbl 11

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. This parameter is guaranteed but not tested.

Set-up Time, HIGH or LOW

CEA, CEB

to CPA, CPB

Hold Time, HIGH or LOW

CEA, CEB

to CPA, CPB

Clock Pulse Width HIGH or

(3)

LOW

Min

(2)

.

Max. Min

(2)

.

Max. Min

(2)

.

Max. Min

(2)

.

Max. Unit

2.0 6.3 2.0 7.3 2.0 4.5 — — ns

1.5 7.0 1.5 8.0 1.5 5.6 — — ns

1.5 6.5 1.5 7.5 1.5 4.3 — — ns

2.5 — 2.5 — 1.5 — — — ns

1.5 — 1.5 — 1.0 — — — ns

3.0 — 3.0 — 2.0 — — — ns

2.0 — 2.0 — 1.0 — — — ns

3.0 — 3.0 — 3.0 — — — ns

6.1 6

IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION

Test Switch

V

CC

7.0V

Open Drain
Disable Low

Enable Low

All Other Tests

Generator.

Pulse

Generator

500Ω

V

V

IN

D.U.T.

T

R

OUT

50pF

C L

500Ω

2629 drw 03

DEFINITIONS:

C

L= Load capacitance: includes jig and probe capacitance.
T = Termination resistance: should be equal to ZOUT of the Pulse

R

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

tSU

tSU

tH

tREM

tH

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V

0V

3V

1.5V
0V

2629 drw 04

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

Closed

Open

2629 lnk 12

1.5V

tW

1.5V

2629 drw 05

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

tPLH

OUTPUT

tPLH tPHL

OPPOSITE PHASE

INPUT TRANSITION

tPHL

3V

1.5V
0V

V

OH

1.5V

VOL

3V

1.5V
0V

2629 drw 06

ENABLE DISABLE

3V

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

SWITCH
CLOSED

3.5V

1.5V

t

PLZtPZL

0.3V

1.5V
0V

3.5V

VOL

tPZH tPHZ

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

SWITCH
OPEN

1.5V
0V

F ≤ 2.5ns; tR ≤ 2.5ns

0.3V

VOH

0V

2629 drw 07

6.1 7

IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

XX

Temp. Range

29FCT XX

X

Family

XX

Device Type

Package

X

Process

Blank

Blank
B

B

P
D
E
L
SO
PY
Q

52AT
53AT
52BT
53BT
52CT
53CT
52DT

Blank
20

54
74

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package

Non-inverting Octal Registered Transceiver
Inverting Octal Registered Transceiver

High Drive
Balanced Drive

°

C to +125°C

–55

°

C to +70°C

0

2629 drw 08

6.1 8