IDT IDT23S08T User Manual

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IDT23S08T

2.5V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL TEMPERATURE RANGE

2.5V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE

FEA TURES:

• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency

• Distributes one clock input to two banks of four outputs

• Separate output enable for each output bank

• External feedback (FBK) pin is used to synchronize the outputs
to the clock input

• Output Skew <200 ps

• Low jitter <200 ps cycle-to-cycle

• 1/2x, 1x, 2x, 4x output options (see table):

– IDT23S08T-1 1x
– IDT23S08T-2 1x, 2x
– IDT23S08T-3 2x, 4x
– IDT23S08T-4 2x
– IDT23S08T-5 1/2x

• No external RC network required

• Operates at 2.5V VDD

• Spread spectrum compatible

• Available in SOIC package

IDT23S08T

ADVANCE

INFORMATION

DESCRIPTION:

The IDT23S08T is a high-speed phase-lock loop (PLL) clock multiplier. It
is designed to address high-speed clock distribution and multiplication applica­tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.

The IDT23S08T has two banks of four outputs each that are controlled via
two select addresses. By proper selection of input addresses, both banks can
be put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08T enters power down. In this mode, the device will
draw less than 12µA, and the outputs are tri-stated.

The IDT23S08T is available in six unique configurations for both pre­scaling and multiplication of the Input REF Clock. (See available options
table.)

The PLL is closed externally to provide more flexibility by allowing the user

to control the delay between the input clock and the outputs.

The IDT23S08T is characterized for Commercial operation.

FUNCTIONAL BLOCK DIAGRAM

(-3, -4)

16

FBK

REF

S2

S1

2

1

2

(-5)

8

9

PLL

Control

Logic

(-2, -3)

2

CLKA1

3

CLKA2

14

CLKA3

15

CLKA4

2

6

CLKB1

7

CLKB2

10

CLKB3

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

2003 Integrated Device Technology, Inc. DSC - 6510/4c

11

CLKB4

NOVEMBER 2003

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IDT23S08T

2.5V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

REF

CLKA1
CLKA2

VDD

GND
CLKB1
CLKB2

S2

2
3
4

5
6

7
8

SOIC

TOP VIEW

PIN DESCRIPTION

Pin Number Functional Description

(1)

REF

(2)

CLKA1

(2)

CLKA2

VDD 4 2.5V Supply

GND 5 Ground

(2)

CLKB1

(2)

CLKB2

(3)

S2

(3)

S1

(2)

CLKB3

(2)

CLKB4

GND 12 Ground

VDD 13 2.5V Supply

(2)

CLKA3

(2)

CLKA4

FBK 16 PLL Feedback Input

1 Input Reference Clock, 3.3V Tolerant Input
2 Clock Output for Bank A
3 Clock Output for Bank A

6 Clock Output for Bank B
7 Clock Output for Bank B
8 Select Input, Bit 2

9 Select Input, Bit 1
1 0 Clock Output for Bank B
1 1 Clock Output for Bank B

1 4 Clock Output for Bank A
1 5 Clock Output for Bank A

161
15
14
13
12

11
10

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Max. Unit

VDD Supply Voltage Range –0.5 to +4.6 V

(2)

FBK

VI
V

I Input Voltage Range –0.5 to V

CLKA4

CLKA3

DD

V

GND
CLKB4

CLKB3

9

S1

IIK (VI < 0) Input Clamp Current –5 0 mA
IO Continuous Output Current ±50 mA
(VO = 0 to VDD)
VDD or GND Continuous Current ±100 mA
TA = 55°C Maximum Power Dissipation 0.7 W
(in still air)
TSTG Storage Temperature Range –65 to +150 °C
Operating Commercial Temperature 0 to +70 °C
Temperature Range

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

2. The input and output negative-voltage ratings may be exceeded if the input and output

3. The maximum package power dissipation is calculated using a junction temperature

(3)

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

clamp-current ratings are observed.

of 150°C and a board trace length of 750 mils.

Input Voltage Range (REF) –0.5 to +5.5 V

(except REF) VDD+0.5

(1)

APPLICATIONS:

• SDRAM

• Telecom

• Datacom

• PC Motherboards/Workstations

• Critical Path Delay Designs

NOTES:

1. Weak pull down.

2. Weak pull down on all outputs.

3. Weak pull ups on these inputs.

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IDT23S08T

2.5V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL TEMPERATURE RANGE

FUNCTION TABLE

(1)

SELECT INPUT DECODING

S2 S1 CLK A CLK B Output Source PLL Shut Down

L L Tri-State Tri-State PLL Y

L H Driven Tri-State PLL N
H L Driven Driven REF Y
H H Driven Driven PLL N

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level

AVAILABLE OPTIONS FOR IDT23S08T

Device Feedback From Bank A Frequency Bank B Frequency

IDT23S08T-1 Bank A or Bank B Reference Reference
IDT23S08T-2
IDT23S08T-2
IDT23S08T-3
IDT23S08T-3
IDT23S08T-4
IDT23S08T-5

NOTES:

1. Contact factory for availability.

2. Output phase is indeterminant (0° or 180° from input clock).

(1)

(1)

(1)

(1)

(1)

(1)

Bank A Reference Reference/2
Bank B 2 x Reference Reference
Bank A 2 x Reference Reference or Reference

Bank B 4 x Reference 2 x Reference
Bank A or Bank B 2 x Reference 2 x Reference
Bank A or Bank B Reference/2 Reference/2

(2)

SPREAD SPECTRUM COMPATIBLE

Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.

ZERO DELA Y AND SKEW CONTROL

To close the feedback loop of the IDT23S08T, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.

For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.

OPERATING CONDITIONS

Symbol Parameter Test Conditions Min. Max. Unit

VDD Supply Voltage 2.3 2.7 V

TA Operating Temperature (Ambient Temperature) 0 7 0 °C

CL Load Capacitance from 10MHz to 133MHz — 1 5 pF

CIN Input Capacitance

(1)

—7pF

NOTE:

1. Applies to both REF and FBK.

3

IDT23S08T

2.5V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Conditions Min. Typ.

VIL Input LOW Voltage Level — — 0.7 V
VIH Input HIGH Voltage Level 1.7 — — V

IIL Input LOW Current VIN = 0V — — 50 µA

IIH Input HIGH Current VIN = VDD — — 100 µA
VOL Output LOW Voltage IOL = 8mA — — 0.3 V
VOH Output HIGH Voltage IOH = -8mA 2 — — V

IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — — 12 µA

100MHz CLKA — — 45

IDD Supply Current Unloaded Outputs 66MHz CLKA — — 32 mA

Select Inputs at VDD or GND 33MHz CLKA — — 1 8

(1)

Max. Unit

SWITCHING CHARACTERISTICS

Symbol Parameter Conditions Min. Typ. Max. Unit

t1 Output Frequency 15pF Load 10 — 133.3 MHz

Duty Cycle = t2 ÷ t1 Measured at VDD/2, FOUT = 66.66MHz, 15pF Load 40 50 60 %
t3 Rise Time Measured between 0.7V and 1.7V, 15pF Load — — 2.5 ns
t4 Fall Time Measured between 0.7V and 1.7V, 15pF Load — — 2.5 ns
t5 Output to Output Skew on same Bank All outputs equally loaded — — 200 ps

(-1, -2, -3, -4, -5)

Output Bank A to Output Bank B (-1, -4, -5) All outputs equally loaded — — 200 ps

Output Bank A to Output Bank B Skew (-2, -3) All outputs equally loaded — — 400 ps
t6 Delay, REF Rising Edge to FBK Rising Edge Measured at VDD/2 — 0 ±350 ps
t7 Device to Device Skew Measured at VDD/2 on the FBK pins of devices — 0 700 ps

tJ Cycle to Cycle Jitter (-1, -4, -5) Measured at 66.67 MHz, loaded outputs, 15pF Load — — 20 0 ps

Measured at 133.3 MHz, loaded outputs, 15pF Load — — 20 0

tJ Cycle to Cycle Jitter (-2, -3) Measured at 66.67 MHz, loaded outputs, 15pF Load — — 400 ps

tLOCK PLL Lock Time Stable Power Supply, valid clocks presented — — 1 ms

on REF and FBK pins

4

IDT23S08T

2.5V ZERO DELAY CLOCK MULTIPLIER

SWITCHING WAVEFORMS

COMMERCIAL TEMPERATURE RANGE

t1

t2

Output

Output

VDD/2

t5

Output

V

VDD/2

0.7V

t3

DD/2

VDD/2 VDD/2

Duty Cycle Timing

1.7V

1.7V

All Outputs Rise/Fall Time

0.7V
t4

Input

FBK

V

t6

DD/2

2.5V
0V

DD/2

V

FBK, Device 1

FBK, Device 2

Output to Output Skew

DD/2

V

t7

Device to Device Skew

V

DD/2

Input to Output Propagation Delay

TEST CIRCUIT

0.1µF

0.1µF
GND GND

Test Circuit for all Parameters

VDD

VDD

OUTPUT S

CLK

OUT

CLOAD

5

IDT23S08T

2.5V ZERO DELAY CLOCK MULTIPLIER

ORDERING INFORMATION

XXXXX XX X

IDT

Device Type

Package Process

COMMERCIAL TEMPERATURE RANGE

Blank

DC

Commercial (0oC to +70oC)

Small Outline

23S08T-1
23S08T-2
23S08T-3
23S08T-4

2.5V Ze ro Delay Clock Buffer, Spr e ad
Spectrum Compatible

23S08T-5

Ordering Code Package Type Operating Range

IDT23S08T-1DC 16-Pin SOIC Commercial
IDT23S08T-2DC
IDT23S08T-3DC
IDT23S08T-4DC
IDT23S08T-5DC

NOTE:

1. Contact factory for availability.

(1)

(1)

(1)

(1)

16-Pin SOIC Commercial
16-Pin SOIC Commercial
16-Pin SOIC Commercial
16-Pin SOIC Commercial

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 [e-mail]
Santa Clara, CA 95054 fax: [phone] [phone]

www.idt.com

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