IDT IDT2308 Technical data

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IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

3.3V ZERO DELAY
CLOCK MULTIPLIER

FEA TURES:

• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency

• Distributes one clock input to two banks of four outputs

• Separate output enable for each output bank

• External feedback (FBK) pin is used to synchronize the outputs
to the clock input

• Output Skew <200 ps

• Low jitter <200 ps cycle-to-cycle

• 1x, 2x, 4x output options (see table):

– IDT2308-1 1x
– IDT2308-2 1x, 2x
– IDT2308-3 2x, 4x
– IDT2308-4 2x
– IDT2308-1H, -2H, and -5H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Available in SOIC and TSSOP packages

IDT2308

DESCRIPTION:

The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica­tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.

The IDT2308 has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT2308 enters power down, and the outputs are tri-stated. In
this mode, the device will draw less than 25µA.

The IDT2308 is available in six unique configurations for both pre­scaling and multiplication of the Input REF Clock. (See available options
table.)

The PLL is closed externally to provide more flexibility by allowing the user

to control the delay between the input clock and the outputs.

The IDT2308 is characterized for both Industrial and Commercial operation.
NOTE: For new designs, refer to AN-233.

FUNCTIONAL BLOCK DIAGRAM

(-3, -4)

16

FBK

REF

S2

S1

2

1

2

(-5)

8

9

PLL

Control

Logic

(-2, -3)

2

CLKA1

3

CLKA2

14

CLKA3

15

CLKA4

2

6

CLKB1

7

CLKB2

10

CLKB3

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2003 Integrated Device Technology, Inc. DSC 5173/9c

1

11

CLKB4

APRIL 2003

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

PIN CONFIGURATION

REF

CLKA1
CLKA2

VDD

GND
CLKB1
CLKB2

S2

2
3
4

5
6

7
8

SOIC/ TSSOP

TOP VIEW

PIN DESCRIPTION

Pin Number Functional Description

(1)

REF

(2)

CLKA1

(2)

CLKA2

VDD 4 3.3V Supply

GND 5 Ground

(2)

CLKB1

(2)

CLKB2

(3)

S2

(3)

S1

(2)

CLKB3

(2)

CLKB4

GND 12 Ground

VDD 13 3.3V Supply

(2)

CLKA3

(2)

CLKA4

FBK 16 PLL Feedback Input

1 Input Reference Clock, 5 Volt Tolerant Input
2 Clock Output for Bank A
3 Clock Output for Bank A

6 Clock Output for Bank B
7 Clock Output for Bank B
8 Select Input, Bit 2

9 Select Input, Bit 1
1 0 Clock Output for Bank B
1 1 Clock Output for Bank B

1 4 Clock Output for Bank A
1 5 Clock Output for Bank A

161
15
14
13
12

11
10

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Max. Unit

VDD Supply Voltage Range –0.5 to +4.6 V

(2)

FBK

VI
V

I Input Voltage Range –0.5 to V

CLKA4

CLKA3

DD

V

GND
CLKB4

CLKB3

9

S1

IIK (VI < 0) Input Clamp Current –5 0 mA
IOK Terminal Voltage with Respect ±50 mA
(VO < 0 or VO > VDD) to GND (inputs VIH 2.5, VIL 2.5)
I

O Continuous Output Current ±50 mA

(VO = 0 to VDD)
VDD or GND Continuous Current ±100 mA
TA = 55°C Maximum Power Dissipation 0.7 W
(in still air)
TSTG Storage Temperature Range –65 to +150 °C
Operating Commercial Temperature 0 to +70 °C
Temperature Range
Operating Industrial Temperature -40 to +85 °C
Temperature Range

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

2. The input and output negative-voltage ratings may be exceeded if the input and output

3. The maximum package power dissipation is calculated using a junction temperature

(3)

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

clamp-current ratings are observed.

of 150°C and a board trace length of 750 mils.

Input Voltage Range (REF) –0.5 to +5.5 V

(except REF) VDD+0.5

(1)

APPLICATIONS:

• SDRAM

• Telecom

• Datacom

• PC Motherboards/Workstations

• Critical Path Delay Designs

NOTES:

1. Weak pull down.

2. Weak pull down on all outputs.

3. Weak pull ups on these inputs.

2

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FUNCTION TABLE

S2 S1 CLK A CLK B Output Source PLL Shut Down

L L Tri-State Tri-State PLL Y

L H Driven Tri-State PLL N
H L Driven Driven REF Y
H H Driven Driven PLL N

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level

(1)

SELECT INPUT DECODING

AVAILABLE OPTIONS FOR IDT2308

Device Feedback From Bank A Frequency Bank B Frequency

IDT2308-1 Bank A or Bank B Reference Reference

IDT2308-1H Bank A or Bank B Reference Reference

IDT2308-2 Bank A Reference Reference/2

IDT2308-2 Bank B 2 x Reference Reference
IDT2308-2H Bank A Reference Reference/2
IDT2308-2H Bank B 2 x Reference Reference

IDT2308-3 Bank A 2 x Reference Reference or Reference

IDT2308-3 Bank B 4 x Reference 2 x Reference

IDT2308-4 Bank A or Bank B 2 x Reference 2 x Reference
IDT2308-5H Bank A or Bank B Reference/2 Reference/2

NOTE:

1. Output phase is indeterminant (0° or 180° from input clock).

(1)

3

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

ZERO DELA Y AND SKEW CONTROL

To close the feedback loop of the IDT2308, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will
be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.

For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay
adjustments are required, use the Output Load Difference Chart to calculate loading differences between the feedback output and remaining outputs.
Ensure the outputs are loaded equally, for zero output-output skew.

REF TO CLKA/CLKB DELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS

1500

1000

500

0

-30 -25 -20

-500

REF to CLKA/CLKB Delay (ps)

-1000

-1500

OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS ( pF)

-15

-10

-5

05

10 15 20 25

30

4

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

OPERATING CONDITIONS- COMMERCIAL

Symbol Parameter Test Conditions Min. Max. Unit

VDD Supply Voltage 3 3.6 V

TA Operating Temperature (Ambient Temperature) 0 7 0 °C
CL Load Capacitance below 100MHz — 3 0 pF

Load Capacitance from 100MHz to 133MHz — 1 5 pF

C

IN Input Capacitance

NOTE:

1. Applies to both REF and FBK.

(1)

—7pF

DC ELECTRICAL CHARACTERISTICS - COMMERCIAL

Symbol Parameter Conditions Min. Typ.

VIL Input LOW Voltage Level — — 0.8 V
VIH Input HIGH Voltage Level 2 — — V

IIL Input LOW Current VIN = 0V — — 50 µA

IIH Input HIGH Current VIN = VDD — — 100 µA

VOL Output LOW Voltage IOL = 8mA (-1, -2, -3, -4) — — 0.4 V

IOL = 12mA (-1H, -2H, -5H)

VOH Output HIGH Voltage IOH = -8mA (-1, -2, -3, -4) 2.4 — — V

IOH = -12mA (-1H, -2H, -5H)

IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — — 12 µA

100MHz CLKA (-1, -2, -3, -4) — — 45
100MHz CLKA (-1H, -2H, -5H) — — 70

IDD Supply Current Unloaded Outputs 66MHz CLKA (-1, -2, -3, -4) — — 32 mA

Select Inputs at VDD or GND 66MHz CLKA (-1H, -2H, -5H) — — 50

33MHz CLKA (-1, -2, -3, -4) — — 18
33MHz CLKA (-1H, -2H, -5H) — — 30

(1)

Max. Unit

5

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS - COMMERCIAL

Symbol Parameter Conditions Min. Typ. Max. Unit

t1 Output Frequency 30pF Load, all devices 1 0 — 100 MHz
t1 Output Frequency 20pF Load, -1H, -2H, -5H Devices
t1 Output Frequency 15pF Load, -1, -2, -3, -4 devices 1 0 — 133.3 MHz

Duty Cycle = t

2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 4 0 50 60 %

(-1, -2, -3, -4, -1H, -2H, -5H) 30pF Load
Duty Cycle = t

2 ÷ t1 Measured at 1.4V, FOUT = 50MHz 45 50 55 %

(-1, -2, -3, -4, -1H, -2H, -5H) 15pF Load
t3 Rise Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 30pF Load — — 2.2 ns
t3 Rise Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 15pF Load — — 1.5 ns
t3 Rise Time (-1H, -2H, -5H) Measured between 0.8V and 2V, 30pF Load — — 1.5 ns
t4 Fall Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 30pF Load — — 2. 2 ns
t4 Fall Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 15pF Load — — 1. 5 ns
t4 Fall Time (-1H, -5H) Measured between 0.8V and 2V, 30pF Load — — 1.25 ns
t5 Output to Output Skew on same Bank All outputs equally loaded — — 20 0 ps

(-1, -2, -3, -4)

Output to Output Skew (-1H, -2H, -5H) All outputs equally loaded — — 20 0 ps

Output Bank A to Output Bank B (-1, -4, -2H, -5H) All outputs equally loaded — — 20 0 ps

Output Bank A to Output Bank B Skew (-2, -3) All outputs equally loaded — — 40 0 ps
t6 Delay, REF Rising Edge to FBK Rising Edge Measured at VDD/2 — 0 ±250 ps

t7 Device to Device Skew Measured at VDD/2 on the FBK pins of devices — 0 70 0 ps
t8 Output Slew Rate Measured between 0.8V and 2V on -1H, -2H, -5H 1 — — V/ns

device using Test Circuit 2

tJ Cycle to Cycle Jitter Measured at 66.67 MHz, loaded outputs, 15pF Load — — 20 0

(-1, -1H, -4, -5H) Measured at 66.67 MHz, loaded outputs, 30pF Load — — 2 00 ps

Measured at 133.3 MHz, loaded outputs, 15pF Load — — 10 0

tJ Cycle to Cycle Jitter Measured at 66.67 MHz, loaded outputs, 30pF Load — — 40 0 ps

(-2, -2H, -3) Measured at 66.67 MHz, loaded outputs, 15pF Load — — 40 0

tLOCK PLL Lock Time Stable Power Supply, valid clocks presented — — 1 ms

on REF and FBK pins

NOTE:

1. IDT2308-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67MHz.

(1)

10 — 133.3 MHz

6

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

OPERATING CONDITIONS- INDUSTRIAL

Symbol Parameter Test Conditions Min. Max. Unit

VDD Supply Voltage 3 3.6 V

TA Operating Temperature (Ambient Temperature) -40 +85 °C
CL Load Capacitance below 100MHz — 3 0 pF

Load Capacitance from 100MHz to 133MHz — 1 5 pF

CIN Input Capacitance

NOTE:

1. Applies to both REF and FBK.

(1)

—7pF

DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL

Symbol Parameter Conditions Min. Typ.

VIL Input LOW Voltage Level — — 0 .8 V
VIH Input HIGH Voltage Level 2 — — V

IIL Input LOW Current VIN = 0V — — 50 µA

IIH Input HIGH Current VIN = VDD — — 100 µA

VOL Output LOW Voltage IOL = 8mA (-1, -2, -3, -4) — — 0 .4 V

IOL = 12mA (-1H, -2H, -5H)

VOH Output HIGH Voltage IOH = -8mA (-1, -2, -3, -4) 2.4 — — V

IOH = -12mA (-1H, -2H, -5H)

IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — — 25 µ A

100MHz CLKA (-1, -2, -3, -4) — — 45
100MHz CLKA (-1H, -2H, -5H) — — 70

IDD Supply Current Unloaded Outputs 66MHz CLKA (-1, -2, -3, -4) — — 32 mA

Select Inputs at VDD or GND 66MHz CLKA (-1H, -2H, -5H) — — 50

33MHz CLKA (-1, -2, -3, -4) — — 18
33MHz CLKA (-1H, -2H, -5H) — — 30

(1)

Max. Unit

7

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS - INDUSTRIAL

Symbol Parameter Conditions Min. Typ. Max. Unit

t1 Output Frequency 30pF Load, all devices 1 0  100 MHz
t1 Output Frequency 20pF Load, -1H, -2H, -5H Devices
t1 Output Frequency 15pF Load, -1, -2, -3, -4 devices 1 0  133.3 MHz

Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 4 0 50 60 %

(-1, -2, -3, -4, -1H, -2H, -5H) 30pF Load

Duty Cycle = t

2 ÷ t1 Measured at 1.4V, FOUT = 50MHz 45 50 55 %

(-1, -2, -3, -4, -1H, -2H, -5H) 15pF Load
t3 Rise Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 30pF Load 2.2 ns
t3 Rise Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 15pF Load 1.5 ns
t3 Rise Time (-1H, -2H, -5H) Measured between 0.8V and 2V, 30pF Load 1.5 ns
t4 Fall Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 30pF Load 2.5 ns
t4 Fall Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 15pF Load 1.5 ns
t4 Fall Time (-1H, -5H) Measured between 0.8V and 2V, 30pF Load 1.25 ns
t5 Output to Output Skew on same Bank All outputs equally loaded 200 ps

(-1, -2, -3, -4)

Output to Output Skew (-1H, -2H, -5H) All outputs equally loaded 200 ps

Output Bank A to Output Bank B (-1, -4, -2H, -5H) All outputs equally loaded 200 ps

Output Bank A to Output Bank B Skew (-2, -3) All outputs equally loaded 400 ps
t6 Delay, REF Rising Edge to FBK Rising Edge Measured at VDD/2  0±250ps
t7 Device to Device Skew Measured at VDD/2 on the FBK pins of devices  0 700 ps

t8 Output Slew Rate Measured between 0.8V and 2V on -1H, -2H, -5H 1 V/ns

device using Test Circuit 2

tJ Cycle to Cycle Jitter Measured at 66.67 MHz, loaded outputs, 15pF Load 200

(-1, -1H, -4, -5H) Measured at 66.67 MHz, loaded outputs, 30pF Load 200 ps

Measured at 133.3 MHz, loaded outputs, 15pF Load 100

tJ Cycle to Cycle Jitter Measured at 66.67 MHz, loaded outputs, 30pF Load 400 ps

(-2, -2H, -3) Measured at 66.67 MHz, loaded outputs, 15pF Load 400

tLOCK PLL Lock Time Stable Power Supply, valid clocks presented 1ms

on REF and FBK pins

NOTE:

1. IDT2308-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67MHz.

(1)

10  133.3 MHz

8

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

SWITCHING WAVEFORMS

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

t1

t2

Output

1.4V

0.8V

t3

Output

Output

1.4V

Duty Cycle Timing

2V

2V

0.8V
t4

All Outputs Rise/Fall Time

1.4V

1.4V

t5

1.4V

3.3V
0V

Input

FBK

Input to Output Propagation Delay

FBK, Device 1

FBK, Device 2

Output to Output Skew

V

DD/2

t6

DD/2

V

t7

Device to Device Skew

V

V

DD/2

DD/2

9

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

TYPICAL DUTY CY CLE

(for 30pf loads over frequency - 3.3V, 25C)

Duty Cycle vs V

60
58
56

)

54

%

(
e

52

l

c

y
C

50

y

t

u
D

48

46
44
42
40

3

3.1

3.2

Duty Cycle vs Frequency

(for 30pf loads over te m perature - 3. 3V)

60

58

56

)

54

%

(
e

l

c

52

y
C
y

50

t

u
D

48

46
44

42

40

20

40

60

Frequency (MHz)

I

DD vs Number of Loaded Outputs

140

(for 30pf loads over frequenc y - 3.3V, 25C)

DD

3.4

3.3

VDD (V)

80 100 120 140

(1)

AND IDD TRENDS

33MHz

66MHz
100MHz

3.5 3.6

-40C
0C
25C
70C
85C

(2)

FOR IDT2308-1, 2, 3, AND 4

Duty Cycle vs V

DD

(for 15pF loads over frequency - 3.3V, 25C)

60
58
56

)

54

%

(
e

52

l

c

y
C

50

y

t

u
D

48
46

44

42
40

3

3.1

3.2

3.3

3.4

VDD (V)

Duty Cycle vs Frequency

(for 15pF loads over temperature - 3.3V)

60

58

56

)

54

%

(
e

l

c

52

y
C
y

50

t

u
D

48
46
44
42
40

20

40

80 100 120 140

60

Frequency (MHz)

I

DD vs Number of Loaded Outputs

140

(for 15pF loads over frequency - 3.3V, 25C)

3.5 3.6

33MHz
66MHz
100MHz
133MHz

-40C
0C
25C
70C
85C

120

100

80

)
A

m

(

D

60

D

I

40

20

0

02

Number of Loaded Outputs

33MHz

66MHz
100MHz

4

6

8

120

100

80

)
A

m

(

D

60

D

I

40

20

0

02

Number of Loaded Outputs

33MHz

66MHz
100MHz

4

6

8

NOTES:

1. Duty Cycle is taken from typical chip measured at 1.4V.

2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the Unloaded Current (n = Number of Outputs; C = Capacitance Load per Output (F); V = Voltage Supply(V);
f = Frequency (Hz).

10

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

TYPICAL DUTY CY CLE

(for 30pf loads over fr equency - 3.3V, 25C)

Duty Cycle vs V

60
58
56

)

54

%

(
e

52

l

c

y
C

50

y

t

u
D

48
46

44

42
40

3

3.1

3.2

Duty Cycle vs Frequency

(for 30pf loads over temp erature - 3.3V)

60

58

56

)

54

%

(
e

l

c

52

y
C
y

50

t

u
D

48
46
44
42
40

20

40

60

Frequency (MHz)

I

DD vs Number of Loaded Outputs

(for 30pf loads over fr equency - 3.3V, 25C)

160

140

120

DD

3.4

3.3

VDD (V)

80 100 120 140

(1)

AND IDD TRENDS

33MHz

66MHz
100MHz

3.5 3.6

-40C
0C
25C
70C
85C

(2)

FOR IDT2308-1H, -2H, AND -5H

Duty Cycle vs V

DD

(for 15pF loads over frequency - 3.3V, 25C)

60

58

56

)

54

%

(
e

52

l

c

y
C

50

y

t

u
D

48

46

44

42
40

3

3.1

3.2

3.3

3.4

3.5 3.6

VDD (V )

Duty Cycle vs Frequency

(for 15pF loads over tem perature - 3.3V)

60
58
56

)

54

%

(
e

l

c

52

y
C
y

50

t

u
D

48

46
44
42
40

20

40

80 100 120 140

60

Frequency (MHz)

DD vs Number of Loaded Outputs

I

(for 15pF loads over frequency - 3.3V, 25C)

160
140
120

33MHz

66MHz
100MHz
133MHz

-40C
0C
25C
70C
85C

100

80

)
A

m

(

D

60

D

I

40

20

NOTES:

0

02

Number of Loaded Outputs

33MHz

66MHz
100MHz

4

6

8

100

80

)
A

m

(

D

60

D

I

40

20

0

02

Number of Loaded Outputs

33MHz

66MHz
100MHz

4

6

8

1. Duty Cycle is taken from typical chip measured at 1.4V.

2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the Unloaded Current (n = Number of Outputs; C = Capacitance Load per Output (F); V = Voltage Supply(V);
f = Frequency (Hz).

11

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

TEST CIRCUITS

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

0.1µF

0.1µF

TEST CIRCUIT 1

VDD

DD

V

OUTPUTS

CLK

OUT

C

LOAD

GND GND

Test Circuit for all Parameters Except t8

TEST CIRCUIT 1

0.1µF

VDD

OUTPUTS

1KΩ

CLK

1KΩ

DD

V

0.1µF
GND

GND

Test Circuit for t8, Output Slew Rate On -1H, -2H, and -5H Device

OUT

10pF

12

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

ORDERING INFORMATION

XXXXX XX X

IDT

Device Type

Package Process

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Blank
I

DC
DCG
PG

2308-1
2308-2
2308-3
2308-4
2308-1H
2308-2H
2308-5H

Ordering Code Package Type Operating Range

IDT2308-1DC 16-Pin SOIC Commercial
IDT2308-1DCI 16-Pin SOIC Industrial
IDT2308-1HDC 16-Pin SOIC Commercial
IDT2308-1HDCG 16-Pin SOIC Commercial
IDT2308-1HDCI 16-Pin SOIC Industrial
IDT2308-1HPG 16-Pin TSSOP Commercial
IDT2308-1HPGI 16-Pin TSSOP Industrial
IDT2308-2DC 16-Pin SOIC Commercial
IDT2308-2DCG 16-Pin SOIC Commercial
IDT2308-2DCI 16-Pin SOIC Industrial
IDT2308-2DCGI 16-Pin SOIC Industrial
IDT2308-2HDC 16-Pin SOIC Commercial
IDT2308-2HDCI 16-Pin SOIC Industrial
IDT2308-3DC 16-Pin SOIC Commercial
IDT2308-3DCI 16-Pin SOIC Industrial
IDT2308-4DC 16-Pin SOIC Commercial
IDT2308-4DCI 16-Pin SOIC Industrial
IDT2308-5HDC 16-Pin SOIC Commercial
IDT2308-5HDCI 16-Pin SOIC Industrial
IDT2308-5HPG 16-Pin TSSOP Commercial
IDT2308-5HPGI 16-Pin TSSOP Industrial

Commercial (0oC to +70oC)
Industrial (-40

Small Outline
SOIC - Green
Thin Shrink Small Outline Package

Zero Delay Clock Buffer With Standard Drive

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Zero Delay Clock Buffer with High Drive

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o

C to +85oC)

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 [e-mail]
Santa Clara, CA 95054 fax: [phone] [phone]

www.idt.com

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