IDT ICS1526GLF Schematic [ru]

Integrated Circuit Systems

Video Clock Synthesizer

ICS1526

General Description

The ICS1526 is a low-cost, high-performance
frequency generator. It is suited to general purpose
phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using ICS’s advanced low-voltage
CMOS mixed-mode technology, the ICS1526 is an
effective clock synthesizer that supports video
projectors and displays at resolutions from VGA to
beyond XGA.

The ICS1526 offers single-ended clock outputs to 110
MHz. The HSYNC_out, and VSYNC_out pins provide
the regenerated versions of the HSYNC and VSYNC
inputs synchronous to the CLK output.

The advanced PLL uses its internal programmable
feedback divider. The device is programmed by a
standard I
a TSSOP16 package.

2

C-bus™ serial interface and is available in

ICS1526 Functional Diagram

OSC

HSYNC

VSYNC

2

I

ICS1526

C

HSYNC_out

VSYNC_out

CLK

LOCK

Features

• Lead-free packaging (Pb-free)

• Low jitter (typical 27 ps short term jitter)

• Wide input frequency range

• 8 kHz to 100 MHz

• LVCMOS single-ended clock outputs

• Up to 110 MHz

• Uses 3.3 V power supply

• 5 Volt tolerant Inputs (HSYNC, VSYNC)

• Coast (ignore HSYNC) capability via VSYNC pin

• Industry standard I

• PLL Lock detection via I

• 16-pin TSSOP package

2

C-bus programming interface

2

C or LOCK output pin

Applications

• Frequency synthesis

• LCD monitors, video projectors and plasma displays

• Genlocking multiple video subsystems

Pin Configuration (16-pin TSSOP)

VSSD

SDA

SCL
VSYNC
HSYNC

VDDA
VSSA

OSC

1
2
3
4
5
6
7

16
15
14
13
12
11
10

8 9

VDDD
VSSQ
VSYNC_out
VDDQ
CLK
HSYNC_out
LOCK
I2CADR

MDS 1526 K Revision 110905

ICS reserves the right to make changes in the preliminary device data
identified in this publication without notice. ICS advises its customers
to obtain the latest version of all device data to verify that information

being relied upon is current and accurate.

Section 1 OverviewICS1526 Data Sheet

Section 1 Overview

The ICS1526 is a user-programmable,
high-performance general purpose clock generator. It
is intended for graphics system line-locked and
genlocked applications and provides the clock signals
required by high-performance analog-to-digital
converters.

Figure 1-1 Simplified Block Diagram

OSC

HSYNC

VSYNC

Divider

3..129

PFD

The ICS1526 has the ability to operate in line-locked
mode with the HSYNC input.

1.1 Phase-Locked Loop

The phase-locked loop has a very wide input frequency
range (8 kHz to 100 MHz). Not only is the ICS1526 an
excellent, general purpose clock synthesizer, but it is
also capable of line-locked operation. Refer to the
block diagram below.

CP VCO

FD

12..4103

VCOD

2,4,8,16

Flip-flop

Flip-flop

CLK

HSYNC_out

VSYNC_out

Note: Polarity controls and other circuit elements are not shown in above diagram for simplicity

The heart of the ICS1526 is a voltage controlled
oscillator (VCO). The VCOs speed is controlled by the
voltage on the loop filter. This voltage will be described

The input HSYNC and VSYNC can be conditioned by a
high-performance Schmitt-trigger by sharpening the
rising/falling edge.

later in this section.

The HSYNC_out and VSYNC_out signals are aligned

The VCOs clock output is first passed through the VCO

with the output clock (CLK) via a set of flip flops.
Divider (VCOD). The VCOD allows the VCO to operate
at higher speeds than the required output clock.

NOTE: Under normal, locked operation the VCOD has
no effect on the speed of the output clocks, just the
VCO frequency.

The output of the VCOD is the full speed output
frequency seen on the CLK. This clock is then sent

1.2 Output Drivers and Logic Inputs

The ICS1526 uses low-voltage TTL (LVTTL) inputs and

LVCMOS outputs, operating at the 3.3 V supply

voltage. The LVTTL inputs are 5 V tolerant.

The LVCMOS drive resistive terminations or

transmission lines.
through the 12-bit internal Feedback Divider (FD). The
feedback divider controls how many clocks are seen
during every cycle of the input reference.

1.3 Automatic Power-On Reset Detection

The ICS1526 has automatic power-on reset detection
The Phase Frequency Detector (PFD) then compares

the feedback to the input and controls the filter voltage
by enabling and disabling the charge pump. The

(POR) circuitry and it resets itself if the supply voltage

drops below threshold values. No external connection

to a reset signal is required.
charge pump has programmable current drive and will

source and sink current as appropriate to keep the
input and the clock output aligned.

MDS 1526 K 2 Revision 110905

Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel [phone] www.icst.com

1.4 I2C Bus Serial Interface

The ICS1526 uses a 5 volt tolerant, industry-standard

2

C-bus serial interface that runs at either low speed

I
(100 kHz) or high speed (400 kHz). The interface uses
12 word addresses for control and status: one
write-only, eight read/write, and three read-only
addresses.

Section 1 OverviewICS1526 Data Sheet

Two ICS1526 devices can sit on the same I

2

C bus,
each selected by the Master according to the state of
the I2CADR pin. The 7-bit device address is 0100110
(binary) when I2CADR is low. The device address is
0100111 (binary) when I2CADR is high. See Section 4,

“Programming”

MDS1526 K 3 Revision 110905

Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel [phone] www.icst.com

Section 2 Pin DescriptionsICS1526 Data Sheet

Section 2 Pin Descriptions

Table 2-1 ICS1526 Pin Descriptions

PIN NO. PIN NAME TYPE DESCRIPTION COMMENTS Notes

1 VSSD

2SDA

3SCL

4 VSYNC

5HSYNC

6VDDA

7 VSSA

8OSC

9I2CADR

10 LOCK

11 HSYNC_out

12 CLK

13 VDDQ

14 VSYNC_out

15 VSSQ

16 VDDD

POWER Digital ground

IN/OUT Serial data I2C-bus 1

IN Serial clock I2C-bus 1

IN Vertical sync 1 & 2

IN Horizontal sync Clock input to PLL 1 & 2

POWER Analog supply Power for analog circuitry

POWER Analog ground Ground for analog circuitry

IN Oscillator Input from crystal oscillator package 1 & 2

IN I2C device address Chip I2C address select

LVCMOS

Lock PLL Lock detect

OUT

LVCMOS

OUT

LVCMOS

HSYNC output Schmitt-trigger filtered HSYNC

realigned with the output pixel clock

Pixel clock output LVCMOS driver for full speed clock

OUT

POWER Output driver supply Power for output drivers

LVCMOS

OUT

VSYNC output Schmitt-trigger filtered VSYNC

realigned with the output pixel clock

POWER Output driver ground Ground for output drivers

POWER Digital supply Power for digital sections

Notes: 1. These LVTTL inputs are 5 V tolerant.

2. Connect to ground if unused.

MDS 1526 K 4 Revision 110905

Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel [phone] www.icst.com