IDT EB8T5A Eval Board Manual

®

IDT™ 89EBPES8T5A

Evaluation Board Manual

(Eval Board: 18-636-002)

July 2009

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: [phone] • [phone] • FAX: [phone]

©2009 Integrated Device Technology, Inc.

Printed in U.S.A.

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

DISCLAIMER

Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analysis be performed.

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

LIFE SUPPORT POLICY

Table of Contents

®

Notes

Description of the EB8T5A Eval Board

Introduction .....................................................................................................................................1-1

Board Features ...............................................................................................................................1-2

Hardware ................................................................................................................................ 1-2

Software..................................................................................................................................1-2

Other....................................................................................................................................... 1-2

Revision History..............................................................................................................................1-3

Installation of the EB8T5A Eval Board

EB8T5A Installation ........................................................................................................................2-1

Hardware Description .....................................................................................................................2-1

Host System ...........................................................................................................................2-1

Reference Clocks............................................................................................................................2-1

Power Sources................................................................................................................................2-3

External Power Source...........................................................................................................2-3

Vaux Support..........................................................................................................................2-4

PCI Express Serial Data Transmit Termination Voltage Converter........................................ 2-6

PCI Express Digital Power Voltage Converter........................................................................2-6

PCI Express Analog Power Voltage Converter ......................................................................2-6

Core Logic Voltage Converter ................................................................................................2-6

3.3V I/O Power Module...........................................................................................................2-6

Power-up Sequence ...............................................................................................................2-6

Required Jumpers ..................................................................................................................2-6

Reset...............................................................................................................................................2-6

Fundamental Reset ................................................................................................................2-6

Downstream Reset .................................................................................................................2-7

Boot Configuration Vector............................................................................................................... 2-7

SMBus Interfaces............................................................................................................................2-8

SMBus Slave Interface ...........................................................................................................2-8

SMBus Master Interface .......................................................................................................2-10

JTAG Header................................................................................................................................2-10

Attention Buttons...........................................................................................................................2-11

Miscellaneous Jumpers, Headers................................................................................................. 2-11

LEDs .............................................................................................................................................2-12

PCI Express Connectors...............................................................................................................2-14

EB8T5A Board Figure................................................................................................................... 2-16

Software for the EB8T5A Eval Board

Introduction .....................................................................................................................................3-1

Device Management Software........................................................................................................ 3-1

Schematics

Schematics .....................................................................................................................................4-1

EB8T5A Eval Board Manual i July 23, 2009

IDT Table of Contents

Notes

EB8T5A Eval Board Manual ii July 23, 2009

List of Tables

®

Notes

Table 2.1 Clock Source Selection .......................................................................................................2-1

Table 2.2 Clock Frequency Selection ................................................................................................. 2-2

Table 2.3 Spread Spectrum Clock Selection ...................................................................................... 2-2

Table 2.4 SMA Connectors - Onboard Reference Clock .................................................................... 2-2

Table 2.5 External Power Connector - J4 ........................................................................................... 2-3

Table 2.6 Downstream Reset Selection .............................................................................................2-7

Table 2.7 Boot Configuration Vector Signals ...................................................................................... 2-7

Table 2.8 Boot Configuration Vector Switches S3, S4, and S5 (ON=0, OFF=1) ................................ 2-8

Table 2.9 Slave SMBus Interface Connector ......................................................................................2-9

Table 2.10 SMBus Slave Interface Address Configuration ...................................................................2-9

Table 2.11 PES8T5A SMBus Slave Interface Address Setting ............................................................ 2-9

Table 2.12 EEPROM SMBus Address Setting ...................................................................................2-10

Table 2.13 JTAG Connector Pin Out .................................................................................................. 2-11

Table 2.14 Attention Buttons ..............................................................................................................2-11

Table 2.15 Miscellaneous Jumpers, Headers .....................................................................................2-11

Table 2.16 LED Indicators ..................................................................................................................2-13

Table 2.17 PCI Express x4 Connector Pinout ....................................................................................2-14

Table 2.18 PCI Express x1 Connector Pinout ....................................................................................2-15

EB8T5A Eval Board Manual iii July 23, 2009

IDT List of Tables

Notes

EB8T5A Eval Board Manual iv July 23, 2009

List of Figures

®

Notes

Figure 1.1 Function Block Diagram of the EB8T5A Eval Board ..........................................................1-1

Figure 2.1 Clock Distribution Block Diagram .......................................................................................2-3

Figure 2.2 Power Distribution Block Diagram ......................................................................................2-4

Figure 2.3 APWRDIS# Timing ............................................................................................................2-5

Figure 2.4 APWRDIS# Timing Circuit .................................................................................................2-5

EB8T5A Eval Board Manual v July 23, 2009

IDT List of Figures

Notes

EB8T5A Eval Board Manual vi July 23, 2009

Chapter 1

Description of the EB8T5A

Eval Board

®

Notes

Introduction

In this manual, references to the PES8T5A also apply to the PES6T5 and PES5T5 unless otherwise

indicated.

The 89HPES8T5A switch (also referred to as PES8T5A in this manual) is a member of IDT’s PCI
Express® standard (PCIe®) based line of products. It is an 8-lane, 5-port switch. One upstream port is
provided for connecting to the root complex (RC), and up to four downstream ports are available for
connecting to PCIe endpoints or to another switch. More information on this device can be found in the
appropriate User Manual (89HPES8T5A, 89HPES6T5, or 89HPES5T5).

The 89EBPES8T5A Evaluation Board (also referred to as EB8T5A in this manual) provides an evalua­tion platform for the PES8T5A switch. It is also a cost effective way to add a PCIe downstream port (x1) to
an existing system with a limited number of PCIe downstream ports. The EB8T5A eval board is designed to
function as an add-on card to be plugged into a x4 PCIe slot available on a motherboard hosting an appro­priate root complex, microprocessor(s), and four downstream ports. The EB8T5A is a vehicle to test and
evaluate the functionality of the PES8T5A chip. Customers can use this board to get a headstart on soft­ware development prior to the arrival of their own hardware. The EB8T5A is also used by IDT to reproduce
system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block
diagram representing the main parts of the EB8T5A board.

JTAG

Header

SSC Clock
Buffer

25 MHz

Clock

Fanout

Main

Reset

x1

I/O Expander

PCA9555

EEPROM

24LC512

SMBus

SMBUS
HEADER

Figure 1.1 Function Block Diagram of the EB8T5A Eval Board

EB8T5A Eval Board Manual 1 - 1 July 23, 2009

PCI Express
Switch

PES8T5A

x4 (PES8T5A)
x2 (PES6T5)
x1 (PES5T5)

PCIe x4 Upstream Edge

x1

x1

x1

Power

Module

PTH08T240

PCIe x1 Downstream Slot

PCIe x1 Downstream Slot

PCIe x1 Downstream Slot

PCIe x1 Downstream Slot

External Power
Connector

Voltages on board
+12V, +3.3V, +1.5V, +1.0V

IDT Description of the EB8T5A Eval Board

Notes

Board Features

Hardware



PCIe 5 port switch

– PES8T5A — Five ports (one x4 port and four x1 ports), 8 PCIe lanes
– PES6T5 — Five ports (one x2 port and four x1 ports), 6 PCIe lanes
– PES5T5 — Five ports (five x1 ports), 5 PCIe lanes
– PCIe Base Specification Revision 1.1 compliant
– Integrates eight 2.5 Gbps embedded SerDes
– Up to 256 byte maximum Payload Size
– Automatic lane reversal and polarity inversion supported on all lanes
– Automatic per port link width negotiation to x4, x2, x1
– Load configuration from an optional serial EEPROM via SMBUS



Upstream, Downstream Port

– One edge connector on the upstream port, to be plugged into a slot with at least x4 capable

mechanical slot connector on a host motherboard

– Four slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.



Numerous user selectable configurations set using onboard jumpers and DIP-switches

– Source of clock - host clock or onboard clock generator
– Two clock rates and spread spectrum settings
– Boot mode selection



Vaux Support



SMBUS Slave Interface (4 pin header)



SMBUS Master Interface connected to the Serial EEPROMs through I/O expander



“Attention” button for each downstream port to initiate a hot swap event on each port



Four pin connector for optional external power supply



Push button for Warm Reset



Several LEDs to display status, reset, power, “Attention”, etc.



One 14-pin JTAG header

Software

There is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES8T5A within host systems
running popular operating systems.



Installation programs

– Operating Systems Supported: Windows2000, WindowsXP, Linux



GUI based application for Windows and Linux

– Allows users to view and modify registers in the PES8T5A
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.

Other



A metal bracket is required to firmly hold in place the four endpoints plugged into the EB8T5A
board.



An external power supply may be required under some conditions.



SMBUS cable may be required for certain evaluation exercises.



SMA connectors are provided on the EB8T5A board for specific test points.

EB8T5A Eval Board Manual 1 - 2 July 23, 2009

IDT Description of the EB8T5A Eval Board

Notes

Revision History

September 10, 2007: Initial publication of board manual.

July 23, 2009: Added PES6T5 and PES5T5 devices to eval board manual. Updated Power Sources

section, Table 2.15, and Schematics. Added Note after Table 2.17.

EB8T5A Eval Board Manual 1 - 3 July 23, 2009

IDT Description of the EB8T5A Eval Board

Notes

EB8T5A Eval Board Manual 1 - 4 July 23, 2009

Chapter 2

Installation of the EB8T5A

Eval Board

®

Notes

EB8T5A Installation

This chapter discusses the steps required to configure and install the EB8T5A evaluation board. All
available DIP switches and jumper configurations are explained in detail.

The primary installation steps are:

1. Configure jumper/switch options suitable for the evaluation or application requirements.

2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.

3. Insert the evaluation board into the host system (motherboard with root complex chipset).

4. Apply power to the host system.

The EB8T5A board is shipped with all jumpers and switches configured to their default settings. In most
cases, the board does not require further modification or setup.

Hardware Description

The PES8T5 is an 8-lane, 5-port PCI Express® switch. It is a peripheral chip that performs PCI Express
based switching with a feature set optimized for high performance applications such as servers and
storage. It provides fan-out and switching functions between a PCI Express upstream port and 4 down­stream ports or peer-to-peer switching between downstream ports.

The EB8T5A has four PCI Express downstream ports, accessible through four x4 open-ended connec­tors.

Basic requirements for the board to run are:

– Host system with a PCI Express root complex supporting x4 configuration through a PCI Express

– PCI Express Endpoint Cards capable of training x1 link.

x4 slot.

Host System

The evaluation board cannot be operated as a standalone unit. A host system implementing a PCI
Express root complex supporting x4 configuration through a PCI Express x4 slot is required to take full
advantage of the PES8T5’s capabilities.

Reference Clocks

The PES8T5A requires a differential reference clock. The EB8T5A derives this clock from a common
source which is user-selectable. The common source can be either the host system’s reference clock or the
onboard clock generator. Selection is made by resistor switch described in Table 2.1.

Clock Configuration Switch - S3[3]

S3[3] Clock Source

ON Onboard Reference Clock – Use onboard clock generator

OFF Upstream Reference Clock – Host system provides clock (Default)

Table 2.1 Clock Source Selection

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IDT Installation of the EB8T5A Eval Board

Notes

The source for the onboard clock is the ICS9FG104 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB8T5A allows selection between multiple
clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively.
Spread Spectrum technology reduces peak EMI emissions by modulating the frequency to spread the peak
energy over a wider bandwidth.

Clock Frequency Switch - S3[1]

S3[1] Clock Frequency

OFF 125MHz

ON 100MHz (Default)

Table 2.2 Clock Frequency Selection

Clock Spread Spectrum Switch - S3[2]

S3[2] Spread Spectrum

OFF Enable Spread Spectrum

ON Disable Spread Spectrum (Default)

Table 2.3 Spread Spectrum Clock Selection

If the Clock Spread Spectrum is used to modulate data rate, then both ports must use same modulated
clock source. Therefore, if your system uses SSC, the on-board clock generator must be disabled and the
upstream reference clock should be used instead.

The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.4. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.

Onboard Reference Clock Output (Differential) – J18, J19

J19 Positive Reference Clock

J18 Negative Reference Clock

Table 2.4 SMA Connectors - Onboard Reference Clock

Figure 2.1 illustrates the clock distribution block diagram for the EB8T5A evaluation board.

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IDT Installation of the EB8T5A Eval Board

Notes

Upstream PEREFCLK

25MHz

ISC9FG104

Power Sources

Power for the EB8T5A is generated from the 12.0V PCI Express upstream slot power or optionally from

3.3Vaux. A 12.0V to 3.3V DC-DC converter will be used to provide power to four DC-DC converters to
generate VDDcore, VDDpe, VDDpea, and VTT voltages. The 3.3V from the 12.0V converter is used to
power VDDio. When in power down mode the DC-DC converters is powered directly from 3.3Vaux through
a MOSFET switch.

If add-in cards require more power than the upstream slot can support, an external source is required to
supply this extra power via an auxiliary 4-pin power connector on the board. Header W1, W5, and W11 (see
Table 2.15) are used to select the proper power source for the switch and all downstream ports.

PEREFCLK0

ICS557-06

Figure 2.1 Clock Distribution Block Diagram

SMA - J18,J19

ICS9DB803D

Port2
Port3
Port4

Port5

External Power Source

If necessary, external power is supplied to the EB8T5A board through a 4-pin auxiliary power connector
attached to J4. The external power supply provides +12V to the EB8T5A as described in Table 2.5. The
+5V is unused.

Pin Signal

1+12V

2GND

3GND

4+5V

Table 2.5 External Power Connector - J4

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IDT Installation of the EB8T5A Eval Board

Notes

Figure 2.2 Power Distribution Block Diagram

Vaux Support

Power supply support will be provided to EB8T5A from 12.0V upstream power to 3.3Vaux upstream
power when in sleep mode. The WAKE# signal direction, both an input and output will be supported by
jumper selection. The APWRDIS# signal for auxiliary power disable requires the following timing on power­up.

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IDT Installation of the EB8T5A Eval Board

Notes

Figure 2.3 APWRDIS# Timing

On initial power up APWRDIS# must be held low initially for 8 clocks after PERST# is removed. Then it
must be sampled high 256 clocks after PERSTN# is removed to enable L2 mode. Subsequent PERST# will
not affect the APWRDIS# state. This timing will be provided by the following circuit.

Figure 2.4 APWRDIS# Timing Circuit

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IDT Installation of the EB8T5A Eval Board

Notes

PCI Express Serial Data Transmit Termination Voltage Converter

A DC-DC converter (U6) provides a 1.5V PCI Express serial data transmit termination voltage (shown
as VTTPE or VPETVTT) to the PES8T5A.

PCI Express Digital Power Voltage Converter

A separate DC-DC converter (U16) provides a 1.0V PCI Express digital power voltage (VDDPE) to the
PES8T5A.

PCI Express Analog Power Voltage Converter

A separate DC-DC converter (U7) provides a 1.0V PCI Express analog power voltage (shown as
VDDAPE or VDDPEA) to the PES8T5A.

Core Logic Voltage Converter

A separate DC-DC converter (U1) provides the 1.0V core voltage (VDDCORE) to the PES8T5A.

3.3V I/O Power Module

A 12V to 3.3V power module (U5) provides the 3.3V I/O voltage (VDDIO) to the PES8T5A.

Power-up Sequence

The power-up sequence must be as following:

1. VDDIO - 3.3V

2. VDDCORE, VDDAPE, VDDPE - 1.0V

3. VTTPE - 1.5V

When powering up, each voltage level must ramp up and stabilize prior to applying the next voltage in
the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations
between sequential valid power level requirements. To insure that the sequencing requirements are met, a

0.047µF is used at the SOFTSTART cap on the VTTPE’s voltage converter (U6 pin 36) in the EB8T5A.

Required Jumpers

To deliver power to the PES8T5A switch, the following jumpers must be shunted: W4, W10, W23, W24,
and W25. These jumpers were implemented so that the power consumption of the PES8T5A can be
measured.

Reset

The PES8T5A supports two types of reset mechanisms as described in the PCI Express specification:

– Fundamental Reset: This is a system-generated reset that propagates along the PCI Express

tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES8T5A, and the endpoints.

– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to

another. Hot Reset may be initiated by software. This is further discussed in the 89HPES8T5A
User Manual. The EB8T5A evaluation board provides seamless support for Hot Reset.

Fundamental Reset

There are two types of Fundamental Resets which may occur on the EB8T5A evaluation board:

– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI

Express Reset (PERSTN) input pin of the PES8T5A.

– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be

initiated by two methods:

• Pressing a push-button switch (S1) located on EB8T5A board

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IDT Installation of the EB8T5A Eval Board

Notes

• The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB8T5A. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W2.

Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES8T5A while power is on.

Downstream Reset

The PES8T5A provides a a choice of either a software-controlled reset for each downstream port
through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in
Table 2.6.

Port # Jumper Selection

5 W8 [1-2] Software controlled reset through GPIO10

[2-3] Fundamental reset PERST# (default)

4 W9 [1-2] Software controlled reset through GPIO1

[2-3] Fundamental reset PERST# (default)

3 W6 [1-2] Software controlled reset through GPIO9

[2-3] Fundamental reset PERST# (default)

2 W7 [1-2] Software controlled reset through GPIO0

[2-3] Fundamental reset PERST# (default)

Table 2.6 Downstream Reset Selection

Boot Configuration Vector

A boot configuration vector consisting of the signals listed in Table 2.7 is sampled by the PES8T5A
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S3, S4, and S5 as defined in Table 2.8.

Signal Description

CCLKDS Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a com-

mon clock is being used between the downstream device and the downstream port.

Default: 0x1

CCLKUS Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common

clock is being used between the upstream device and the upstream port. Default: 0x1

MSMBSMODE Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus

should operate at 100 KHz instead of 400 kHz. Default: 0x0

RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the

PES8T5A executes the reset procedure and remains in a reset state with the Master and
Slave SMBuses active. This allows software to read and write registers internal to the
device before normal device operation begins. The device exits the reset state when the
RSTHALT bit is cleared in the P0_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register.

Default: 0x0

Table 2.7 Boot Configuration Vector Signals (Part 1 of 2)

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IDT Installation of the EB8T5A Eval Board

Notes

Signal Description

SWMODE[2:0] Switch Mode. These configuration pins determine the PES8T5A switch operating mode.

Default: 0x0

0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 through 0x8 - Reserved

REFCLKM PCI Express Reference Clock Mode Select. This signal selects the frequency of the ref-

erence clock input. Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz

MSMBADDR[2:0] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM

from which configuration information is loaded. Default: 0x0

APWRDIS# Auxiliary Power Disable. When this pin is active, it disables the device from using auxil-

iary power supply. Default: 0x0

Table 2.7 Boot Configuration Vector Signals (Part 2 of 2)

Signal Description Default

S3[4] CCLKDS OFF

S3[5] CCLKUS OFF

S3[6] MSMBSMODE ON

S5[6] RSTHALT ON

S5[1] SWMODE[0] ON

S5[2] SWMODE[1] ON

S5[3] SWMODE[2] ON

S5[5] APWRDIS# ON

S4[5] MSMBADDR[1] ON

S4[6] MSMBADDR[2] ON

S4[7] MSMBADDR[3] ON

S4[8] MSMBADDR[4] ON

Table 2.8 Boot Configuration Vector Switches S3, S4, and S5 (ON=0, OFF=1)

SMBus Interfaces

The System Management Bus (SMBus) is a two-wire interface through which various system compo-

2

nent chips can communicate. It is based on the principles of operation of I
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.

The PES8T5A contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface.
The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all soft­ware-visible registers. The Master SMBus interface provides connection to the external serial EEPROMs
used for initialization and the I/O expander used for hot-plug signals.

C. Implementation of the SMBus

SMBus Slave Interface

On the PES8T5A board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.9.

EB8T5A Eval Board Manual 2 - 8 July 23, 2009

IDT Installation of the EB8T5A Eval Board

Notes

.

Slave SMBus Interface Connector

J21

Pin Signal

1N/C

2SCL

3GND

4SDA

Table 2.9 Slave SMBus Interface Connector

A fixed slave SMBus address specified by the SSMBADDR[5,3:1] pins is used.

For a fixed address, the SMBus address of the PES8T5A slave interface is 0b1110111 by default and is
configurable using DIP switch S4 as described in Tables 2.10 and 2.11.

Slave Interface Address Configuration

Address Bit Signal

1 SSMBUSADDR[1]

2 SSMBUSADDR[2]

3 SSMBUSADDR[3]

40

5 SSMBUSADDR[5]

61

71

Table 2.10 SMBus Slave Interface Address Configuration

SMBUS Slave Interface Address Setting

S4[4]

SSMBADDR[5]

S4[3]

SSMBADDR[3]

S4[2]

SSMBADDR[2]

S4[1]

SSMBADDR[1]

Slave Interface

Bus Address

OFF OFF OFF OFF 0b1110111 (Default)

OFF OFF OFF ON 0b1110110

OFF OFF ON OFF 0b1110101

OFF OFF ON ON 0b1110100

OFF ON OFF OFF 0b1110011

OFF ON OFF ON 0b1110010

OFF ON ON OFF 0b1110001

OFF ON ON ON 0b1110000

ON OFF OFF OFF 0b1100111

ON OFF OFF ON 0b1100110

Table 2.11 PES8T5A SMBus Slave Interface Address Setting (Part 1 of 2)

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IDT Installation of the EB8T5A Eval Board

Notes

SMBUS Slave Interface Address Setting

S4[4]

SSMBADDR[5]

ON OFF ON OFF 0b1100101

ON OFF ON ON 0b1100100

ON ON OFF OFF 0b1100011

ON ON OFF ON 0b1100010

ON ON ON OFF 0b1100001

ON ON ON ON 0b1100000

Table 2.11 PES8T5A SMBus Slave Interface Address Setting (Part 2 of 2)

S4[3]

SSMBADDR[3]

S4[2]

SSMBADDR[2]

S4[1]

SSMBADDR[1]

Slave Interface

Bus Address

The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:

– Byte and Word Write/Read
– Block Write/Read

SMBus Master Interface

Connected to the master SMBus interface are four 16-bit I/O Expanders (PCA9555) and a serial
EEPROM (24LC512). Four I/O Expanders are used as the interface for the onboard hot-plug controllers
(MIC2591B).

The bus address for the selected EEPROM device is

0b1010000 by default and the lower four bits is

configurable using switch S4 as described in Table 2.12.

S4[8] S4[7] S4[6] S4[5] Bus Address

OFF OFF OFF OFF 0b1111

OFF OFF OFF ON 0b1110

OFF OFF ON OFF 0b1101

OFF OFF ON ON 01100

OFF ON OFF OFF 0b1011

OFF ON OFF ON 0b1010

OFF ON ON OFF 0b1001

OFF ON ON ON 0b1000

ON ON ON ON 0b0000 (Default)

Table 2.12 EEPROM SMBus Address Setting

JTAG Header

The PES8T5A provides a JTAG connector J4 for access to the PES8T5A JTAG interface. The
connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.12 for the JTAG Connector J2
pin out.

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IDT Installation of the EB8T5A Eval Board

Notes

Pin Signal Direction Pin Signal Direction

1 /TRST - Test reset Input 2 GND —

3 TDI - Test data Input 4 GND —

5 TDO - Test data Output 6 GND —

7 TMS - Test mode select Input 8 GND —

9 TCK - Test clock Input 10 GND —

Attention Buttons

The PES8T5A features four attention buttons, shown in Table 2.13. Each button corresponds to a partic­ular port and is used to initiate hot-swapping events.

JTAG Connector J2

Table 2.13 JTAG Connector Pin Out

Button Description

SW4 Port 5 Attention Button

SW3 Port 4 Attention Button

SW2 Port 3 Attention Button

SW1 Port 2 Attention Button

Table 2.14 Attention Buttons

Miscellaneous Jumpers, Headers

Miscellaneous Jumpers, Headers

Ref.

Designator

S2[1] Switch OFF Port2: Manually-operated Retention Latch

S2[2] Switch OFF Port3: Manually-operated Retention Latch

S2[3] Switch OFF Port4: Manually-operated Retention Latch

S2[4] Switch OFF Port5: Manually-operated Retention Latch

S6[4] Switch OFF Bypass hot-plug controller - Enables direct power (+12V and

S6[3] Switch OFF Bypass hot-plug controller - Enables direct power (+12V and

S6[2] Switch OFF Bypass hot-plug controller - Enables direct power (+12V and

S6[1] Switch OFF Bypass hot-plug controller - Enables direct power (+12V and

Type Default Description

+3.3V) to Port 5 (Default)

+3.3V) to Ports 4 (Default)

+3.3V) to Ports 3 (Default)

+3.3V) to Ports 2 (Default)

Table 2.15 Miscellaneous Jumpers, Headers (Part 1 of 2)

EB8T5A Eval Board Manual 2 - 11 July 23, 2009

IDT Installation of the EB8T5A Eval Board

Notes

Miscellaneous Jumpers, Headers

Ref.

Designator

W32 Header 2-3 Shunted 1-2: Port 2, +3.3V source base on hot-plug controller

W31 Header 2-3 Shunted 1-2: Port 2, +12V source base on hot-plug controller

W30 Header 2-3 Shunted 1-2: Port 2, +3.3Vaux source base on hot-plug controller

W35 Header 2-3 Shunted 1-2: Port 3, +3.3V source base on hot-plug controller

W34 Header 2-3 Shunted 1-2: Port 3, +12V source base on hot-plug controller

W33 Header 2-3 Shunted 1-2: Port 3, +3.3Vaux source base on hot-plug controller

W38 Header 2-3 Shunted 1-2: Port4, +3.3V source base on hot-plug controller

W37 Header 2-3 Shunted 1-2: Port 4, +12V source base on hot-plug controller

W36 Header 2-3 Shunted 1-2: Port 4, +3.3Vaux source base on hot-plug controller

W50 Header 2-3 Shunted 1-2: Port 5, +3.3V source base on hot-plug controller

Type Default Description

2-3: Port 2, +3.3V source from upstream port power

2-3: Port 2, +12V source from upstream port power

2-3: Port 2, +3.3Vaux source from upstream port power

2-3: Port 3, +3.3V source from upstream port power

2-3: Port 3, +12V source from upstream port power

2-3: Port 3, +3.3Vaux source from upstream port power

2-3: Port 4, +3.3V source from upstream port power

2-3: Port 4, +12V source from upstream port power

2-3: Port 4, +3.3Vaux source from upstream port power

2-3: Port 5, +3.3V source from upstream port power

W40 Header 2-3 Shunted 1-2: Port 5, +12V source base on hot-plug controller

2-3: Port 5, +12V source from upstream port power

W39 Header 2-3 Shunted 1-2: Port 5, +3.3Vaux source base on hot-plug controller

2-3: Port 5, +3.3Vaux source from upstream port power

W15 Header Open 1-2: Select WAKEN# as an input

2-3: Select WAKE# as in output

S2[6] Switch On Power Good Enable Force On switch for ICS90DB803 clock

output enable (OE2#)

S2[1] Switch On Power Good Enable Force On switch for ICS90DB803 clock

output enable (OE3#)

S6[6] Switch On Power Good Enable Force On switch for ICS90DB803 clock

output enable (OE4#)

S6[5] Switch On Power Good Enable Force On switch for ICS90DB803 clock

output enable (OE5#)

W1, W5, W11 Header 1-2 Shunted 1-2: +12V source from upstream port (Default)

2-3: +12V source from external power connect

W3 Header Shunted Disable EEPROM Write protect feature (Default)

Table 2.15 Miscellaneous Jumpers, Headers (Part 2 of 2)

LEDs

There are several LED indicators on the EB8T5A which convey status feedback. A description of each is
provided in Table 2.15.

EB8T5A Eval Board Manual 2 - 12 July 23, 2009

IDT Installation of the EB8T5A Eval Board

Notes

Location Color Definition

DS87 Green Port 2: Power-is-good indicator

DS86 Green Port 3: Power-is-good indicator

DS85 Green Port 4: Power-is-good indicator

DS84 Green Port 5: Power-is-good indicator

DS83 Amber Port2: Attention Input indicator

DS82 Amber Port3: Attention Input indicator

DS81 Amber Port4: Attention Input indicator

DS80 Amber Port5: Attention Input indicator

DS79 Green Port2: Presence Detect indicator

DS78 Green Port3: Presence Detect indicator

DS77 Green Port4: Presence Detect indicator

DS76 Green Port5: Presence Detect indicator

DS64 Amber Port2: Attention Output indicator

DS63 Amber Port3: Attention Output indicator

DS62 Amber Port4: Attention Output indicator

DS61 Amber Port5: Attention Output indicator

DS57 Green Port 2: Power indicator

DS56 Green Port 3: Power indicator

DS55 Green Port 4: Power indicator

DS54 Green Port 5: Power indicator

DS91 Red Port 2: MRL indicator

DS90 Red Port 3: MRL indicator

DS89 Red Port 4: MRL indicator

DS88 Red Port 5: MRL indicator

DS95 Red Port 2: Power Fault indicator

DS94 Red Port 3: Power Fault indicator

DS93 Red Port 4: Power Fault indicator

DS92 Red Port 5: Power Fault indicator

DS99 Green Port 2: Link Up indicator

DS98 Green Port 3: Link Up indicator

DS97 Green Port 4: Link Up indicator

DS96 Green Port 5: Link Up indicator

DS100 Green Port 0: Link Up indicator

DS105 Amber Port0: Link Activity indicator

DS104 Amber Port2: Link Activity indicator

Table 2.16 LED Indicators (Part 1 of 2)

EB8T5A Eval Board Manual 2 - 13 July 23, 2009

IDT Installation of the EB8T5A Eval Board

Notes

Location Color Definition

DS103 Amber Port3: Link Activity indicator

DS102 Amber Port4: Link Activity indicator

DS101 Amber Port5: Link Activity indicator

Table 2.16 LED Indicators (Part 2 of 2)

PCI Express Connectors

Pin Side A Side B

1 +12V 12V power PRSNT1# Hot-Plug presence detect

2 +12V 12V power +12V 12V power

3 RSVD Reserved +12V 12V power

4 GND Ground GND Ground

5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p

6 SMDAT SMBus Data JTAG TDI (Test Data Input)

7 GND Ground JTAG TDO (Test Data Output)

8 +3.3V 3.3V power JTAG TMS (Test Mode Select)

9 JTAG1 TRST# (Test/Reset) resets

JTAG i/f

10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power

11 WAKE# Signal for Link reactivation PERST# Fundamental Reset

Mechanical Key

12 RSVD Reserved GND Ground

13 GND Ground REFCLK+ REFCLK Reference clock

14 PETp0 Transmitter differential REFCLK- (differential pair)

15 PETn0 pair, Lane 0 GND Ground

16 GND Ground PERp0 Receiver differential

17 PRSNT2# Hot-Plug presence detect PERn0 pair, Lane 0

18 GND Ground GND Ground

19 PETp1 Transmitter differential RSVD Reserved

20 PETn1 pair, Lane 1 GND Ground

21 GND Ground PERp1 Receiver differential

22 GND Ground PERn1 pair, Lane 1

23 PETp2 Transmitter differential GND Ground

24 PETn2 pair, Lane 2 GND Ground

25 GND Ground PERp2 Receiver differential

+3.3V 3.3V power

26 GND Ground PERn2 pair, Lane 2

Table 2.17 PCI Express x4 Connector Pinout (Part 1 of 2)

EB8T5A Eval Board Manual 2 - 14 July 23, 2009

IDT Installation of the EB8T5A Eval Board

Notes

Pin Side A Side B

27 PETp3 Transmitter differential GND Ground

28 PETn3 pair, Lane 3 GND Ground

29 GND Ground PERp3 Receiver differential

30 RSVD Reserved PERn3 pair, Lane 3

31 PRSNT2# Hot-Plug presence detect GND Ground

32 GND Ground RSVD Reserved

Table 2.17 PCI Express x4 Connector Pinout (Part 2 of 2)

Note: R347 should be populated with a 0 ohm resistor (0402) for systems that require PRSNT2#

for the x1 width to be connected.

Pin Side A Side B

1 +12V 12V power PRSNT1# Hot-Plug presence detect

2 +12V 12V power +12V 12V power

3 RSVD Reserved +12V 12V power

4 GND Ground GND Ground

5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p

6 SMDAT SMBus Data JTAG TDI (Test Data Input)

7 GND Ground JTAG TDO (Test Data Output)

8 +3.3V 3.3V power JTAG TMS (Test Mode Select)

9 JTAG1 TRST# (Test/Reset)

resets JTAG i/f

10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power

11 WAKE# Signal for Link reactiva-

tion

Mechanical Key

12 RSVD Reserved GND Ground

13 GND Ground REFCLK+ REFCLK Reference clock

14 PETp0 Transmitter differential REFCLK- (differential pair)

15 PETn0 pair, Lane 0 GND Ground

16 GND Ground PERp0 Receiver differential

17 PRSNT2# Hot-Plug presence detect PERn0 pair, Lane 0

18 GND Ground GND Ground

Table 2.18 PCI Express x1 Connector Pinout

+3.3V 3.3V power

PERST# Fundamental Reset

Note: These x4 and x1 PCI Express connectors comply with the PCIe specification. The
EB8T5A uses x1 (mechanically x4) connector on all downstream ports. According to the PCI
Express specification, the PRSNT1# pin should be wired to the farthest available PRSNT2# pin
on the connector. In the EB8T5A, all PRSNT2# pins are tied together. This allows the board to be
installed in a x1 or a x4 slot. The open-ended x4 slot allows the insertion of physical lane width
greater than x4 to be installed without the need of slot reducer.

EB8T5A Eval Board Manual 2 - 15 July 23, 2009

IDT Installation of the EB8T5A Eval Board

EB8T5A Board Figure

EB8T5A Eval Board Manual 2 - 16 July 23, 2009

Chapter 3

Software for the EB8T5A Eval Board

®

Notes

Introduction

This chapter discusses some of the main features of the available software to give users a better under­standing of what can be achieved with the EB8T5A evaluation board using the device management soft­ware.

Device management software and related user documentation are available on a CD which is included
in the Evaluation Board Kit. This information is also available on IDT’s FTP site. For more information,
contact IDT at [e-mail].

Device Management Software

The primary use of the Device Management Software package is to enable users of the evaluation
board to access all the registers in the PES8T5 device. This access can be achieved using the PCI Express
in-band configuration cycles through the upstream port on the PES8T5.

This software also enables users to save a snapshot of the current register set into a dump file which
can be used for debugging purposes. An export/import facility is also available to create and use “Configu­ration” files which can be used to initialize the switch device with specific values in specific registers.

A conversion utility is also provided to translate a configuration file into an EEPROM programmable data
structure. This enables the user to program an appropriate serial EEPROM with desirable register settings
for the PES8T5, and then to populate that EEPROM onto the Evaluation Board. It is also possible to
program the EEPROM directly on the Evaluation Board using a feature provided by the software package.

The front end of the Device Management Software is a user-friendly Graphical User Interface which
allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the
software in “simulation” mode with no real hardware attached, allowing the creation of configuration files for
the PES8T5 in the absence of the actual device.

Much of the Device Management Software is written with device-independent and OS-independent
code. The software will be guaranteed to work on Linux (/sys interface) and MS Windows XP. It may func­tion flawlessly on various flavors of MS Windows, but may not be validated on all. The fact that the software
is device-independent assures its scalability to future PCIe parts from IDT. Once users are familiar with the
GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each
device through an XML device description file which includes information on the number of ports, registers,
types of registers, information on bit-fields within each register, etc.

EB8T5A Eval Board Manual 3 - 1 July 23, 2009

IDT Software for the EB8T5A Eval Board

Notes

EB8T5A Eval Board Manual 3 - 2 July 23, 2009

Chapter 4

Schematics

®

Notes

Schematics

EB8T5A Eval Board Manual 4 - 1 July 23, 2009

8

6

57

BLOCK DIAGRAM

4

3

DCN

PCB-0161R01 1.0 INTIAL RELEASE 2008-04-14 T. TRAN

REV

2

DESCRIPTION

REVISIONS

DATE

1

CHANGE BY

D

SHEET

1
2
3
4
5
6
7
8
9

DESCRIPTION

TABLE OF CONTENTS
POWER REGULATORS PES8T5A
POWER MOSFETS FOR 3.3VAUX
CLOCKS
RESET,SMBUS,JTAG,DIPSW
APWRDISN TIMING CIRCUIT
EPROM ATTN_SW WAKE

IO EXPANDERS
IO EXPANDER LEDS

D

CC

10
11
12
13
14
15
16
17

A

HOT SWAP CONTROL PORT 2/4
HOT SWAP CONTROL PORT 3/5
PES8T5A - CLOCK,SMBUS,GPIO
PES8T5A - PORT 0

PES8T5A - DOWNSTREAM PORTS
DOWNSTREAM PORT 2/3 CONNECTORS
DOWNSTREAM PORT 4/5 CONNECTORS

PES8T5A - POWER

TITLE

89HPES8T5A EVALUATION BOARD

BB

A

89EBPES8T5A

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

7

65 4

2008

3

AUTHOR

T. Tran
Tue Apr 15 14:25:57 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 1 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

12_0V

C16

10V

10V

220UF

3_3V

C28

C29

0.1UF

0.1UF

C31

C32

0.1UF

0.1UF

C34

0.1UF

YEL

YEL

TP2

TP3

D

C11

C10

16V

25V

22UF

330UF

EXT P/S 12V -> 3.3V

U5

PTH08T240WAH

R55

1%

VO_SEN+

Vout

VO_SEN-

GND2
GND1

10

11

2

1
9

8

Vin

Track
SYNC
TURBOTRANS
Inhibit

Vo_Adj

1.21K

6
5
7
4

3

C15

47UF

12_0V_US

W1

C113

10UF

13
14
15
16
17

18
38
3

8
2
35

37
23
22
21
20

W5

W11

YEL

TP4

C14

47UF

C C

J4

POWER CONN

+12V

GND

GND

+5V

1

12_0V_PS

2
3
4

C110

10UF

C111

10UF

C112

10UF

B B

+3.3V_pe

25
26
27
28

32

30
36

C8

25V

22UF

A A

34
31

C9

29
33

10

0.015UF

11
12

VDDPE 1.0V

VIN
VIN
VIN
VIN

AVIN

6

ENABLE
ROCP
SOFTSTART
VS0
VS1
VS2

AGND

9

PGND
PGND
PGND
PGND

COMP

1

EN5330

EAOUT

EAIN

5

4

U16

NC

VDRAIN

7

19

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

VOUT_PAD

VSENSE

XOV
XFB
POK

PGND
PGND
PGND
PGND
PGND

NC

24

12_0V

SILKSCREEN

-------------------------------------­| 12V POWER SELECT | W1 | W5 | W11 |

12_0V

12_0V

-------------------------------------­| EDGE CONNECTOR | 1-2 | 1-2 | 1-2 |

-------------------------------------­| EXTERNAL INPUT | 2-3 | 2-3 | 2-3 |

--------------------------------------

PLACE R321 NEAR LOAD

1

1%

R56

499

10V

R9

1%

R125

1K

3

2

CW

0

2K

R320

0%

1_0V_pe

0%

R321

0

+3.3V_VTT

C17

25V

22UF

3_3V

C37

C35

C36

0.1UF

0.1UF

0.1UF

25
26
27
28

32

30
36
34

C18

31
29

33

0.047UF

10
11
12

6

9

VTT 1.5V

VIN
VIN
VIN
VIN

AVIN

ENABLE
ROCP
SOFTSTART
VS0
VS1
VS2

AGND

PGND
PGND
PGND
PGND

COMP

1

DNP
DNP

EN5330

EAOUT

EAIN

5

4

+3.3V_core

C1

25V

C2

22UF

0.015UF

U6

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

VOUT_PAD

VSENSE

XOV
XFB
POK

PGND
PGND
PGND
PGND
PGND

NC

NC

VDRAIN

7

19

24

R302

DNP

NA

R303

NA

13
14
15
16
17
18
38
3

8
2
35

37
23
22
21
20

C66

VDD_CORE 1.0V

25
26
27
28

32

30
36
34
31
29

33

10
11
12

6

9

VIN
VIN
VIN
VIN

AVIN

ENABLE
ROCP
SOFTSTART
VS0
VS1
VS2

AGND

PGND
PGND
PGND
PGND

DNP

YEL

TP5

COMP

1

DNP
DNP

C27

47UF

C67
C69

EN5330

EAIN

4

10V

U1

VDRAIN

EAOUT

5

19

1%

R304

1%

R305

604 499

DNPDNP

VOUT_PAD

NC

NC

7

24

R306

NA

R307

NA

R14

1K

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

VSENSE

XOV
XFB
POK

PGND
PGND
PGND
PGND
PGND

DNP

1

CW

3

R308

NA

13
14
15
16
17
18
38
3

8
2
35

37
23
22
21
20

C80

YEL

TP1

PLACE R325 NEAR LOAD

1

1%

C7

10V

47UF

R2

499

1%

R57

R142

1K

3

2

CW

2K

DNP
DNP

C87
C89

1_5V_vtt

DNP

R309

NA

+3.3V_pea

0

R324

0%

1_0V_core

0%

R325

0

DISTRIBUTE EVENLY AROUND BOARD

TP9

WHT

TP11

WHT

YEL

TP7

TP24

WHT

TP6

WHT

1_0V_pea

VDDPEA 1.0V

0%

R323

0

R322

0

2

0%

C30

16V

10UF

C33

0.015UF

25
26
27
28

32

30
36
34
31
29

33

10
11
12

6

9

VIN
VIN
VIN
VIN

AVIN

ENABLE
ROCP
SOFTSTART
VS0
VS1
VS2

AGND

PGND
PGND
PGND
PGND

TITLE

U7

EN5330

VOUT_PAD

NC

NC

VDRAIN

EAOUT

EAIN

COMP

1

7

5

4

19

24

DNP
DNP

R310

NA

R311

NA

89EBPES8T5A

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

VSENSE

XOV
XFB
POK

PGND
PGND
PGND
PGND
PGND

DNP

13
14
15
16
17
18
38
3

8
2
35

37
23
22
21
20

C91

C38

10V

47UF

DNP
DNP

PLACE R327 NEAR LOADPLACE R323 NEAR LOAD

1%

R15

499

1%

R16

2K

C93
C97

1

R145

1K

3

DNP

0%

R327

2

CW

R312

NA

0

R326

0%

0

D

R299

DNP
DNP

NA

R300

NA

DNP

C63

DNP
DNP

C64
C65

DNP

8

R301

NA

POWER REGULATORS 8T5A

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:10 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 2 OF 17

1

REV.

1.0

3_3VAUX

7

3_3VAUX

6

+3.3V_VIO

3_3VAUX

3_3VAUX

4

+3.3V_pe

38 5

3_3VAUX

2

3_3VAUX

1

+3.3V_pea

1%

R646

1

3

D

C

MMBT3904

1

R61

Q20

B

E

23

1%

15

R648

5%

1K

Q17

4

C52

2

S2

S3

D3

D4

876

S1

TPS1101D

D1

D2

5

R647

1%

1%

R649

C683

47UF

DNP

3_3V

487

3

2

S2

S3

D3

D4

876

487

1

S1

TPS1101D

D1

D2

5

1%

R72

487

1%

R75

487

47UF

12_0V

R80

10K

1K

R81

1K

1%

1%

R85

5%

3_3VAUX

5%

R65

1K

R67

15

C

MMBT3904

1

Q24

B

E

23

5%

Q9

4

C54

DNP

1%

R45

10K

1K

10K

R58

5%

12_0V

C C

1%

1K

1%

R122

1K

R112

15

5%

C

MMBT3904

1

R93

Q22

B

E

23

1%

3_3VAUX

10K

5%

R105

1K

R111

15

C

MMBT3904

1

Q27

B

E

23

5%

4

C76

DNP

C77

DNP

Q14

4

Q15

3

2

S2

S3

D3

D4

876

3

S3

D4

876

1

S1

TPS1101D

D1

D2

5

R115

487

1

2

S1

S2

TPS1101D

D1

D2

D3

5

R117

1%

487

1%

R116

487

1%

R353

1

3

2

S2

S3

D3

D4

876

S1

TPS1101D

D1

D2

5

R129

1%

C24C25

10V

47UF47UF

1K

R128

15

C

MMBT3904

1

1%

R123

Q23

B

E

23

5%

4

C78

Q16

DNP

3_3V 3_3V

10K

12_0V

1%

R119

10K

1%

R118

487

10V

R120

1K

1%

R121

5%

3_3VAUX

5%

R124

1K

R127

15

5%

C

MMBT3904

1

Q28

B

E

23

4

C79

DNP

Q18

3

2

S2

S3

D3

D4

876

487

1

S1

TPS1101D

D1

D2

5

1%

1%

R131

487

1%

R130

R132

4871%487

C47

10V

47UF

C26

10V

47UF

1K

2008

+3.3V_VTT

TITLE

89EBPES8T5A

POWER MOSFETS FOR 3.3VAUX

SIZE

DRAWING NO.

SCH-00162

B

AUTHOR

T. Tran
Thu Apr 24 10:22:11 2008

3

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 3 OF 17

1

REV.

1.0

3_3VAUX

3_3VAUX

1%

R82

B B

1K

R70

15

5%

C

MMBT3904

1

R60

Q19

B

E

23

1%

Q10

4

C55

DNP

10K

12_0V

3_3VAUX

5%

R66

3

2

S2

S3

D3

D4

876

1

S1

TPS1101D

D1

D2

5

1%

R71

487

1%

R74

487

3_3V

C20 C19

10V 10V 10V

47UF

+3.3V_core

12_0V

1%

1

3

1%

R48 R47

A A

1K

15

R68

5%

4

Q11

10K

C

MMBT3904

1

Q25

B

E

23

C57

DNP

1%

R49

1K

R59

5%

2

S2

S3

D3

D4

876

S1

TPS1101D

D1

D2

5

1%

R73

R76

487

487

1%

C21

10V

47UF

10K

1%

R78 R77

1K

1K

3_3VAUX

1%

R92

1K

C

MMBT3904

1

1%

R83

10K

Q21

B

E

23

3_3VAUX

15

R84

5%

R91

5%

1K

R86

15

C

R79
5%

MMBT3904

1

Q26

B

E

23

C58

DNP

5%

Q12

4

4

C59

DNP

Q13

3_3VAUX

3

2

S2

S3

D3

D4

876

3

S3

D4

876

1

S1

TPS1101D

D1

D2

5

R106

487

1

2

S1

S2

TPS1101D

D1

D2

D3

5

1%

R110

487

1%

R113

487

1%

R114

487

1%

47UF47UF

3_3V

C23 C22

10V10V

1K

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

45

D

7

6

4

38 5

2

1

3_3V

C768

0.1UF

15

OUT

15

OUT

15

OUT

15

OUT

16

OUT

16

OUT

16

OUT

16

OUT

J3

CONNSMA

54
1

32

221789-3

OUT
OUT

3_3V

C762

C763

0.1UF

0.1UF

4
4

FB3

89

1189

3_3V

C764

10

10

89

10

C765

4
4

7

71189

IREFCLKP

IN

IREFCLKN

IN

P2PWRGOODN

IN

P3PWRGOODN

IN

P4PWRGOODN

IN

P5PWRGOODN

IN

3_3V

5%

R5

D

10K

OE
GND

5

5

25MHZ

IN

IN

Y1

VCC
OUT

ICS_SPREAD

ICS_FS

SG-8002CA25.0000-PCB

1

2

C C

12

3_3V 3_3V

4
3

22

C109

C3

22UF

0.1UF

R313

5%

1%

10K1%10K

25V

1%

R8R7R20

10K

13
14

15
16
17

24
25

10
20
27

1
2

6

4

ICS9FG104

CLKIN

X2
SDATA

SCLK

STOPN
SPREAD
SEL
FS2

FS1

FS0

GND0
GND1
GND2

GNDA

U8

VDD0
VDD1
VDD2

VDDA

CLK3P
CLK3N

CLK2P
CLK2N

CLK1P
CLK1N

CLK0P
CLK0N

REFOUT

IREF

3
9
21
28

7
8

11
12

19
18

23
22

5
26

10

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22

1%

R22

475

C43

C40

0.1UF

0.01UF

R23

5%

R24
R25

R26
R27

R133
R28

R29
R30

R290

5%

C41

C42

0.1UF

0.1UF

1%
1%

1%
1%

1%
1%

1%
1%

1%

1%1%1%

R291

R292

R293

49.91%49.9

49.9

C203

0.1UF

YEL

TP30

YEL

TP31

CLKREFP
CLKREFN

1%

R294

R295

R296

49.9

49.9

49.9

C210

C39

YEL

TP32

YEL

TP33

YEL

TP34

1%

1%

R314

R297

49.9

49.9

FB1

YEL

TP36

YEL

TP35

3_3V

1%

R167

10K

2

VDD
VDD
VDD

4

SRC_IN

5

SRC_IN#

6

OE0#

14

OE1#

15

OE2#

7

OE3#

43

OE4#

35

OE5#

36

OE6#

44

OE7#

27

DIFF_STOP

26

PD

28

HIGH_BW#

40

OE_INV

22

BYPASS#/PLL

23

SCLK

24

SDATA

1

SRC_DIV#

3

GND

10

GND

18

GND

U20

ICS9DB803

OE_INV=1

VDD
VDD

VDDA

DIF_0

DIF_0#

DIF_1

DIF_1#

DIF_2

DIF_2#

DIF_3

DIF_3#

DIF_4

DIF_4#

DIF_5

DIF_5#

DIF_6

DIF_6#

DIF_7

DIF_7#

LOCK
IREF

GNDA

GND
GND

11
3119
4839

8
9

12
13

16
17

20
21

30
29

34
33

38
37

42
41

45
46

47
32
25

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

475

22.1

C359

C357

0.1UF

0.1UF

R146
R147

R149
R150

R151
R152

R153

R154
R155

R156
R157

R158
R159

R161
R163

YEL

TP37

R169

1%

C361

0.1UF

R148

C363

C365

0.1UF

0.1UF

1%
1%

1%

1%
1%

1%
1%

1%
1%

1%
1%

1%
1%

1%
1%

1%

1%

1%

1%

R101

R202

R102

49.9

49.9

49.9

1%1%1%

1%

R103

R104

R107

49.9

49.9

49.9

1%

R219

R108

49.9

49.9

1%

1%

R223

R109

49.9

49.9

R227

49.91%49.9

FB2

C766

0.1UF

S2_REFCLKP
S2_REFCLKN

S3_REFCLKP
S3_REFCLKN

S4_REFCLKP
S4_REFCLKN

S5_REFCLKP
S5_REFCLKN

1%

1%

R233

R231

R235

R237

R239

49.91%49.91%49.91%49.9

B B

ICS557-06

0.1UF

0.1UF

0.1UF

0.1UF

54

VDDIN

VDDOUT

10

16

3

IN1P

4

IN1N

6

IN2P

7

IN2N

1

SEL1

8

OE

5

PDN
IREF

9

GND
GND

CLKDP
CLKDN

CLKCP
CLKCN

CLKBP
CLKBN

CLKAP
CLKAN

13
13

U_REFCLKP

IN

U_REFCLKN

IN

4

IN

4

IN

5

IN

CLKREFP
CLKREFN

ICS_SEL

DNP
DNP
475

R64
R69
R87

1%

R88

R89

A A

2
15

12
11

14
13

18
17

20
19

22.1

22.1

22.1

22.1

22.1

22.1

22.1

22.1

R182
R183

R94
R95

R96
R97

R188
R189

1%
1%

1%
1%

1%
1%

1%
1%

0.1UF

0.1UF

C104
C105

IREFCLKP
IREFCLKN

PEREFCLK0P
PEREFCLK0N

PEREFCLK1P
PEREFCLK1N

SMAOUT_CLKP
SMAOUT_CLKN

4

OUT

4

OUT

12

OUT

12

OUT
OUT

OUT

J18

CONNSMA

54

1

J19

CONNSMA

54

1

221789-3

1

32

J1

CONNSMA

221789-3

32

32

DNP

DNP

U17

1%

1%

221789-3

D

TITLE

R200

R98

R201

R203

R205

R207

R99

R100

89EBPES8T5A

CLOCKS

SIZE

49.9

49.91%49.91%49.91%49.91%49.91%49.91%49.9

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

T. Tran
Thu Apr 24 10:22:12 2008

SCH-00162

B

AUTHOR

DRAWING NO.

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 4 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

3_3V

3_3V

3_3V

3_3V

3_3V

POWER INDICATOR
PLACE NEAR TOP EDGE
LABEL 'POWER'

TP16

5%

R46

1K

3_3V

3_3V

R35

DS2

GRN 330

5%

10V

5%

R10

10K

RED

DS1

1%

R13

1K

W2

U_PERSTN

3.3

3_3V

IN

PERSTN

13

56

OUT

12 15 16

3_3V

5%

52R-459-000

J2

JTAG

1

1
3

5
7

9

9

10

11

12

13

14

TSW-107-07-T-D

2

2

43

4

65

6

87

8

10
12
1413

12

12
12

12
12

OUT
OUT

IN
OUT
OUT

DUT_JTAG_TRST_N
DUT_JTAG_TDI
DUT_JTAG_TDO
DUT_JTAG_TMS
DUT_JTAG_TCK

1K

HAMILTON JTAG

11

5%

5%

R39

R43 R42

1K

1K

D

R6

5%

BOARD RESET

5%

R1

1

10K

IN

PERSTN

13

56

C C

3_3V

S1

PB_SW

NC NO

S

2
43

1

OE*

2

A

3

GND

SN74LVC1G125

10K

2

RESINN

7

SENSE

1

CONTROL
CT

U2

5

VCC

C12

10UF

4

Y

C81

U4

TLC7733D

RESET

RESETN

VCC

GND

8
6
5
43

C13

47UF

0.1UF

3_3V

D

5%

5%

R50

LABEL
MASTER

D
C

J20

1K

R52

1K

MSMBDAT
MSMBCLK

OUT
OUT

87

78

12

12

LABEL
SLAVE

D
C

J21

5%6V5%

R51

1K

R53

1K

SSMBDAT
SSMBCLK

OUT
OUT

12

12

LABEL

PWR

D
C

DNP

J25

5%

R11

1K

5%

R12

1K

PWR_SDA
PWR_SCL

OUT
OUT

10

10

11

11

B B

3_3V

R141

3_3V

10K
10K
10K
10K
10K
10K

R134
R135
R136
R137
R138
R139

5%
5%

5%
5%
5%

5%

10K
10K 5%
10K
10K
10K 5%
10K 5%
10K

S4

S3

SILKSCREEN:

SM_SW6

1

S1A

2

S2A

3

S3A
S4A
S5A

A A

S6A

S1B
S2B
S3B
S4B
S5B
S6B

12
11

10
94
85
76

ICS_FS
ICS_SPREAD
ICS_SEL
CCLKDS
CCLKUS
MSMBSMODE

OUT
OUT
OUT
OUT
OUT
OUT

4
4
4
12
12
12

12

ICS_FS
ICS_SPREAD

ICS_SEL
CCLKDS
CCLKUS
MSMBSMODE

SM_SW8

1

S1A

2

S2A

3

S3A

4

S4A

5

S5A

6

S6A

7

S7A
S8A

S1B
S2B
S3B
S4B
S5B
S6B
S7B
S8B

16

SSMBADDR1

15

SSMBADDR2

14

SSMBADDR3

13

SSMBADDR5

12

MSMBADDR1

11

MSMBADDR2

10

MSMBADDR3

98

MSMBADDR4

R144
R160
R162
R164
R166
R168
R170

5%10K
5%

5%

5%

5%

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

SILKSCREEN:

12
12
12
12
7
7
7
12

12
12
12

SSMBADDR1
SSMBADDR2
SSMBADDR3
SSMBADDR5
MSMBADDR1
MSMBADDR2
MSMBADDR3
MSMBADDR4

1
2
3

3_3V

S5

SM_SW6

S1B

S1A

S2B

S2A

S3B

S3A

S4B

S4A

S5B

S5A

S6B

S6A

10K
10K
10K
10K
10K
10K

12

SWMODE0

11

SWMODE1

10

SWMODE2
DIP_SPARE

94

DIP_APWRDIS

85
76

RSTHALT

R171
R172
R173
R174
R175
R206

5%
5%

5%
5%
5%

5%

SILKSCREEN:

12

OUT

12

OUT

12

OUT
OUT

6

OUT

12

OUT

SWMODE0
SWMODE1
SWMODE2
SPARE
APWRDIS
RSTHALT

TITLE

89EBPES8T5A

RESET, JTAG, SMBUS, DIPSW

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:13 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 5 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

D

3_3VAUX

3_3VAUX 3_3VAUX

C50

5%

R140

C6

3_3VAUX

0.1UF

10K

OE
GND

Y2

8MHZ

VCC
OUT

4
3

SG-8002CA8.0000M-PCBB:ROHS

1

2

C C

5

IN

5

13

IN

DIP_APWRDIS

PERSTN

3_3VAUX

0.1UF

3_3VAUX

C49

22

R211

5%

3_3VAUX

C51

10

9
6

5
4
3

7
2

1

16

8

VCC GND

PE*

P3
P2
P1
P0

CEP
CET
CP

MR*

74AC161D

TC

Q3
Q2
Q1
Q0

U10

15
11

12
13
14

C53

0.1UF

513

U11

PG

NC

4

APWRDISN

OUT

12

2

B B

1%

R210

10K

C48

25V

0.1UF

513

U3

PG

2

4

NC

513

U9

PG

2

NC

0.1UF

4

D

1UF

A A

TITLE

89EBPES8T5A

APWRDISN TIMING CIRCUIT

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:13 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 6 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

3_3VAUX

5%

R37

D

10K

U19

15

IN

S2_WAKEN

1

OE*

VCC

2

A

3

GND

SN74LVC1G125

3_3VAUX 3_3VAUX

Y

3_3VAUX

C83

3_3VAUX

5%

R41

3_3VAUX

S2

YELYEL

TP39TP38

SM_SW6

1

S1A

2

0.1UF

5

15

IN

S3_WAKEN

4

10K

U14

1

OE*

2

A

3

GND

SN74LVC1G125

3_3VAUX 3_3VAUX

VCC

5

4

Y

C86

0.1UF

S2A

3

S3A
S4A
S5A
S6A

S1B
S2B
S3B
S4B
S5B
S6B

12
11
10
94
85
76

1%

1%

R315

R328

10K

10K

1%

1%

R330

R329

R331

10K

10K1%10K

1%

R332

10K

P3PWRGOODN

P2MRLIN
P3MRLIN
P4MRLIN
P5MRLIN

P2PWRGOODN

3_3V

OUT
OUT
OUT
OUT
OUT
OUT

11 4 8 9
89
89
89
89

489

10

C C

5%

16

IN

S4_WAKEN

R232

10K

1

OE*

2

A

3

GND

SN74LVC1G125

U12

VCC

C82

0.1UF

5

16

4

Y

IN

S5_WAKEN

5%

R234

10K

1

OE*

2

A

3

GND

SN74LVC1G125

U15

VCC

Y

C85

0.1UF

1%

1%

R317

3_3V

1%

R318

5

4

R44

0

0%

U_WAKEN_IN

OUT

12

1%

R212

R316

D

B B

ITT_KSC201J

1

1

2

2

3_3V

PLACE EEPROM ON SOCKET

3_3V

5%

5%

R36

R38

EEPROM

U13

24LC512

2.7K

2.7K

6
5

3
2
1

SCL

VCC

SDA
A2

A1
A0

WP

GND

52-298-000

IN
IN

IN
IN
IN

MSMBCLK

MSMBDAT

MSMBADDR3
MSMBADDR2
MSMBADDR1

58

12

58

12

A A

12
12
12

5
5
5

5%

R40

8

7

SILKSCREEN:
WP

2.7K

W3

4

C84

0.1UF

ITT_KSC201J

1

1

2

2

ITT_KSC201J

1

1

2

2

ITT_KSC201J

1

1

2

2

SW1

SW2

SW3

SW4

TITLE

3
4

3
4

3
4

3
4

10K

3
4

3
4

3
4

3
4

89EBPES8T5A

10K

10K

10K

P2ATTNIN

P3ATTNIN

P4ATTNIN

P5ATTNIN

OUT

OUT

OUT

OUT

89

89

89

89

EEPROM ATTN_SW WAKE MRL

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:14 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 7 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

3_3V

5%

5%

R216

R218

R222

D

2.7K

2.7K5%2.7K

12

12

587

0

0

0

IN

BI

R226
0%

R229
0%

R230
0%

MSMBCLK
MSMBDAT

C C

3_3V

5%

5%

R217

R221

R225

3_3V

C671

0.1UF

3_3V

MAX7311AUG

24

V+

21

A0

2

A1

3

A2

22

SCL

23

SDA

12

VSS

U23

P10
P11
P12
P13
P14
P15

INT_N

1%

1%1K

1%1K

1%

R586

R176

R194

R204

R214

1K

1K 1%

2K

4

P0

5

P1

6

P2

7

P3

8

P4

9

P5

10

P6

11

P7

13

P8

14

P9

15
16
17
18
19

20

1

1%1%1%

1%1%1%

P2ATTNIN
P2PRDETN

P2PWRFLTN
P2MRLIN

P2ATTNIND

P2PWRIND
P2PWREN

P2INTRLCK
P4ATTNIN
P4PRDETN
P4PWRFLTN
P4MRLIN

P4ATTNIND

P4PWRIND
P4PWREN

P4INTRLCK

IOEXP0_INTN

IN
IN
IN

IN
OUT
OUT
OUT
OUT

IN

IN

IN

IN
OUT
OUT
OUT
OUT

OUT

79

15

9

10

9

79

9
9
10

79

9578

16
10

9

79

9
9
10

8

12

3_3V

R257

2.7K

3_3V

5%

R259

2.7K

12

5%

R258

5%

R282

2.7K

DNP

12

5%

R281

5%

0

0

587

5%

R283

3_3V

R286

0%

R284

NA

R285

0%

578

IN

BI

MSMBCLK
MSMBDAT

C673

0.1UF

3_3V

MAX7311AUG

24
21

2
3

22
23

12

U46

V+

A0
A1
A2

SCL
SDA

VSS

P10
P11
P12
P13
P14
P15

INT_N

4

P0

5

P1

6

P2

7

P3

8

P4

9

P5

10

P6

11

P7

13

P8

14

P9

15
16
17
18
19
20

1

R351

R319

1K

2K

1%

P2PWRGOODN
P3PWRGOODN
P4PWRGOODN
P5PWRGOODN

IOEXP2_INTN

DNP

7

10

IN
IN
IN
IN

R348

IOEXP0_INTN

NA

R352

0

0%

GPIO4

49
71149
10

49

10

11 4 9

OUT

OUT

8

12

12

D

12

2.7K

12

2.7K

578

587

2.7K

DNP

IN

BI

0

0

R287

0%

R288

0%

R289

NA

MSMBCLK
MSMBDAT

C675

0.1UF

MAX7311AUG

24

V+

21

A0

2

A1

3

A2

22

SCL

23

SDA

12

VSS

U48

P10
P11
P12
P13
P14
P15

INT_N

1%

R590

1K

4

P0

5

P1

6

P2

7

P3

8

P4

9

P5

10

P6

11

P7

13

P8

14

P9

15
16
17
18
19

20

P0_LINKUPN

P2_LINKUPN
P3_LINKUPN
P4_LINKUPN
P5_LINKUPN

P0_ACTIVEN

P2_ACTIVEN
P3_ACTIVEN
P4_ACTIVEN
P5_ACTIVEN

OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT

9

9
9
9
9

9

9
9
9
9

1

2.7K

2.7K5%2.7K

DNP

B B

12

12

578
587

BI

0

0

IN

R253

NA

R254

0%

R256

0%

MSMBCLK
MSMBDAT

24
21

22
23

C672

12

0.1UF

U45

MAX7311AUG

V+

A0

2

A1

3

A2

SCL
SDA

VSS

INT_N

P10
P11
P12
P13
P14
P15

R349

R177

R195

R208

R220

1K

1K

1K

1K

2K

4

P0

5

P1

6

P2

7

P3

8

P4

9

P5

10

P6

11

P7

13

P8

14

P9

15
16
17
18
19

20

IOEXP1_INTN

1

P3ATTNIN
P3PRDETN

P3PWRFLTN
P3MRLIN

P3ATTNIND

P3PWRIND
P3PWREN

P3INTRLCK
P5ATTNIN
P5PRDETN
P5PWRFLTN
P5MRLIN

P5ATTNIND

P5PWRIND
P5PWREN

P5INTRLCK

DNP

R215
NA

R350

0

0%

79

IN

15

IN

11 9

IN

79

IN

9

OUT

9

OUT

11

OUT
OUT

79

IN

16

IN

11 9

IN

79

IN

9

OUT

9

OUT

11

OUT
OUT

IOEXP0_INTN

GPIO3

9

9

8

OUT

OUT

12

12

A A

TITLE

89EBPES8T5A

IO EXPANDERS

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:14 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 8 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

POWER INDICATOR LED (GREEN)

3_3V

MRL LED (RED)

3_3V

D

78

IN

8

IN

8

IN

8

IN

8

IN

P5PWRIND
P4PWRIND
P3PWRIND
P2PWRIND

150
150
150
150

R823

5%

R824

5%

R825

5%

R826

5%

DS54
DS55
DS56
DS57

GRN
GRN
GRN
GRN

PORT 5
PORT 4
PORT 3
PORT 2

78

IN

78

IN

78

IN

P5MRLIN
P4MRLIN
P3MRLIN
P2MRLIN

1K
1K
1K
1K

R126

1%

R854

1%

R855

1%

R856

1%

DS88
DS89
DS90
DS91

RED
RED
RED
RED

PORT 5
PORT 4
PORT 3
PORT 2

POWER FAULT LED (RED)

ATTENTION OUTPUT LED (AMBER)

8

C C

IN

8

IN

8

IN

8

IN

P5ATTNIND
P4ATTNIND
P3ATTNIND
P2ATTNIND

1K
1K
1K
1K

R838

1%

R839

1%

R840

1%

R841

1%

DS61
DS62
DS63
DS64

ORG
ORG
ORG
ORG

PORT 5
PORT 4
PORT 3
PORT 2

3_3V

PRESENCE DETECT LED (GREEN)

16

8

IN

16

8

IN

15

8

IN

15

8

B B

IN

P5PRDETN
P4PRDETN
P3PRDETN
P2PRDETN

150
150
150
150

R62

5%

R885

5%

R886

5%

R887

5%

DS76
DS77
DS78
DS79

GRN
GRN
GRN
GRN

PORT 5
PORT 4
PORT 3
PORT 2

118

IN

10

8

IN

118

IN

10

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

P5PWRFLTN
P4PWRFLTN
P3PWRFLTN
P2PWRFLTN

LINK UP LED (GREEN)

P5_LINKUPN

P4_LINKUPN

P3_LINKUPN

P2_LINKUPN

P0_LINKUPN

150
150
150
150

150

1K
1K
1K
1K

R143

1%

R869

1%

R870

1%

R871

1%

R165

5%

R915

5%

R916

5%

R917

5%

R919

5%

DS92
DS93
DS94
DS95

DS96
DS97
DS98
DS99

DS100

RED
RED
RED
RED

GRN
GRN
GRN
GRN

GRN

PORT 5
PORT 4
PORT 3
PORT 2

3_3V

PORT 5
PORT 4
PORT 3
PORT 2

PORT 0

D

LINK ACTIVITY LED (AMBER)

ATTENTION INPUT LED (AMBER)

78

IN

78

IN

78

IN

78

IN

P5ATTNIN
P4ATTNIN
P3ATTNIN
P2ATTNIN

1K
1K
1K
1K

R63

1%

R900

1%

R901

1%

R902

1%

DS80
DS81
DS82
DS83

ORG
ORG
ORG
ORG

3_3V

PORT 5
PORT 4
PORT 3
PORT 2

8

IN

8

IN

8

IN

8

IN

8

IN

P5_ACTIVEN

P4_ACTIVEN

P3_ACTIVEN

P2_ACTIVEN

P0_ACTIVEN

A A

1K
1K
1K
1K

1K

R298

1%

R931

1%

R932

1%

R933

1%

R935

1%

DS101
DS102
DS103
DS104

DS105

ORG
ORG
ORG
ORG

ORG

PORT 5
PORT 4
PORT 3
PORT 2

PORT 0

POWER GOOD LED (GREEN)

10

1148

IN

10

48

IN

71148

IN

7

10

48

IN

P5PWRGOODN

P4PWRGOODN

P3PWRGOODN

P2PWRGOODN

150
150
150
150

R90

5%

R947

5%

R948

5%

R949

5%

8

DS84
DS85
DS86
DS87

GRN
GRN
GRN
GRN

67

PORT 5
PORT 4
PORT 3
PORT 2

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

2008

45

3

TITLE

89EBPES8T5A

IO EXPANDER LEDS

SIZE

DRAWING NO.

SCH-00162

B

AUTHOR

T. Tran
Thu Apr 24 10:22:15 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

REV.

1.0

SHEET 9 OF 17

1

7

6

4

38 5

2

1

110K

C61

0.01UF

3_3VAUX

R240

1%

C62

0.01UF

11

26
20

35

28

45
42

44
43

39
40
41

47
48

38

18
19

30

2

9

4

7

U21

MIC2592B_2YTQ

VSTBYA
VSTBYB

RFILTERAB

CFILTERA
CFILTERB

FORCE_ONA_N
FORCE_ONB_N

AUXENA
AUXENB

ONA
ONB

A2
A1
A0

SCL
SDA

GPI_A0
GPI_B0

NC1
NC2
NC3
NC4

12VSENSEA

12VSENSEB

53R-1120-000

POWER CONTROLLER PORT 2&4

37

INT_N

15

VAUXA

5

12VINA

8

12VGATEA

12VOUTA

3VINA

3VSENSEA

3VGATEA

3VOUTA

12VINB

12VGATEB

12VOUTB

3VINB

3VSENSEB

3VGATEB

3VOUTB

VAUXB

PWRGDA_N
PWRGDB_N
FAULTA_N
FAULTB_N

GND1
GND2
GND3

3

10
12
13
14

16
32
29
34
27
25
24
23
21
22
6

31

1
36

17
33
46

15

R241

5%

15

3_3V

5%

R252

10K

5%

R255

10K

S2_3VAUX

S2_12V

S2_3V

S4_12V

S4_3V

S4_3VAUX

P2PWRGOODN
P4PWRGOODN
P2PWRFLTN
P4PWRFLTN

YEL

TP42

OUT

OUT

OUT

OUT

OUT
OUT

OUT
OUT
OUT
OUT

15

15

15

16

16
16

7489
10

489
89
89

5%

5%

5%

R251

R249

R250

C72

0.1UF

4

2%

R248

0.012

876

D4D3D2

S3S2S1

3

2

5

D1

SI4420DY

1

10K

10K

10K

2%

C68

R243

0.1UF

0.02

1

3

R242

5%

15

2

S3S2S1

D4D3D2

876

SI4435DY

D1

5

Q2

R244

5%

Q1

4

C70

2%

2%

R245

0.1UF

0.012

876

5

D4D3D2

D1

4

SI4420DY

S3S2S1

1

3

2

Q3

4

R246

15

5%

C71

0.1UF

3

2

S3S2S1

D4D3D2

876

R247

0.02

1

SI4435DY

D1

5

Q4

12_0V

3_3V

D

C116

25V

C117

10V

10UF
47UF

C60

0.1UF

3_3V

5%

5%

5%

R3R4R236

10K

10K

10K

3_3VAUX

5%10K

R337

R336

R238

10K 5%

10K 5%

C C

S6

SM_SW6

1

S1A

2

S2A

3

S3A
S4A
S5A
S6A

B B

YEL

YEL

TP41

TP40

S1B
S2B
S3B
S4B
S5B
S6B

12

S2_FORCE_ON

11

S3_FORCE_ON

10

S4_FORCE_ON

94

S5_FORCE_ON

85

P5PWRGOODN

76

P4PWRGOODN

8

IN

8

IN

511

IN

511

IN

P2PWREN
P4PWREN

PWR_SCL
PWR_SDA

10K
10K

R224

5%

R228

5%

3_3V

11

OUT

11

OUT

11 4 8 9

OUT

10

OUT

489

R782

0

R783

0

DNP
DNP
DNP

0
0
0

0.01UF = 5MS

0.1 UF = 50MS

R333
R334
R335
R786
R787
R788

D

A A

TITLE

89EBPES8T5A

HOT SWAP CONTROL PORT 2/3

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:16 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 10 OF 17

1

REV.

1.0

OUT

OUT

OUT

OUT

OUT
OUT

OUT
OUT
OUT
OUT

1

15

15

15

16

16
16

7489
10

489
89
89

3_3V

5%

R278

R279

10K

10K

5%

2

YEL

TP45

S3_3VAUX

S3_12V

S3_3V

S5_12V

S5_3V

S5_3VAUX

P3PWRGOODN
P5PWRGOODN
P3PWRFLTN
P5PWRFLTN

4

38 5

12_0V

7

3_3VAUX

3_3V

6

POWER CONTROLLER PORT 3&5

D

C4

10UF

25V

C5

47UF

10V

C73

3_3V

3_3VAUX

C108

C95

2%

R269

C99

2%

R271

C101

2%

R273

C103

2%

R274

R275

10K

R266

1%

C75

0.01UF

0.1UF

11

26
20

2

35

9

28

45
42

44
43

39
40
41

47
48

4

38

7
18
19

30

U22

MIC2592B_2YTQ

VSTBYA
VSTBYB

RFILTERAB

CFILTERA
CFILTERB

FORCE_ONA_N
FORCE_ONB_N

AUXENA
AUXENB

ONA
ONB

A2
A1
A0

SCL
SDA

GPI_A0
GPI_B0

NC1
NC2
NC3
NC4

12VSENSEA

12VSENSEB

53R-1120-000

INT_N

VAUXA

12VINA

12VGATEA

12VOUTA

3VINA

3VSENSEA

3VGATEA

3VOUTA

12VINB

12VGATEB

12VOUTB

3VINB

3VSENSEB

3VGATEB

3VOUTB

VAUXB

PWRGDA_N
PWRGDB_N
FAULTA_N
FAULTB_N

GND1
GND2
GND3

37
15
5
8
3
10
12
13
14
16
32
29
34
27
25
24
23
21
22
6

31
1
36

17
33
46

15

R267

5%

15

0.012

5

D1

0.1UF

3

2

S3S2S1

D4D3D2

0.1UF

0.1UF

0.02

1

3

15

S3S2S1

D4D3D2

876

R268

5%

2

SI4435DY

5

R270

5%

D1

876

Q6

4

D4D3D2

S3S2S1

3

2

SI4420DY

1

Q7

4

Q5

4

876

R272

15

5%

0.1UF
5%

5%

5%

5%

5%

5%

R342

R341

R262

R263

R264

R265

10K

10K

110K

10K

10K

10K

10K

C C

10

IN

10

IN

8

IN

8

IN

B B

5

10

IN

5

10

IN

TP44

YEL

TP43

YEL

S3_FORCE_ON
S5_FORCE_ON

P3PWREN
P5PWREN

PWR_SCL
PWR_SDA

10K
10K

R260

5%

R261

5%

3_3V

R31

0

R32

0

DNP
DNP

DNP

0.01UF = 5MS

0.1 UF = 50MS

R338
R339
R340

0

R33

0

R34

0

R54

C74

0.01UF

0.02

1

SI4435DY

D1

5

Q8

4

0.1UF

0.012

876

D4D3D2

S3S2S1

3

2

5

D1

SI4420DY

1

5%

5%

R276

10K

5%

R277

10K

D

A A

TITLE

89EBPES8T5A

HOT SWAP CONTROL PORT 3/5

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:16 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 11 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

D

YELYELYELYELYELYEL

U18

89HPES8T5AXXBCG

IN
IN
IN
IN
IN
IN

IN
IN

IN
IN
IN
BI
BI

IN
IN
IN
IN
IN

MSMBADDR4
MSMBADDR3

MSMBADDR2

MSMBADDR1
MSMBCLK
MSMBDAT

MSMBSMODE

SSMBADDR5
SSMBADDR3
SSMBADDR2

SSMBADDR1

SSMBCLK

SSMBDAT

DUT_JTAG_TCK
DUT_JTAG_TDI
DUT_JTAG_TDO
DUT_JTAG_TMS
DUT_JTAG_TRST_N

5
57
57
57
578
587

5

5
5
5
5

5

5

5
5

C C

5
5
5

G1
H3
H2
H1
G2
F1

M13

F3
E2
F2
E1
D1
D2

L1
K1
J1
J3
J2

MSMBADDR_4
MSMBADDR_3
MSMBADDR_2
MSMBADDR_1
MSMBCLK
MSMBDAT

MSMBSMODE

2of7
SSMBADDR_5
SSMBADDR_3
SSMBADDR_2
SSMBADDR_1
SSMBCLK
SSMBDAT

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*

GPIO_10
GPIO_09
GPIO_08
GPIO_07
GPIO_06
GPIO_05
GPIO_04
GPIO_03
GPIO_02
GPIO_01
GPIO_00

L13
L14
K13
K14
J13
H12
J14
H13
H14
G13
F12

5%

R343

10K

3_3VAUX

R280

5%

R344

10K

5%

5%

R213

R345

10K

10K

5%

5%

R346

10K

TP47TP46TP29TP28TP27TP17

P5RSTN
P3RSTN
GPIO8
GPEN
TSTCLK1
TSTCLK0
GPIO4
GPIO3
IOEXP0_INTN
P4RSTN
P2RSTN

OUT
OUT

BI
OUT
OUT
OUT

IN

IN

IN
OUT
OUT

16
15

8
8
8
16
15

D

W15

U18

89HPES8T5AXXBCG

6

B B

IN

4

IN

4

IN

54

IN

5

IN

5

IN

1516

5

IN

5

IN

5

IN

5

IN

5

IN

7

IN

APWRDISN

PEREFCLK0P
PEREFCLK0N

ICS_FS

CCLKUS
CCLKDS

U_PERSTN
RSTHALT
SWMODE2

SWMODE1
SWMODE0

U_WAKEN_IN

C2
P1

N1

M12

C3

C10
F13
G14
D13

D14
C14

APWRDISN

REFCLKP
REFCLKN

REFCLKM

CCLKUS
CCLKDS

PERSTN

RSTHALT

SWMODE_2
SWMODE_1
SWMODE_0

WAKEN

10f7

C1

DUT_WAKEN

2.7K

U_WAKEN

OUT

13

A A

TITLE

89EBPES8T5A

PES8T5A CLOCK, SMBUS, GPIO

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:17 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 12 OF 17

1

REV.

1.0

12_0V_US

7

6

4

38 5

2

1

3_3V_US

D

3_3VAUX

12

IN

13

IN

13

IN

C C

13
13

13
13

13
13

IN
IN

IN
IN

IN
IN

U_WAKEN

U_PERN0
U_PERP0

U_PERP1
U_PERN1

U_PERP2
U_PERN2

U_PERP3
U_PERN3

C44

25V

10UF

C45

25V

6.8UF

DNP

R347
NA

PCIE_X4_EDGE

B1

+12V

B2

+12V

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDAT

B7

GND

B8

+3.3V

B9

JTAG_TRSTN

B10

3.3VAUX

B11

WAKE#

B12

RSVD

B13

GND

B14

PETP0

B15

PETN0

B16

GND

B17

PRSTN2#

B18

GND

B19

PETP1

B20

PETN1

B21

GND

B22

GND

B23

PETP2

B24

PETN2

B25

GND

B26

GND

B27

PETP3

B28

PETN3

B29

GND

B30

RSVD

B31

PRSTN2#

B32

GND

P1

PRSTN1#

+12V
+12V

GND
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

+3.3V
+3.3V

PERST#

GND

REFCLK+
REFCLK-

GND

PERP0
PERN0

GND

RSVD

GND

PERP1
PERN1

GND

GND

PERP2
PERN2

GND

GND

PERP3
PERN3

GND

RSVD

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

C46

25V

10UF

C56

25V

6.8UF

PORT 0 UPSTREAM EDGE CONNECTOR PROVIDES ALL POWER FOR BOARD

PERSTN

U_REFCLKP
U_REFCLKN

U_PETP0
U_PETN0

U_PETP1
U_PETN1

U_PETP2
U_PETN2

U_PETP3
U_PETN3

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

56

4
4

13
13

13
13

13
13

13
13

D

B B

U18

89HPES8T5AXXBCG

13
13
13
13
13
13
13
13

IN
IN
IN
IN
IN
IN
IN
IN

U_PERP0
U_PERN0
U_PERP1
U_PERN1
U_PERP2
U_PERN2
U_PERP3
U_PERN3

A13
B13

B8
A8
B7
A7
A2
B2

PE0RP00
PE0RN00
PE0RP01
PE0RN01
PE0RP02
PE0RN02
PE0RP03
PE0RN03

3of7

PE0TP00
PE0TN00
PE0TP01
PE0TN01
PE0TP02
PE0TN02
PE0TP03
PE0TN03

B11
A11
A10
B10
A5
B5
B4
A4

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF
C152

0.1UF
C153

0.1UF
C154

0.1UF
C155

C160
C161
C162
C163

U_PETP0
U_PETN0
U_PETP1
U_PETN1
U_PETP2
U_PETN2
U_PETP3
U_PETN3

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

13
13
13
13
13
13
13
13

A A

TITLE

89EBPES8T5A

PES8T5A PORT 0 EDGE CONN

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:17 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 13 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

D

U18

89HPES8T5AXXBCG

15

IN

15

15
15

16
16

16
16

IN

IN
IN

IN
IN

IN
IN

C C

S2_PERP0
S2_PERN0

S3_PERP0
S3_PERN0

S4_PERP0
S4_PERN0

S5_PERP0
S5_PERN0

P3
N3

P8
N8

N9
P9

P14
N14

PE2RP00
PE2RN00

PE3RP00
PE3RN00

PE4RP00
PE4RN00

PE5RP00
PE5RN00

4of7

PE2TP00
PE2TN00

PE3TP00
PE3TN00

PE4TP00
PE4TN00

PE5TP00
PE5TN00

N5
P5

P6
N6

P11
N11

N12
P12

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF
C88

0.1UF
C90

0.1UF
C92

0.1UF
C94

C96

C98

C100

C102

S2_PETP0
S2_PETN0

S3_PETP0
S3_PETN0

S4_PETP0
S4_PETN0

S5_PETP0
S5_PETN0

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

15
15

15
15

16
16

16
16

D

B B

A A

TITLE

89EBPES8T5A

PES8T5A DOWNSTREAM PORTS

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:18 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 14 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

W31

25V

C118

10UF

J9

3_3VAUX

W32

C119

25V

10UF

PRSTN1#

JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V

PERST#

REFCLK+
REFCLK-

PERP0
PERN0

PERP1
PERN1

PERP2
PERN2

PERP3
PERN3

12_0V

25V

+12V
+12V

GND

GND

GND

GND

RSVD

GND

GND
GND

GND
GND

GND

RSVD

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

3_3V

R199

0

0%

S2_RSTN

S2_REFCLKP
S2_REFCLKN

S2_PERP0
S2_PERN0

IN

IN
IN

OUT
OUT

15

4
4

14
14

7

OUT

14

IN

14

IN

89

OUT

1-2 : HOT-PLUG

2-3 : PC PWR

IN

IN

IN

S3_3VAUX

S3_12V

S3_3V

11

11

11

S3_WAKEN

S3_PETP0
S3_PETN0

P3PRDETN

W33

C120

C121

25V

10UF

10UF

W34

25V

W35

C122

25V

10UF

3_3VAUX

C123

25V

10UF

3_3V

5.1K

R190

12_0V

5%

3_3V

J14

PCIE_CONN_x4_OPEN_SLOT

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

+12V
+12V
RSVD
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1

3.3VAUX
WAKE#

RSVD
GND
PETP0
PETN0
GND
PRSTN2#
GND
PETP1
PETN1
GND
GND
PETP2
PETN2
GND
GND
PETP3
PETN3
GND
RSVD
PRSTN2#
GND

108051-301AC

PRSTN1#

JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V

PERST#

REFCLK+
REFCLK-

PERP0
PERN0

PERP1
PERN1

PERP2
PERN2

PERP3
PERN3

+12V
+12V

GND

GND

GND

GND

RSVD

GND

GND
GND

GND
GND

GND

RSVD

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

LABEL:
PORT 3

PCIE X4 (1)

W6

15

15

OUT

OUT

S3_RSTN

W7

S2_RSTN

R193

0

S3_RSTN

S3_REFCLKP
S3_REFCLKN

S3_PERP0
S3_PERN0

U_PERSTN

P3RSTN

U_PERSTN

P2RSTN

0%

IN

IN
IN

OUT
OUT

IN

IN

IN

IN

15

4
4

14
14

5

12

5

12

12 15 16

12 15 16

1-2 : HOT-PLUG
2-3 : PC PWR

10

S2_3VAUX

IN

W30

D

NA

S2_12V

S2_3V

C106

25V

10UF

C107

10UF

10

10

IN

IN

3_3V

R209

DNP

C C

PCIE_CONN_x4_OPEN_SLOT

B1

+12V

B2

+12V

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDAT

B7

GND

B8

+3.3V

B9

JTAG1

B10

3.3VAUX

7

OUT

B B

S2_WAKEN

14
14

IN
IN

S2_PETP0
S2_PETN0

3_3V

5.1K

5%

R196

89

OUT

P2PRDETN

B11
B12

B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

WAKE#

RSVD
GND
PETP0
PETN0
GND
PRSTN2#
GND
PETP1
PETN1
GND
GND
PETP2
PETN2
GND
GND
PETP3
PETN3
GND
RSVD
PRSTN2#
GND

108051-301AC

LABEL:

A A

PORT 2
PCIE X4 (1)

D

TITLE

89EBPES8T5A

PORT 2 AND PORT 3

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:18 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 15 OF 17

1

REV.

1.0

7

6

4

38 5

2

1

W37

C126

25V

10UF

PRSTN1#

JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V

PERST#

REFCLK+
REFCLK-

PERP0
PERN0

PERP1
PERN1

PERP2
PERN2

PERP3
PERN3

3_3VAUX

W38

25V

+12V
+12V

GND

GND

GND

GND

RSVD

GND

GND
GND

GND
GND

GND

RSVD

12_0V

C127

25V

10UF

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

3_3V

R187

0

0%

S4_RSTN

S4_REFCLKP
S4_REFCLKN

S4_PERP0
S4_PERN0

7

OUT

IN

IN
IN

OUT
OUT

S5_WAKEN

16

4
4

14
14

11

IN

11

IN

11

IN

14

IN

14

IN

89

OUT

1-2 : HOT-PLUG

2-3 : PC PWR

P5PRDETN

W39

S5_3VAUX

S5_12V

S5_3V

C128

C129

25V

S5_PETP0
S5_PETN0

3_3VAUX

W40

W50

C130

25V

25V

3_3V

5.1K

R178

12_0V

C131

25V

5%

3_3V

J17

PCIE_CONN_x4_OPEN_SLOT

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

+12V
+12V
RSVD
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1

3.3VAUX
WAKE#

RSVD
GND
PETP0
PETN0
GND
PRSTN2#
GND
PETP1
PETN1
GND
GND
PETP2
PETN2
GND
GND
PETP3
PETN3
GND
RSVD
PRSTN2#
GND

108051-301AC

PRSTN1#

JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V

PERST#

REFCLK+
REFCLK-

PERP0
PERN0

PERP1
PERN1

PERP2
PERN2

PERP3
PERN3

+12V
+12V

GND

GND

GND

GND

RSVD

GND

GND
GND

GND
GND

GND

RSVD

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

LABEL:
PORT 5

PCIE X4 (1)

W8

16

16

OUT

OUT

S5_RSTN

W9

S4_RSTN

R181

0

0%

S5_RSTN

S5_REFCLKP
S5_REFCLKN

S5_PERP0
S5_PERN0

U_PERSTN

P5RSTN

U_PERSTN

P4RSTN

IN

IN
IN

OUT
OUT

IN

IN

IN

IN

16

4
4

14
14

5

12 15 16

12

12 15 16

5

12

1-2 : HOT-PLUG

2-3 : PC PWR

10

IN

S4_3VAUX

W36

D

IN

IN

S4_12V

S4_3V

C124

25V

10UF

C125

10UF

10

10

C C

J16

PCIE_CONN_x4_OPEN_SLOT

B1

+12V

B2

+12V

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDAT

B7

GND

B8

+3.3V

B9

JTAG1

B10

3.3VAUX

B11
B12

B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

WAKE#

RSVD
GND
PETP0
PETN0
GND
PRSTN2#
GND
PETP1
PETN1
GND
GND
PETP2
PETN2
GND
GND
PETP3
PETN3
GND
RSVD
PRSTN2#
GND

108051-301AC

IN
IN

S4_WAKEN

S4_PETP0
S4_PETN0

3_3V

7

OUT

B B

14
14

5.1K

5%

R184

89

OUT

P4PRDETN

D

10UF

A A

LABEL:
PORT 4

PCIE X4 (1)

10UF

TITLE

89EBPES8T5A

10UF

10UF

PORT 4 AND PORT 5

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:19 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 16 OF 17

1

REV.

1.0

7

W23

1_5V_vtt 1_0V_pe 1_0V_core

W4

W10 W25

+3.3V_VIO

JUMPERS MUST BE POPULATED FOR NORMAL OPERATION

6

4

38 5

2

1

D

DUT_VTT

C170

DUT_VDDPE

C212

DUT_3_3V

1.0UF1.0UF1.0UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C214

C215
C216
C217
C218
C219
C220

C C

C169

C168

C171
C172
C173
C174

0.1UF

0.1UF

0.1UF

0.1UF

47UF

10V

47UF

10V

C191
C192
C193
C194

C190

C189

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C221
C222
C223
C224
C225
C226
C227
C228
C229
C230
C231
C232

47UF

10V

47UF

10V

0.1UF

0.1UF

0.1UF

0.1UF

DUT_VDDCORE

1.0UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

47UF

10V

47UF

10V

C246

C247
C248
C249
C250
C251
C252
C253
C254
C255

C243
C244

C7
C8
K3
M7
M8

U18

89HPES8T5AXXBCG

VDDAPE1
VDDAPE2
VDDAPE3
VDDAPE4
VDDAPE5

5of7

VDDPE1
VDDPE2
VDDPE3
VDDPE4

D7
D8
L7
L8

D5
D6
D9

D11

E4
E10
E13

F6

F7

F9
F10

G5

G8

H4

H6

H7
H10
H11

J4

J6

J8

J9

K5
K11

L5

L6

L9
L10

M2

M3

U18

89HPES8T5AXXBCG

VDDCORE1
VDDCORE2
VDDCORE3
VDDCORE4
VDDCORE5
VDDCORE6
VDDCORE7
VDDCORE8
VDDCORE9
VDDCORE10
VDDCORE11
VDDCORE12
VDDCORE13
VDDCORE14
VDDCORE15
VDDCORE16
VDDCORE17
VDDCORE18
VDDCORE19
VDDCORE20
VDDCORE21
VDDCORE22
VDDCORE23
VDDCORE24
VDDCORE25
VDDCORE26
VDDCORE27
VDDCORE28
VDDCORE29
VDDCORE30

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8

VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16

VTT1
VTT2
VTT3
VTT4

6of7

C12
D4
D10
E3
E12
F4
F11
G3
G12
J11
J12
K2
L4
M5
M10
M11

C6
C9
M6
M9

A1
A3
A6

A9
A12
A14

B1

B3

B6

B9
B12
B14

C4

C5
C11
C13

D3
D12

E5

E6

E7

E8

E9
E11
E14

F5

F8
F14

G4

G6

G7

G9

U18

89HPES8T5AXXBCG

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16

7of7
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32

VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64

G10
G11
H5
H8
H9
J5
J7
J10
K4
K6
K7
K8
K9
K10
K12
L2
L3
L11
L12
M1
M4
M14
N2
N4
N7
N10
N13
P2
P4
P7
P10
P13

D

B B

1_0V_pea

W24

C187

C188

A A

FB6

FB4

FB5

DUT_VDDPEA

C233

C234

C235

C236

C277

10V

47UF

C278

10V

47UF

C213

1.0UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1.0UF

TITLE

89EBPES8T5A

PES8T5A POWER

SIZE

DRAWING NO.

SCH-00162

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

T. Tran
Thu Apr 24 10:22:19 2008

2

FAB P/N

18-636-002

CHECKED BY

D. Huang

SHEET 17 OF 17

1

REV.

1.0