IDT EB4T4 Eval Board Manual
®
IDT™ 89EBPES4T4
Evaluation Board Manual
(Eval Board: 18-637-001)
August 2007
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284- 2775
©2007 Integrated Device Technology, Inc.
Printed in U.S.A.
Integrated Device Technology, Inc. reserves t h e right to make changes to its produc ts or specifications at any time, without notice, in order to improve design or perfor mance
and to supply the best possible product. IDT does not assume any responsibility for use of any circui try described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
DISCLAIMER
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analy sis be performed.
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agr eement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for su rgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly us ed in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a significant injury to the user.
2. A critical co mpo nent is an y com pon en t s of a lif e sup po rt dev ice or sy s te m who se f ai lu re t o perform can be re aso na bl y exp ect ed to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT lo go, and Integrated Device Technology are trademarks or registered trademarks of I ntegrated Device Technology, Inc.
LIFE SUPPORT POLICY
Table of Contents
®
Notes
Description of the EB4T4 Eval Board
Introduction.....................................................................................................................................1-1
Board Features...............................................................................................................................1-2
Hardware................................................................................................................................1-2
Software..................................................................................................................................1-2
Other.......................................................................................................................................1-2
Revision History..............................................................................................................................1-2
Installation of the EB4T4 Eval Board
EB4T4 Installation...........................................................................................................................2-1
Hardware Description.....................................................................................................................2-1
Host System...........................................................................................................................2-1
Reference Clocks............................................................................................................................2-1
Power Sources................................................................................................................................2-3
Vaux Support..........................................................................................................................2-3
PCI Express Serial Data Transmit Termination Voltage Converter........................................2-5
PCI Express Digital Power Voltage Converter........................................................................2-5
PCI Express Analog Power Voltage Converter......................................................................2-5
Core Logic Voltage Converter................................................................................................2-5
3.3V I/O Power Module...........................................................................................................2-5
Power-up Sequence...............................................................................................................2-5
Required Jumpers..................................................................................................................2-5
Reset...............................................................................................................................................2-5
Fundamental Reset................................................................................................................2-5
Downstream Reset.................................................................................................................2-6
Boot Configuration Vector...............................................................................................................2-6
SMBus Interfaces............................................................................................................................2-7
SMBus Master Interface.........................................................................................................2-7
Attention Buttons.............................................................................................................................2-7
Miscellaneous Jumpers, Headers...................................................................................................2-8
LEDs...............................................................................................................................................2-9
PCI Express Connectors...............................................................................................................2-10
EB4T4 Board Figure.....................................................................................................................2-12
Software for the EB4T4 Eval Board
Introduction.....................................................................................................................................3-1
Device Management Software........................................................................................................3-1
Schematics
Schematics.....................................................................................................................................4-1
EB4T4 Eval Board Manual i August 20, 2007
IDT Table of Contents
Notes
EB4T4 Eval Board Manual ii August 20, 2007
List of Tables
®
Notes
Table 2.1 Clock Source Selection .......................................................................................................2-1
Table 2.2 Spread Spectrum Clock Selection ......................................................................................2-2
Table 2.3 SMA Connectors - Onboard Reference Clock ....................................................................2-2
Table 2.4 Downstream Reset Selection .............................................................................................2-6
Table 2.5 Boot Configuration Vector Signals ......................................................................................2-6
Table 2.6 Boot Configuration Vector Switches S3 and S5 (ON=0, OFF=1) .......................................2-7
Table 2.7 JTAG Connector Pin Out ....................................................................................................2-7
Table 2.8 Attention Buttons ................................................................................................................2-8
Table 2.9 Miscellaneous Jumpers, Headers .......................................................................................2-8
Table 2.10 LED Indicators ....................................................................................................................2-9
Table 2.11 PCI Express x4 Connector Pinout ....................................................................................2-10
Table 2.12 PCI Express x1 Connector Pinout ....................................................................................2-11
EB4T4 Eval Board Manual iii August 20, 2007
IDT List of Tables
Notes
EB4T4 Eval Board Manual iv August 20, 2007
List of Figures
®
Notes
Figure 1.1 Function Block Diagram of the EB4T4 Eval Board ............................................................1-1
Figure 2.1 Clock Distribution Block Diagram .......................................................................................2-2
Figure 2.2 Power Distribution Block Diagram ......................................................................................2-3
Figure 2.3 APWRDIS# Timing ............................................................................................................2-4
Figure 2.4 APWRDIS# Timing Circuit .................................................................................................2-4
EB4T4 Eval Board Manual v August 20, 2007
IDT List of Figures
Notes
EB4T4 Eval Board Manual vi August 20, 2007
Chapter 1
Description of the EB4T4
Eval Board
®
Notes
Introduction
The 89HPES4T4 switch (also referred to as PES4T4 in this manual) is a member of IDT’s PCI Express®
standard (PCIe®) based line of products. It is an 4-lane, 4-port switch. One upstream port is provided for
connecting to the root complex (RC), and up to three downstream ports are available for connecting to PCIe
endpoints or to another switch. More information on this device can be found in the 89HPES4T4 User
Manual.
The 89EBPES4T4 Evaluation Board (also referred to as EB4T4 in this manual) provides an evaluation
platform for the PES4T4 switch. It is also a cost effective way to add a PCIe downstream port (x1) to an
existing system with a limited number of PCIe downstream ports. The EB4T4 eval board is designed to
function as an add-on card to be plugged into a x1 PCIe slot available on a motherboard hosting an appropriate root complex, microprocessor(s), and three downstream ports. The EB4T4 is a vehicle to test and
evaluate the functionality of the PES4T4 chip. Customers can use this board to get a headstart on software
development prior to the arrival of their own hardware. The EB4T4 is also used by IDT to reproduce
system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block
diagram representing the main parts of the EB4T4 board.
JTAG
Header
Clock
Fanout
SSC Clock
Buffer
25 MHz
Main
Reset
I/O Expander
PCA9555
EEPROM
24LC512
SMBUS
HEADER
x1
PCI Express
Switch
PES4T4
SMBus
PCIe x1 Upstream Edge
Figure 1.1 Function Block Diagram of the EB4T4 Eval Board
x1
x1
x1
x1
Power
Module
PTH08T240
PCIe x1 Downstream Slot
PCIe x1 Downstream Slot
PCIe x1 Downstream Slot
External Power
Connector
Voltages on board
+12V, +3.3V, +1.5V, +1.0V
EB4T4 Eval Board Manual 1 - 1 August 20, 2007
IDT Description of the EB4T4 Eval Board
Notes
Board Features
Hardware
PES4T4 PCIe 4 port switch
– Four ports (x1), 4 PCIe lanes
– PCIe Base Specification Revision 1.1 compliant
– Integrates four 2.5 Gbps embedded SerDes
– Up to 256 byte maximum Payload Size
– Automatic polarity inversion supported on all lanes
– Load configuration from an optional serial EEPROM via SMBUS
Upstream, Downstream Port
– One edge connector on the upstream port, to be plugged into a x1 slot on a host motherboard
– Three slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.
Numerous user selectable configurations set using onboard jumpers and DIP-switches
– Source of clock - host clock or onboard clock generator
– One clock rate (100 MHz) and spread spectrum setting
– Boot mode selection
Vaux Support
SMBUS Master Interface connected to the Serial EEPROMs through I/O expander
“Attention” button for each downstream port to initiate a hot swap event on each port
Four pin connector for optional external power supply
Push button for Warm Reset
Several LEDs to display status, reset, power, “Attention”, etc.
One 10-pin JTAG connector (pitch 2.54 mm x 2.54 mm)
Software
There is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES4T4 within host systems
running popular operating systems.
Installation programs
– Operating Systems Supported: Windows2000, WindowsXP, Linux
GUI based application for Windows and Linux
– Allows users to view and modify registers in the PES4T4
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.
Other
A metal bracket is required to firmly hold in place the three endpoints plugged into the EB4T4
board.
An external power supply may be required under some conditions.
SMBUS cable may be required for certain evaluation exercises.
SMA connectors are provided on the EB4T4 board for specific test points.
Revision History
August 20, 2007: Initial publication of board manual.
EB4T4 Eval Board Manual 1 - 2 August 20, 2007
Chapter 2
Installation of the EB4T4
Eval Board
®
Notes
EB4T4 Installation
This chapter discusses the steps required to configure and install the EB4T4 evaluation board. All available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.
3. Insert the evaluation board into the host system (motherboard with root complex chipset).
4. Apply power to the host system.
The EB4T4 board is shipped with all jumpers and switches configured to their default settings. In most
cases, the board does not require further modification or setup.
Hardware Description
The PES4T4 is an 4-lane, 4-port PCI Express® switch. It is a peripheral chip that performs PCI Express
based switching with a feature set optimized for high performance applications such as servers and
storage. It provides fan-out and switching functions between a PCI Express upstream port and three downstream ports or peer-to-peer switching between downstream ports.
The EB4T4 has three PCI Express downstream ports, accessible through three x4 open-ended connectors.
Basic requirements for the board to run are:
– Host system with a PCI Express root complex supporting x4 configuration through a PCI Express
– PCI Express Endpoint Cards capable of training x1 link.
x1 slot.
Host System
The evaluation board cannot be operated as a standalone unit. A host system implementing a PCI
Express root complex supporting x1 configuration through a PCI Express x1 slot is required to take full
advantage of the PES4T4’s capabilities.
Reference Clocks
The PES4T4 uses one differential reference clock (100 MHz). The EB4T4 derives this clock from a
common source which is user-selectable. The common source can be either the host system’s reference
clock or the onboard clock generator. Selection is made by resistors described in Table 2.1.
Clock Configuration R32, R53, R51, R62
Installed Clock Source
R32, R53 Onboard Reference Clock – Use onboard clock generator
R51, R62 Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection
EB4T4 Eval Board Manual 2 - 1 August 20, 2007
IDT Installation of the EB4T4 Eval Board
Notes
The source for the onboard clock is the ICS9FG104 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB4T4 allows the selection of spread spectrum settings via DIP switches as described in Table 2.2 . Spread Spectrum technology reduces peak EMI
emissions by modulating the frequency to spread the peak energy over a wider bandwidth.
Clock Spread Spectrum Switch - S3[2]
S3[2] Spread Spectrum
OFF Enable Spread Spectrum
ON Disable Spread Spectrum (Default)
Table 2.2 Spread Spectrum Clock Selection
If the Clock Spread Spectrum is used to modulate data rate, then both ports must use same modulated
clock source. Therefore, if your system uses SSC, the on-board clock generator must be disabled and the
upstream reference clock should be used instead.
The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.3. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.
Onboard Reference Clock Output (Differential) – J3, J1
J3 Positive Reference Clock
J1 Negative Reference Clock
Table 2.3 SMA Connectors - Onboard Reference Clock
Figure 2.1 illustrates the clock distribution block diagram for the EB4T4 evaluation board.
Resistor Switch
PEREFCLK0
Upstream PEREFCLK
25MHz
ICS9DB803D
ISC9FG104
Figure 2.1 Clock Distribution Block Diagram
PEREFCLK1
Port2
Port3
Port4
SMA - J1
SMA - J3
EB4T4 Eval Board Manual 2 - 2 August 20, 2007
IDT Installation of the EB4T4 Eval Board
Notes
Power Sources
Power for the EB4T4 is generated from the 12.0V PCI Express upstream slot power or optionally from
3.3Vaux. A 12.0V to 3.3V DC-DC converter will be used to provide power to four DC-DC converters to
generate VDDcore, VDDpe, VDDpea, and VTT voltages. The 3.3V from the 12.0V converter is used to
power VDDio. When in power down mode the DC-DC converters is powered directly from 3.3Vaux through
a MOSFET switch.
Figure 2.2 Power Distribution Block Diagram
Vaux Support
Power supply support will be provided to EB4T4 from 12.0V upstream power to 3.3Vaux upstream
power when in sleep mode. The WAKE# signal direction, both an input and output will be supported by
jumper selection. The APWRDIS# signal for auxiliary power disable requires the following timing on powerup:
EB4T4 Eval Board Manual 2 - 3 a
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