IDT CPS-1848 User Manual
®
CPS-1848™ User Manual
Titl
Central Packet Switch
Formal Status
June 2, 2014
GENERAL DISCLAIMER
Integrated Device Technology, Inc. (“IDT”) reserves the right to make changes to its products or specifications at any time, without notice,
in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein other than the
circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or
otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product
performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified herein as
“reserved” or “undefined” are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising
from the future definition of such items. IDT products have not been designed, tested, or manufactured for use in, and thus are not
warranted for, applications where the failure, malfunction, or any inaccuracy in the application carries a risk of death, serious bodily injury ,
or damage to tangible property . Code examples provided herein by IDT are for illustrative purposes only and should not be relied upon for
developing applications. Any use of such code examples shall be at the user's sole risk.
Copyright ©2014 Integrated Device Technology, Inc.
The IDT logo is registered to Integrated Device Technology, Inc.
Table of Contents
o
About this Document....................................................................................................................17
Content Summary....................................................................................................................................................................................17
Additional Resources...............................................................................................................................................................................17
Document Conventions and Definitions...................................................................................................................................................17
Device Revision Information....................................................................................................................................................................18
Revision History.......................................................................................................................................................................................18
1. Device Overview...................... .................................................................................................... 23
1.1 Device Description...................................................................................................................................................................................23
1.2 Key Features ...........................................................................................................................................................................................23
1.3 Block Diagrams........................................................................................................................................................................................25
1.4 Typical Applications................................................................................................................................................................................. 26
1.4.1 Wireless Application Benefits...................................................................................................................................................26
1.4.2 Defense and Aerospace Application Benefits.......................................................................................................................... 27
1.4.3 Video and Imaging Application Benefits...................................................................................................................................27
2. RapidIO Por t s .......................... ......................... .......................... .. ......................... .. .................... 28
2.1 Overview..................................................................................................................................................................................................28
2.2 Key Features ...........................................................................................................................................................................................29
2.3 Packet Routing ........................................................................................................................................................................................30
2.3.1 Packet Routing Overview.........................................................................................................................................................30
2.3.2 Unicast Programming Model....................................................................................................................................................31
2.3.3 Multicast Programming Model..................................................................................................................................................33
2.3.4 Programming Examples...........................................................................................................................................................34
2.4 Flow Control.............................................................................................................................................................................................38
2.4.1 Transmitter- and Receiver-Controlled Flow Control Programming Model................................................................................38
2.5 Multicast Event Control Symbols.............................................................................................................................................................39
2.6 Port Reconfiguration Operations..............................................................................................................................................................39
2.6.1 Disabling IDLE2 Operation.......................................................................................................................................................40
2.7 Reset Control Symbol Processing........................................................................................................................................................... 40
2.7.1 Per-Port Reset..........................................................................................................................................................................40
2.7.2 Port Disable/Enable..................................................................................................................................................................42
2.7.3 Generating a Reset Request....................................................................................................................................................42
2.8 Hot Extraction/Insertion............................................................................................................................................................................42
2.8.1 Hot Extraction...........................................................................................................................................................................43
2.8.2 Controlled Removal/Reset........................................................................................................................................................43
2.8.3 Link Partner Insertion............................................................................................................................................................... 48
2.9 Packet Trace and Filtering.......................................................................................................................................................................53
2.9.1 Packet Trace............................................................................................................................................................................53
2.9.2 Packet Filtering.........................................................................................................................................................................57
2.10 Packet Generation and Capture..............................................................................................................................................................57
2.10.1 Packet Generation and Capture Mode Overview.....................................................................................................................58
2.10.2 Packet Generation and Capture Mode Programming Model....................................................................................................59
C
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2.11 Packet Transfer Validation and Debug.....................................................................................................................................................62
2.11.1 Overview...................................................................................................................................................................................62
2.11.2 Successful Packet Transfer...................................................................................................................................................... 63
2.11.3 Switch Cannot Accept Packets.................................................................................................................................................63
2.11.4 Switch Is Not Routing Packets Correctly..................................................................................................................................65
2.11.5 Switch Cannot Transmit Packets..............................................................................................................................................66
2.11.6 Requesting Debug Assistance.................................................................................................................................................68
3. RapidIO Lanes ............................................................................................................................. 69
3.1 Lane to Port Mapping ..............................................................................................................................................................................70
3.2 Lane and Port Speeds.............................................................................................................................................................................73
3.2.1 Lane Speed Change Examples................................................................................................................................................73
3.3 Lane, PLL, and Port Power-Down...........................................................................................................................................................75
3.4 Port and Lane Initialization Sequence.....................................................................................................................................................75
3.4.1 Signal Quality Optimization......................................................................................................................................................76
3.5 Loopback Capabilities..............................................................................................................................................................................82
3.5.1 Lane Loopback Modes.............................................................................................................................................................83
3.5.2 Port Loopback Mode................................................................................................................................................................ 83
3.6 Bit Error Rate Testing...............................................................................................................................................................................84
3.6.1 PRBS Polynomials...................................................................................................................................................................84
3.6.2 User-Defined Patterns..............................................................................................................................................................84
3.6.3 PRBS Pattern Generator..........................................................................................................................................................85
3.6.4 PRBS Pattern Checker and Log (Revision C)..........................................................................................................................85
4. Switch Fabric............................................................................................................................... 87
4.1 Key Features ...........................................................................................................................................................................................87
4.2 Switch Fabric Architecture.......................................................................................................................................................................88
4.3 Input Buffer..............................................................................................................................................................................................89
4.4 Input Buffer to Crosspoint Buffer Transfers..............................................................................................................................................89
4.4.1 VoQ Fairness/Starvation Avoidance.........................................................................................................................................90
4.4.2 Multicast Packets......................................................................................................................................................................90
4.5 Crosspoint Buffers...................................................................................................................................................................................90
4.6 Crosspoint Buffer to Final Buffer Transfers..............................................................................................................................................91
4.7 Maintenance Transaction Support...........................................................................................................................................................91
4.8 Final Buffer...............................................................................................................................................................................................92
5. Performance ................................................................................................................................ 93
5.1 Overview..................................................................................................................................................................................................93
5.1.1 Throughput...............................................................................................................................................................................93
5.1.2 Latency.....................................................................................................................................................................................93
5.1.3 Latency Variation...................................................................................................................................................................... 94
5.2 Performance Monitoring...........................................................................................................................................................................94
5.2.1 Traffic Efficiency.......................................................................................................................................................................95
5.2.2 Congestion Detection...............................................................................................................................................................95
5.2.3 Resetting Performance Registers.............................................................................................................................................95
5.3 Performance Measurements....................................................................................................................................................................96
5.3.1 Buffer Management Settings....................................................................................................................................................96
5.3.2 Store-and-Forward or Cut-Through Mode................................................................................................................................98
5.3.3 Transmitter-Controlled or Receiver-Controlled Flow Control Mode..........................................................
................................98
5.4 Port-to-Port Performance Characteristics................................................................................................................................................99
5.4.1 Packet Latency Performance................................................................................................................................................... 99
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5.4.2 Packet Throughput Performance............................................................................................................................................100
5.4.3 Multicast Latency Performance..............................................................................................................................................102
5.4.4 Multicast Throughput Performance........................................................................................................................................ 102
5.4.5 Multicast-Event Control Symbol (MECS) Latency..................................................................................................................103
6. Event Management. .. .. .. ............................ .. ........................... ... ........................... ...................... 104
6.1 Event Management Overview................................................................................................................................................................104
6.1.1 Logical/Transport Layer Events Overview..............................................................................................................................108
6.1.2 Physical Layer Error Management Overview.........................................................................................................................109
6.1.3 Lane Error Management Overview..........................................................................................................................................111
6.1.4 I2C Error Management Overview............................................................................................................................................112
6.1.5 Configuration Error Management Overview............................................................................................................................113
6.2 Event Detection ......................................................................................................................................................................................113
6.2.1 Logical and Transport Layer Events........................................................................................................................................113
6.2.2 Physical Layer Events.............................................................................................................................................................115
6.2.3 Lane Events............................................................................................................................................................................124
6.2.4 I2C Events..............................................................................................................................................................................126
6.2.5 JTAG Events (Revision A/B Only).......................................................................................................................................... 126
6.2.6 Configuration Block Events.................................................................................................................................................... 127
6.2.7 Trace and Filter Events..........................................................................................................................................................127
6.2.8 Packet Generation and Capture Mode Events.......................................................................................................................127
6.2.9 Error Log Events.....................................................................................................................................................................127
6.3 Event Notification...................................................................................................................................................................................137
6.3.1 Logical Layer Events Notification........................................................................................................................................... 137
6.3.2 Physical Layer Events Notification.........................................................................................................................................139
6.3.3 Lane Event Notification...........................................................................................................................................................146
6.3.4 I2C Event Notification.............................................................................................................................................................146
6.3.5 JTAG 1149.1 Event Notification (Revision A/B Only).............................................................................................................147
6.3.6 Configuration Block Event Notification...................................................................................................................................147
6.3.7 Trace and Filter Event Notification.........................................................................................................................................147
6.3.8 Packet Generation and Capture Mode Event Notification......................................................................................................147
6.3.9 Port-Write Formats, Programming Model, and Generation....................................................................................................148
6.3.10 Interrupt Notification...............................................................................................................................................................152
6.3.11 Error Log Event Notification Programming Model..................................................................................................................152
6.4 Event Isolation.......................................................................................................................................................................................154
6.4.1 Fatal Link Response Timeout Isolation..................................................................................................................................156
6.4.2 Received Retry Count Trigger Congestion Isolation ..............................................................................................................157
6.4.3 TTL Event Isolation.................................................................................................................................................................157
6.4.4 Transmit Packet Dropped via CRC Retransmit Limit Isolation...............................................................................................157
6.4.5 Packet Received With a CRC Error While CRC Error Suppression Enabled Isolation..........................................................157
6.4.6 Software Controlled Isolation Functions.................................................................................................................................158
6.5 Event Clearing and Recovery................................................................................................................................................................ 158
6.5.1 Logical Layer Event Clearing and Handling........................................................................................................................... 158
6.5.2 Physical Layer Events Clearing and Handling........................................................................................................................159
6.5.3 Lane Event Clearing and Handling......................................................................................................................................... 167
6.5.4 I2C Event Clearing and Handling...........................................................................................................................................167
6.5.5 JTAG 1149.1 Events (Revision A/B Only)..............................................................................................................................168
6.5.6 Configuration Block Events....................................................................................................................................................168
6.5.7 Trace, Filter, and PGC Events................................................................................................................................................169
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7. I2C Interface.............................................................................................................................. 170
7.1 Overview................................................................................................................................................................................................170
7.2 Master/Slave Configuration....................................................................................................................................................................170
7.3 Temporary Master Mode........................................................................................................................................................................ 170
7.3.1 Obtaining Configuration in Master Mode................................................................................................................................171
7.3.2 Commanded Master Mode.....................................................................................................................................................171
7.3.3 Master Clock Frequency.........................................................................................................................................................171
7.3.4 EEPROM Format....................................................................................................................................................................171
7.3.5 CRC Calculation.....................................................................................................................................................................173
7.3.6 Register Map Example...........................................................................................................................................................175
7.3.7 EEPROM Format Example.....................................................................................................................................................175
7.3.8 I2C Master Mode Validation Debug........................................................................................................................................176
7.4 Slave Mode............................................................................................................................................................................................177
7.4.1 Signaling in Slave Mode.........................................................................................................................................................177
7.4.2 Connecting to Standard-, Fast-, and Hs-Mode Devices as a Slave.......................................................................................180
7.4.3 CPS-1848 Memory Access through I2C as a Slave...............................................................................................................180
8. JTAG and Boundary Scan.......................................................................................................... 183
8.1 Overview................................................................................................................................................................................................183
8.2 JTAG and AC Extest Compliance..........................................................................................................................................................183
8.3 Test Instructions.....................................................................................................................................................................................184
8.4 Device ID Register.................................................................................................................................................................................184
8.5 Initialization and Reset...........................................................................................................................................................................185
8.6 Configuration Register Access (Revision A/B).......................................................................................................................................185
8.6.1 Configuration Register Access – Writes.................................................................................................................................186
8.6.2 Configuration Register Access – Reads................................................................................................................................. 186
8.7 Configuration Register Access (Revision C).......................................................................................................................................... 187
8.7.1 Inter-Command Delay............................................................................................................................................................188
8.7.2 Configuration Register Access – Writes.................................................................................................................................190
8.7.3 Configuration Register Access – Reads................................................................................................................................. 190
8.8 JTAG Clock Constraints.........................................................................................................................................................................191
8.9 Boundary Scan......................................................................................................................................................................................191
9. Reset and Initialization ............................................................................................................. 192
9.1 Hardware Reset.....................................................................................................................................................................................192
9.1.1 Power-Up Reset.....................................................................................................................................................................192
9.1.2 Resets after Power-Up...........................................................................................................................................................192
9.2 Initialization............................................................................................................................................................................................ 193
9.2.1 I2C Initialization......................................................................................................................................................................193
9.2.2 Link Initialization.....................................................................................................................................................................193
9.2.3 Register Initialization..............................................................................................................................................................194
9.2.4 Computing Timeout Values....................................................................................................................................................195
10. Registers ................................................................................................................................... 197
10.1 Overview................................................................................................................................................................................................197
10.1.1 RapidIO Compliance..............................................................................................................................................................197
10.1.2 Interpretation of Reserved Register Bits.................................................................................................................................198
10.1.3 Backward Compatibility..........................................................................................................................................................198
10.1.4 Register Type Field Definitions...............................................................................................................................................198
10.2 Address Map..........................................................................................................................................................................................198
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10.3 RapidIO Capability Registers (CARs)....................................................................................................................................................212
10.3.1 Device Identity CAR...............................................................................................................................................................212
10.3.2 Device Information CAR.........................................................................................................................................................213
10.3.3 Assembly Identity CAR........................................................................................................................................................... 214
10.3.4 Assembly Information CAR....................................................................................................................................................214
10.3.5 Processing Element Features CAR........................................................................................................................................ 215
10.3.6 Switch Port Information CAR.................................................................................................................................................. 217
10.3.7 Source Operations CAR.........................................................................................................................................................218
10.3.8 Switch Multicast Support CAR................................................................................................................................................219
10.3.9 Switch Route Table Entries Table Limit CAR..........................................................................................................................220
10.3.10 Switch Multicast Information CAR..........................................................................................................................................221
10.4 RapidIO Control and Status Registers (CSRs)......................................................................................................................................222
10.4.1 Host Base deviceID Lock CSR............................................................................................................................................... 222
10.4.2 Component Tag CSR..............................................................................................................................................................222
10.4.3 Standard Route Table Entries Configuration destID Select CSR...........................................................................................223
10.4.4 Standard Route Table Entry Configuration Port Select CSR..................................................................................................224
10.4.5 Standard Route Table Entry Default Port CSR....................................................................................................................... 225
10.4.6 Multicast Mask Port CSR........................................................................................................................................................226
10.4.7 Multicast Association Selection CSR......................................................................................................................................227
10.4.8 Multicast Association Operations CSR................................................................................................................................... 228
10.5 LP-Serial Extended Features Registers with Software Assisted Error Recovery..................................................................................229
10.5.1 Port Maintenance Block Header Register..............................................................................................................................229
10.5.2 Port Link Timeout Control CSR..............................................................................................................................................230
10.5.3 Port General Control CSR......................................................................................................................................................230
10.5.4 Port {0..17} S-RIO Extended Features Base Addresses........................................................................................................231
10.5.5 Port {0..17} Link Maintenance Request CSR.........................................................................................................................232
10.5.6 Port {0..17} Link Maintenance Response CSR.......................................................................................................................233
10.5.7 Port {0..17} Local ackID CSR.................................................................................................................................................234
10.5.8 Port {0..17} Error and Status CSR.......................................................................................................................................... 235
10.5.9 Port {0..17} Control 1 CSR.....................................................................................................................................................238
10.5.10 Port {0..17} Control 2 CSR.....................................................................................................................................................242
10.6 Virtual Channel Extended Features Block Registers.............................................................................................................................244
10.6.1 VC Register Block Header Register.......................................................................................................................................244
10.7 Error Management Extensions Block Registers....................................................................................................................................245
10.7.1 Error Management Extensions Block Header Register..........................................................................................................245
10.7.2 Logical/Transport Layer Error Detect CSR............................................................................................................................. 246
10.7.3 Logical/Transport Layer Error Enable CSR............................................................................................................................247
10.7.4 Logical/Transport Layer deviceID Capture CSR....................................................................................................................248
10.7.5 Logical/Transport Layer Control Capture CSR....................................................................................................................... 249
10.7.6 Port-Write Target deviceID CSR.............................................................................................................................................251
10.7.7 Packet Time to Live CSR.......................................................................................................................................................252
10.7.8 Port Error Management Register Base Addresses................................................................................................................253
10.7.9 Port {0..17} Error Detect CSR.................................................................................................................................................254
10.7.10 Port {0..17} Error Rate Enable CSR.......................................................................................................................................256
10.7.11 Port {0..17} Attributes Capture CSR.......................................................................................................................................258
10.7.12 Port {0..17} Capture 0 CSR....................................................................................................................................................259
10.7.13 Port {0..17} Capture 1 CSR....................................................................................................................................................260
10.7.14 Port {0..17} Capture 2 CSR....................................................................................................................................................260
10.7.15 Port {0..17} Capture 3 CSR....................................................................................................................................................261
10.7.16 Port {0..17} Error Rate CSR...................................................................................................................................................262
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10.7.17 Port {0..17} Error Rate Threshold CSR..................................................................................................................................264
10.8 Lane Status Registers ........................................................................................................................................................................... 265
10.8.1 Lane {0..47} Status Base Addresses...................................................................................................................................... 265
10.8.2 Lane Status Block Header Register.......................................................................................................................................267
10.8.3 Lane {0..47} Status 0 CSR.....................................................................................................................................................268
10.8.4 Lane {0..47} Status 1 CSR.....................................................................................................................................................270
10.8.5 Lane {0..47} Status 2 CSR.....................................................................................................................................................272
10.8.6 Lane {0..47} Status 3 CSR.....................................................................................................................................................273
10.8.7 Lane {0..47} Status 4 CSR.....................................................................................................................................................275
10.9 IDT Specific Miscellaneous Registers....................................................................................................................................................276
10.9.1 Route Port Select Register.....................................................................................................................................................276
10.9.2 Multicast Route Select Register.............................................................................................................................................277
10.9.3 Port n Watermarks Base Addresses......................................................................................................................................278
10.9.4 Port {0..17} Watermarks Register........................................................................................................................................... 279
10.9.5 Broadcast Watermarks Register.............................................................................................................................................280
10.10 IDT Specific Event Notification Control Registers..................................................................................................................................281
10.10.1 Aux Port Error Capture Enable Register................................................................................................................................281
10.10.2 Aux Port Error Detect Register...............................................................................................................................................282
10.10.3 Configuration Block Error Capture Enable Register...............................................................................................................283
10.10.4 Configuration Block Error Detect Register..............................................................................................................................284
10.10.5 Impl. Specific Logical/Transport Layer Address Capture Register......................................................................................... 286
10.10.6 Logical/Transport Layer Error Report Enable Register...........................................................................................................287
10.10.7 Port {0..17} Error Report Enable Base Addresses.................................................................................................................288
10.10.8 Port {0..17} Error Report Enable Register..............................................................................................................................289
10.10.9 Port {0..17} Implementation Specific Error Report Enable Register.......................................................................................291
10.10.10 Broadcast Port Error Report Enable Register........................................................................................................................ 294
10.10.11 Broadcast Port Implementation Specific Error Report Enable Register.................................................................................296
10.10.12 Lane n Error Report Enable Base Addresses........................................................................................................................ 298
10.10.13 Lane {0..47} Error Report Enable Register.............................................................................................................................300
10.10.14 Broadcast Lane Error Report Enable Register.......................................................................................................................301
10.11 Packet Generation and Capture Registers............................................................................................................................................302
10.11.1 Packet Generation and Capture Base Addresses.................................................................................................................. 302
10.11.2 Port {0..17} Packet Generation and Capture Mode Configuration Register...........................................................................303
10.11.3 Port {0..17} Packet Generation and Capture Mode Data Register......................................................................................... 304
10.12 IDT Specific Routing Table Registers....................................................................................................................................................305
10.12.1 Base Addresses for IDT Specific Routing Table Registers.....................................................................................................305
10.12.2 Broadcast Device Route Table Register {0..255}...................................................................................................................306
10.12.3 Broadcast Domain Route Table Register {0..255}..................................................................................................................307
10.12.4 Port {0..17} Device Route Table Register {0..255}..................................................................................................................308
10.12.5 Port {0..17} Domain Routing Table Register {0..255}.............................................................................................................309
10.13 Trace Comparison Values and Masks Registers...................................................................................................................................310
10.13.1 Base Addresses for Trace Comparison Values and Masks Registers...................................................................................310
10.13.2 Port {0..17} Trace 0 Value 0 Register......................................................................................................................................311
10.13.3 Port {0..17} Trace 0 Value 1 Register......................................................................................................................................311
10.13.4 Port {0..17} Trace 0 Value 2 Register..................................................................................................................................... 312
10.13.5 Port {0..17} Trace 0 Value 3 Register..................................................................................................................................... 312
10.13.6 Port {0..17} Trace 0 Value 4 Register..................................................................................................................................... 313
10.13.7 Port {0..17} Trace 0 Mask 0 Register.....................................................................................................................................313
10.13.8 Port {0..17} Trace 0 Mask 1 Register.....................................................................................................................................314
10.13.9 Port {0..17} Trace 0 Mask 2 Register.....................................................................................................................................314
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10.13.10 Port {0..17} Trace 0 Mask 3 Register.....................................................................................................................................315
10.13.11 Port {0..17} Trace 0 Mask 4 Register.....................................................................................................................................315
10.13.12 Port {0..17} Trace 1 Value 0 Register.....................................................................................................................................316
10.13.13 Port {0..17} Trace 1 Value 1 Register.....................................................................................................................................316
10.13.14 Port {0..17} Trace 1 Value 2 Register.....................................................................................................................................317
10.13.15 Port {0..17} Trace 1 Value 3 Register.....................................................................................................................................317
10.13.16 Port {0..17} Trace 1 Value 4 Register.....................................................................................................................................318
10.13.17 Port {0..17} Trace 1 Mask 0 Register.....................................................................................................................................318
10.13.18 Port {0..17} Trace 1 Mask 1 Register.....................................................................................................................................319
10.13.19 Port {0..17} Trace 1 Mask 2 Register.....................................................................................................................................319
10.13.20 Port {0..17} Trace 1 Mask 3 Register.....................................................................................................................................320
10.13.21 Port {0..17} Trace 1 Mask 4 Register.....................................................................................................................................320
10.13.22 Port {0..17} Trace 2 Value 0 Register.....................................................................................................................................321
10.13.23 Port {0..17} Trace 2 Value 1 Register.....................................................................................................................................321
10.13.24 Port {0..17} Trace 2 Value 2 Register.....................................................................................................................................322
10.13.25 Port {0..17} Trace 2 Value 3 Register.....................................................................................................................................322
10.13.26 Port {0..17} Trace 2 Value 4 Register.....................................................................................................................................323
10.13.27 Port {0..17} Trace 2 Mask 0 Register.....................................................................................................................................323
10.13.28 Port {0..17} Trace 2 Mask 1 Register.....................................................................................................................................324
10.13.29 Port {0..17} Trace 2 Mask 2 Register.....................................................................................................................................324
10.13.30 Port {0..17} Trace 2 Mask 3 Register.....................................................................................................................................325
10.13.31 Port {0..17} Trace 2 Mask 4 Register.....................................................................................................................................325
10.13.32 Port {0..17} Trace 3 Value 0 Register.....................................................................................................................................326
10.13.33 Port {0..17} Trace 3 Value 1 Register.....................................................................................................................................326
10.13.34 Port {0..17} Trace 3 Value 2 Register.....................................................................................................................................327
10.13.35 Port {0..17} Trace 3 Value 3 Register.....................................................................................................................................327
10.13.36 Port {0..17} Trace 3 Value 4 Register.....................................................................................................................................328
10.13.37 Port {0..17} Trace 3 Mask 0 Register.....................................................................................................................................328
10.13.38 Port {0..17} Trace 3 Mask 1 Register.....................................................................................................................................329
10.13.39 Port {0..17} Trace 3 Mask 2 Register.....................................................................................................................................329
10.13.40 Port {0..17} Trace 3 Mask 3 Register.....................................................................................................................................330
10.13.41 Port {0..17} Trace 3 Mask 4 Register.....................................................................................................................................330
10.13.42 Broadcast Trace 0 Value 0 Register.......................................................................................................................................331
10.13.43 Broadcast Trace 0 Value 1 Register.......................................................................................................................................331
10.13.44 Broadcast Trace 0 Value 2 Register.......................................................................................................................................332
10.13.45 Broadcast Trace 0 Value 3 Register.......................................................................................................................................332
10.13.46 Broadcast Trace 0 Value 4 Register.......................................................................................................................................333
10.13.47 Broadcast Trace 0 Mask 0 Register.......................................................................................................................................333
10.13.48 Broadcast Trace 0 Mask 1 Register.......................................................................................................................................334
10.13.49 Broadcast Trace 0 Mask 2 Register.......................................................................................................................................334
10.13.50 Broadcast Trace 0 Mask 3 Register.......................................................................................................................................335
10.13.51 Broadcast Trace 0 Mask 4 Register.......................................................................................................................................335
10.13.52 Broadcast Trace 1 Value 0 Register.......................................................................................................................................336
10.13.53 Broadcast Trace 1 Value 1 Register.......................................................................................................................................336
10.13.54 Broadcast Trace 1 Value 2 Register.......................................................................................................................................337
10.13.55 Broadcast Trace 1 Value 3 Register.......................................................................................................................................337
10.13.56 Broadcast Trace 1 Value 4 Register.......................................................................................................................................338
10.13.57 Broadcast Trace 1 Mask 0 Register.......................................................................................................................................338
10.13.58 Broadcast Trace 1 Mask 1 Register.......................................................................................................................................339
10.13.59 Broadcast Trace 1 Mask 2 Register.....................................................................................
..................................................339
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10.13.60 Broadcast Trace 1 Mask 3 Register.......................................................................................................................................340
10.13.61 Broadcast Trace 1 Mask 4 Register.......................................................................................................................................340
10.13.62 Broadcast Trace 2 Value 0 Register.......................................................................................................................................341
10.13.63 Broadcast Trace 2 Value 1 Register.......................................................................................................................................341
10.13.64 Broadcast Trace 2 Value 2 Register.......................................................................................................................................342
10.13.65 Broadcast Trace 2 Value 3 Register.......................................................................................................................................342
10.13.66 Broadcast Trace 2 Value 4 Register.......................................................................................................................................343
10.13.67 Broadcast Trace 2 Mask 0 Register.......................................................................................................................................343
10.13.68 Broadcast Trace 2 Mask 1 Register.......................................................................................................................................344
10.13.69 Broadcast Trace 2 Mask 2 Register.......................................................................................................................................344
10.13.70 Broadcast Trace 2 Mask 3 Register.......................................................................................................................................345
10.13.71 Broadcast Trace 2 Mask 4 Register.......................................................................................................................................345
10.13.72 Broadcast Trace 3 Value 0 Register.......................................................................................................................................346
10.13.73 Broadcast Trace 3 Value 1 Register.......................................................................................................................................346
10.13.74 Broadcast Trace 3 Value 2 Register.......................................................................................................................................347
10.13.75 Broadcast Trace 3 Value 3 Register.......................................................................................................................................347
10.13.76 Broadcast Trace 3 Value 4 Register.......................................................................................................................................348
10.13.77 Broadcast Trace 3 Mask 0 Register.......................................................................................................................................348
10.13.78 Broadcast Trace 3 Mask 1 Register.......................................................................................................................................349
10.13.79 Broadcast Trace 3 Mask 2 Register.......................................................................................................................................349
10.13.80 Broadcast Trace 3 Mask 3 Register.......................................................................................................................................350
10.13.81 Broadcast Trace 3 Mask 4 Register.......................................................................................................................................350
10.14 Global Device Configuration Registers..................................................................................................................................................351
10.14.1 Device Control 1 Register.......................................................................................................................................................351
10.14.2 Configuration Block Error Report Register.............................................................................................................................353
10.14.3 Aux Port Error Report Enable Register..................................................................................................................................354
10.14.4 RapidIO Domain Register.......................................................................................................................................................355
10.14.5 Port-Write Control Register....................................................................................................................................................356
10.14.6 RapidIO Assembly Identification CAR Override.....................................................................................................................357
10.14.7 RapidIO Assembly Information CAR Override....................................................................................................................... 357
10.14.8 Device Soft Reset Register....................................................................................................................................................358
10.14.9 I2C Master Control Register...................................................................................................................................................358
10.14.10 I2C Master Status and Control Register ................................................................................................................................. 360
10.14.11 JTAG Control Register (Revision A/B)....................................................................................................................................361
10.14.12 External MCES Trigger Counter Register..............................................................................................................................362
10.14.13 Maintenance Dropped Packet Counter Register....................................................................................................................362
10.14.14 Switch Parameters 1 Register................................................................................................................................................363
10.14.15 Switch Parameters 2 Register................................................................................................................................................365
10.14.16 Quadrant Configuration Register............................................................................................................................................ 366
10.14.17 Device Reset and Control Register........................................................................................................................................368
10.15 Implementation Specific Multicast Mask Registers................................................................................................................................369
10.15.1 Implementation Specific Multicast Mask Base Addresses.....................................................................................................369
10.15.2 Broadcast Multicast Mask Register {0..39}............................................................................................................................. 370
10.15.3 Port {0..17} Multicast Mask Register {0..39}...........................................................................................................................371
10.16 Port Function Registers.........................................................................................................................................................................372
10.16.1 Port {0..17} Function Registers Base Addresses...................................................................................................................372
10.16.2 Port {0..17} Operations Register.............................................................................................................................................373
10.16.3 Port {0..17} Implementation Specific Error Detect Register....................................................................................................376
10.16.4 Port {0..17} Implementation Specific Error Rate Enable Register........................................................
..................................379
10.16.5 Port {0..17} VC0 Acknowledgements Transmitted Counter Register.....................................................................................382
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Table of Contents
10.16.6 Port {0..17} Not Acknowledgements Transmitted Counter Register.......................................................................................382
10.16.7 Port {0..17} VC0 Retry Symbols Transmitted Counter Register............................................................................................. 383
10.16.8 Port {0..17} VC0 Packets Transmitted Counter Register........................................................................................................383
10.16.9 Port {0..17} Trace Match Counter Value 0 Register................................................................................................................384
10.16.10 Port {0..17} Trace Match Counter Value 1 Register................................................................................................................384
10.16.11 Port {0..17} Trace Match Counter Value 2 Register................................................................................................................385
10.16.12 Port {0..17} Trace Match Counter Value 3 Register................................................................................................................385
10.16.13 Port {0..17} Filter Match Counter Value 0 Register.................................................................................................................386
10.16.14 Port {0..17} Filter Match Counter Value 1 Register.................................................................................................................386
10.16.15 Port {0..17} Filter Match Counter Value 2 Register.................................................................................................................387
10.16.16 Port {0..17} Filter Match Counter Value 3 Register.................................................................................................................387
10.16.17 Port {0..17} VC0 Acknowledgements Received Counter Register.........................................................................................388
10.16.18 Port {0..17} Not Acknowledgements Received Counter Register...........................................................................................388
10.16.19 Port {0..17} VC0 Retry Symbols Received Counter Register................................................................................................. 389
10.16.20 Port {0..17} VC0 Switch Crosspoint Buffer Output Packet Counter Register.........................................................................389
10.16.21 Port {0..17} VC0 Packets Received Counter Register............................................................................................................390
10.16.22 Port {0..17} Trace Port-Write Reset Register..........................................................................................................................391
10.16.23 Port {0..17} Lane Synchronization Register............................................................................................................................392
10.16.24 Port {0..17} VC0 Received Packets Dropped Counter Register.............................................................................................393
10.16.25 Port {0..17} VC0 Transmitted Packets Dropped Counter Register.........................................................................................394
10.16.26 Port {0..17} VC0 TTL Packets Dropped Counter Register..................................................................................................... 395
10.16.27 Port {0..17} VC0 CRC Limit Packets Dropped Counter Register........................................................................................... 395
10.16.28 Port {0..17} Congestion Retry Counter Register.....................................................................................................................396
10.16.29 Port {0..17} Status and Control Register................................................................................................................................397
10.16.30 Broadcast Port Operations Register....................................................................................................................................... 398
10.16.31 Broadcast Port Implementation Specific Error Detect Register.............................................................................................. 401
10.16.32 Broadcast Port Implementation Specific Error Rate Enable Register....................................................................................404
10.17 Implementation Specific Error Logging Registers.................................................................................................................................. 407
10.17.1 Error Log Register..................................................................................................................................................................407
10.17.2 Error Log Data Register..........................................................................................................................................................408
10.18 Special Error Registers..........................................................................................................................................................................408
10.18.1 Special Error Registers Base Addresses...............................................................................................................................408
10.18.2 Error Log Match Register {0..7}..............................................................................................................................................409
10.18.3 Error Log Match Status Register............................................................................................................................................410
10.18.4 Error Log Events Register.......................................................................................................................................................411
10.18.5 Error Log Control 2 Register...................................................................................................................................................412
10.19 PLL Registers........................................................................................................................................................................................413
10.19.1 PLL Register Base Addresses................................................................................................................................................413
10.19.2 PLL {0..11} Control 1 Register................................................................................................................................................414
10.19.3 PLL {0..11} Control 2 Register................................................................................................................................................415
10.19.4 Broadcast PLL Control Register.............................................................................................................................................416
10.20 Lane Control Registers..........................................................................................................................................................................417
10.20.1 Lane Control Base Addresses................................................................................................................................................ 417
10.20.2 Lane {0..47} Control Register.................................................................................................................................................419
10.20.3 Lane {0..47} PRBS Generator Seed Register........................................................................................................................423
10.20.4 Lane {0..47} PRBS Error Counter Register............................................................................................................................424
10.20.5 Lane {0..47} Error Detect Register.........................................................................................................................................425
10.20.6 Lane {0..47} Error Rate Enable Register................................................................................
................................................426
10.20.7 Lane {0..47} Attributes Capture Register................................................................................................................................428
10.20.8 Lane {0..47} Data Capture 0 Register....................................................................................................................................429
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Table of Contents
10.20.9 Lane {0..47} Data Capture 1 Register....................................................................................................................................429
10.20.10 Lane {0..47} DFE 1 Register...................................................................................................................................................430
10.20.11 Lane {0..47} DFE 2 Register...................................................................................................................................................432
10.20.12 Broadcast Lane Control Register...........................................................................................................................................434
10.20.13 Broadcast Lane PRBS Generator Seed Register...................................................................................................................438
10.20.14 Broadcast Lane Error Detect Register....................................................................................................................................439
10.20.15 Broadcast Lane Error Rate Enable Register..........................................................................................................................440
10.20.16 Broadcast Lane Attributes Capture Register..........................................................................................................................441
10.20.17 Broadcast Lane DFE 1 Register............................................................................................................................................. 442
10.20.18 Broadcast Lane DFE 2 Register............................................................................................................................................. 444
10.21 Error Management Broadcast Registers................................................................................................................................................445
10.21.1 Broadcast Port Error Detect Register.....................................................................................................................................445
10.21.2 Broadcast Port Error Rate Enable Register............................................................................................................................447
11. References................................................................................................................................. 449
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List of Figures
Figure 1: CPS-1848 Block Diagram...........................................................................................................................................................................25
Figure 2: CPS-1848 Interconnect Diagram................................................................................................................................................................26
Figure 3: Wireless Application....................................................................................................................................................................................26
Figure 4: Military Open VPX System Application.......................................................................................................................................................27
Figure 5: Video and Imaging Application...................................................................................................................................................................27
Figure 6: S-RIO Port Diagram.................................................................................................................................................................................... 29
Figure 7: Routing Table Flowchart.............................................................................................................................................................................30
Figure 8: Trace Criteria..............................................................................................................................................................................................53
Figure 9: Trace Function within a Port.......................................................................................................................................................................54
Figure 10: System Connectivity Test in PGC Mode – Transmitted Directly to Link Partner.........................................................................................58
Figure 11: System Testing using PGC Mode – Cabled Loopback through SerDes.....................................................................................................59
Figure 12: S-RIO Lane Block Diagram.........................................................................................................................................................................69
Figure 13: Optimizing Lane Signal Quality...................................................................................................................................................................76
Figure 14: Loopback Locations....................................................................................................................................................................................82
Figure 15: Switch Fabric Block Diagram......................................................................................................................................................................88
Figure 16: Latency Example........................................................................................................................................................................................94
Figure 17: Event Management Overview (Revision A/B)...........................................................................................................................................105
Figure 18: Event Management Overview (Revision C) .............................................................................................................................................106
Figure 19: Logical/Transport Layer Error Management Programming Model Flow Chart ....................................................................................... 108
Figure 20: Standard Physical Layer Error Management Programming Model Flow Chart .....................................................................................109
Figure 21: Implementation Specific Physical Layer Error Management Programming Model Flow Chart ...............................................................110
Figure 22: Lane Error Management Programming Model Flow Chart ......................................................................................................................111
Figure 23: I2C Error Management Programming Model Flow Chart .........................................................................................................................112
Figure 24: Configuration Error Management Programming Model Flow Chart .........................................................................................................113
Figure 25: Error Management Block Architecture......................................................................................................................................................128
Figure 26: Type 1 Port-Write Packet Data Payload Format.......................................................................................................................................149
Figure 27: Bit Transfer on the I2C Bus.......................................................................................................................................................................178
Figure 28: START and STOP Signaling.....................................................................................................................................................................178
Figure 29: Data Transfer............................................................................................................................................................................................178
Figure 30: Acknowledgment.......................................................................................................................................................................................178
Figure 31: Master Addressing a Slave with a 7-bit Address (Transfer Direction is Not Changed).............................................................................179
Figure 32: Master Reads a Slave Immediately After the First Byte........................................................................................................................... 179
Figure 33: Combined Format.....................................................................................................................................................................................179
Figure 34: Master Addresses a Slave-Receiver with 10-bit Address.........................................................................................................................179
Figure 35: Master Addresses a Slave Transmitter with 10-bit Address.....................................................................................................................179
Figure 36: Combined Format – Master Addresses a Slave with 10-bit Address........................................................................................................179
Figure 37: Combined Format – Master Transmits Data to Two Slaves, Both with 10-bit Address.............................................................................180
Figure 38: Write Protocol with 10-bit Slave Address (ADS is 1) ................................................................................................................................ 181
Figure 39: Read Protocol with 10-bit Slave Address (ADS is 1)................................................................................................................................181
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List of Figures
Figure 40: Write Protocol with 7-bit Slave Address (ADS is 0) .................................................................................................................................. 181
Figure 41: Read Protocol with 7-bit Slave Address (ADS is 0)..................................................................................................................................182
Figure 42: JTAG Write Access Timing Diagram.........................................................................................................................................................186
Figure 43: JTAG Read Access Timing Diagram.........................................................................................................................................................186
Figure 44: Inter-Command Delay............................................................................................................................................................................... 189
Figure 45: JTAG Register Access – Write Timing Diagram.......................................................................................................................................190
Figure 46: JTAG Register Access – Read Timing Diagram.......................................................................................................................................190
Figure 47: JTAG Clock Constraints............................................................................................................................................................................191
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List of Tables
Table 1: Route Table Reference Restrictions...........................................................................................................................................................31
Table 2: Unicast Programming Examples – Indirect Programming..........................................................................................................................34
Table 3: Unicast Programming Examples – Direct Programming.............................................................................................................................36
Table 4: Multicast Programming Examples – Indirect Programming Model.............................................................................................................37
Table 5: Multicast Programming Examples – Direct Programming Model................................................................................................................38
Table 6: Port Reconfiguration Operations.................................................................................................................................................................39
Table 7: Disabling IDLE2 Operation on Port 3.......................................................................................................................................................... 40
Table 8: Preparation For Hot Extraction on Port Y...................................................................................................................................................44
Table 9: Preparation For Hot Insertion on Port Y......................................................................................................................................................45
Table 10: Preparation of Port That Can be Subjected to Unexpected Hot Extraction Event......................................................................................47
Table 11: System Recovery Controller Operation, HS-LP on Port Y..........................................................................................................................49
Table 12: HS-LP Recovery Controller.........................................................................................................................................................................50
Table 13: PGC Mode Example – Connectivity Test....................................................................................................................................................59
Table 14: Success Case Packet Transfer Counters...................................................................................................................................................63
Table 15: Packet Counters and Configuration Issues – Switch Cannot Accept Packets............................................................................................63
Table 16: Configuration and Status Values to Check – Switch Cannot Accept Packets............................................................................................64
Table 17: Packet Counters and Configuration Issues – Switch Is Not Routing Packets Correctly.............................................................................65
Table 18: Packet Counters and Configuration Issues – Switch Cannot Transmit Packets.........................................................................................66
Table 19: Configuration and Status Values to Check – Switch Cannot Transmit Packets..........................................................................................67
Table 20: Lane to Port Mapping..................................................................................................................................................................................70
Table 21: PWIDTH_OVRD Examples.........................................................................................................................................................................72
Table 22: Changing Lane Speed Group on Ports 0 and 12 – Example 1...................................................................................................................73
Table 23: Changing Lane Speed on Port 5 – Example 2............................................................................................................................................74
Table 24: Configuring Bit Error Measurement............................................................................................................................................................81
Table 25: Programming Model for CPS-1848 Data Generation, Link Partner Checking............................................................................................85
Table 26: Input Buffer Allocation Mode.......................................................................................................................................................................89
Table 27: Crosspoint Buffer Allocation Mode..............................................................................................................................................................90
Table 28: Final Buffer Allocation.................................................................................................................................................................................92
Table 29: Performance Monitoring Parameters..........................................................................................................................................................95
Table 30: 4x/2x/1x Latency Numbers Under No Congestion......................................................................................................................................99
Table 31: Typical Latency from Receipt of Packet EOP to Packet Accept Issuance................................................................................................100
Table 32: 4x/2x/1x Multicast Latency Numbers Under No Congestion.....................................................................................................................102
Table 33: 4x/2x/1x Multicast-Event Control Symbol Latency Numbers....................................................................................................................103
Table 34: Event Management Enable Bits................................................................................................................................................................107
Table 35: Logical/Transport Layer Event Enable and Information Capture Summary...............................................................................................114
Table 36: Physical Layer Events Information Captured Value Descriptions..............................................................................................................115
Table 37: Physical Layer “Leaky Bucket” Events and Information Capture Summary..............................................................................................117
Table 38: Lane Event Information Captured Value Descriptions..............................................................................................................................124
Table 39: Lane Event Enable and Information Capture Summary...........................................................................................................................125
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List of Tables
Table 40: I2C Event Enable and Information Capture Summary.............................................................................................................................. 126
Table 41: JTAG Event Enable and Information Capture Summary (Revision A/B Only)..........................................................................................126
Table 42: Configuration Block Event Enable and Information Capture Summary....................................................................................................127
Table 43: Event Source Encoding............................................................................................................................................................................128
Table 44: Error Codes for Implementation Specific LT Errors..................................................................................................................................131
Table 45: Error Log Standard Port Error Encoding ................................................................................................................................................... 131
Table 46: Error Log Implementation Specific Port Error Encoding...........................................................................................................................132
Table 47: Error Log Lane Level Encoding................................................................................................................................................................135
Table 48: I2C Errors and Codes...............................................................................................................................................................................135
Table 49: JTAG Errors and Codes (Revision A/B Only)...........................................................................................................................................136
Table 50: Configuration Errors and Codes...............................................................................................................................................................136
Table 51: Trace, Filter, and PGC Mode Error Log Encoding....................................................................................................................................136
Table 52: Logical/Transport Layer Event Notification Control...................................................................................................................................138
Table 53: Physical Layer Event Notification Control.................................................................................................................................................140
Table 54: Port-Write Programming Model Registers and Fields...............................................................................................................................148
Table 55: Standard (Type 1) Port-Write Format........................................................................................................................................................149
Table 56: IDT (Type 2) Port-Write Format................................................................................................................................................................151
Table 57: Error Log Event Notification Examples.....................................................................................................................................................153
Table 58: Standard Event Isolation Behaviors.......................................................................................................................................................... 154
Table 59: Additional Packet Discard Isolation Trigger Functions..............................................................................................................................155
Table 60: Logical/Transport Layer Event Enable and Information Capture Summary..............................................................................................158
Table 61: Physical Layer Events and Information Capture Summary......................................................................................................................159
Table 62: Lane Event Clearing and Handling...........................................................................................................................................................167
Table 63: I2C Event Clearing and Handling..............................................................................................................................................................167
Table 64: JTAG Event Clearing and Handling (Revision A/B Only)..........................................................................................................................168
Table 65: Configuration Block Event Clearing and Handling....................................................................................................................................168
Table 66: Trace, Filter, and PGC Mode Event Clearing............................................................................................................................................169
Table 67: EEPROM Register Address Map .............................................................................................................................................................. 172
Table 68: Register Map Example..............................................................................................................................................................................175
Table 69: EEPROM Format Example.......................................................................................................................................................................175
Table 70: I2C Address Pins......................................................................................................................................................................................177
Table 71: Test Instructions........................................................................................................................................................................................184
Table 72: Configuration Registers............................................................................................................................................................................185
Table 73: JTAG Configuration Register Access Command and Status Instruction..................................................................................................187
Table 74: Minimum Inter-Command Delay...............................................................................................................................................................189
Table 75: Address Map............................................................................................................................................................................................. 198
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About this Document
This document includes hardware and software information for the IDT CPS-1848 Central Packet Switch. The CPS-1848 is a
high-performance Serial RapidIO 2.1-compliant switch that supports up to 18 1x ports.
Content Summary
• Device Overview provides an overview the CPS-1848’s capabilities.
• RapidIO Ports explains the operation of the device’s S-RIO ports.
• RapidIO Lanes discusses lane to port mapping, Loopback, and PRBS functions.
• Switch Fabric describes the switch core behavior and flow control processes.
• Performance discusses the packet switching performance characteristics of the CPS-1848.
• Event Management explains the CPS-1848’s Error Management block. This block detects, filters, logs, count s, and reports
error events from all of the device’s functional blocks.
• I2C Interface describes the standard I2C bus interface used in the CPS-1848.
• JTAG and Boundary Scan describes the CPS-1848 JTAG Interface.
• Reset and Initialization provides reset and initialization steps.
• Registers provides the full memory map and complete description of the CPS-1848’s registers.
• References provides a list of specifications referred to in this manual.
Additional Resources
In addition to this user manual, which explains the functionality of the CPS-1848 and how to use the device, and the device’s
datasheet which covers all electrical specifications, there are many additional resources available. For more information,
contact IDT technical support at srio@idt.com.
Document Conventions and Definitions
This manual uses the following conventions and terms:
• To indicate signal states:
— Differential signals use the suffix “_P” to indicate the positive half of a differential pair.
— Differential signals use the suffix “_N” to indicate the negative half of a differential pair.
— Non-differential signals use the suffix “_N” to indicate an active-low state.
• To define buses, the most significant bit (MSB) is on the left and least significant bit (LSB) is on the right. No leading zeros
are included.
• To represent numerical values, either decimal, binary, or hexadecimal formats are used. The binary format is as follows:
0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows: 0xDD, where “D” represents the
hexadecimal digit(s); otherwise, it is decimal.
• Unless otherwise denoted, a byte is an 8-bit quantity; a word is a 32-bit quantity, and a double-word is an 8-byte (64-bit)
quantity. This is in accordance with RapidIO convention.
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• A bit is set when its value is 0b1. A bit is cleared when its value is 0b0.
Bit 0 Bit 7
MS Bit LS Bit
Most Signficant Byte
Address offset: 0
Bit 8 Bit 15
MS Bit LS Bit
Address Offset: 1
Bit 16 Bit 23
MS Bit LS Bit
Address offset: 2
Bit 24 Bit 31
MS Bit LS Bit
Least Signficant Byte
Address offset: 3
Big
Endian
Bit 31 Bit 24
MS Bit LS Bit
Most Signficant Byte
Address Offset: 3
Bit 23 Bit 16
MS Bit LS Bit
Address Offset: 2
Bit 15 Bit 8
MS Bit LS Bit
Address Offset: 1
Bit 7 Bit 0
MS Bit LS Bit
Least Signficant Byte
Address Offset: 0
Little
Endian
• This device follows big-endian convention (see figure). The ordering of bytes within words is called either “big endian” or
“little endian”. Big-endian systems label byte zero as the most significant (left-most) byte of a word. Little-endian systems
label byte zero as the least significant (right-most) byte of a word.
• A read-only register, bit, or field can be read but not modified.
• A sticky bit remains set after it is set by hardware until a zero is written to it. Writing a one to a sticky has no effect on its
value.
This symbol indicates important configuration information or suggestions.
This symbol indicates procedures or operating levels that ma y result in misuse or damag e
to the device.
Device Revision Inf o rmation
This document supports all device revisions of the CPS-1848. Features that are applicable to a specific revision of the device
are highlighted throughout the document (for more information, see Device Information CAR).
Revision History
June 2, 2014, Formal Manual
• Added an overview section to Packet Transfer Validation and Debug
• Added a note to PRBS Pattern Checker and Log (Revision C) (see the first note in the section)
• Updated the maintenance error information in Table 35, Table 44, Table 52, and Table 60 to align with the Logical/Transport
Layer Control Capture CSR
• Updated the first three bullets in Error Log Event Notification Programming Model to indicate that ERR_XXX_MASK should
be set to 0 to complete a comparison
• Changed the bit encoding of “4x to 1x lane 2” for Downgrade to 0b010 from 0b011 (see Table36)
• Updated the description of Logical/Transport Layer Error Detect CSR[ILL_TRAN and UNSUP_TRAN]
• Changed bit 23 to reserved in Port {0..17} Operations Register and Broad ca st Port Operat ion s Regi ste r
• Updated the description of “Maintenance Packet Received that was Too Small or Too Large” and “Maintenance Transaction
Field Error” in the table below Logical/Transport Layer Control Capture CSR
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October 24, 2013, Formal Manual
• Updated steps 2 and 5 in Table 13
• Updated the caution in VoQ Fairness/Starvation Avoidance
• Updated Input Scheduler
• Updated the second paragraph after Table 34
• Updated Figure 19
• Updated Logical and Transport Layer Events, including the addition of a note
• Updated Table 37, Table 53, Table59, Table 60, Table 61
• Added a note to Physical Layer Events Notification
• Updated Table 67
• Added a note to Error Log Event Notification Programming Model
• Updated the description of Clearing and Handling Port Fail and Port Degraded Events
• Completed other minor improvements throughout the document
July 11, 2013, Formal Manual
• Updated the Register Values in Table57 to indicate the correct reset values for the Error Log Match Register
• Updated the last example in Multicast Programming Examples – Direct Programming Model
• Completed other minor improvements throughout the document
February 7, 2013, Formal Manual
• Updated Maintenance Packet Routing
• Updated the caution in Generating a Reset Request
• Added a caution to Hot Extraction/Insertion
• Updated Switch Is Not Routing Packets Correctly
• Updated EEPROM Format Example
• Completed other minor improvements throughout the document
August 10, 2012, Formal Manual
• Changed the procedural order for checking a received PRBS sequence wit hout 8b /10b encodin g in PRBS Pattern Checker
and Log (Revision C)
• Updated the second paragraph in Alert on Trace Match
• Changed the “error rate threshold” event in Table 37 to indicate “No Information is Captured”
• Updated Event Isolation, Table 8, and Table 9 with additional information about when a port detects an OUTPUT_FAIL
condition
• Added a note to OUTPUT_PORT_EN in Port {0..17} Control 1 CSR
• Updated the introduction to Logical/Transport Layer Error Enable CSR
• Updated the description of STOP_EM in Error Log Control 2 Register
• Added a note to PRBS_MODE in Lane {0..47} Control Register
May 7, 2012, Formal Manual
• Updated Step 4 in Table 8 (Preparation For Hot Extraction on Port Y)
• Added a section on Packet Transfer Validation and Debug
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• Added a footnote to Table 7 (disabling IDLE2 operation)
• Updated User-Defined Patterns
• Added a section on 10-bit Loopback Mode Restrictions
• Added a note to Maintenance Packets with Enabled Trace Ports
• Added overview sections on error management in Event Management Overview
• Added a section on Packet Acknowledge Latency
• Updated Packet Throughput Performance
• Added a section on I2C Master Mode Validation Debug
• Added a section on Computing Time out Values
• Updated the description of the [1:1] bit setting in Table 58
• Updated the procedure for Clearing and Handling Port Fail and Port Degraded Events
• Updated Inter-Command Delay and Table 74
• Updated the description of Port {0..17} VC0 Packets Received Counter Register.COUNT
• Added cautionary notes to the following error management registers: Logical/Transport Layer Error Enable CSR,
Logical/Transport Layer Error Report Enable Register, Port {0..17} Error Report Enable Register, Port {0..17}
Implementation Specific Error Rate Enable Register, and Lane {0..47} Error Report Enable Register
• Updated Note A associated with Port {0..17} Error and Status CSR.PORT_ERR
• Updated the description of AMP_PROG_EN and NEG1_CMD in Lane {0..47} Status 3 CSR
• Updated the description of Lane {0..47} Status 3 CSR.AMP_PROG_EN
• Updated the description of TX_SYMBOL_CTL and LANE_DIS in the Lane {0..47} Control Register and Broadcast Lane
Control Register
• Changed the definition of the [20:31] fields to reserved in Lane {0..47} DFE 1 Register and Broadcast Lane DFE 1 Register
• Changed the definition of the [19:21] and [25:26] fields in the following registers to reserved: Lane {0..47} Error Report
Enable Register, Lane {0..47} Error Rate Enable Register, Broadcast Lane Error Report Enable Register, and Broadcast
Lane Error Rate Enable Register. These updates also impacted the following tables: Table 39, Table 47, and Table 62.
• Changed the definition of the [19:20] and [2 5] fields in the foll owing registers t o reserved: Lane {0..4 7} Error Detect Register
and Broadcast Lane Error Detect Register. These updates also impacted the following tables: Table 39, Table 47, and
Table 62.
• Added a note to OUTPUT_CREDIT_RSVN in the Switch Parameters 1 Register, and additional information to Switch
Parameters 2 Register
• Updated the description of SELF_MCAST_EN in Port {0..17} Opera tion s Regi st er and Broadcast Port Operations Register
February 16, 2012, Formal Manual. Updated the document to support Revision C silicon and completed numerous
improvements. Key changes include:
• Updated procedure in PRBS Pattern Checker and Log (Revision C)
. Also changed description to indicate that PRBS
Pattern Checker applies only to Revision C.
• Updated Table 41, Table 49, and Table 64 to indicate that a “JTAG incomplete write” error applies only to RevisionA/B
• Added a note to Configuration Register Access (Revision A/B) regarding the system reset sequence
• Added a note to Buffer Management Settings regarding the input buffer
• Added a new JTAG section that discusses Revision C functionality, Configuration Register Access (Revision C)
• Updated MINOR_REV and JTAG_REV in Device Information CAR
• Updated MAX_DESTID and MCAST_MASK in Switch Multicast Information CAR
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Integrated Device Technology
• Updated JTAG_ERR_EN in Aux Port Error Capture Enable Register
• Updated JTAG_ERR in Aux Port Error Detect Register
• Updated JTAG_LOG_EN in Aux Port Error Report Enable Register
• Updated JTAG Control Register (Revision A/B) to indicate it applies only to Revision A/B
• Added CC_MONITOR_STATUS, CC_MONITOR_EN, and CC_MONITOR_THRESH to Lane {0..47} Status 4 CSR
• Changed the 0b0010 setting of PRBS_MODE to in Lane {0..47} Control Register
• Added PRBS_RX_CHECKER_MODE to Lane {0..47} Control Register
• Added a note to Maintenance Dropped Packet Counter Register
• Changed the reset value of Port {0..17} Control 1 CSR[OUTPUT_PORT_EN] to 0b1
• Changed the reset value of Port {0..17} Lane Synchronization Re gister[VMIN] t o 0b001, and upd ated the defi nition of VMI N
• Added Figure18 to support Indy Revision C event management
• Added a note in Output Scheduler
• Added a note to Time to Live Events
• Added two notes to Port {0..17} Lane Synchronization Register
• Added a fourth register access to step 2 in Table 11
• Added Table 57 to indicate where events are enabled in various registers
• Added a new section on JTAG Clock Constraints
• Updated step 7 in I2C EEPROM Format
• Updated Received Retry Count Trigger Congestion Isolation
• Updated Link Initialization and Register Initialization
• Updated Port Reconfiguration Operations and Disabling IDLE2 Operation
• Updated Table 8 and Table 9 (Hot extraction)
• Updated the first note in Per-Port Reset
• Added a caution to 10-bit Loopback Mode and 8-bit Loopback Mode
• Removed the first (disable ports) and last rows (enable ports) from the tables in Lane Speed Change Examples
• Added a new paragraph (the last one) to Port and Lane Initialization Sequence
• Added a second caution to Alert on Trace Match
• Updated hot insertion/extraction procedure in Table 11 and Table 12
• Updated IMP_SPEC_ERR in Logical/Transport Layer Error Detect CSR and Logical/Transport Layer Error Enable CSR
• Updated IMP_SPEC in Logical/Transport Layer Control Capture CSR
• Added a note to Port {0..17} Link Maintenance Request CSR[CMD]
• Added a caution to Port {0..17} Local ackID CSR
• Updated COUNT in Port {0..17} VC0 Packets Received Counter Register
• Added a note to Port {0..17} VC0 Retry Symbols Transmitted Counter Register
• Added a note to Port {0..17} Link Maintenance Request CSR
• Added a caution to the beginning of Lane Speed Change Examples
• Updated Port {0..17} Error and Status CSR[PORT_UNAVL]
• Added a note to COUNT in each Counter register in Port Function Registers
• Added a note to Port {0..17} Error and Status CSR[OUTPUT_DROP]
CPS-1848 User Manual 21 June 2, 2014
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Integrated Device Technology
• Added a note to Device Reset and Control Register[RESET_TYPE]
• Updated Port {0..17} Control 2 CSR[SCRAM_DIS]
• Added a note to Lane {0..47} PRBS Generator Seed Register[PRBS_SEED]
• Added a note to Lane {0..47} Control Register[LANE_DIS]
• Added a note to Multicast Association Operations CSR[CMD]
• Added a note to Port {0..17} Operations Register[TX_FLOW_CTL_DIS]
• Added a note to Lane {0..47} Control Register[TX_RATE and RX_RATE]
• Updated bit 17 in Port {0..17} Error Detect CSR
November 1, 2011, Preliminary Manual
• Updated hot insertion/extraction procedure in Table 8, Table 10, and Table 12
• Updated JTAG_REV in the Device Information CAR to indicate multiple revision identifiers
• Completed various improvements throughout the document
October 12, 2011, Preliminary Manual. Updated the instructions for Hot Extraction/Insertion; introduced numerous
improvements to the Registers; and completed various minor changes throughout the document.
July 15, 2011, Preliminary Manual
• Added a new chapter about Performance
• Removed references to SerDes TX to RX Loopback Mode and Port Level Loopback features, and their respective register
functionality (SERDES_LPBK and PORT_LEVEL_LPBK_SWITCH_SIDE_EN fields)
• Completed other minor improvements throughout the document
February 22, 2011, Preliminary Manual
• Fixed minor errors and completed numerous improvements
November 2, 2010, Preliminary Manual
• Added a caution about JTAG register access in Configuration Register Access (Revision A/B)
• Added additional information about Port Reconfiguration Operations
• Updated Table 8, Table 9, and Table 10 in Hot Insertion/Extraction
• Added a new section, Signal Quality Optimization
• Added a second note about Port {0..17} Control 1 CSR.PWIDTH_OVRD
July 23, 2010, Preliminary Manual
• Changed the order of the PLL_SEL and PORT_SEL fi elds in the Device Reset Control Register; th e PLL and port n umbers
were incorrectly reversed in these fields
• Added a note to PWIDTH_OVRD in the Port n Control 1 CSR
• Changed the default value of RX_DFE_DIS in Lane n DFE 1 CSR to 0b1
• Added a note to MAX_DESTID in the Switch Multicast Information CAR clarifying an incorrect default value for the field
• Added the VC Register Block Header Register into the registers chapter; however, this register is not supported by the
CPS-1848.
• Added a new section called Port Reconfiguration Operations
CPS-1848 User Manual 22 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
1. Device Overview
This chapter provides an overview of the CPS-1848’s capabilities. Topics discussed include the following:
• Device Description
• Key Features
• Block Diagrams
• Typical Applications
1.1 Device Description
The CPS-1848 is a low-latency, 18 port, 48 lane, Gen2 RapidIO switch that supports a peak sustained throu ghput of 240Gbps
(see Figure 1). The switch is ideal for interconnecting Gen1 and Gen2 RapidIO endpoints, including microprocessors, DSPs,
FPGAs, ASICs, and bridges. The CPS-1848 supports port widths of 1x, 2x, and 4x, and lane speeds of 1.25, 2.5, 3.125, 5.0,
and 6.25 Gbaud. The switch supports the RapidIO long run specif ication (10 0 cm of FR4 with tw o connector s), so it i s ideal for
backplane and interchassis switching applications, as well as on-board interconnect.
All RapidIO packets that are compliant to the RapidIO Specification (Rev.2.1), Part 6: LP-Serial Physical Layer Specification
and Part 3: Common Transport Specification, are accepted and routed by the CPS-1848. Packets are scheduled based on
priority in accordance with the RapidIO specification. This includes FType 9 data streaming packets described in the RapidIO
specification, Part 10:Data Streaming Specification.
RapidIO switching supports standard RapidIO routing functionality, including unicast and up to 40 multicast groups. The
CPS-1848 exceeds the RapidIOSpecification (Rev .2.1) to support broadcast routing of packets and an innovative hierarchical
routing scheme that supports all 64K 16-bit destIDs. The CPS-184 8 supports the CRF bit to e nable flow control ba sed on eight
separate priorities. The CPS-1848’s queue aging function also ensures that high priority traffic does not starve low priority
traffic under congestion. In addition, the CPS-1848 supports a powerful packet trace and filter functionality, and a separate
routing path for maintenance packets.
The CPS-1848 is designed to support fault tolerant systems. RapidIO Specification (Rev.2.1), Part 8 “Error Management
Extensions” support is supplemented by additional implementation specific event detection and notification functionality. Fault
isolation support includes the RapidIO standard “leaky bucket” port failure handling, as well as implementation specific
functions. Hot swap is fully supported through the use of “per port”' reset capability.
In addition to the RapidIO Interface, the CPS-1848 supports JTAG 1149.1 and 1149.6 test and register access interface, as
well as I2C master and slave access.
1.2 Key Features
• RapidIO Interfaces
— Up to 18 RapidIO Specification (Rev.2.1) compliant ports
— Up to 48 RapidIO Specification (Rev.2.1) compliant full duplex lanes, supporting 4x, 2x, and 1xports
— 1.25, 2.5, 3.125, 5, or 6.25Gbaud lane rates selectable for each port
CPS-1848 User Manual 23 June 2, 2014
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Integrated Device Technology
1. Device Overview > Key Features
— Short-, Medium-, and Long-run reach allow power to be optimized for short links while enabling connections up to 100
cm with two connectors
— Receiver- and Transmitter-Controlled Flow Control
— User-adjustable transmitter drive strength and emphasis
— User-adjustable receiver equalization
— Packet Trace: Each port can match the first 160 bits of every packet against up to four programmable values as
comparison criteria to copy the matching packet to a programmable trace port
•Switch Fabric
— Peak throughput of 240Gbps
— Cut-through and store-and-forward modes
— Non-blocking architecture for both of unicast and multicast flows
— Multicast splitting provides HOL blocking avoidance for congested multicast legs
— Per-priority buffering
— Supports eight RapidIO priorities
— Supports Multicast Event Control Symbol Receipt and Generation
— 40 Multicast masks with broadcast capability
— Global route and per-port local route modes
• Supervision, Fault Management, Congestion Management
— Compliant with RapidIO Specification (Rev.2.1), Part 8: Error Management Extensions Specification
— IDT-specific Error Handling including error event history logging and interrupt generation
— Event detect, count, watermark, threshold, data capture, and host notification capabilities
— Packet-Retry detect, count, threshold, and host notification capabilities
— Software-assisted error recovery and per-port reset support seamless hot swap and port recovery
2
C Interface
•I
— Provides I2C port for maintenance and error reporting
— Master or slave operation
— Master allows power-on configuration from external ROM
— Master mode configuration with external image compressing and checksum
• Clock and reset
— Single input reference clock
— Global hardware reset
— Software resets
• Diagnostics, Performance Monitors, and Built-in Self Tests
— BER measurement facilities including SerDes PRBS testing and protocol decode error counters
— Various loopback modes
— Memory BIST and SerDes BIST tests
— Extensive packet counters and diagnostic counters
• Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)
CPS-1848 User Manual 24 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
1. Device Overview > Block Diagrams
Lanes 0-3, 16-19, 32-35
Lanes 4-7, 20-23, 36-39
Quadrant 0 Quadrant 3
Quadrant 1 Quadrant 2
Ports 0, 4, 8, 12, 16 Ports 3, 7, 11, 15
Lanes 12-15, 28-31, 44-47
Ports 1, 5, 9, 13, 17
Lanes 8-11, 24-27, 40-43
Ports 2, 6, 10, 14
CPS-1848
RapidIO Gen2
Switch Fabric
Event Management and Maintenance
Registers
I2C Controller JTAG Controller
1.3 Block Diagrams
Figure 1 shows a high-level overview of the device. Conceptually, the CPS-1848 consists of four quadrants numbered 0 to 3.
Each quadrant consists of 12 lanes that can be mapped to four or five ports. Each quadrant can have combinations of 1x, 2x,
and 4x ports (for more information, see Lane to Port Mapping).
The ports are connected through a non-blocking switch fabric. The ports and switch fabric support a separate routing path for
2
maintenance packets which provides register access from any RapidIO p ort. In addition, the I
C Interface and the JTAG 1 149.1
Interface also support access to the CPS-1848's registers. Figure 1 is expanded upon in the following chapters as more
information is provided about the device’s lanes, ports, and switch fabric.
Figure 1: CPS-1848 Block Diagram
Figure 2 provides a summary of the device’s interface signals.
CPS-1848 User Manual 25 June 2, 2014
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Integrated Device Technology
1. Device Overview > Typical Applications
CPS-1848
48 Differential S-RIO Lanes
1.25, 2.5, 3.125, 5 or 6.25
Gbps
I
2
C Interface
400KHz
JTAG Interface
RST_N
REF_CLK
IRQ_N
Rext
FSEL[1:0]
QCFG[7:0]
MCAST
SPD[2:0]
FPGA or ASIC
OFDMA PHY
Processing
x4 S-RIO
x4 S-RIO
Backplane
Antenna Interface
CPRI/OBSAI
DSP S-RIO 2
DSP S-RIO 2
DSP S-RIO 2
DSP S-RIO 2
MAC Layer +
Control
Processor
x4 S-RIO
x4 S-RIO
x4 S-RIO
x4 S-RIO
x4 S-RIO
IDT Clock
156.25
MHz
CPS-1848
RapidIO Switch
Figure 2: CPS-1848 Interconnect Diagram
1.4 Typical Applications
The CPS-1848, in tandem with other RapidIO ecosystem switches and endpoints, enables next-generation compute density
and power efficiency. This significantly increases channel capacity for 3G to 4G wireless infrastructure, media gateways, video
conferencing, and military and medical imaging systems. Full peer-to-peer networking makes systems of arbitrary topology
possible.
1.4.1 Wireless Application Benefits
• Carrier-grade reliable packet transport
• Gen2 performance to power ratio allows unprecedented compute density to enable 3G and 4G systems
• Switched architecture allows highly scalable system for micro and macro BTS implementations
• Carrier-grade 6.25 Gbaud SerDes enables backplane-based modular systems and system scaling by inter-chassis cabling
• Ecosystem-standard support for four priorities plus Critical Request flow provides strong QoS support for multiple data
flows plus control plane
Figure 3: Wireless Application
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Integrated Device Technology
1. Device Overview > Typical Applications
4 x4 S-RIO
S-RIO Payload Card S-RIO x4 Switch Card
IDT Clock
156.25
MHz
CPS-1848
RapidIO
Switch
IDT Clock
156.25
MHz
FPGA
S-RIO
FPGA
S-RIO
FPGA
S-RIO
FPGA
S-RIO
FPGA
S-RIO
PowerPC
S-RIO
CPS-1848
RapidIO
Switch
CPS-1848
RapidIO
Switch
CPS-1848
RapidIO
Switch
CPS-1848
RapidIO
Switch
CPS-1848
RapidIO
Switch
CPS-1848
RapidIO
Switch
x4 S-RIO
x4 S-RIO
Backplane
CPS-1848
RapidIO Switch
IDT Clock
156.25
MHz
DSP S-RIO 2
DSP S-RIO 2
DSP S-RIO 2
DSP S-RIO 2
x4 S-RIO
x4 S-RIO
x4 S-RIO
x4 S-RIO
PCIe to
S-RIO
Bridge
1.4.2 Defense and Aerospace Application Benefits
• S-RIO Error Management Extension support including Time-to-Live enables fault-tolerant systems
• VITA 41, Open VPX, and ATCA fabric mappings enable rapid development of modular, standards-based systems
• RapidIO-standard true peer-to-peer networking allows scaling of arbitrary topology and simplifies hot swap software
implementation
• Per-port filter feature allows blocking errant packets or malicious attack (for example, denial of service, system memory
reads and writes)
Figure 4: Military Open VPX System Application
1.4.3 Video and Imaging Application Benefits
• 40 multicast masks per port provides strong support for broadcasting or multicasting a specific data stream to multiple
endpoints executing unique transforms, scaling, and CODECs
Figure 5: Video and Imaging Application
CPS-1848 User Manual 27 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
2. RapidIO Ports
This chapter describes the S-RIO port functionality of the CPS-1848. Topics discussed include the following:
• Overview
• Key Features
• Packet Routing
• Flow Control
• Multicast Event Control Symbols
• Port Reconfiguration Operations
• Reset Control Symbol Processing
• Hot Extraction/Insertion
• Packet Trace and Filtering
• Packet Generation and Capture
• Packet Transfer Validation and Debug
2.1 Overview
Each CPS-1848 S-RIO port is compliant to the RapidIOSpecification (Rev.2.1). Each port provides the S-RIO defined
Physical Coding Sublayer (PCS) functionality and the packet exchange protocol management. Each port also connects to the
associated SerDes blocks and the switch fabric block, as displayed in Figure6.
CPS-1848 User Manual 28 June 2, 2014
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Integrated Device Technology
2. RapidIO Ports > Key Features
Lanes
Ports
Lanes
Ports
Lanes
Ports
Lanes
Switch
Fabric
Registers
I2C JTAG
Ports
Quadrant
Quadrant
Quadrant
Quadrant
Lane to Port Connection
Packet
Routing
Trace &
Filter
Input Buffer
CS RX CS TX
RapidIO Flow Control
Error Mgmt
Final Buffer
S-RIO Port Block
Figure 6: S-RIO Port Diagram
Figure 6 shows a block diagram of an S-RIO Port Block. The key components of this port diagram are discussed throughout
the chapter.
2.2 Key Features
The S-RIO Block supports the following:
• 8b/10b codec
• Data scrambling/descrambling
• Lane/Link initialization management
• Control symbol generation
• Control symbol reception/decode
• IDLE sequence generation/control
• Receiver- and transmitter-controlled flow control
• S-RIO-based reset support
• Packet retransmission management
• Link maintenance and software-assisted error recovery
• Packet transmission cancellation
• Link error detection and recovery
• Packet forwarding
• IDT-specifi c pac ke t trace and filtering
This functionality is compliant to the following S-RIO specifications:
• RapidIO Specification (Rev.2.1), Part 1: Input/Output Logical Specification
• RapidIO Specification (Rev. 2.1), Part 2: Message Passing Logical Specification
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Integrated Device Technology
2. RapidIO Ports > Packet Routing
8-bit destID?
Yes
destID[15:8]
matches
RIO_DOMAIN
Use Device Route
(Value 0xDD)
Yes
destID In
DOMAIN ROUTE
Use destID[15:8] to
Index Domain Routing
Table
DEVICE ROUTE
Use destID[7:0] to
Index Local Routing
Table
Drop Packet
(0xDF)
RTE_
DEFAULT_
PORT_
CSR
Multicast
Mask
(0x40-0x67)
Send Packet
to Port n
Multicast, 0xDF or Invalid
Port n
0xDE
Port n
Multicast
0xDF
0xDF or Invalid
0xDE
P
o
r
t
n
No No
• RapidIO Specification (Rev.2.1), Part 3: Common Transport Specificat io n
• RapidIO Specification (Rev. 2.1), Part 6: LP-Serial Physical Layer Specification
• RapidIO Specification (Rev. 2.1), Part 7: System and Device Interoperability Specification
• RapidIO Specification (Rev.2.1), Part 8: Error Management Extensions Specification
• RapidIO Specification (Rev.2.1), Part 9: Flow Control Logic Layer Extensions Specification
• RapidIO Specification (Rev. 2.1), Part 11: Multicast Extensions Specification
• RapidIO Specification (Rev.2.1), Annex I: Software/System Bring Up Specification
2.3 Packet Routing
The main function of each S-RIO port is to route received packets to the appropriate port(s) on the switch. Packet routing is
supported in a RapidIO standard method usin g routing table s and standard RapidIO re gisters for mult icast functionality. Packet
routing is supplemented by implementation-specific registers for both the routing tables and for multicast. In addition, debug
features such as packet trace and filtering augment the normal packet routing.
The following sections describe routing table operation and programming, multicast operation and programming, and the
packet trace/filtering debug functionality.
2.3.1 Packet Routing Overview
Each S-RIO port provides a 256 entry Device Routing Table and a 256 entry Domain Routing Table. The scenario for the use
of the Domain and Device Routing Tables is a large system that has multiple chassis connected together, and multiple boards
in each chassis. The Domain Routing Table selects which chassis/board to route packets to, while the Device Routing Table
routes packets to a specific processing element on a board.
Figure 7: Routing Table Flowchart
CPS-1848 User Manual 30 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
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