IDT AV9173-15CS08, MK9173-01CS08, MK9173-15CS08 Schematic [ru]

DATASHEET

VIDEO GENLOCK PLL MK9173-01/-15

Description

The MK9173-01/-15 provide the analog PLL circuit blocks
to implement a frequency multiplier. Because the device is
configured to use an external divider in the PLL clock
feedback path, a large divider can be used to result in a
large frequency multiplication ratio. This is useful when
using a low frequency input clock to generate a high
frequency output clock. The MK9173-01/-15 contains a
phase detector, charge pump, loop filter, and
voltage-controlled oscillator (VCO). The ICS674-01 can be
used as the external feedback divider.

A common application of the MK9173-01/-15 is the
implementation of a video genlock circuit. Because of this,
the MK9173-01/-15 inputs operate on the negative-going
clock edge.

The MK9173-01/-15 is pin and function compatible to the
AV9173-01/15.

Block Diagram

Features

• Phase-detector/VCO circuit block

• Ideal for genlock system

• Reference clock range 12 kHz to 1 MHz for full output

clock range

• Output clock range of 1.25 to 75 MHz (-01), and 0.625 to

37.5 MHz (-15). See “Allowable Input Frequency to
Output Frequency” table for conditions

• On-chip loop filter

• Single 5 V power supply

• Low power CMOS technology

• 8-pin SOIC package

• For new video genlock applications, please refer to the

ICS673-01, ICS1522 or ICS1523.

IDT™

VIDEO GENLOCK PLL 1

MK9173-01/-15 REV C 12/21/06

MK9173-01/-15
VIDEO GENLOCK PLL CLOCK SYNTHESIZER

Pin Assignment

FBIN

IN

GND

FS0

2

3

4

8 pin SOIC

8

CLK21

VDD

7

CLK1

6

5

OE

Pin Descriptions

Pin Number Pin Name Pin Type Pin Description

1 FBIN Input Feedback input.

2 IN Input Input for reference sync pulse.

3 GND Power Ground.

4 FS0 Input Frequency select 0 input.

5 OE Input Output enable.

6 CLK1 Output Clock output 1.

7 VDD Power Power supply (+5 V).

8 CLK2 Output Clock output 2.

Allowable Input Frequency to Output Frequency for MK9173-01 (in MHz)

(MK9173-15 outputs run at exactly half of the MK9173-01 frequencies)

f

for FS = 0 f

OUT

f

(kHz)

IN

12 <

fIN < 14 kHz 44.0 to 75 22.0 to 37.5 11.0 to 18.75 5.5 to 9.375

14 < f

17 < f

30 < f

35 < f

< 17 kHz 30.0 to 75 15.0 to 37.5 7.5 to 18.75 3.75 to 9.375

IN

< 30 kHz 25.0 to 75 12.5 to 37.5 6.25 to 18.75 3.125 to 9.375

IN

< 35 kHz 15.0 to 75 7.5 to 37.5 3.75 to 18.75 1.875 to 9.375

IN

< 1000 kHz 10.0 to 75 5.0 to 37.5 2.5 to 18.75 1.25 to 9.375

IN

CLK1 Output CLK2 Output CLK1 Output CLK2 Output

for FS = 1

OUT

IDT™

VIDEO GENLOCK PLL 2

MK9173-01/-15 REV C 12/21/06

MK9173-01/-15
VIDEO GENLOCK PLL CLOCK SYNTHESIZER

Using the MK9173-01/-15 in Genlock Applications

Most video sources, such as video cameras, are
asynchronous, free-running devices. To digitize video or
synchronize one video source to another free-running
reference video source, a video “genlock” (generator lock)
circuit is required. The MK9173-01/-15 integrate the analog
blocks which make the task much easier.

In the complete video genlock circuit, the primary function of
the MK9173-01/-15 is to provide the analog circuitry
required to generate the video dot clock within a PLL. This
application is illustrated in Figure 1. The input reference
signal for this circuit is the horizontal synchronization
(H-SYNC) signal. If a composite video reference source is
being used, the h-sync pulses must be separated from the
composite signal. A video sync separator circuit, such as the
National Semiconductor LM1881, can be used for this
purpose.

The clock feedback divider shown in Figure 1 is a digital
divider used within the PLL to multiply the reference
frequency. Its divide ratio establishes how many video dot
clock cycles occur per h-sync pulse. For example, if 880
pixel clocks are desired per h-sync pulse, then the divider
ratio is set to 880. Hence, together the h-sync frequency and
external divider ratio establish the dot clock frequency:

The output hook-ups of the MK9173-01/-15 are dictated by
the desired dot clock frequency. The primary consideration
is the internal VCO which operates over a frequency range
of 10 MHz to 75 MHz. Because of the selectable VCO
output divider and the additional divider on output CLK2,
four distinct output frequency ranges can be achieved. The
following Table lists these ranges and the corresponding
device configuration.

FS0

State

Output

Used

0 CLK1 10 to 75 MHz 5 to 37.5 MHz

0 CLK2 5 to 37.5 MHz 2.5 to 18.75 MHz

1 CLK1 2.5 to 18.75 MHz 1.25 to 9.375 MHz

1 CLK2 1.25 to 9.375 MHz 0.625 to 4.6875 MHz

Frequency /Range

MK9173-01

Frequency /Range

MK9173-15

Note that both outputs, CLK1 and CLK2, are available
during operation even though only one is fed back via the
external clock divider.

Pin 5, OE, tristates both CLK1 and CLK2 upon logic low
input. This feature can be used to revert dot clock control to
the system clock when not in genlock mode (hence, when in
genlock mode the system dot clock must be tristated).

f

= fIN x N where N is external divide ratio

OUT

Both input pins IN and FBIN respond only to negative-going
clock edges of the input signal. The H-SYNC signal must be
constant frequency in the 12 kHz to 1 MHz range and stable
(low clock jitter) for creation of a stable output clock.

Figure 1: Typical Application of MK9173-01/-15 in a Video Genlock System

When unused, inputs FS0 and OE must be tied to either
GND (logic low) or VDD (logic high).

IDT™

VIDEO GENLOCK PLL 3

MK9173-01/-15 REV C 12/21/06