IDT 8A3 Programming Manual

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8A3xxxx Family Programming Guide

8A3xxxx

v4.7

How to Use this Document

The 8A3xxxx Family Programming Guide contains information on how to access internal registers and what those registers do in detail for all devices in the 8A3xxxx family. Not all devices in the family support all the same features or quantities of logic blocks, however the register blocks all behave and are addressed at the same locations in all device. Some devices will not make use of all register blocks since the associated feature or block of circuitry may not be available in that particular device. A Programming Guide Addendum for each specific device will indicate which register modules are support in that device.

In addition, there are several other pieces of documentation that describe specific functions or details for the family or individual devices.

Table 1 shows related documents.

Table 1: Related Documentation for Devices in the 8A3xxx Family

Document Title Document Description

<device name> Datasheet Contains a functional overview of the device and hardware-design related details

including pinouts, AC & DC specifications and applications information related to power filtering and terminations.

<device name>-<dash code> Datasheet Addendum Indicates pre-programmed power-up / reset configurations of this specific ‘dash

code’ part number

8A3xxxx Family Programming Guide (v4.7) Contains detailed register descriptions and address maps for all members of the

family of devices. Please check the <device name> datasheet to check the version used by that device. All devices that use this version number use some subset of this register map, as indicated in their device-specific Programming Guide Addendum document..

Evaluation Board Reference Manual Describes the Evaluation Board. Evaluation boards are available for the 8A34001

(144BGA) or 8A34002 (72QFN) devices. These devices contain a superset of the functionality available in all other members of the 8A3xxxx Family. So they can serve as evaluation tools for any of the less fully-featured family members.

Timing Commander Personality User Manual Detailed description of how to use IDT’s Timing Commander configuration tool. At

this time, a personality file is only available for 8A34001. This personality contains a superset of the functionality available in all other members of the 8A3xxxx family. Since all members of the 8A3xxxx family share register locations and resource numbering, configurations generated using the 8A34001 personality can be used in any member of the 8A3xxxx family. Functionality that is not available on the other family members will of course not respond to any configuration of it that is made.

This document discusses the registers supported by a particular version of the Firmware (FW) running on the internal micro-controller within the 8A3xxxx family of devices. Register maps may change between major releases of the FW, so please check the Revision History section of this document to ensure this document aligns with the FW revision being used on the device. FW version numbering follows the format:

v<major release number>.<minor release number>.<hotfix number>

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8A3xxxx Family Programming Guide

This document is broken into several sections:

▪ Introduction (this section) - describes documentation structure for the 8A3xxxx ▪ Serial Port Overview - repeating selected information from the 8A3xxxx Datasheet to discuss how the serial ports function, overall device

memory map and register addresses

▪ I2C Slave Operation - discusses register accessing topics related to I

C operation on a serial port

▪ SPI Operation - discusses register accessing topics related to SPI operation on a serial port ▪ Register Table Overview - discusses register table format and abbreviations ▪ Register Set Descriptions - describes a set of registers that is made available for users to quickly and simply access the commonly-used

features of the 8A3xxxx.

▪ Revision History ▪ IDT Contact information

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Serial Port Overview

The 8A3xxxx family supports up to 3 serial ports. One is a dedicated I two are configurable slave device. In some variants of the device, the

I2C or SPI ports that can be used at any time after the reset sequence is complete to monitor and/or configure the

I2C Master port share pins with an I2C slave port.

8A3xxxx Family Programming Guide

C Master port used for loading configuration data at reset and the other

Operation of the

I2C Master Port is only used by the device to access an external serial EEPROM and so won’t be discussed here.

Two slave ports have been provided to allow independent access to any of the device’s internal registers. This allows high priority accesses not to be queued behind lower priority ones on a shared external serial interface. Note that internal to the device, both slave serial ports access a single instance of each register over a shared internal bus. The device ensures that a burst access on one bus will complete atomically once begun, before the other port can gain access to the shared internal bus or registers. However it does not guarantee the order in which the two serial ports will be granted access to any shared resource.

Please refer to the appropriate section below for details on the operation of the slave

I2C or SPI ports.

Either slave port can be reconfigured over either serial port at any time by accessing the appropriate registers. This includes both configuration options with each protocol or switching between protocols (

configuration, including page sizes for registers, for each serial port be set in the initial configuration data read from OTP or external EEPROM (see Device Initial Configuration in the 8A3xxxx Datasheet for details).

Addressing Registers within a Device

The address space that is externally accessible within the device is 64kbytes in size and so needs 16-bits of address offset information to be

I2C to SPI or vice versa). However it is recommended that the full operating mode

provided during slave serial port accesses. Of that 64kbytes, only the upper 32kbytes contains user accessible registers.

The user may choose to operate either serial port providing the full offset address within each burst or to operate in a paged mode where part of the address offset is provided in each transaction and part comes from an internal page register in each serial port. The decision may be made independently on each slave serial port and each slave serial port has its own page register to avoid conflicts. Figure 1 shows how page register and offset bytes from each serial transaction interact to address a register within the 8A3xxxx.

Figure 1: Register Addressing Modes via Serial Port

I2C Slave Operation

The I2C slave protocol of the 8A3xxx family complies with Version 2.1 of the I2C specification. Figure 2 shows the sequence of states on the

I2C SDATA signal for the supported modes of operation.

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Figure 2: I2C Slave Sequencing Diagram

Sequential 16-bit Read

S Dev Addr + W A Data X A Data X+1 A A Data X+n A

Offset Addr X

MSB

A Sr Dev Addr + R A

Sequential 16-bit Write

S Dev Addr + W A

Data X PA Data X+1 A A Data X+n A

from master to slave

from slave to master

Offset Addr X

MSB

S = start Sr = repeated start A = acknowledge A

= non-acknowledge

P = stop

Sequential 8-bit Read

S Dev Addr + W A Data X A Data X+1 A A Data X+n A POffset Addr X A Sr Dev Addr + R A

Sequential 8-bit Write

S Dev Addr + W A

Data X PA Data X+1 A A Data X+n A

Offset Addr X A

Offset Addr X

LSB

Offset Addr X

LSB

8A3xxxx Family Programming Guide

The Dev Addr shown in the figure represents the base address of the 8A3xxxx device. This 7-bit value can be set in an internal register which can have a user-defined value loaded at reset from internal OTP memory or an external EEPROM. The default value if those methods are not used is 0000000 (binary). Note that the levels on the S_A0 and S_A1 inputs can be used to control Bit 0 and Bit 1 (respectively) of this address. These pins are available independently for each serial port. In I functions when the part is in SPI mode. The resulting base address is the I

C operation these inputs are expected to remain static. They have different

C bus address that this device will respond to. The default address

may be over-written at any time.

When I2C operation is selected for either slave serial port, selection of 1-byte (1B) or 2-byte (2B) offset addressing must also be selected independently for each slave serial port. These offsets are used in conjunction with the page register for each serial port to access registers internal to the device. Because the I

C protocol already includes a read/write bit with the Dev Addr, all bits of the 1B or 2B offset field can be

used to address internal registers.

▪ In 1B mode, the lower 8-bits of the register offset address come from the Offset Addr byte and the upper 8-bits come from the page register

(see Table 2 for description of the 8-bit I

C Page Register). The page register can be accessed at any time, no matter what page the serial port is currently on, using an offset byte value of FCh. This 4-byte register must be written in a single burst write transaction. The page register is replicated on every register page to always be accessible.

▪ In 2B mode, the full 16-bit register address can be obtained from the Offset Addr bytes, so the page register only needs to be set once after

reset using a 3-byte burst access starting from address FFFDh (see Table 3 for description of the 16-bit I

Table 2: I2C 1B Mode Page Register Bit Field Locations and Descriptions

Offset

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

I2C 1B Mode Page Register Bit Field Locations

C Page Register).

FC PAGE_ADDR[7:0]

FD PAGE_ADDR[15:8]

FE PAGE_ADDR[23:16]

FF PAGE_ADDR[31:24]

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8A3xxxx Family Programming Guide

I2C 1B Mode Page Register Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PAGE_ADDR[7:0] R/W 00h The values in this field are always replaced by the bits in I

C transaction itself

and so have no meaning.

PAGE_ADDR[15:8] R/W 00h Select which register page to access. Forms the upper 8-bits of the 16-bit

PAGE_ADDR[23:16] R/W 10h Must be set to 10h in all cases

PAGE_ADDR[31:24] R/W 20h Must be set to 20h in all cases

Table 3: I2C 2B Mode Page Register Bit Field Locations and Descriptions

Offset

I2C 2B Mode Page Register Bit Field Locations

Address

(Hex)

FFFD

D7 D6 D5 D4 D3 D2 D1 D0

PAGE_ADDR[15:8]

FFFE PAGE_ADDR[23:16]

FFFF PAGE_ADDR[31:24]

1. Burst access must begin at this non-aligned offset and all 3 bytes must be written in the same I

C burst access. A burst beginning at the

32-bit aligned address of FFFCh will not correctly set this register.

I2C 2B Mode Page Register Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PAGE_ADDR[15:8] R/W 00h The values in this field are always replaced by the bits in I

C transaction itself

and so have no meaning.

PAGE_ADDR[23:16] R/W 10h Must be set to 10h in all cases

PAGE_ADDR[31:24] R/W 20h Must be set to 20h in all cases

I2C burst mode operation is required to ensure data integrity of multi-byte registers. When accessing a multi-byte register, all data bytes must be written or read in a single I page (Offset Addr FFh in 1B mode, no limit in 2B mode). An internal address pointer is incremented automatically as each data byte is written or read.

C burst access. Bursts may be of greater length if desired, but must not extend beyond the end of the register

C 1-byte (1B) Addressing Examples

8A3xxxx I2C 7-bit I2C address is 0x5B with LSB=R/W

Example Write “0x50” to register 0xCBE4

B6* FC 00 CB 10 20 #Set Page Register, *I B6 E4 50 #Write data 5B to CB E4

C Address is left-shifted one bit.

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8A3xxxx Family Programming Guide

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

Hi-Z

SCLK

SDI

(4-wire)

SDIO

(4-wire)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14R/W

SCLK

SDI

(4-wire)

SDIO

(4-wire)

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

Hi-Z

SPI Read Sequence*

SPI Write Sequence*

XX (SDI unused while data being read)

A14-A7 are omitted in 7b SPI Addressing Mode Data byte from Address provided Data byte from Address + 1

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

A14-A7 are omitted in 7b SPI Addressing Mode Data byte from Address provided Data byte from Address + 1

* refer to timing diagrams for exact timing relationships

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13R/W

SDIO

(3-wire)

D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6

A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDIO driven by Master SDIO driven by Slave

Example read from register 0xC024

B6* FC 00 C0 10 20 #Set Page Register, *I B6 24* #Set I

C pointer to 0xC024, *I2C instruction should use “No Stop”

C Address is left-shifted one bit.

B7 <read back data> #Send address with Read bit set.

C 2-byte (2B) Addressing

8A3xxxx I

C 7-bit I2C address is 0x5B with LSB=R/W

Example Write “50” to register 0xCBE4

B6* FF FD 00 10 20 #Set Page Register, *I

C Address is left-shifted one bit.

B6 CB E4 50 #Write data to CB E4

Example read from register 0xC024:

B6* FF FD 00 10 20 #Set Page Register (*I B6 C0 24* #Set I

C pointer to 0xC024, *I2C instruction should use “No Stop”

C Address is left-shifted one bit.)

B7 <read back data> #Send address with Read bit set.

SPI Operation

The 8A3xxxx Family devices support SPI operation on their main and alternate serial ports. Figure 3 shows the sequencing of address and data on the serial port in SPI mode.

Figure 3: SPI Sequencing Diagram

Each serial port can be independently configured for the following settings. These settings can come from register defaults or from an internal OTP or external EEPROM configuration loaded at reset:

— 1-byte (1B) or 2-byte (2B) offset addressing (see Figure 1)

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8A3xxxx Family Programming Guide

– In 1B operation, the 16-bit register address is formed by using the 7-bits of address supplied in the SPI access and taking the upper

9-bits from the page register.The page register is accessed, no matter what page the serial port is currently on, using an Offset Address of 7Ch - 7Fh. It must be accessed in a single 4-byte burst write transaction. The page register is replicated on every register page to always be accessible.

– In 2B operation, the 16-bit register address is formed by using the 15-bits of address supplied in the SPI access and taking the upper

1-bit from the page register. Note that this bit will always be ‘1’ for register accesses, so the page register only needs to be set once in 2B operation. The page register can be accessed, no matter what page the serial port is currently on, using an Offset Address of 7FFDh - 7FFFh. It should be accessed in a single 3-byte burst write transaction to set it. The page register is replicated on every

register page to always be accessible. — Data sampling on falling or rising edge of SCLK — Output (read) data positioning relative to active SCLK edge — 4-wire (SCLK, SCSb, SDATA, SDO) or 3-wire (SCLK, SCSb, SDATA) operation

– In 3-wire mode, SDATA is a bi-directional data pin.

— Output signal protocol compatibility / drive strength and termination voltage

Table 4: SPI 1B Mode Page Register Bit Field Locations and Descriptions

Offset

SPI 1B Mode Page Register Bit Field Locations

Address

(Hex)

7C PAGE_ADDR

D7 D6 D5 D4 D3 D2 D1 D0

PAGE_ADDR[6:0]

[7]

7D PAGE_ADDR[15:8]

7E PAGE_ADDR[23:16]

7F PAGE_ADDR[31:24]

SPI 1BMode Page Register Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PAGE_ADDR[6:0] R/W - The values in this field are always replaced by the bits in SPI transaction itself

and so have no meaning.

PAGE_ADDR[15:7] R/W 000000000b Select which register page to access. Forms the upper 9-bits of the 16-bit

PAGE_ADDR[23:16] R/W 10h Must be set to 10h in all cases

PAGE_ADDR[31:24] R/W 20h Must be set to 20h in all cases

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Table 5: SPI 2B Mode Page Register Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

SPI 2B Mode Page Register Bit Field Locations

Address

(Hex)

7FFD

D7 D6 D5 D4 D3 D2 D1 D0

PAGE_ADDR

PAGE_ADDR[14:8]

[15]

7FFE PAGE_ADDR[23:16]

7FFF PAGE_ADDR[31:24]

1. Burst access must begin at this non-aligned offset and all 3 bytes must be written in the same SPI burst access. A burst beginning at the 32-bit aligned address of 7FFCh will not correctly set this register.

SPI 2B Mode Page Register Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PAGE_ADDR[14:8] R/W 0000000b The values in this field are always replaced by the bits in SPI transaction itself

and so have no meaning.

PAGE_ADDR[15] R/W 0b Select which register page to access. Forms the most-significant bit of the 16-bit

PAGE_ADDR[23:16] R/W 10h Must be set to 10h in all cases

PAGE_ADDR[31:24] R/W 20h Must be set to 20h in all cases

SPI burst mode operation is required to ensure data integrity of multi-byte registers. When accessing a multi-byte register, all data bytes must be written or read in a single SPI burst access. Bursts may be of greater length if desired, but must not extend beyond the end of the register page. An internal address pointer is incremented automatically as each data byte is written or read.

SPI 1-byte (1B) Addressing Example

Example Write to “50” to register 0xCBE4

7C 80 CB 10 20 #Set Page register 64* 50 #*MSB is 0 for write transactions

Example Read from 0xC024:

7C 00 C0 10 20 #Set Page register A4* 00 #*MSB is set, so this is a read command

SPI 2-byte (2B) Addressing Example

Example Write to “50” to register 0xCBE4

7F FD 80 10 20 #Set Page register 4B E4* 50 #*MSB is 0 for write transactions

Example Read from 0xC024:

7F FD 80 10 20 #Set Page register C0* 24 00 #*MSB is set, so this is a read command

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8A3xxxx Family Programming Guide

Register Table Overview

When programming an 8A3xxxx family device, it is necessary to read or write values to one or more ‘bit-fields’ within the device. A bit-field

provides status and/or control information on a single aspect of a single feature. A bit field may be as small as a single-bit or many bytes in length. A bit-field should be treated as an indivisible entity and all bytes of each bit-field should be read or written in a single serial port burst.

Access to bit-fields is performed using byte-oriented addressing. A bit-field may take up multiple byte address and/or multiple bit-fields may occupy a single byte. When there are multiple bit-fields within a single byte, all bit fields are read from or written to during an access to that byte address over the serial port. When a bit-field spans multiple byte addresses, all bytes should be read or written in the same serial port burst transaction to ensure consistency. For bit-fields spanning multiple bytes, the least-significant bits of that bit-field are contained in the byte with the lowest address.

Bit-fields are grouped into registers and registers are in turn grouped into modules. In the documentation that follows, bit-fields are shown mapped into register bytes in a table called a Bit-Field Location table. The function of each bit-field is shown in an associated Bit-Field Description table. One or more bit-fields are grouped into a register. Registers show an address offset for each byte within that register.

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8A3xxxx Family Programming Guide

A number of registers are grouped together into a module. In general a module contains all the registers needed to interact with a functional block within the device. Each module in the standard register set is listed in a Register Module Index table showing its module base address, a brief description of the module’s function and a link to that module’s location in the document. In each module’s sub-section is a similar table listing all the registers within that module, a brief description of the register and a link to that register’s detailed description. This is shown in

Figure 4

Many register modules include a trigger register at the end of the module that must be written to for any other register changes within that module to take effect. This allows multiple parameters to be setup then all to take effect at the same time for a particular function within the device. Where present, the trigger register is always the last register in the module to allow a burst write to be used, triggering on the last write of the burst. Users must ensure that the trigger register is written to, even if its contents don’t change to trigger the module update.

Figure 4: Finding a Register’s Detailed Description in this Document.

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8A3xxxx Family Programming Guide

The device contains multiple copies of many functional blocks and each will have its own associated register module for status and control. To keep the documentation clear and concise, only the first instance of a register module for a specific functional block will be shown in detail. The module table will show all instantiations of the module with their unique base addresses, but the links will all point to the same descriptive section (see blue arrows in Figure 5). Please ensure that when addressing a register that the base address of the correct instantiation of the module is used (see red arrows in Figure 5). Note that the base address indicated in the table description is for the first instantiation of the module only (see green arrow in Figure 5). For example, as shown below, to access the DPLL_MANUAL_HOLDOVER_VALUE bit-field for DPLL4, take the base address of that instantiation (C480h) and add the register offset of that specific register (008h). Note that since this bit-field is more than one byte, all bytes should be accessed in a single serial port burst transaction starting at C488h.

Figure 5: Determining the Address to Access a Specific Register.

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8A3xxxx Family Programming Guide

Terminology

The following terminology and abbreviations are used in the register tables.

If a bit-field has more than a single bit, the bit-field will be written as BIT_FIELD_NAME[msb:lsb] (e.g. DPLL_MANUAL_HOLDOVER_VALUE[39:0]

Binary numbers will be written with a lowercase ‘b’ after them (e.g. 0101b )

Hexadecimal numbers will be written with a lowercase ‘h’ after them (e.g. C480h).

R/W indicates a register is readable and write-able by the user

R/O indicates that a register should only be read by the user. Writing to a R/O register has an undefined effect.

W/O indicates that a register should only be written to by the user. The read value is undefined and has no associated meaning.

RW1C indicates a register that can be read, but a ‘1’ needs to be written to the bit to clear it back to 0. This is generally used for ‘sticky’ status bits that are latched high whenever a transient condition occurs. The user will need to write to clear the latched status.

N/A means Not Applicable. This is only used for Reserved bit-fields who’s behaviour is not defined.

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Register Set Descriptions

Table 6: Register Set Module Index

Module Base Address

(Hex)

8180h Module: HW_REVISION Hardware Revision ID register

C000h Module: RESET_CTRL General reset management.

C014h Module: GENERAL_STATUS Chip hardware status registers.

C03Ch Module: STATUS Live status of alarms and events.

C160h Module: GPIO_USER_CONTROL GPIO user control.

C164h Module: STICKY_STATUS_CLEAR Sticky status clear.

8A3xxxx Family Programming Guide

Link Module Description

C16Ch Module:

GPIO_TOD_NOTIFICATION_CLEAR

C170h RESERVED This module must not be modified from the read value

C180h RESERVED This module must not be modified from the read value

C188h Module: ALERT_CFG Notification configuration.

C194h Module: SYS_DPLL_XO System DPLL XO configuration.

C19Ch Module: SYS_APLL System APLL configuration.

C1B0h Module: INPUT_0 Input 0 configuration.

C1C0h INPUT_1 Input 1 configuration.

C1D0h INPUT_2 Input 2 configuration.

C200h INPUT_3 Input 3 configuration.

C210h INPUT_4 Input 4 configuration.

C220h INPUT_5 Input 5 configuration.

Clear GPIO output Time of Day read notification.

Same as INPUT_0.

C230h INPUT_6 Input 6 configuration.

Same as INPUT_0.

C240h INPUT_7 Input 7 configuration.

Same as INPUT_0.

C250h INPUT_8 Input 8 configuration.

Same as INPUT_0.

C260h INPUT_9 Input 9 configuration.

Same as INPUT_0.

C280h INPUT_10 Input 10 configuration.

Same as INPUT_0.

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Table 6: Register Set Module Index

Module Base Address

(Hex)

C290h INPUT_11 Input 11 configuration.

C2A0h INPUT_12 Input 12 configuration.

C2B0h INPUT_13 Input 13 configuration.

C2C0h INPUT_14 Input 14 configuration.

C2D0h INPUT_15 Input 15 configuration.

C2E0h Module: REF_MON_0 Reference monitor 0.

C2ECh REF_MON_1 Reference monitor 1.

8A3xxxx Family Programming Guide

Link Module Description

Same as INPUT_0.

Same as REF_MON_0.

C300h REF_MON_2 Reference monitor 2.

Same as REF_MON_0.

C30Ch REF_MON_3 Reference monitor 3.

Same as REF_MON_0.

C318h REF_MON_4 Reference monitor 4.

Same as REF_MON_0.

C324h REF_MON_5 Reference monitor 5.

Same as REF_MON_0.

C330h REF_MON_6 Reference monitor 6.

Same as REF_MON_0.

C33Ch REF_MON_7 Reference monitor 7.

Same as REF_MON_0.

C348h REF_MON_8 Reference monitor 8.

Same as REF_MON_0.

C354h REF_MON_9 Reference monitor 9.

Same as REF_MON_0.

C360h REF_MON_10 Reference monitor 10.

Same as REF_MON_0.

C36Ch REF_MON_11 Reference monitor 11.

Same as REF_MON_0.

C380h REF_MON_12 Reference monitor 12.

Same as REF_MON_0.

C38Ch REF_MON_13 Reference monitor 13.

Same as REF_MON_0.

C398h REF_MON_14 Reference monitor 14.

Same as REF_MON_0.

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Table 6: Register Set Module Index

Module Base Address

(Hex)

C3A4h REF_MON_15 Reference monitor 15.

C3B0h Module: DPLL_0 DPLL 0 configuration registers.

C400h DPLL_1 DPLL 1 registers.

C438h DPLL_2 DPLL 2 registers.

C480h DPLL_3 DPLL 3 registers.

C4B8h DPLL_4 DPLL 4 registers.

C500h DPLL_5 DPLL 5 registers.

8A3xxxx Family Programming Guide

Link Module Description

Same as REF_MON_0.

Same as DPLL_0.

C538h DPLL_6 DPLL 6 registers.

Same as DPLL_0.

C580h DPLL_7 DPLL 7 registers.

Same as DPLL_0.

C5B8h Module: SYS_DPLL System DPLL registers.

C600h Module: DPLL_CTRL_0 DPLL 0 control registers.

C63Ch DPLL_CTRL_1 DPLL 1 control registers.

Same as DPLL_CTRL_0.

C680h DPLL_CTRL_2 DPLL 2 control registers.

Same as DPLL_CTRL_0.

C6BCh DPLL_CTRL_3 DPLL 3 control registers.

Same as DPLL_CTRL_0.

C700h DPLL_CTRL_4 DPLL 4 control registers.

Same as DPLL_CTRL_0.

C73Ch DPLL_CTRL_5 DPLL 5 control registers.

Same as DPLL_CTRL_0.

C780h DPLL_CTRL_6 DPLL 6 control registers.

Same as DPLL_CTRL_0.

C7BCh DPLL_CTRL_7 DPLL 7 control registers.

Same as DPLL_CTRL_0.

C800h Module: SYS_DPLL_CTRL System DPLL control registers.

C818h Module: DPLL_PHASE_0 DPLL 0 write phase.

C81Ch DPLL_PHASE_1 DPLL 1 write phase.

Same as DPLL_PHASE_0.

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Table 6: Register Set Module Index

Module Base Address

(Hex)

C820h DPLL_PHASE_2 DPLL 2 write phase.

C824h DPLL_PHASE_3 DPLL 3 write phase.

C828h DPLL_PHASE_4 DPLL 4 write phase.

C82Ch DPLL_PHASE_5 DPLL 5 write phase.

C830h DPLL_PHASE_6 DPLL 6 write phase.

C834h DPLL_PHASE_7 DPLL 7 write phase.

C838h Module: DPLL_FREQ_0 DPLL 0 write frequency.

8A3xxxx Family Programming Guide

Link Module Description

Same as DPLL_PHASE_0.

C840h DPLL_FREQ_1 DPLL 1 write frequency.

Same as DPLL_FREQ_0.

C848h DPLL_FREQ_2 DPLL 2 write frequency.

Same as DPLL_FREQ_0.

C850h DPLL_FREQ_3 DPLL 3 write frequency.

Same as DPLL_FREQ_0.

C858h DPLL_FREQ_4 DPLL 4 write frequency.

Same as DPLL_FREQ_0.

C860h DPLL_FREQ_5 DPLL 5 write frequency.

Same as DPLL_FREQ_0.

C868h DPLL_FREQ_6 DPLL 6 write frequency.

Same as DPLL_FREQ_0.

C870h DPLL_FREQ_7 DPLL 7 write frequency.

Same as DPLL_FREQ_0.

C880h Module: DPLL_PHASE_PULL_IN_0 DPLL 0 phase pull-in control.

C888h DPLL_PHASE_PULL_IN_1 DPLL 1 phase pull-in control.

Same as DPLL_PHASE_PULL_IN_0.

C890h DPLL_PHASE_PULL_IN_2 DPLL 2 phase pull-in control.

Same as DPLL_PHASE_PULL_IN_0.

C898h DPLL_PHASE_PULL_IN_3 DPLL 3 phase pull-in control.

Same as DPLL_PHASE_PULL_IN_0.

C8A0h DPLL_PHASE_PULL_IN_4 DPLL 4 phase pull-in control.

Same as DPLL_PHASE_PULL_IN_0.

C8A8h DPLL_PHASE_PULL_IN_5 DPLL 5 phase pull-in control.

Same as DPLL_PHASE_PULL_IN_0.

Page 17

Table 6: Register Set Module Index

Module Base Address

(Hex)

C8B0h DPLL_PHASE_PULL_IN_6 DPLL 6 phase pull-in control.

C8B8h DPLL_PHASE_PULL_IN_7 DPLL 7 phase pull-in control.

C8C0h Module: GPIO_CFG GPIO global configuration.

C8C2h Module: GPIO_0 GPIO 0 registers.

C8D4h GPIO_1 GPIO 1 registers.

C8E6h GPIO_2 GPIO 2 registers.

C900h GPIO_3 GPIO 3 registers.

C912h GPIO_4 GPIO 4 registers.

8A3xxxx Family Programming Guide

Link Module Description

Same as DPLL_PHASE_PULL_IN_0.

Same as GPIO_0.

C924h GPIO_5 GPIO 5 registers.

Same as GPIO_0.

C936h GPIO_6 GPIO 6 registers.

Same as GPIO_0.

C948h GPIO_7 GPIO 7 registers.

Same as GPIO_0.

C95Ah GPIO_8 GPIO 8 registers.

Same as GPIO_0.

C980h GPIO_9 GPIO 9 registers.

Same as GPIO_0.

C992h GPIO_10 GPIO 10 registers.

Same as GPIO_0.

C9A4h GPIO_11 GPIO 11 registers.

Same as GPIO_0.

C9B6h GPIO_12 GPIO 12 registers.

Same as GPIO_0.

C9C8h GPIO_13 GPIO 13 registers.

Same as GPIO_0.

C9DAh GPIO_14 GPIO 14 registers.

Same as GPIO_0.

CA00h GPIO_15 GPIO 15 registers.

Same as GPIO_0.

CA12h Module: OUT_DIV_MUX Output divider multiplexers.

CA14h Module: OUTPUT_0 Output 0 registers.

Page 18

Table 6: Register Set Module Index

Module Base Address

(Hex)

CA24h OUTPUT_1 Output 1 register.

CA34h OUTPUT_2 Output 2 register.

CA44h OUTPUT_3 Output 3 register.

CA54h OUTPUT_4 Output 4 register.

CA64h OUTPUT_5 Output 5 register.

CA80h OUTPUT_6 Output 6 register.

CA90h OUTPUT_7 Output 7 register.

8A3xxxx Family Programming Guide

Link Module Description

Same as OUTPUT_0.

CAA0h OUTPUT_8 Output 8 register.

Same as OUTPUT_0.

CAB0h OUTPUT_9 Output 9 register.

Same as OUTPUT_0.

CAC0h OUTPUT_10 Output 10 register.

Same as OUTPUT_0.

CAD0h OUTPUT_11 Output 11 register.

Same as OUTPUT_0.

CAE0h Module: SERIAL Serial Interfaces registers.

CB00h Module: PWM_ENCODER_0 PWM 0 encoder registers.

CB08h PWM_ENCODER_1 PWM 1 encoder registers.

Same as PWM_ENCODER_0.

CB10h PWM_ENCODER_2 PWM 2 encoder registers.

Same as PWM_ENCODER_0.

CB18h PWM_ENCODER_3 PWM 3 encoder registers.

Same as PWM_ENCODER_0.

CB20h PWM_ENCODER_4 PWM 4 encoder registers.

Same as PWM_ENCODER_0.

CB28h PWM_ENCODER_5 PWM 5 encoder registers.

Same as PWM_ENCODER_0.

CB30h PWM_ENCODER_6 PWM 6 encoder registers.

Same as PWM_ENCODER_0.

CB38h PWM_ENCODER_7 PWM 7 encoder registers.

Same as PWM_ENCODER_0.

CB40h Module: PWM_DECODER_0 PWM 0 decoder registers.

Page 19

Table 6: Register Set Module Index

Module Base Address

(Hex)

CB48h PWM_DECODER_1 PWM 1 decoder registers.

CB50h PWM_DECODER_2 PWM 2 decoder registers.

CB58h PWM_DECODER_3 PWM 3 decoder registers.

CB60h PWM_DECODER_4 PWM 4 decoder registers.

CB68h PWM_DECODER_5 PWM 5 decoder registers.

CB70h PWM_DECODER_6 PWM 6 decoder registers.

CB80h PWM_DECODER_7 PWM 7 decoder registers.

8A3xxxx Family Programming Guide

Link Module Description

Same as PWM_DECODER_0.

CB88h PWM_DECODER_8 PWM 8 decoder registers.

Same as PWM_DECODER_0.

CB90h PWM_DECODER_9 PWM 9 decoder registers.

Same as PWM_DECODER_0.

CB98h PWM_DECODER_10 PWM 10 decoder registers.

Same as PWM_DECODER_0.

CBA0h PWM_DECODER_11 PWM 11 decoder registers.

Same as PWM_DECODER_0.

CBA8h PWM_DECODER_12 PWM 12 decoder registers.

Same as PWM_DECODER_0.

CBB0h PWM_DECODER_13 PWM 13 decoder registers.

Same as PWM_DECODER_0.

CBB8h PWM_DECODER_14 PWM 14 decoder registers.

Same as PWM_DECODER_0.

CBC0h PWM_DECODER_15 PWM 15 decoder registers.

Same as PWM_DECODER_0.

CBC8h Module: PWM_USER_DATA PWM user data registers.

CBCCh Module: TOD_0 TOD 0 registers.

CBCEh TOD_1 TOD 1 registers.

Same as TOD_0.

CBD0h TOD_2 TOD 2 registers.

Same as TOD_0.

CBD2h TOD_3 TOD 3 registers.

Same as TOD_0.

CC00h Module: TOD_WRITE_0 Write TOD 0 registers.

Page 20

Table 6: Register Set Module Index

Module Base Address

(Hex)

CC10h TOD_WRITE_1 Write TOD 1 registers.

CC20h TOD_WRITE_2 Write TOD 2 registers.

CC30h TOD_WRITE_3 Write TOD 3 registers.

CC40h Module: TOD_READ_PRIMARY_0 Read TOD 0 primary registers.

CC50h TOD_READ_PRIMARY_1 Read TOD 1 primary registers.

CC60h TOD_READ_PRIMARY_2 Read TOD 2 primary registers.

CC80h TOD_READ_PRIMARY_3 Read TOD 3 primary registers.

8A3xxxx Family Programming Guide

Link Module Description

Same as TOD_WRITE_0.

Same as TOD_READ_PRIMARY_0.

CC90h Module: TOD_READ_SECONDARY_0 Read TOD 0 secondary registers.

CCA0h TOD_READ_SECONDARY_1 Read TOD 1 secondary registers.

Same as TOD_READ_SECONDARY_0.

CCB0h TOD_READ_SECONDARY_2 Read TOD 2 secondary registers.

Same as TOD_READ_SECONDARY_0.

CCC0h TOD_READ_SECONDARY_3 Read TOD 3 secondary registers.

Same as TOD_READ_SECONDARY_0.

CCD0h Module: OUTPUT_TDC_CFG Output TDC global configuration.

CD00h Module: OUTPUT_TDC_0 Output TDC 0.

CD08h OUTPUT_TDC_1 Output TDC 1.

Same as OUTPUT_TDC_0.

CD10h OUTPUT_TDC_2 Output TDC 2.

Same as OUTPUT_TDC_0.

CD18h OUTPUT_TDC_3 Output TDC 3.

Same as OUTPUT_TDC_0.

CD20h Module: INPUT_TDC Input TDC

CF50h Module: SCRATCH User multipurpose registers.

CF60h RESERVED This module must not be modified from the read value

CF68h Module: EEPROM EEPROM.

CF70h Module: OTP OTP.

CF80h Module: BYTE OTP registers.

D000h RESERVED This module must not be modified from the read value

Page 21

8A3xxxx Family Programming Guide

Module: HW_REVISION

Hardware Revision Information.Note that while this register can be accessed directly from the serial port by software, in IDT’s TIming Commander GUI tool, it must be accessed indirectly since it is located in the hardware only register space.

Table 7: HW_REVISION Register Index

Offset

(Hex)

07Ah HW_REVISION.REV_ID Device Hardware Revision Number

HW_REVISION.REV_ID

Table 8: HW_REVISION.REV_ID Bit Field Locations and Descriptions

Individual Register Name Register Description

Offset

HW_REVISION.REV_ID Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

07Ah REV_ID[7:0]

HW_REVISION.REV_ID Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REV_ID[7:0] R/O 2 Hardware Revision Register

1: RevA 2: RevB

Module: RESET_CTRL

Reset configuration.

Table 9: RESET_CTRL Register Index

Offset

(Hex)

000h RESERVED This register must not be modified from the read value

Individual Register Name Register Description

001h RESERVED This register must not be modified from the read value

002h RESERVED This register must not be modified from the read value

003h RESERVED This register must not be modified from the read value

004h RESERVED This register must not be modified from the read value

005h RESERVED This register must not be modified from the read value

006h RESERVED This register must not be modified from the read value

007h RESERVED This register must not be modified from the read value

008h RESERVED This register must not be modified from the read value

009h RESERVED This register must not be modified from the read value

Page 22

8A3xxxx Family Programming Guide

Table 9: RESET_CTRL Register Index

Offset

(Hex)

Individual Register Name Register Description

00Ah RESERVED This register must not be modified from the read value

00Bh RESERVED This register must not be modified from the read value

00Ch RESERVED This register must not be modified from the read value

00Dh RESERVED This register must not be modified from the read value

00Eh RESERVED This register must not be modified from the read value

00Fh RESERVED This register must not be modified from the read value

010h RESERVED This register must not be modified from the read value

011h RESERVED This register must not be modified from the read value

012h RESET_CTRL.SM_RESET Reset state machine.

RESET_CTRL.SM_RESET

Enable state machine reset.

TRIGGER: Writing to this byte triggers a read and activation in hardware of all the bytes of the RESET_CTRL module.

Table 10: RESET_CTRL.SM_RESET Bit Field Locations and Descriptions

Offset

RESET_CTRL.SM_RESET Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

012h RESET[7:0]

RESET_CTRL.SM_RESET Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESET[7:0] R/W 0 Reset state machine.

0x5a = initiate state machine reset Write 0x5A to perform state machine reset. All other values are ignored. Self clearing. During a state machine reset, all registers starting from GENERAL_STATUS returns to reset values and the device proceeds with the start-up sequence as if the device was just powered on. The digital core is not reset.

Page 23

8A3xxxx Family Programming Guide

Module: GENERAL_STATUS

Notification for hardware status.

Table 11: GENERAL_STATUS Register Index

Offset

(Hex)

000h RESERVED This register must not be modified from the read value

001h RESERVED This register must not be modified from the read value

002h RESERVED This register must not be modified from the read value

003h RESERVED This register must not be modified from the read value

004h GENERAL_STATUS.OTP_STATUS Current status of OTP.

008h GENERAL_STATUS.EEPROM_STATUS Current status of EEPROM.

00Ah RESERVED This register must not be modified from the read value

00Bh RESERVED This register must not be modified from the read value

00Ch RESERVED This register must not be modified from the read value

Individual Register Name Register Description

00Dh RESERVED This register must not be modified from the read value

00Eh RESERVED This register must not be modified from the read value

00Fh RESERVED This register must not be modified from the read value

010h GENERAL_STATUS.MAJ_REL Major release number.

011h GENERAL_STATUS.MIN_REL Minor release number.

012h GENERAL_STATUS.HOTFIX_REL Hotfix release number.

014h RESERVED This register must not be modified from the read value

015h RESERVED This register must not be modified from the read value

016h RESERVED This register must not be modified from the read value

017h RESERVED This register must not be modified from the read value

018h RESERVED This register must not be modified from the read value

019h RESERVED This register must not be modified from the read value

01Ah RESERVED This register must not be modified from the read value

01Bh RESERVED This register must not be modified from the read value

01Ch GENERAL_STATUS.JTAG_DEVICE_ID JTAG device identity.

01Eh GENERAL_STATUS.PRODUCT_ID Product identity.

020h GENERAL_STATUS.TEMPERATURE Device internal temperature in degrees Celsius.

022h GENERAL_STATUS.OTP_SCSR_CONFIG_SE

LECT

Selected soft CSR configuration loaded from OTP.

Page 24

Table 11: GENERAL_STATUS Register Index

Offset

(Hex)

Individual Register Name Register Description

023h GENERAL_STATUS.OTP_CONFIG_STATUS OTP soft CSR configuration status.

8A3xxxx Family Programming Guide

024h GENERAL_STATUS.OTP_CSR_CONFIG_STA

OTP hard CSR configuration status.

TUS

025h RESERVED This register must not be modified from the read value

026h GENERAL_STATUS.EEPROM_CONFIG_STATUSEEPROM soft CSR configuration status.

GENERAL_STATUS.OTP_STATUS

Indicates status of OTP.

Table 12: GENERAL_STATUS.OTP_STATUS Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.OTP_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

004h OTP_STATUS[7:0]

005h OTP_STATUS[15:8]

006h OTP_STATUS[23:16]

007h OTP_STATUS[31:24]

Page 25

GENERAL_STATUS.OTP_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

OTP_STATUS[31:0] R/O 0 Current status of OTP.

0x000000 = no status 0x100000 = success 0x100001 = corrupted header 0x100002 = address out of range 0x100003 = corrupted section 0x100004 = invalid cluster index 0x100005 = redundant cluster not available 0x100006 = redundant cluster invalid index 0x100007 = redundant cluster program fail 0x100008 = cluster program fail 0x100009 = cluster read fail 0x10000A = main memory program fail 0x10000B = no header available 0x10000C = not enough space 0x10000D = header fail 0x10000E = invalid boot row index 0x10000F = invalid header index 0x100010 = header not found 0x100011 = more data available 0x100012 = wrong confirmation code 0x100013 = OTP programming locked 0x1000FE = OTP access modeI is disabled 0x1000FF = unknown command

8A3xxxx Family Programming Guide

GENERAL_STATUS.EEPROM_STATUS

Indicates status of EEPROM.

Table 13: GENERAL_STATUS.EEPROM_STATUS Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.EEPROM_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

008h EEPROM_STATUS[7:0]

009h EEPROM_STATUS[15:8]

Page 26

GENERAL_STATUS.EEPROM_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

EEPROM_STATUS[15:0] R/O 0 Current status of EEPROM.

0x0000 = no status 0x8000 = ok 0x8001 = unknown command 0x8002 = wrong size 0x8003 = out of range 0x8004 = read failed 0x8005 = write failed 0x8006 = verification failed

GENERAL_STATUS.MAJ_REL

Major release number. e.g.. X.0.0

Table 14: GENERAL_STATUS.MAJ_REL Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

GENERAL_STATUS.MAJ_REL Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

010h MAJOR[7:1] PR_BUILD[0]

GENERAL_STATUS.MAJ_REL Bit Field Descriptions

Bit Field Name Field Type Default Value Description

MAJOR[7:1] R/O 0 Numeric major release. e.g.. X.0.0

PR_BUILD[0] R/O 0 Product release status.

1 if a product release or 0 if a development release..

GENERAL_STATUS.MIN_REL

Minor release number. e.g.. 1.Y.0

Table 15: GENERAL_STATUS.MIN_REL Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.MIN_REL Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

011h MINOR[7:0]

GENERAL_STATUS.MIN_REL Bit Field Descriptions

Bit Field Name Field Type Default Value Description

MINOR[7:0] R/O 0 Minor release number. e.g.. 1.Y.0

Page 27

GENERAL_STATUS.HOTFIX_REL

Hotfix release number. e.g.. 1.2.Z

Table 16: GENERAL_STATUS.HOTFIX_REL Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

GENERAL_STATUS.HOTFIX_REL Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

012h HOTFIX[7:0]

GENERAL_STATUS.HOTFIX_REL Bit Field Descriptions

Bit Field Name Field Type Default Value Description

HOTFIX[7:0] R/O 0 Hotfix release number. e.g.. 1.2.Z

GENERAL_STATUS.JTAG_DEVICE_ID

16-bit subset of JTAG ID as determined by BOND_ID.

Table 17: GENERAL_STATUS.JTAG_DEVICE_ID Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.JTAG_DEVICE_ID Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

01Ch JTAG_DEVICE_ID[7:0]

01Dh JTAG_DEVICE_ID[15:8]

GENERAL_STATUS.JTAG_DEVICE_ID Bit Field Descriptions

Bit Field Name Field Type Default Value Description

JTAG_DEVICE_ID[15:0] R/O 0 16-bit ID code for this specific device, please refer to the Programming Guide

Addendum for the specific device for expected value here.

GENERAL_STATUS.PRODUCT_ID

16-bit numeric value that correlates to the part number.

Table 18: GENERAL_STATUS.PRODUCT_ID Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.PRODUCT_ID Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

01Eh PRODUCT_ID[7:0]

01Fh PRODUCT_ID[15:8]

Page 28

8A3xxxx Family Programming Guide

GENERAL_STATUS.PRODUCT_ID Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PRODUCT_ID[15:0] R/O 0 16-bit Product ID code for this specific device, please refer to the Programming

Guide Addendum for the specific device for expected value here.

GENERAL_STATUS.TEMPERATURE

2s complement signed 16-bit numerical value in degrees Celsius.

Table 19: GENERAL_STATUS.TEMPERATURE Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.TEMPERATURE Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

020h TEMP_CELSIUS[7:0]

021h TEMP_CELSIUS[15:8]

GENERAL_STATUS.TEMPERATURE Bit Field Descriptions

Bit Field Name Field Type Default Value Description

TEMP_CELSIUS[15:0] R/O 0 Device temperature as measured by the device's internal temperature sensor.

2s complement number in degrees Celsius.

GENERAL_STATUS.OTP_SCSR_CONFIG_SELECT

The index of the soft CSR configuration loaded from OTP.

Table 20: GENERAL_STATUS.OTP_SCSR_CONFIG_SELECT Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.OTP_SCSR_CONFIG_SELECT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

022h OTP_SCSR_CONFIG_SELECTION[7:0]

GENERAL_STATUS.OTP_SCSR_CONFIG_SELECT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

OTP_SCSR_CONFIG_SE

R/O 0 Index of OTP SCSR configuration currently selected via startup GPIO function.

LECTION[7:0]

Page 29

8A3xxxx Family Programming Guide

GENERAL_STATUS.OTP_CONFIG_STATUS

Status of soft CSR configuration loaded from OTP.

Table 21: GENERAL_STATUS.OTP_CONFIG_STATUS Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.OTP_CONFIG_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

023h OTP_SCSR_CONFIG_STATUS[7:0]

GENERAL_STATUS.OTP_CONFIG_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

OTP_SCSR_CONFIG_ST

ATUS[7:0]

R/O 0 Status code.

0 = success 1 = not found 2 = incomplete 3 = wrong offset 4 = wrong length 5 = SCSR out of range 6 = CRC error

GENERAL_STATUS.OTP_CSR_CONFIG_STATUS

Status of hard CSR configuration loaded from OTP.

Table 22: GENERAL_STATUS.OTP_CSR_CONFIG_STATU S Bit Fiel d Loc ations and Descriptions

Offset

GENERAL_STATUS.OTP_CSR_CONFIG_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

024h OTP_CSR_CONFIG_STATUS[7:0]

GENERAL_STATUS.OTP_CSR_CONFIG_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

OTP_CSR_CONFIG_STAT

US[7:0]

R/O 0 Status code.

0 = success 1 = not found 2 = incomplete 3 = wrong offset 4 = wrong length 5 = CSR out of range 6 = CRC error 7 = serializer wrong length 8 = serializer write fail

Page 30

8A3xxxx Family Programming Guide

GENERAL_STATUS.EEPROM_CONFIG_STATUS

Status of configuration loaded from EEPROM.

Table 23: GENERAL_STATUS.EEPROM_CONFIG_STATUS Bit Field Locations and Descriptions

Offset

GENERAL_STATUS.EEPROM_CONFIG_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

026h EEPROM_CONFIG_STATUS[7:0]

GENERAL_STATUS.EEPROM_CONFIG_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

EEPROM_CONFIG_STAT

US[7:0]

R/O 0 Status code.

0x0 = success 0x1 = not found 0x2 = incomplete 0x3 = wrong offset 0x4 = wrong length 0x5 = SCSR out of range 0x6 = CRC error 0xA = corrupt header 0xB = EEPROM out of range

Module: STATUS

Live status of alarms and events.

Table 24: STATUS Register Index

Offset

(Hex)

Individual Register Name Register Description

000h STATUS.I2CM_STATUS I2C master status.

001h RESERVED This register must not be modified from the read value

002h STATUS.SER0_STATUS Status of serial interface 0.

003h STATUS.SER0_SPI_STATUS Status of serial interface 0 SPI.

004h STATUS.SER0_I2C_STATUS Status of serial interface 0 I2C.

005h STATUS.SER1_STATUS Status of serial interface 1.

006h STATUS.SER1_SPI_STATUS Status of serial interface 1 SPI.

007h STATUS.SER1_I2C_STATUS Status of serial interface 1 I2C.

008h STATUS.IN0_MON_STATUS Input 0 reference monitor status.

009h STATUS.IN1_MON_STATUS Input 1 reference monitor status.

00Ah STATUS.IN2_MON_STATUS Input 2 reference monitor status.

00Bh STATUS.IN3_MON_STATUS Input 3 reference monitor status.

Page 31

Table 24: STATUS Register Index

Offset

(Hex)

Individual Register Name Register Description

00Ch STATUS.IN4_MON_STATUS Input 4 reference monitor status.

00Dh STATUS.IN5_MON_STATUS Input 5 reference monitor status.

00Eh STATUS.IN6_MON_STATUS Input 6 reference monitor status.

00Fh STATUS.IN7_MON_STATUS Input 7 reference monitor status.

010h STATUS.IN8_MON_STATUS Input 8 reference monitor status.

011h STATUS.IN9_MON_STATUS Input 9 reference monitor status.

012h STATUS.IN10_MON_STATUS Input 10 reference monitor status.

013h STATUS.IN11_MON_STATUS Input 11 reference monitor status.

014h STATUS.IN12_MON_STATUS Input 12 reference monitor status.

015h STATUS.IN13_MON_STATUS Input 13 reference monitor status.

016h STATUS.IN14_MON_STATUS Input 14 reference monitor status.

8A3xxxx Family Programming Guide

017h STATUS.IN15_MON_STATUS Input 15 reference monitor status.

018h STATUS.DPLL0_STATUS DPLL 0 status.

019h STATUS.DPLL1_STATUS DPLL 1 status.

01Ah STATUS.DPLL2_STATUS DPLL 2 status.

01Bh STATUS.DPLL3_STATUS DPLL 3 status.

01Ch STATUS.DPLL4_STATUS DPLL 4 status.

01Dh STATUS.DPLL5_STATUS DPLL 5 status.

01Eh STATUS.DPLL6_STATUS DPLL 6 status.

01Fh STATUS.DPLL7_STATUS DPLL 7 status.

020h STATUS.DPLL_SYS_STATUS System DPLL status.

021h STATUS.SYS_APLL_STATUS System APLL status.

022h STATUS.DPLL0_REF_STAT DPLL 0 input reference status.

023h STATUS.DPLL1_REF_STAT DPLL 1 input reference status.

024h STATUS.DPLL2_REF_STAT DPLL 2 input reference status.

025h STATUS.DPLL3_REF_STAT DPLL 3 input reference status.

026h STATUS.DPLL4_REF_STAT DPLL 4 input reference status.

027h STATUS.DPLL5_REF_STAT DPLL 5 input reference status.

028h STATUS.DPLL6_REF_STAT DPLL 6 input reference status.

029h STATUS.DPLL7_REF_STAT DPLL 7 input reference status.

02Ah STATUS.DPLL_SYS_REF_STAT System DPLL input reference status.

044h STATUS.DPLL0_FILTER_STATUS DPLL 0 loop filter status.

Page 32

8A3xxxx Family Programming Guide

Table 24: STATUS Register Index

Offset

(Hex)

Individual Register Name Register Description

04Ch STATUS.DPLL1_FILTER_STATUS DPLL 1 loop filter status.

054h STATUS.DPLL2_FILTER_STATUS DPLL 2 loop filter status.

05Ch STATUS.DPLL3_FILTER_STATUS DPLL 3 loop filter status.

064h STATUS.DPLL4_FILTER_STATUS DPLL 4 loop filter status.

06Ch STATUS.DPLL5_FILTER_STATUS DPLL 5 loop filter status.

074h STATUS.DPLL6_FILTER_STATUS DPLL 6 loop filter status.

07Ch STATUS.DPLL7_FILTER_STATUS DPLL 7 loop filter status.

084h STATUS.DPLL_SYS_FILTER_STATUS System DPLL loop filter status.

08Ah STATUS.USER_GPIO0_TO_7_STATUS User controlled GPIO level.

08Bh STATUS.USER_GPIO8_TO_15_STATUS User controlled GPIO level.

08Ch STATUS.IN0_MON_FREQ_STATUS Input 0 reference monitor frequency status and unit.

08Eh STATUS.IN1_MON_FREQ_STATUS Input 1 reference monitor frequency status and unit.

090h STATUS.IN2_MON_FREQ_STATUS Input 2 reference monitor frequency status and unit.

092h STATUS.IN3_MON_FREQ_STATUS Input 3 reference monitor frequency status and unit.

094h STATUS.IN4_MON_FREQ_STATUS Input 4 reference monitor frequency status and unit.

096h STATUS.IN5_MON_FREQ_STATUS Input 5 reference monitor frequency status and unit.

098h STATUS.IN6_MON_FREQ_STATUS Input 6 reference monitor frequency status and unit.

09Ah STATUS.IN7_MON_FREQ_STATUS Input 7 reference monitor frequency status and unit.

09Ch STATUS.IN8_MON_FREQ_STATUS Input 8 reference monitor frequency status and unit.

09Eh STATUS.IN9_MON_FREQ_STATUS Input 9 reference monitor frequency status and unit.

0A0h STATUS.IN10_MON_FREQ_STATUS Input 10 reference monitor frequency status and unit.

0A2h STATUS.IN11_MON_FREQ_STATUS Input 11 reference monitor frequency status and unit.

0A4h STATUS.IN12_MON_FREQ_STATUS Input 12 reference monitor frequency status and unit.

0A6h STATUS.IN13_MON_FREQ_STATUS Input 13 reference monitor frequency status and unit.

0A8h STATUS.IN14_MON_FREQ_STATUS Input 14 reference monitor frequency status and unit.

0AAh STATUS.IN15_MON_FREQ_STATUS Input 15 reference monitor frequency status and unit.

0ACh STATUS.OUTPUT_TDC_CFG_STATUS Output TDC global status.

0ADh STATUS.OUTPUT_TDC0_STATUS Output TDC 0 status.

0AEh STATUS.OUTPUT_TDC1_STATUS Output TDC 1 status.

0AFh STATUS.OUTPUT_TDC2_STATUS Output TDC 2 status.

0B0h STATUS.OUTPUT_TDC3_STATUS Output TDC 3 status.

0B4h STATUS.OUTPUT_TDC0_MEASUREMENT Output TDC 0 measurement status.

Page 33

8A3xxxx Family Programming Guide

Table 24: STATUS Register Index

Offset

(Hex)

Individual Register Name Register Description

0BAh RESERVED This register must not be modified from the read value

0BBh RESERVED This register must not be modified from the read value

0C4h STATUS.OUTPUT_TDC1_MEASUREMENT Output TDC 1 measurement status.

0CAh RESERVED This register must not be modified from the read value

0CBh RESERVED This register must not be modified from the read value

0CCh STATUS.OUTPUT_TDC2_MEASUREMENT Output TDC 2 measurement status.

0D2h RESERVED This register must not be modified from the read value

0D3h RESERVED This register must not be modified from the read value

0D4h STATUS.OUTPUT_TDC3_MEASUREMENT Output TDC 3 measurement status.

0DAh RESERVED This register must not be modified from the read value

0DBh RESERVED This register must not be modified from the read value

0DCh STATUS.DPLL0_PHASE_STATUS Phase offset at output of decimator.

0E1h RESERVED This register must not be modified from the read value

0E2h RESERVED This register must not be modified from the read value

0E3h RESERVED This register must not be modified from the read value

0E4h STATUS.DPLL1_PHASE_STATUS Phase offset at output of decimator.

0E9h RESERVED This register must not be modified from the read value

0EAh RESERVED This register must not be modified from the read value

0EBh RESERVED This register must not be modified from the read value

0ECh STATUS.DPLL2_PHASE_STATUS Phase offset at output of decimator.

0F1h RESERVED This register must not be modified from the read value

0F2h RESERVED This register must not be modified from the read value

0F3h RESERVED This register must not be modified from the read value

0F4h STATUS.DPLL3_PHASE_STATUS Phase offset at output of decimator.

0F9h RESERVED This register must not be modified from the read value

0FAh RESERVED This register must not be modified from the read value

0FBh RESERVED This register must not be modified from the read value

0FCh STATUS.DPLL4_PHASE_STATUS Phase offset at output of decimator.

101h RESERVED This register must not be modified from the read value

102h RESERVED This register must not be modified from the read value

103h RESERVED This register must not be modified from the read value

104h STATUS.DPLL5_PHASE_STATUS Phase offset at output of decimator.

Page 34

8A3xxxx Family Programming Guide

Table 24: STATUS Register Index

Offset

(Hex)

Individual Register Name Register Description

109h RESERVED This register must not be modified from the read value

10Ah RESERVED This register must not be modified from the read value

10Bh RESERVED This register must not be modified from the read value

10Ch STATUS.DPLL6_PHASE_STATUS Phase offset at output of decimator.

111h RESERVED This register must not be modified from the read value

112h RESERVED This register must not be modified from the read value

113h RESERVED This register must not be modified from the read value

114h STATUS.DPLL7_PHASE_STATUS Phase offset at output of decimator.

119h RESERVED This register must not be modified from the read value

11Ah RESERVED This register must not be modified from the read value

11Bh RESERVED This register must not be modified from the read value

11Ch STATUS.DPLL0_PHASE_PULL_IN_STATUS DPLL0 phase pull-in status

11Dh STATUS.DPLL1_PHASE_PULL_IN_STATUS DPLL1 phase pull-in status

11Eh STATUS.DPLL2_PHASE_PULL_IN_STATUS DPLL2 phase pull-in status

11Fh STATUS.DPLL3_PHASE_PULL_IN_STATUS DPLL3 phase pull-in status

120h STATUS.DPLL4_PHASE_PULL_IN_STATUS DPLL4 phase pull-in status

121h STATUS.DPLL5_PHASE_PULL_IN_STATUS DPLL5 phase pull-in status

122h STATUS.DPLL6_PHASE_PULL_IN_STATUS DPLL6 phase pull-in status

123h STATUS.DPLL7_PHASE_PULL_IN_STATUS DPLL7 phase pull-in status

STATUS.I2CM_STATUS

Status of the I2C master (port selection and speed).

Table 25: STATUS.I2CM_STATUS Bit Field Locations and Descriptions

Offset

STATUS.I2CM_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

000h RESERVED[7:4] I2CM_SPEED[3:2] I2CM_PORT_SEL[1:0]

Page 35

STATUS.I2CM_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

I2CM_SPEED[3:2] R/O 0 I2C Master speed.

Indicates the I2C speed. 0 = 100 KHz 1 = 400 KHz 2 = 1 MHz

I2CM_PORT_SEL[1:0] R/O 0 I2C Master port pin selection.

Indicates the pins the I2C master is connected to. 0 = I2C master 1 = serial interface 0 2 = serial interface 1

STATUS.SER0_STATUS

Status of serial interface 0.

8A3xxxx Family Programming Guide

Table 26: STATUS.SER0_STATUS Bit Field Locations and Descriptions

Offset

STATUS.SER0_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

002h RESERVED[7:3] ADDRESS_S

IZE[2]

STATUS.SER0_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

ADDRESS_SIZE[2] R/O 0 Serial Interface 0 address size.

Indicates the SSI address size. 0 = 1-byte 1 = 2-byte

MODE[1:0] R/O 0 Serial interface 0 mode.

Indicates the SSI protocol. 0 = undefined 1 = I2C 2 = SPI 3 = disabled

MODE[1:0]

Page 36

STATUS.SER0_SPI_STATUS

Status of serial interface 0 SPI.

Table 27: STATUS.SER0_SPI_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.SER0_SPI_STATUS Bit Field Locations

Address

(Hex)

003h RESERVED[7:5] SPI_SDO_D

D7 D6 D5 D4 D3 D2 D1 D0

SPI_CLOCK

ELAY[4]

_SELECTIO

N[3]

STATUS.SER0_SPI_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

SPI_SDO_DELAY[4] R/O 0 SPI delay SDO driving edge.

0 = driving edge used for SDO 1 = SDO driving edge delayed half-cycle of SCLK

SPI_CLOCK_SELECTION[

R/O 0 SPI Clock Selection for SDI sampling.

Indicates if the SPI clock selection is on a rising or falling edge. 0 = rising edge 1 = falling edge

SPI_DUPLEX_MODE[2] R/O 0 SPI 4-wire or 3-wire.

Indicates if the SPI is in full duplex or half duplex mode. 0 = full duplex 1 = half duplex

SPI_DUPLE

X_MODE[2]

RESERVED[1:0]

RESERVED N/A - This field must not be modified from the read value

STATUS.SER0_I2C_STATUS

Status of serial interface 0 I2C.

Table 28: STATUS.SER0_I2C_STATUS Bit Field Locations and Descriptions

Offset

STATUS.SER0_I2C_STATUS Bit Field Locations

Address

(Hex)

004h RESERVED[

D7 D6 D5 D4 D3 D2 D1 D0

DEVICE_ADDRESS[6:0]

STATUS.SER0_I2C_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DEVICE_ADDRESS[6:0] R/O 0 I2C address of this I2C slave.

7-bit I2C address.

Page 37

STATUS.SER1_STATUS

Status of serial interface 1.

Table 29: STATUS.SER1_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.SER1_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

005h RESERVED[7:3] ADDRESS_S

IZE[2]

STATUS.SER1_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

ADDRESS_SIZE[2] R/O 0 Serial interface 1 address size.

Indicates the SSI address size. 0 = 1-byte 1 = 2-byte

MODE[1:0] R/O 0 Serial interface 1 mode.

Indicates the SSI protocol. 0 = undefined 1 = I2C 2 = SPI 3 = disabled

MODE[1:0]

STATUS.SER1_SPI_STATUS

Status of serial interface 1 SPI.

Table 30: STATUS.SER1_SPI_STATUS Bit Field Locations and Descriptions

Offset

STATUS.SER1_SPI_STATUS Bit Field Locations

Address

(Hex)

006h RESERVED[7:5] SPI_SDO_D

D7 D6 D5 D4 D3 D2 D1 D0

SPI_CLOCK

ELAY[4]

_SELECTIO

N[3]

SPI_DUPLE

X_MODE[2]

RESERVED[1:0]

Page 38

STATUS.SER1_SPI_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

SPI_SDO_DELAY[4] R/O 0 SPI delay SDO driving edge.

0 = driving edge used for SDO 1 = SDO driving edge delayed half-cycle of SCLK

8A3xxxx Family Programming Guide

SPI_CLOCK_SELECTION[

R/O 0 SPI Clock Selection for SDI sampling.

Indicates if the SPI clock selection is on a rising or falling edge. 0 = rising edge 1 = falling edge

SPI_DUPLEX_MODE[2] R/O 0 SPI 4-wire or 3-wire.

Indicates if the SPI is in full duplex or half duplex mode. 0 = full duplex 1 = half duplex

RESERVED N/A - This field must not be modified from the read value

STATUS.SER1_I2C_STATUS

Status of serial interface 1 I2C.

Table 31: STATUS.SER1_I2C_STATUS Bit Field Locations and Descriptions

Offset

STATUS.SER1_I2C_STATUS Bit Field Locations

Address

(Hex)

007h RESERVED[

D7 D6 D5 D4 D3 D2 D1 D0

DEVICE_ADDRESS[6:0]

STATUS.SER1_I2C_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DEVICE_ADDRESS[6:0] R/O 0 I2C address of this I2C slave.

7-bit I2C address.

STATUS.IN0_MON_STATUS

Input 0 reference monitor status.

Table 32: STATUS.IN0_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN0_MON_STATUS Bit Field Locations

Address

(Hex)

008h RESERVED[7]IN0_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN0_NO_AC

TIVITY_STIC

KY[5]

IN0_LOS_ST

ICKY[4]

RESERVED[3]IN0_FREQ_

OFFS_LIM_L

IVE[2]

IN0_NO_AC

TIVITY_LIVE

[1]

IN0_LOS_LI

VE[0]

Page 39

STATUS.IN0_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN0_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 0. 0 = no change 1 = live status changed

IN0_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 0. 0 = no change 1 = live status changed

IN0_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 0. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN0_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 0. 0 = inactive 1 = active

IN0_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 0. 0 = inactive 1 = active

IN0_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 0. 0 = inactive 1 = active

STATUS.IN1_MON_STATUS

Input 1 reference monitor status.

Table 33: STATUS.IN1_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN1_MON_STATUS Bit Field Locations

Address

(Hex)

009h RESERVED[7]IN1_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN1_NO_AC

TIVITY_STIC

KY[5]

IN1_LOS_ST

ICKY[4]

RESERVED[3]IN1_FREQ_

OFFS_LIM_L

IVE[2]

IN1_NO_AC

TIVITY_LIVE

[1]

IN1_LOS_LI

VE[0]

Page 40

STATUS.IN1_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN1_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 1. 0 = no change 1 = live status changed

IN1_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 1. 0 = no change 1 = live status changed

IN1_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 1. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN1_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 1. 0 = inactive 1 = active

IN1_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 1. 0 = inactive 1 = active

IN1_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 1. 0 = inactive 1 = active

STATUS.IN2_MON_STATUS

Input 2 reference monitor status.

Table 34: STATUS.IN2_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN2_MON_STATUS Bit Field Locations

Address

(Hex)

00Ah RESERVED[7]IN2_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN2_NO_AC

TIVITY_STIC

KY[5]

IN2_LOS_ST

ICKY[4]

RESERVED[3]IN2_FREQ_

OFFS_LIM_L

IVE[2]

IN2_NO_AC

TIVITY_LIVE

[1]

IN2_LOS_LI

VE[0]

Page 41

STATUS.IN2_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN2_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 2. 0 = no change 1 = live status changed

IN2_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 2. 0 = no change 1 = live status changed

IN2_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 2. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN2_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 2. 0 = inactive 1 = active

IN2_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 2. 0 = inactive 1 = active

IN2_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 2. 0 = inactive 1 = active

STATUS.IN3_MON_STATUS

Input 3 reference monitor status.

Table 35: STATUS.IN3_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN3_MON_STATUS Bit Field Locations

Address

(Hex)

00Bh RESERVED[7]IN3_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN3_NO_AC

TIVITY_STIC

KY[5]

IN3_LOS_ST

ICKY[4]

RESERVED[3]IN3_FREQ_

OFFS_LIM_L

IVE[2]

IN3_NO_AC

TIVITY_LIVE

[1]

IN3_LOS_LI

VE[0]

Page 42

STATUS.IN3_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN3_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 3. 0 = no change 1 = live status changed

IN3_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 3. 0 = no change 1 = live status changed

IN3_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 3. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN3_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 3. 0 = inactive 1 = active

IN3_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 3. 0 = inactive 1 = active

IN3_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 3. 0 = inactive 1 = active

STATUS.IN4_MON_STATUS

Input 4 reference monitor status.

Table 36: STATUS.IN4_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN4_MON_STATUS Bit Field Locations

Address

(Hex)

00Ch RESERVED[7]IN4_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN4_NO_AC

TIVITY_STIC

KY[5]

IN4_LOS_ST

ICKY[4]

RESERVED[3]IN4_FREQ_

OFFS_LIM_L

IVE[2]

IN4_NO_AC

TIVITY_LIVE

[1]

IN4_LOS_LI

VE[0]

Page 43

STATUS.IN4_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN4_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 4. 0 = no change 1 = live status changed

IN4_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 4. 0 = no change 1 = live status changed

IN4_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 4. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN4_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 4. 0 = inactive 1 = active

IN4_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 4. 0 = inactive 1 = active

IN4_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 4. 0 = inactive 1 = active

STATUS.IN5_MON_STATUS

Input 5 reference monitor status.

Table 37: STATUS.IN5_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN5_MON_STATUS Bit Field Locations

Address

(Hex)

00Dh RESERVED[7]IN5_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN5_NO_AC

TIVITY_STIC

KY[5]

IN5_LOS_ST

ICKY[4]

RESERVED[3]IN5_FREQ_

OFFS_LIM_L

IVE[2]

IN5_NO_AC

TIVITY_LIVE

[1]

IN5_LOS_LI

VE[0]

Page 44

STATUS.IN5_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN5_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 5. 0 = no change 1 = live status changed

IN5_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 5. 0 = no change 1 = live status changed

IN5_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 5. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN5_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 5. 0 = inactive 1 = active

IN5_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 5. 0 = inactive 1 = active

IN5_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 5. 0 = inactive 1 = active

STATUS.IN6_MON_STATUS

Input 6 reference monitor status.

Table 38: STATUS.IN6_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN6_MON_STATUS Bit Field Locations

Address

(Hex)

00Eh RESERVED[7]IN6_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN6_NO_AC

TIVITY_STIC

KY[5]

IN6_LOS_ST

ICKY[4]

RESERVED[3]IN6_FREQ_

OFFS_LIM_L

IVE[2]

IN6_NO_AC

TIVITY_LIVE

[1]

IN6_LOS_LI

VE[0]

Page 45

STATUS.IN6_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN6_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 6. 0 = no change 1 = live status changed

IN6_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 6. 0 = no change 1 = live status changed

IN6_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 6. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN6_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 6. 0 = inactive 1 = active

IN6_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 6. 0 = inactive 1 = active

IN6_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 6. 0 = inactive 1 = active

STATUS.IN7_MON_STATUS

Input 7 reference monitor status.

Table 39: STATUS.IN7_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN7_MON_STATUS Bit Field Locations

Address

(Hex)

00Fh RESERVED[7]IN7_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN7_NO_AC

TIVITY_STIC

KY[5]

IN7_LOS_ST

ICKY[4]

RESERVED[3]IN7_FREQ_

OFFS_LIM_L

IVE[2]

IN7_NO_AC

TIVITY_LIVE

[1]

IN7_LOS_LI

VE[0]

Page 46

STATUS.IN7_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN7_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 7. 0 = no change 1 = live status changed

IN7_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 7. 0 = no change 1 = live status changed

IN7_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 7. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN7_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 7. 0 = inactive 1 = active

IN7_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 7. 0 = inactive 1 = active

IN7_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 7. 0 = inactive 1 = active

STATUS.IN8_MON_STATUS

Input 8 reference monitor status.

Table 40: STATUS.IN8_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN8_MON_STATUS Bit Field Locations

Address

(Hex)

010h RESERVED[7]IN8_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN8_NO_AC

TIVITY_STIC

KY[5]

IN8_LOS_ST

ICKY[4]

RESERVED[3]IN8_FREQ_

OFFS_LIM_L

IVE[2]

IN8_NO_AC

TIVITY_LIVE

[1]

IN8_LOS_LI

VE[0]

Page 47

STATUS.IN8_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN8_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 8. 0 = no change 1 = live status changed

IN8_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 8. 0 = no change 1 = live status changed

IN8_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 8. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN8_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 8. 0 = inactive 1 = active

IN8_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 8. 0 = inactive 1 = active

IN8_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 8. 0 = inactive 1 = active

STATUS.IN9_MON_STATUS

Input 9 reference monitor status.

Table 41: STATUS.IN9_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN9_MON_STATUS Bit Field Locations

Address

(Hex)

011h RESERVED[7]IN9_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN9_NO_AC

TIVITY_STIC

KY[5]

IN9_LOS_ST

ICKY[4]

RESERVED[3]IN9_FREQ_

OFFS_LIM_L

IVE[2]

IN9_NO_AC

TIVITY_LIVE

[1]

IN9_LOS_LI

VE[0]

Page 48

STATUS.IN9_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN9_FREQ_OFFS_LIM_ST

ICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 9. 0 = no change 1 = live status changed

IN9_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 9. 0 = no change 1 = live status changed

IN9_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 9. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN9_FREQ_OFFS_LIM_LI

VE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 9. 0 = inactive 1 = active

IN9_NO_ACTIVITY_LIVE[

R/O 0 No activity live status.

Indicates no activity on input 9. 0 = inactive 1 = active

IN9_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 9. 0 = inactive 1 = active

STATUS.IN10_MON_STATUS

Input 10 reference monitor status.

Table 42: STATUS.IN10_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN10_MON_STATUS Bit Field Locations

Address

(Hex)

012h RESERVED[7]IN10_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN10_NO_A

CTIVITY_STI

CKY[5]

IN10_LOS_S

TICKY[4]

RESERVED[3]IN10_FREQ_

OFFS_LIM_L

IVE[2]

IN10_NO_A

CTIVITY_LIV

E[1]

IN10_LOS_LI

VE[0]

Page 49

STATUS.IN10_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN10_FREQ_OFFS_LIM_S

TICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 10. 0 = no change 1 = live status changed

IN10_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 10. 0 = no change 1 = live status changed

IN10_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 10. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN10_FREQ_OFFS_LIM_L

IVE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 10. 0 = inactive 1 = active

IN10_NO_ACTIVITY_LIVE

[1]

R/O 0 No activity live status.

Indicates no activity on input 10. 0 = inactive 1 = active

IN10_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 10. 0 = inactive 1 = active

STATUS.IN11_MON_STATUS

Input 11 reference monitor status.

Table 43: STATUS.IN11_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN11_MON_STATUS Bit Field Locations

Address

(Hex)

013h RESERVED[7]IN11_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN11_NO_AC TIVITY_STIC

KY[5]

IN11_LOS_S

TICKY[4]

RESERVED[3]IN11_FREQ_

OFFS_LIM_L

IVE[2]

IN11_NO_AC

TIVITY_LIVE

[1]

IN11_LOS_LI

VE[0]

Page 50

STATUS.IN11_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN11_FREQ_OFFS_LIM_S

TICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 11. 0 = no change 1 = live status changed

IN11_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 11. 0 = no change 1 = live status changed

IN11_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 11. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN11_FREQ_OFFS_LIM_L

IVE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 11. 0 = inactive 1 = active

IN11_NO_ACTIVITY_LIVE

[1]

R/O 0 No activity live status.

Indicates no activity on input 11. 0 = inactive 1 = active

IN11_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 11. 0 = inactive 1 = active

STATUS.IN12_MON_STATUS

Input 12 reference monitor status.

Table 44: STATUS.IN12_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN12_MON_STATUS Bit Field Locations

Address

(Hex)

014h RESERVED[7]IN12_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN12_NO_A

CTIVITY_STI

CKY[5]

IN12_LOS_S

TICKY[4]

RESERVED[3]IN12_FREQ_

OFFS_LIM_L

IVE[2]

IN12_NO_A

CTIVITY_LIV

E[1]

IN12_LOS_LI

VE[0]

Page 51

STATUS.IN12_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN12_FREQ_OFFS_LIM_S

TICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 12. 0 = no change 1 = live status changed

IN12_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 12. 0 = no change 1 = live status changed

IN12_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 12. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN12_FREQ_OFFS_LIM_L

IVE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 12. 0 = inactive 1 = active

IN12_NO_ACTIVITY_LIVE

[1]

R/O 0 No activity live status.

Indicates no activity on input 12. 0 = inactive 1 = active

IN12_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 12. 0 = inactive 1 = active

STATUS.IN13_MON_STATUS

Input 13 reference monitor status.

Table 45: STATUS.IN13_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN13_MON_STATUS Bit Field Locations

Address

(Hex)

015h RESERVED[7]IN13_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN13_NO_A

CTIVITY_STI

CKY[5]

IN13_LOS_S

TICKY[4]

RESERVED[3]IN13_FREQ_

OFFS_LIM_L

IVE[2]

IN13_NO_A

CTIVITY_LIV

E[1]

IN13_LOS_LI

VE[0]

Page 52

STATUS.IN13_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN13_FREQ_OFFS_LIM_S

TICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 13. 0 = no change 1 = live status changed

IN13_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 13. 0 = no change 1 = live status changed

IN13_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 13. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN13_FREQ_OFFS_LIM_L

IVE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 13. 0 = inactive 1 = active

IN13_NO_ACTIVITY_LIVE

[1]

R/O 0 No activity live status.

Indicates no activity on input 13. 0 = inactive 1 = active

IN13_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 13. 0 = inactive 1 = active

STATUS.IN14_MON_STATUS

Input 14 reference monitor status.

Table 46: STATUS.IN14_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN14_MON_STATUS Bit Field Locations

Address

(Hex)

016h RESERVED[7]IN14_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN14_NO_A

CTIVITY_STI

CKY[5]

IN14_LOS_S

TICKY[4]

RESERVED[3]IN14_FREQ_

OFFS_LIM_L

IVE[2]

IN14_NO_A

CTIVITY_LIV

E[1]

IN14_LOS_LI

VE[0]

Page 53

STATUS.IN14_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN14_FREQ_OFFS_LIM_S

TICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 14. 0 = no change 1 = live status changed

IN14_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 14. 0 = no change 1 = live status changed

IN14_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 14. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN14_FREQ_OFFS_LIM_L

IVE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 14. 0 = inactive 1 = active

IN14_NO_ACTIVITY_LIVE

[1]

R/O 0 No activity live status.

Indicates no activity on input 14. 0 = inactive 1 = active

IN14_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 14. 0 = inactive 1 = active

STATUS.IN15_MON_STATUS

Input 15 reference monitor status.

Table 47: STATUS.IN15_MON_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN15_MON_STATUS Bit Field Locations

Address

(Hex)

017h RESERVED[7]IN15_FREQ_

D7 D6 D5 D4 D3 D2 D1 D0

OFFS_LIM_

STICKY[6]

IN15_NO_A

CTIVITY_STI

CKY[5]

IN15_LOS_S

TICKY[4]

RESERVED[3]IN15_FREQ_

OFFS_LIM_L

IVE[2]

IN15_NO_A

CTIVITY_LIV

E[1]

IN15_LOS_LI

VE[0]

Page 54

STATUS.IN15_MON_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

IN15_FREQ_OFFS_LIM_S

TICKY[6]

R/O 0 Frequency offset limit sticky bit.

Indicates that frequency offset limit was exceeded for input 15. 0 = no change 1 = live status changed

IN15_NO_ACTIVITY_STIC

KY[5]

R/O 0 No activity sticky bit.

Indicates that no activity was detected for input 15. 0 = no change 1 = live status changed

IN15_LOS_STICKY[4] R/O 0 LOS sticky bit.

Indicates that loss of signal was detected for input 15. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

IN15_FREQ_OFFS_LIM_L

IVE[2]

R/O 0 Frequency offset limit live status.

Indicates that the current frequency offset exceeds the limit for input 15. 0 = inactive 1 = active

IN15_NO_ACTIVITY_LIVE

[1]

R/O 0 No activity live status.

Indicates no activity on input 15. 0 = inactive 1 = active

IN15_LOS_LIVE[0] R/O 0 LOS live status.

Indicates loss of signal on input 15. 0 = inactive 1 = active

STATUS.DPLL0_STATUS

DPLL 0 status.

Table 48: STATUS.DPLL0_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL0_STATUS Bit Field Locations

Address

(Hex)

018h RESERVED[7:6] DPLL0_HOL

D7 D6 D5 D4 D3 D2 D1 D0

DPLL0_LOC

DOVER_STA

TE_CHANG

E_STICKY[5]

K_STATE_C HANGE_STI

CKY[4]

DPLL0_STATE[3:0]

Page 55

8A3xxxx Family Programming Guide

STATUS.DPLL0_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL0_HOLDOVER_STAT

E_CHANGE_STICKY[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL0_LOCK_STATE_CH

ANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL0_STATE[3:0] R/O 0 Current state of DPLL0.

0 = freerun 1 = lockacq 2 = lockrec 3 = locked 4 = holdover 5 = open loop

STATUS.DPLL1_STATUS

DPLL 1 status.

Table 49: STATUS.DPLL1_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL1_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

019h RESERVED[7:6] DPLL1_HOL

DOVER_STA

TE_CHANG

E_STICKY[5]

DPLL1_LOC K_STATE_C HANGE_STI

CKY[4]

STATUS.DPLL1_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL1_HOLDOVER_STAT

E_CHANGE_STICKY[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL1_STATE[3:0]

Page 56

STATUS.DPLL1_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

DPLL1_LOCK_STATE_CH

ANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL1_STATE[3:0] R/O 0 Current state of DPLL1.

0 = freerun 1 = lockacq 2 = lockrec 3 = locked 4 = holdover 5 = open loop

STATUS.DPLL2_STATUS

DPLL 2 status.

Table 50: STATUS.DPLL2_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL2_STATUS Bit Field Locations

Address

(Hex)

01Ah RESERVED[7:6] DPLL2_HOL

D7 D6 D5 D4 D3 D2 D1 D0

DPLL2_LOC

DOVER_STA

TE_CHANG

E_STICKY[5]

K_STATE_C HANGE_STI

CKY[4]

DPLL2_STATE[3:0]

STATUS.DPLL2_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL2_HOLDOVER_STAT

E_CHANGE_STICKY[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL2_LOCK_STATE_CH

ANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL2_STATE[3:0] R/O 0 Current state of DPLL2.

0 = freerun 1 = lockacq 2 = lockrec 3 = locked 4 = holdover 5 = open loop

Page 57

STATUS.DPLL3_STATUS

DPLL 3 status.

Table 51: STATUS.DPLL3_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL3_STATUS Bit Field Locations

Address

(Hex)

01Bh RESERVED[7:6] DPLL3_HOL

D7 D6 D5 D4 D3 D2 D1 D0

DPLL3_LOC

DOVER_STA

TE_CHANG

E_STICKY[5]

K_STATE_C HANGE_STI

CKY[4]

STATUS.DPLL3_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL3_HOLDOVER_STAT

E_CHANGE_STICKY[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL3_LOCK_STATE_CH

ANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL3_STATE[3:0]

DPLL3_STATE[3:0] R/O 0 Current state of DPLL3.

0 = freerun 1 = lockacq 2 = lockrec 3 = locked 4 = holdover 5 = open loop

STATUS.DPLL4_STATUS

DPLL 4 status.

Table 52: STATUS.DPLL4_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL4_STATUS Bit Field Locations

Address

(Hex)

01Ch RESERVED[7:6] DPLL4_HOL

D7 D6 D5 D4 D3 D2 D1 D0

DPLL4_LOC

DOVER_STA

TE_CHANG

E_STICKY[5]

K_STATE_C HANGE_STI

CKY[4]

DPLL4_STATE[3:0]

Page 58

8A3xxxx Family Programming Guide

STATUS.DPLL4_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL4_HOLDOVER_STAT

E_CHANGE_STICKY[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL4_LOCK_STATE_CH

ANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL4_STATE[3:0] R/O 0 Current state of DPLL4.

0 = freerun 1 = lockacq 2 = lockrec 3 = locked 4 = holdover 5 = open loop

STATUS.DPLL5_STATUS

DPLL 5 status.

Table 53: STATUS.DPLL5_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL5_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

01Dh RESERVED[7:6] DPLL5_HOL

DOVER_STA

TE_CHANG

E_STICKY[5]

DPLL5_LOC K_STATE_C HANGE_STI

CKY[4]

STATUS.DPLL5_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL5_HOLDOVER_STAT

E_CHANGE_STICKY[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL5_STATE[3:0]

Page 59

STATUS.DPLL5_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

8A3xxxx Family Programming Guide

DPLL5_LOCK_STATE_CH

ANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL5_STATE[3:0] R/O 0 Current state of DPLL5.

0 = freerun 1 = lockacq 2 = lockrec 3 = locked 4 = holdover 5 = open loop

STATUS.DPLL6_STATUS

DPLL 6 status.

Table 54: STATUS.DPLL6_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL6_STATUS Bit Field Locations

Address

(Hex)

01Eh RESERVED[7:6] DPLL6_HOL

D7 D6 D5 D4 D3 D2 D1 D0

DPLL6_LOC

DOVER_STA

TE_CHANG

E_STICKY[5]

K_STATE_C HANGE_STI

CKY[4]

DPLL6_STATE[3:0]

STATUS.DPLL6_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL6_HOLDOVER_STAT

E_CHANGE_STICKY[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL6_LOCK_STATE_CH

ANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL6_STATE[3:0] R/O 0 Current state of DPLL6.

0 = Freerun 1 = Lockacq 2 = Lockrec 3 = Locked 4 = Holdover 5 = Open loop

Page 60

STATUS.DPLL7_STATUS

DPLL 7 status.

Table 55: STATUS.DPLL7_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL7_STATUS Bit Field Locations

Address

(Hex)

01Fh RESERVED[7:6] DPLL7_HOL

D7 D6 D5 D4 D3 D2 D1 D0

DPLL7_LOC

DOVER_STA

TE_CHANG

E_STICKY[5]

K_STATE_C HANGE_STI

CKY[4]

STATUS.DPLL7_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL7_HOLDOVER_STAT

E_CHANGE_STICKY[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL7_LOCK_STATE_CH

ANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL7_STATE[3:0]

DPLL7_STATE[3:0] R/O 0 Current state of DPLL7.

0 = freerun 1 = lockacq 2 = lockrec 3 = locked 4 = holdover 5 = open loop

STATUS.DPLL_SYS_STATUS

System DPLL status.

Table 56: STATUS.DPLL_SYS_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL_SYS_STATUS Bit Field Locations

Address

(Hex)

020h RESERVED[7]RESERVED DPLL_SYS_

D7 D6 D5 D4 D3 D2 D1 D0

DPLL_SYS_

HOLDOVER _STATE_CH ANGE_STIC

LOCK_STAT E_CHANGE_

STICKY[4]

KY[5]

DPLL_SYS_STATE[3:0]

Page 61

8A3xxxx Family Programming Guide

STATUS.DPLL_SYS_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL_SYS_HOLDOVER_

STATE_CHANGE_STICKY

[5]

R/O 0 Holdover state change sticky bit.

Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state

DPLL_SYS_LOCK_STATE

_CHANGE_STICKY[4]

R/O 0 Lock state change sticky bit.

Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state

DPLL_SYS_STATE[3:0] R/O 0 Current state of SYS_DPLL.

0 = freerun 1 = lockacq 2 = lockrec 3 = locked 4 = holdover 5 = open loop

STATUS.SYS_APLL_STATUS

System APLL status.

Table 57: STATUS.SYS_APLL_STATUS Bit Field Locations and Descriptions

Offset

STATUS.SYS_APLL_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

021h RESERVED[7:5] SYS_APLL_

RESERVED[3:1] SYS_APLL_

LOSS_LOCK

_STICKY[4]

STATUS.SYS_APLL_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

SYS_APLL_LOSS_LOCK_

STICKY[4]

R/O 0 System APLL loss lock sticky bit.

Indicates that loss of lock was detected for system APLL. 0 = no change 1 = live status changed

RESERVED N/A - This field must not be modified from the read value

SYS_APLL_LOSS_LOCK_

LIVE[0]

R/O 0 System APLL loss lock live status.

Indicates that loss of lock is currently detected for system APLL. 0 = locked 1 = unlocked

LOSS_LOCK

_LIVE[0]

Page 62

STATUS.DPLL0_REF_STAT

Indicates which reference is currently selected for tracking.

Table 58: STATUS.DPLL0_REF_STAT Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL0_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

022h RESERVED[7:5] DPLL0_INPUT[4:0]

STATUS.DPLL0_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL0_INPUT[4:0] R/O 0 Current reference input for DPLL 0.

0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4 0x05 = CLK5 0x06 = CLK6 0x07 = CLK7 0x08 = CLK8 0x09 = CLK9 0x0A = CLK10 0x0B = CLK11 0x0C = CLK12 0x0D = CLK13 0x0E = CLK14 0x0F = CLK15 0x10 = write-phase input 0x11 = write-frequency input 0x12 = XO_DPLL 0x1F = no reference

STATUS.DPLL1_REF_STAT

Indicates which reference is currently selected for tracking.

Table 59: STATUS.DPLL1_REF_STAT Bit Field Locations and Descriptions

Offset

STATUS.DPLL1_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

023h RESERVED[7:5] DPLL1_INPUT[4:0]

Page 63

STATUS.DPLL1_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL1_INPUT[4:0] R/O 0 Current reference input for DPLL 1.

8A3xxxx Family Programming Guide

STATUS.DPLL2_REF_STAT

Indicates which reference is currently selected for tracking.

Table 60: STATUS.DPLL2_REF_STAT Bit Field Locations and Descriptions

Offset

STATUS.DPLL2_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

024h RESERVED[7:5] DPLL2_INPUT[4:0]

Page 64

STATUS.DPLL2_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL2_INPUT[4:0] R/O 0 Current reference input for DPLL 2.

8A3xxxx Family Programming Guide

STATUS.DPLL3_REF_STAT

Indicates which reference is currently selected for tracking.

Table 61: STATUS.DPLL3_REF_STAT Bit Field Locations and Descriptions

Offset

STATUS.DPLL3_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

025h RESERVED[7:5] DPLL3_INPUT[4:0]

Page 65

STATUS.DPLL3_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL3_INPUT[4:0] R/O 0 Current reference input for DPLL 3.

8A3xxxx Family Programming Guide

STATUS.DPLL4_REF_STAT

Indicates which reference is currently selected for tracking.

Table 62: STATUS.DPLL4_REF_STAT Bit Field Locations and Descriptions

Offset

STATUS.DPLL4_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

026h RESERVED[7:5] DPLL4_INPUT[4:0]

Page 66

STATUS.DPLL4_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL4_INPUT[4:0] R/O 0 Current reference input for DPLL 4.

8A3xxxx Family Programming Guide

STATUS.DPLL5_REF_STAT

Indicates which reference is currently selected for tracking.

Table 63: STATUS.DPLL5_REF_STAT Bit Field Locations and Descriptions

Offset

STATUS.DPLL5_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

027h RESERVED[7:5] DPLL5_INPUT[4:0]

Page 67

STATUS.DPLL5_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL5_INPUT[4:0] R/O 0 Current reference input for DPLL 5.

8A3xxxx Family Programming Guide

STATUS.DPLL6_REF_STAT

Indicates which reference is currently selected for tracking.

Table 64: STATUS.DPLL6_REF_STAT Bit Field Locations and Descriptions

Offset

STATUS.DPLL6_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

028h RESERVED[7:5] DPLL6_INPUT[4:0]

Page 68

STATUS.DPLL6_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL6_INPUT[4:0] R/O 0 Current reference input for DPLL 6.

8A3xxxx Family Programming Guide

STATUS.DPLL7_REF_STAT

Indicates which reference is currently selected for tracking.

Table 65: STATUS.DPLL7_REF_STAT Bit Field Locations and Descriptions

Offset

STATUS.DPLL7_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

029h RESERVED[7:5] DPLL7_INPUT[4:0]

Page 69

STATUS.DPLL7_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL7_INPUT[4:0] R/O 0 Current reference input for DPLL 7.

8A3xxxx Family Programming Guide

STATUS.DPLL_SYS_REF_STAT

Indicates which reference is currently selected for tracking.

Table 66: STATUS.DPLL_SYS_REF_STAT Bit Field Locations and Descriptions

Offset

STATUS.DPLL_SYS_REF_STAT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

02Ah RESERVED[7:5] DPLL_SYS_INPUT[4:0]

Page 70

STATUS.DPLL_SYS_REF_STAT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL_SYS_INPUT[4:0] R/O 0 Current reference input for system DPLL.

8A3xxxx Family Programming Guide

STATUS.DPLL0_FILTER_STATUS

DPLL 0 loop filter status.

Table 67: STATUS.DPLL0_FILTER_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL0_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

044h FILTER_STATUS[7:0]

045h FILTER_STATUS[15:8]

046h FILTER_STATUS[23:16]

047h FILTER_STATUS[31:24]

048h FILTER_STATUS[39:32]

049h FILTER_STATUS[47:40]

STATUS.DPLL0_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

Page 71

STATUS.DPLL1_FILTER_STATUS

DPLL 1 loop filter status.

Table 68: STATUS.DPLL1_FILTER_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL1_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

04Ch FILTER_STATUS[7:0]

04Dh FILTER_STATUS[15:8]

04Eh FILTER_STATUS[23:16]

04Fh FILTER_STATUS[31:24]

050h FILTER_STATUS[39:32]

051h FILTER_STATUS[47:40]

STATUS.DPLL1_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

STATUS.DPLL2_FILTER_STATUS

DPLL 2 loop filter status.

Table 69: STATUS.DPLL2_FILTER_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL2_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

054h FILTER_STATUS[7:0]

055h FILTER_STATUS[15:8]

056h FILTER_STATUS[23:16]

057h FILTER_STATUS[31:24]

058h FILTER_STATUS[39:32]

059h FILTER_STATUS[47:40]

STATUS.DPLL2_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

Page 72

STATUS.DPLL3_FILTER_STATUS

DPLL 3 loop filter status.

Table 70: STATUS.DPLL3_FILTER_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL3_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

05Ch FILTER_STATUS[7:0]

05Dh FILTER_STATUS[15:8]

05Eh FILTER_STATUS[23:16]

05Fh FILTER_STATUS[31:24]

060h FILTER_STATUS[39:32]

061h FILTER_STATUS[47:40]

STATUS.DPLL3_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

STATUS.DPLL4_FILTER_STATUS

DPLL 4 loop filter status.

Table 71: STATUS.DPLL4_FILTER_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL4_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

064h FILTER_STATUS[7:0]

065h FILTER_STATUS[15:8]

066h FILTER_STATUS[23:16]

067h FILTER_STATUS[31:24]

068h FILTER_STATUS[39:32]

069h FILTER_STATUS[47:40]

STATUS.DPLL4_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

Page 73

STATUS.DPLL5_FILTER_STATUS

DPLL 5 loop filter status.

Table 72: STATUS.DPLL5_FILTER_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL5_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

06Ch FILTER_STATUS[7:0]

06Dh FILTER_STATUS[15:8]

06Eh FILTER_STATUS[23:16]

06Fh FILTER_STATUS[31:24]

070h FILTER_STATUS[39:32]

071h FILTER_STATUS[47:40]

STATUS.DPLL5_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

STATUS.DPLL6_FILTER_STATUS

DPLL 6 loop filter status.

Table 73: STATUS.DPLL6_FILTER_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL6_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

074h FILTER_STATUS[7:0]

075h FILTER_STATUS[15:8]

076h FILTER_STATUS[23:16]

077h FILTER_STATUS[31:24]

078h FILTER_STATUS[39:32]

079h FILTER_STATUS[47:40]

STATUS.DPLL6_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

Page 74

STATUS.DPLL7_FILTER_STATUS

DPLL 7 loop filter status.

Table 74: STATUS.DPLL7_FILTER_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL7_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

07Ch FILTER_STATUS[7:0]

07Dh FILTER_STATUS[15:8]

07Eh FILTER_STATUS[23:16]

07Fh FILTER_STATUS[31:24]

080h FILTER_STATUS[39:32]

081h FILTER_STATUS[47:40]

STATUS.DPLL7_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

STATUS.DPLL_SYS_FILTER_STATUS

Loop filter status of system DPLL .

Table 75: STATUS.DPLL_SYS_FILTER_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL_SYS_FILTER_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

084h FILTER_STATUS[7:0]

085h FILTER_STATUS[15:8]

086h FILTER_STATUS[23:16]

087h FILTER_STATUS[31:24]

088h FILTER_STATUS[39:32]

089h FILTER_STATUS[47:40]

STATUS.DPLL_SYS_FILTER_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FILTER_STATUS[47:0] R/O 0 System DPLL loop filter status.

Fine phase measurement in units of 50/128 picoseconds.

Page 75

8A3xxxx Family Programming Guide

STATUS.USER_GPIO0_TO_7_STATUS

GPIO 0 - 7 level status.

Table 76: STATUS.USER_GPIO0_TO_7_STATUS Bit Field Locations and Descriptions

Offset

STATUS.USER_GPIO0_TO_7_STATUS Bit Field Locations

Address

(Hex)

08Ah GPIO7_LEV

D7 D6 D5 D4 D3 D2 D1 D0

EL[7]

GPIO6_LEV

EL[6]

GPIO5_LEV

EL[5]

GPIO4_LEV

EL[4]

GPIO3_LEV

EL[3]

STATUS.USER_GPIO0_TO_7_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

GPIO7_LEVEL[7] R/O 0 Level of GPIO pin 7.

0 = low 1 = high

GPIO6_LEVEL[6] R/O 0 Level of GPIO pin 6.

0 = low 1 = high

GPIO5_LEVEL[5] R/O 0 Level of GPIO pin 5.

0 = low 1 = high

GPIO4_LEVEL[4] R/O 0 Level of GPIO pin 4.

0 = low 1 = high

GPIO2_LEV

EL[2]

GPIO1_LEV

EL[1]

GPIO0_LEV

EL[0]

GPIO3_LEVEL[3] R/O 0 Level of GPIO pin 3.

0 = low 1 = high

GPIO2_LEVEL[2] R/O 0 Level of GPIO pin 2.

0 = low 1 = high

GPIO1_LEVEL[1] R/O 0 Level of GPIO pin 1.

0 = low 1 = high

GPIO0_LEVEL[0] R/O 0 Level of GPIO pin 0.

0 = low 1 = high

Page 76

8A3xxxx Family Programming Guide

STATUS.USER_GPIO8_TO_15_STATUS

GPIO 8 - 15 level status.

Table 77: STATUS.USER_GPIO8_TO_15_STATUS Bit Field Locations and Descriptions

Offset

STATUS.USER_GPIO8_TO_15_STATUS Bit Field Locations

Address

(Hex)

08Bh GPIO15_LEV

D7 D6 D5 D4 D3 D2 D1 D0

EL[7]

GPIO14_LEV

EL[6]

GPIO13_LEV

EL[5]

GPIO12_LEV

EL[4]

GPIO11_LEV

EL[3]

STATUS.USER_GPIO8_TO_15_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

GPIO15_LEVEL[7] R/O 0 Level of GPIO pin 15.

0 = low 1 = high

GPIO14_LEVEL[6] R/O 0 Level of GPIO pin 14.

0 = low 1 = high

GPIO13_LEVEL[5] R/O 0 Level of GPIO pin 13.

0 = low 1 = high

GPIO12_LEVEL[4] R/O 0 Level of GPIO pin 12.

0 = low 1 = high

GPIO10_LEV

EL[2]

GPIO9_LEV

EL[1]

GPIO8_LEV

EL[0]

GPIO11_LEVEL[3] R/O 0 Level of GPIO pin 11.

0 = low 1 = high

GPIO10_LEVEL[2] R/O 0 Level of GPIO pin 10.

0 = low 1 = high

GPIO9_LEVEL[1] R/O 0 Level of GPIO pin 9.

0 = low 1 = high

GPIO8_LEVEL[0] R/O 0 Level of GPIO pin 8.

0 = low 1 = high

Page 77

STATUS.IN0_MON_FREQ_STATUS

Input 0 reference monitor frequency status and unit.

Table 78: STATUS.IN0_MON_FREQ_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.IN0_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

08Ch FFO[7:0]

08Dh FFO_UNIT[15:14] FFO[13:8]

STATUS.IN0_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

STATUS.IN1_MON_FREQ_STATUS

Input 1 reference monitor frequency status and unit.

Table 79: STATUS.IN1_MON_FREQ_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN1_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

08Eh FFO[7:0]

08Fh FFO_UNIT[15:14] FFO[13:8]

STATUS.IN1_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

Page 78

STATUS.IN2_MON_FREQ_STATUS

Input 2 reference monitor frequency status and unit.

Table 80: STATUS.IN2_MON_FREQ_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.IN2_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

090h FFO[7:0]

091h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN2_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

STATUS.IN3_MON_FREQ_STATUS

Input 3 reference monitor frequency status and unit.

Table 81: STATUS.IN3_MON_FREQ_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN3_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

092h FFO[7:0]

093h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN3_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

Page 79

STATUS.IN4_MON_FREQ_STATUS

Input 4 reference monitor frequency status and unit.

Table 82: STATUS.IN4_MON_FREQ_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.IN4_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

094h FFO[7:0]

095h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN4_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

STATUS.IN5_MON_FREQ_STATUS

Input 5 reference monitor frequency status and unit.

Table 83: STATUS.IN5_MON_FREQ_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN5_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

096h FFO[7:0]

097h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN5_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

Page 80

STATUS.IN6_MON_FREQ_STATUS

Input 6 reference monitor frequency status and unit.

Table 84: STATUS.IN6_MON_FREQ_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.IN6_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

098h FFO[7:0]

099h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN6_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

STATUS.IN7_MON_FREQ_STATUS

Input 7 reference monitor frequency status and unit.

Table 85: STATUS.IN7_MON_FREQ_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN7_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

09Ah FFO[7:0]

09Bh FFO_UNIT[15:14] FFO[13:8]

STATUS.IN7_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

Page 81

STATUS.IN8_MON_FREQ_STATUS

Input 8 reference monitor frequency status and unit.

Table 86: STATUS.IN8_MON_FREQ_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.IN8_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

09Ch FFO[7:0]

09Dh FFO_UNIT[15:14] FFO[13:8]

STATUS.IN8_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

STATUS.IN9_MON_FREQ_STATUS

Input 9 reference monitor frequency status and unit.

Table 87: STATUS.IN9_MON_FREQ_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN9_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

09Eh FFO[7:0]

09Fh FFO_UNIT[15:14] FFO[13:8]

STATUS.IN9_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

Page 82

STATUS.IN10_MON_FREQ_STATUS

Input 10 reference monitor frequency status and unit.

Table 88: STATUS.IN10_MON_FREQ_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.IN10_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0A0h FFO[7:0]

0A1h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN10_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

STATUS.IN11_MON_FREQ_STATUS

Input 11 reference monitor frequency status and unit.

Table 89: STATUS.IN11_MON_FREQ_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN11_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0A2h FFO[7:0]

0A3h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN11_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

Page 83

STATUS.IN12_MON_FREQ_STATUS

Input 12 reference monitor frequency status and unit.

Table 90: STATUS.IN12_MON_FREQ_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.IN12_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0A4h FFO[7:0]

0A5h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN12_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

STATUS.IN13_MON_FREQ_STATUS

Input 13 reference monitor frequency status and unit.

Table 91: STATUS.IN13_MON_FREQ_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN13_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0A6h FFO[7:0]

0A7h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN13_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

Page 84

STATUS.IN14_MON_FREQ_STATUS

Input 14 reference monitor frequency status and unit.

Table 92: STATUS.IN14_MON_FREQ_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.IN14_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0A8h FFO[7:0]

0A9h FFO_UNIT[15:14] FFO[13:8]

STATUS.IN14_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

STATUS.IN15_MON_FREQ_STATUS

Input 15 reference monitor frequency status and unit.

Table 93: STATUS.IN15_MON_FREQ_STATUS Bit Field Locations and Descriptions

Offset

STATUS.IN15_MON_FREQ_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0AAh FFO[7:0]

0ABh FFO_UNIT[15:14] FFO[13:8]

STATUS.IN15_MON_FREQ_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

FFO_UNIT[15:14] R/O 0 Input clock FFO unit enumeration.

0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm

FFO[13:0] R/O 0 Signed 14-bit input clock fractional frequency offset.

Page 85

8A3xxxx Family Programming Guide

STATUS.OUTPUT_TDC_CFG_STATUS

Indicates when the output TDC is ready for use.

Table 94: STATUS.OUTPUT_TDC_CFG_STATUS Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC_CFG_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0ACh RESERVED[7:2] STATE[1:0]

STATUS.OUTPUT_TDC_CFG_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

STATE[1:0] R/O 0 Indicates whether the output TDC is ready to be used.

Output TDC is by default disabled. Need to enable with OUTPUT_TDC_CFG_GBL_2.enable. After enabling, it takes time for the output TDC clock to stabilize. Output TDC is ready for use when in Ready state. 0 = disabled 1 = initializing 2 = ready

STATUS.OUTPUT_TDC0_STATUS

Indicates the hardware output TDC instance assigned and the status code.

Table 95: STATUS.OUTPUT_TDC0_STATUS Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC0_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0ADh VALID[7] RESERVED[6:4] STATUS[3:0]

STATUS.OUTPUT_TDC0_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

VALID[7] R/O 0 Indicates a valid measurement or alignment has met target phase offset.

When go bit is set, valid is cleared. Measurement mode: Indicates when OUTPUT_TDCn_MEASUREMENT is valid. Alignment mode: Indicates when all the alignment targets are within the OUTPUT_TDC_CTRL_1.TARGET_PHASE_OFFSET. 0 = invalid 1 = valid

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8A3xxxx Family Programming Guide

STATUS.OUTPUT_TDC0_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

STATUS[3:0] R/O 0 Status code.

When output TDC is not enabled, this shows 'Disabled'. When OUTPUT_TDC_CTRL_4.GO is set and the configuration is valid, this transitions to 'In progress'. When the operation completes successfully, status transitions back to 'Idle' and OUTPUT_TDC_CTRL_4.GO will be cleared. When OUTPUT_TDC_CTRL_4.GO is set and there is an invalid configuration, then OUTPUT_TDC_CTRL_4.GO will be cleared and this will indicate the error condition encountered. 0 = disabled 1 = idle 2 = in progress 3 = error - invalid source/target 4 = error - non-uniform master divider freq 5 = error - start failed 6 = error - measurement timeout

STATUS.OUTPUT_TDC1_STATUS

Indicates the hardware output TDC instance assigned and the status code.

Table 96: STATUS.OUTPUT_TDC1_STATUS Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC1_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0AEh VALID[7] RESERVED[6:4] STATUS[3:0]

STATUS.OUTPUT_TDC1_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

VALID[7] R/O 0 Indicates a valid measurement or alignment has met target phase offset.

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8A3xxxx Family Programming Guide

STATUS.OUTPUT_TDC1_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

STATUS[3:0] R/O 0 Status code.

STATUS.OUTPUT_TDC2_STATUS

Indicates the hardware output TDC instance assigned and the status code.

Table 97: STATUS.OUTPUT_TDC2_STATUS Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC2_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0AFh VALID[7] RESERVED[6:4] STATUS[3:0]

STATUS.OUTPUT_TDC2_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

VALID[7] R/O 0 Indicates a valid measurement or alignment has met target phase offset.

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8A3xxxx Family Programming Guide

STATUS.OUTPUT_TDC2_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

STATUS[3:0] R/O 0 Status code.

STATUS.OUTPUT_TDC3_STATUS

Indicates the hardware output TDC instance assigned and the status code.

Table 98: STATUS.OUTPUT_TDC3_STATUS Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC3_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0B0h VALID[7] RESERVED[6:4] STATUS[3:0]

STATUS.OUTPUT_TDC3_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

VALID[7] R/O 0 Indicates a valid measurement or alignment has met target phase offset.

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8A3xxxx Family Programming Guide

STATUS.OUTPUT_TDC3_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

STATUS[3:0] R/O 0 Status code.

STATUS.OUTPUT_TDC0_MEASUREMENT

Indicates output TDC 0 measurement.

Table 99: STATUS.OUTPUT_TDC0_MEASUREMENT Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC0_MEASUREMENT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0B4h PHASE[7:0]

0B5h PHASE[15:8]

0B6h PHASE[23:16]

0B7h PHASE[31:24]

0B8h PHASE[39:32]

0B9h PHASE[47:40]

STATUS.OUTPUT_TDC0_MEASUREMENT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PHASE[47:0] R/O 0 Output TDC measurement.

Signed 48-bit integer in picoseconds. Measurement = sum of samples / number of samples A sample is collected every 100us. Positive value indicates the target edge leads the source edge. i.e.. source edge is to the left of the target edge

Page 90

8A3xxxx Family Programming Guide

STATUS.OUTPUT_TDC1_MEASUREMENT

Indicates output TDC 1 measurement.

Table 100: STATUS.OUTPUT_TDC1_MEASUREMENT Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC1_MEASUREMENT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0C4h PHASE[7:0]

0C5h PHASE[15:8]

0C6h PHASE[23:16]

0C7h PHASE[31:24]

0C8h PHASE[39:32]

0C9h PHASE[47:40]

STATUS.OUTPUT_TDC1_MEASUREMENT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PHASE[47:0] R/O 0 Output TDC measurement.

STATUS.OUTPUT_TDC2_MEASUREMENT

Indicates output TDC 2 measurement.

Table 101: STATUS.OUTPUT_TDC2_MEASUREMENT Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC2_MEASUREMENT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0CCh PHASE[7:0]

0CDh PHASE[15:8]

0CEh PHASE[23:16]

0CFh PHASE[31:24]

0D0h PHASE[39:32]

0D1h PHASE[47:40]

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8A3xxxx Family Programming Guide

STATUS.OUTPUT_TDC2_MEASUREMENT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PHASE[47:0] R/O 0 Output TDC measurement.

STATUS.OUTPUT_TDC3_MEASUREMENT

Indicates output TDC 3 measurement.

Table 102: STATUS.OUTPUT_TDC3_MEASUREMENT Bit Field Locations and Descriptions

Offset

STATUS.OUTPUT_TDC3_MEASUREMENT Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0D4h PHASE[7:0]

0D5h PHASE[15:8]

0D6h PHASE[23:16]

0D7h PHASE[31:24]

0D8h PHASE[39:32]

0D9h PHASE[47:40]

STATUS.OUTPUT_TDC3_MEASUREMENT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

PHASE[47:0] R/O 0 Output TDC measurement.

Page 92

STATUS.DPLL0_PHASE_STATUS

Phase offset at output of decimator.

Table 103: STATUS.DPLL0_PHASE_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL0_PHASE_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0DCh DPLL0_PHASE_STATUS[7:0]

0DDh DPLL0_PHASE_STATUS[15:8]

0DEh DPLL0_PHASE_STATUS[23:16]

0DFh DPLL0_PHASE_STATUS[31:24]

0E0h RESERVED[39:36] DPLL0_PHASE_STATUS[35:32]

STATUS.DPLL0_PHASE_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL0_PHASE_STATUS[

R/O 0 Signed 36-bit phase offset in ITDC_UIs.

35:0]

STATUS.DPLL1_PHASE_STATUS

Phase offset at output of decimator.

Table 104: STATUS.DPLL1_PHASE_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL1_PHASE_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0E4h DPLL1_PHASE_STATUS[7:0]

0E5h DPLL1_PHASE_STATUS[15:8]

0E6h DPLL1_PHASE_STATUS[23:16]

0E7h DPLL1_PHASE_STATUS[31:24]

0E8h RESERVED[39:36] DPLL1_PHASE_STATUS[35:32]

STATUS.DPLL1_PHASE_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL1_PHASE_STATUS[

R/O 0 Signed 36-bit phase offset in ITDC_UIs.

35:0]

Page 93

STATUS.DPLL2_PHASE_STATUS

Phase offset at output of decimator.

Table 105: STATUS.DPLL2_PHASE_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL2_PHASE_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0ECh DPLL2_PHASE_STATUS[7:0]

0EDh DPLL2_PHASE_STATUS[15:8]

0EEh DPLL2_PHASE_STATUS[23:16]

0EFh DPLL2_PHASE_STATUS[31:24]

0F0h RESERVED[39:36] DPLL2_PHASE_STATUS[35:32]

STATUS.DPLL2_PHASE_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL2_PHASE_STATUS[

R/O 0 Signed 36-bit phase offset in ITDC_UIs.

35:0]

STATUS.DPLL3_PHASE_STATUS

Phase offset at output of decimator.

Table 106: STATUS.DPLL3_PHASE_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL3_PHASE_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0F4h DPLL3_PHASE_STATUS[7:0]

0F5h DPLL3_PHASE_STATUS[15:8]

0F6h DPLL3_PHASE_STATUS[23:16]

0F7h DPLL3_PHASE_STATUS[31:24]

0F8h RESERVED[39:36] DPLL3_PHASE_STATUS[35:32]

STATUS.DPLL3_PHASE_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL3_PHASE_STATUS[

R/O 0 Signed 36-bit phase offset in ITDC_UIs.

35:0]

Page 94

STATUS.DPLL4_PHASE_STATUS

Phase offset at output of decimator.

Table 107: STATUS.DPLL4_PHASE_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL4_PHASE_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

0FCh DPLL4_PHASE_STATUS[7:0]

0FDh DPLL4_PHASE_STATUS[15:8]

0FEh DPLL4_PHASE_STATUS[23:16]

0FFh DPLL4_PHASE_STATUS[31:24]

100h RESERVED[39:36] DPLL4_PHASE_STATUS[35:32]

STATUS.DPLL4_PHASE_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL4_PHASE_STATUS[

R/O 0 Signed 36-bit phase offset in ITDC_UIs.

35:0]

STATUS.DPLL5_PHASE_STATUS

Phase offset at output of decimator.

Table 108: STATUS.DPLL5_PHASE_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL5_PHASE_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

104h DPLL5_PHASE_STATUS[7:0]

105h DPLL5_PHASE_STATUS[15:8]

106h DPLL5_PHASE_STATUS[23:16]

107h DPLL5_PHASE_STATUS[31:24]

108h RESERVED[39:36] DPLL5_PHASE_STATUS[35:32]

STATUS.DPLL5_PHASE_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL5_PHASE_STATUS[

R/O 0 Signed 36-bit phase offset in ITDC_UIs.

35:0]

Page 95

STATUS.DPLL6_PHASE_STATUS

Phase offset at output of decimator.

Table 109: STATUS.DPLL6_PHASE_STATUS Bit Field Locations and Descriptions

8A3xxxx Family Programming Guide

Offset

STATUS.DPLL6_PHASE_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

10Ch DPLL6_PHASE_STATUS[7:0]

10Dh DPLL6_PHASE_STATUS[15:8]

10Eh DPLL6_PHASE_STATUS[23:16]

10Fh DPLL6_PHASE_STATUS[31:24]

110h RESERVED[39:36] DPLL6_PHASE_STATUS[35:32]

STATUS.DPLL6_PHASE_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL6_PHASE_STATUS[

R/O 0 Signed 36-bit phase offset in ITDC_UIs.

35:0]

STATUS.DPLL7_PHASE_STATUS

Phase offset at output of decimator.

Table 110: STATUS.DPLL7_PHASE_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL7_PHASE_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

114h DPLL7_PHASE_STATUS[7:0]

115h DPLL7_PHASE_STATUS[15:8]

116h DPLL7_PHASE_STATUS[23:16]

117h DPLL7_PHASE_STATUS[31:24]

118h RESERVED[39:36] DPLL7_PHASE_STATUS[35:32]

STATUS.DPLL7_PHASE_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

RESERVED N/A - This field must not be modified from the read value

DPLL7_PHASE_STATUS[

R/O 0 Signed 36-bit phase offset in ITDC_UIs.

35:0]

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8A3xxxx Family Programming Guide

STATUS.DPLL0_PHASE_PULL_IN_STATUS

DPLL0 phase pull-in status

Table 111: STATUS.DPLL0_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL0_PHASE_PULL_IN_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

11Ch REMAINING_TIME[7:0]

STATUS.DPLL0_PHASE_PULL_IN_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REMAINING_TIME[7:0] R/O 0 Unsigned 8-bit phase pull-in time to finish in seconds.

If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds. If the value = 255, it implies the actual remaining time >= 255 seconds.

STATUS.DPLL1_PHASE_PULL_IN_STATUS

DPLL1 phase pull-in status

Table 112: STATUS.DPLL1_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL1_PHASE_PULL_IN_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

11Dh REMAINING_TIME[7:0]

STATUS.DPLL1_PHASE_PULL_IN_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REMAINING_TIME[7:0] R/O 0 Unsigned 8-bit phase pull-in time to finish in seconds.

If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds. If the value = 255, it implies the actual remaining time >= 255 seconds.

STATUS.DPLL2_PHASE_PULL_IN_STATUS

DPLL2 phase pull-in status

Table 113: STATUS.DPLL2_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL2_PHASE_PULL_IN_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

11Eh REMAINING_TIME[7:0]

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8A3xxxx Family Programming Guide

STATUS.DPLL2_PHASE_PULL_IN_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REMAINING_TIME[7:0] R/O 0 Unsigned 8-bit phase pull-in time to finish in seconds.

If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds. If the value = 255, it implies the actual remaining time >= 255 seconds.

STATUS.DPLL3_PHASE_PULL_IN_STATUS

DPLL3 phase pull-in status

Table 114: STATUS.DPLL3_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL3_PHASE_PULL_IN_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

11Fh REMAINING_TIME[7:0]

STATUS.DPLL3_PHASE_PULL_IN_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REMAINING_TIME[7:0] R/O 0 Unsigned 8-bit phase pull-in time to finish in seconds.

If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds. If the value = 255, it implies the actual remaining time >= 255 seconds.

STATUS.DPLL4_PHASE_PULL_IN_STATUS

DPLL4 phase pull-in status

Table 115: STATUS.DPLL4_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL4_PHASE_PULL_IN_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

120h REMAINING_TIME[7:0]

STATUS.DPLL4_PHASE_PULL_IN_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REMAINING_TIME[7:0] R/O 0 Unsigned 8-bit phase pull-in time to finish in seconds.

If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds. If the value = 255, it implies the actual remaining time >= 255 seconds.

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8A3xxxx Family Programming Guide

STATUS.DPLL5_PHASE_PULL_IN_STATUS

DPLL5 phase pull-in status

Table 116: STATUS.DPLL5_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL5_PHASE_PULL_IN_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

121h REMAINING_TIME[7:0]

STATUS.DPLL5_PHASE_PULL_IN_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REMAINING_TIME[7:0] R/O 0 Unsigned 8-bit phase pull-in time to finish in seconds.

If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds. If the value = 255, it implies the actual remaining time >= 255 seconds.

STATUS.DPLL6_PHASE_PULL_IN_STATUS

DPLL6 phase pull-in status

Table 117: STATUS.DPLL6_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL6_PHASE_PULL_IN_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

122h REMAINING_TIME[7:0]

STATUS.DPLL6_PHASE_PULL_IN_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REMAINING_TIME[7:0] R/O 0 Unsigned 8-bit phase pull-in time to finish in seconds.

If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds. If the value = 255, it implies the actual remaining time >= 255 seconds.

STATUS.DPLL7_PHASE_PULL_IN_STATUS

DPLL7 phase pull-in status

Table 118: STATUS.DPLL7_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions

Offset

STATUS.DPLL7_PHASE_PULL_IN_STATUS Bit Field Locations

Address

(Hex)

D7 D6 D5 D4 D3 D2 D1 D0

123h REMAINING_TIME[7:0]

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8A3xxxx Family Programming Guide

STATUS.DPLL7_PHASE_PULL_IN_STATUS Bit Field Descriptions

Bit Field Name Field Type Default Value Description

REMAINING_TIME[7:0] R/O 0 Unsigned 8-bit phase pull-in time to finish in seconds.

If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds. If the value = 255, it implies the actual remaining time >= 255 seconds.

Module: GPIO_USER_CONTROL

Configures the controls of the GPIO .

Table 119: GPIO_USER_CONTROL Register Index

Offset

(Hex)

000h GPIO_USER_CONTROL.GPIO0_TO_7_OUT GPIO output control.

001h GPIO_USER_CONTROL.GPIO8_TO_15_OUT GPIO output control.

Individual Register Name Register Description

GPIO_USER_CONTROL.GPIO0_TO_7_OUT

Write these bits to define the level on a GPIO output pin when configured for user output control.

Table 120: GPIO_USER_CONTROL.GPIO0_TO_7_OUT Bit Field Locations and Descriptions

Offset

GPIO_USER_CONTROL.GPIO0_TO_7_OUT Bit Field Locations

Address

(Hex)

000h GPIO7_DRIV

D7 D6 D5 D4 D3 D2 D1 D0

E_LEVEL[7]

GPIO6_DRIV

E_LEVEL[6]

GPIO5_DRIV

E_LEVEL[5]

GPIO4_DRIV

E_LEVEL[4]

GPIO3_DRIV

E_LEVEL[3]

GPIO2_DRIV

E_LEVEL[2]

GPIO1_DRIV

E_LEVEL[1]

GPIO_USER_CONTROL.GPIO0_TO_7_OUT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

GPIO7_DRIVE_LEVEL[7] R/W 0 GPIO pin 7 drive level.

Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high

GPIO6_DRIVE_LEVEL[6] R/W 0 GPIO pin 6 drive level.

Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high

GPIO0_DRIV

E_LEVEL[0]

GPIO5_DRIVE_LEVEL[5] R/W 0 GPIO pin 5 drive level.

Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high

Page 100

GPIO_USER_CONTROL.GPIO0_TO_7_OUT Bit Field Descriptions

Bit Field Name Field Type Default Value Description

GPIO4_DRIVE_LEVEL[4] R/W 0 GPIO pin 4 drive level.

Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high

GPIO3_DRIVE_LEVEL[3] R/W 0 GPIO pin 3 drive level.

Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high

GPIO2_DRIVE_LEVEL[2] R/W 0 GPIO pin 2 drive level.

Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high

GPIO1_DRIVE_LEVEL[1] R/W 0 GPIO pin 1 drive level.

Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high

8A3xxxx Family Programming Guide

GPIO0_DRIVE_LEVEL[0] R/W 0 GPIO pin 0 drive level.

Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high

GPIO_USER_CONTROL.GPIO8_TO_15_OUT

Write these bits to define the level on a GPIO output pin when configured for user output control.

TRIGGER: Writing to this byte triggers a read and activation in hardware of all the bytes of the GPIO_USER_CONTROL module.

Table 121: GPIO_USER_CONTROL.GPIO8_TO_15_OUT Bit Field Locations and Descriptions

Offset

GPIO_USER_CONTROL.GPIO8_TO_15_OUT Bit Field Locations

Address

(Hex)

001h GPIO15_DRI

D7 D6 D5 D4 D3 D2 D1 D0

GPIO9_DRIV

E_LEVEL[1]

VE_LEVEL[7

]

GPIO14_DRI VE_LEVEL[6

]

GPIO13_DRI

VE_LEVEL[5

]

GPIO12_DRI VE_LEVEL[4

]

GPIO11_DRI VE_LEVEL[3

]

GPIO10_DRI

VE_LEVEL[2

]

GPIO8_DRIV

E_LEVEL[0]