IDT 89HPES48T12G2 User Manual

®

IDT® 89HPES48T12G2

®

PCI Express

Switch

User Manual

April 2013

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: [phone] • [phone] • FAX: [phone]

©2013 Integrated Device Technology, Inc.

Printed in U.S.A.

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

GENERAL DISCLAIMER

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CODE DISCLAIMER

LIFE SUPPORT POLICY

Notes

®

About This Manual

Introduction

This user manual includes hardware and software information on the 89HPES48T12G2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.

Finding Additional Information

Information not included in this manual such as mechanicals, package pin-outs, and electrical character­istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.

Content Summary

Chapter 1, “PES48T12G2 Device Overview,” provides a complete introduction to the performance
capabilities of the 89HPES48T12G2. Included in this chapter is a summary of features for the device as well
as a system block diagram and pin description.

Chapter 2, “Architectural Overview,” provides a high level architectural overview of the PES48T12G2
device.

Chapter 3, “Switch Core,” provides a description of the PES48T12G2 switch core.

Chapter 4, “Clocking,” provides a description of the PES48T12G2 clocking architecture.

Chapter 5, “Reset and Initialization,” describes the PES48T12G2 reset operations and initialization

procedure.

Chapter 6, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.

Chapter 7, “SerDes,” describes basic functionality and controllability associated with the Serialiazer­Deserializer (SerDes) block in PES48T12G2 ports.

Chapter 7, “Theory of Operation,” describes the general operational behavior of the PES48T12G2.

Chapter 9, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in

the PES48T12G2.

Chapter 10, “Power Management,” describes the power management capability structure located in
the configuration space of each PCI-to-PCI bridge in the PES48T12G2.

Chapter 11, “General Purpose I/O,” describes how the 9 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.

Chapter 12, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the
PES48T12G2.

Chapter 13, “Multicast,” describes how the multicast capability enables a single TLP to be forwarded
to multiple destinations.

Chapter 14, “Register Organization,” describes the organization of all the software visible registers in
the PES48T12G2 and provides the address space for those registers.

Chapter 15, “PCI to PCI Bridge and Proprietary Port Specific Registers,” lists the Type 1 configura­tion header registers in the PES48T12G2 and provides a description of each bit in those registers.

Chapter 16, “Switch Control and Status Registers,” lists the switch control and status registers in the
PES48T12G2 and provides a description of each bit in those registers.

PES48T12G2 User Manual 1 April 5, 2013

IDT

Notes

1 2 3 4

high-to-low

transition

low-to-high

transition

single clock cycle

Chapter 17, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.

Signal Nomenclature

To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.

To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter­preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.

Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.

Figure 1 Signal Transitions

Numeric Representations

To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.

Data Units

The following data unit terminology is used in this document.

Ter m Words By tes Bi ts

Byte 1/2 1 8

PES48T12G2 User Manual 2 April 5, 2013

Word 1 2 16

Doubleword (Dword) 2 4 32

Quadword (Qword) 4 8 64

Table 1 Data Unit Terminology

IDT

Notes

0 1 2 3

bit 0bit 31

Address of Bytes within Words: Big Endian

3 2 1 0

bit 0bit 31

Address of Bytes within Words: Little Endian

In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double­words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.

The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.

Register Terminology

tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial­ization. See Table 2.

Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

Software in the context of this register terminology refers to modifications made by PCIe root configura-

Type Abbreviation Description

Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms

such as pin strapping or serial EEPROM. (System firmware hard­ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.

Read Only and Clear RC Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.

Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.

Reserved Reserved The value read from a reserved register/bit is undefined. Thus,

software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi­tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi­tions and then written back.

Table 2 Register Terminology (Sheet 1 of 2)

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Notes

Type Abbreviation Description

Read Only RO Software can only read registers/bits with this attribute. Contents

are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.

Read and Write RW Software can both read and write bits with this attribute.

Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.

However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.

Read and Write when
Unlocked

Sticky Sticky Register/bits with this designation take on their initial value as a

RWL Software can read the register/bits with this attribute. Writing to

register/bits with this attribute will only cause the value to be modi­fied if the REGUNLOCK bit in the SWCTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis­ter/bits are effectively read-only.
Fields with this attribute are implicitly SWSticky (i.e., their value is
preserved across all resets, except switch fundamental reset).

result of a switch fundamental reset or fundamental reset. Other
resets have no effect.

Switch Sticky SWSticky Register/bits with this designation take on their initial value as a

result of a switch fundamental reset. Other resets have no effect.

Table 2 Register Terminology (Sheet 2 of 2)

Use of Hypertext

In Chapter 14, Tables 14.4, 14.5 and 14.6 contain register names and page numbers highlighted in blue
under the Register Definition column. In pdf files, users can jump from this source table directly to the regis­ters by clicking on the register name in the source table. Each register name in the table is linked directly to
the appropriate register in the register section of Chapters and 16. To return to the source table after having
jumped to the register section, click on the same register name (in blue) in the register section.

Reference Documents

[1] PCI Express Base Specification Revision 2.0., December 20, 2006, PCI-SIG.

[2] Multicast Engineering Change Notice to [1]., May 8, 2008, PCI-SIG.

[3] Internal Error Reporting Engineering Change Notice to [1]., April 24, 2008, PCI-SIG.

[4] SMBus Specification, Version 2.0, August 3, 2000, SBS Implementers Forum.

Revision History

November 5, 2008: Initial publication of preliminary user manual.

January 12, 2009: On page 3-6, added last sentence to Port Arbitration section on page 3-6. In Table

8.10, under Description for Function in D3Hot state, changed reference to 10-1 instead of 9-1.

January 22, 2009: In Chapter 12, Table 12.15, changed the description for bit USA. In Chapter 15,
PCIEDCTL register, changed the description for bit ERO.

PES48T12G2 User Manual 4 April 5, 2013

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Notes

February 9, 2009: In Chapter 1: Table 1.4, for Port 0 Serial Data Receive/Transmit signals, deleted
statement that port 0 is the upstream port; Table 1.8, revised Description for SWMODE[3:0]; Table 1.10,
added “3.3V is preferred” for signal V

I/O. In Chapter 6, deleted footnote in 2nd paragraph under section

DD

Software Management of Link Speed.

February 18, 2009: In Chapter 6, added a note under L2/L3 Ready in Link States section. In Chapter
15, modified Description for REG and EREG fields in the ECFGADDR register, GADDR field in the
GASAADDR register, DATA field in the GASADATA register, and RSE field in the SECSTS register. In
Chapters 14 and 15, added PHYLSTATE0 (0x540) register.

March 18, 2009: In Table 12.11, the address value was changed from zero to 1 for bits 3 and 5.

April 9, 2009: Changes made in register fields in Chapters 15 and 16 (Bridge and Switch Registers), to

conform with device specification and validation.

April 21, 2009: In Table 1.8, deleted reference to pull-down value of 251K ohm resistor for all
PxMERGEN pins. In Footnote 1 for Table 1.11, internal resistor pull-down value was changed to 91K ohms.
In Chapter 16, changed “Bit x in this field corresponds to GPIO pin (x+31)” to “Bit x in this field corresponds
to GPIO pin (x+32)” in the GPIOFUNC1, GPIOCFG1, and GPIOD1 registers. Changed title for Table 12.11.

April 27, 2009: ZB silicon was added to Table 1.3.

May 6, 2009: In Chapter 5, under section Switch Fundamental Reset, deleted bullet referencing

SWFRST bit.

May 14, 2009: In Table 1.11, changed CML to HCSL for PCIe reference clocks.

May 28, 2009: In Chapter 6, revised Crosslink section. In Chapter 7, Tables 7.2, 7.3 and 7.4, changed

column title of TX_EQ_MODE to reflect the register field used to control TX equalization depending on the
operating mode of the link (e.g., TX_EQ_3DBG1). In Chapter 12, revised Introduction section and deleted
references to LAERR bit in Table 12.2, Table 12.15, and Figure 12.8. In Chapter 14, added section Partial­Byte Access to Word and DWord Registers. In Chapter 16, added bit BDISCARD to the Switch Control
register and changed bit 26 in the SMBus Status register from LAERR to Reserved.

June 16, 2009: In Chapters 5 and 6, added footnote explaining LTSSM reference. In Chapter 16,
removed reference to RDETECT bit in Hot-Plug Configuration Control register.

June 22, 2009: In Table 1.11, System Pins section, changed GCLKFSEL to pull-down.

July 30, 2009: In Chapter 16, Switch Registers, changed bits 19:18 in the SMBus Control register from

SSMBMODE to Reserved.

August 17, 2009: In Chapter 16, Switch Registers, revised the description for the RXEQZ and RXEQB
fields in the SerDes x Receiver Equalization Lane Control register.

September 22, 2009: Modified Chapter 4, Clocking. In Chapter 7, SerDes, modified Table 7.2 and
added Note before Figure 7.1. Modified section Transaction Layer Error Pollution in Chapter 9, Theory of
Operation. In Chapter 16, Switch Registers, modified description of the LANESEL field in the SxCTL
register and modified description of the RXEQZ and RXEQB fields in the SxRXEQLCTL register.

September 28, 2009: ZC silicon was added to Table 1.3.

November 6, 2009: In Chapter 3, Switch Core, modified text and figures in Operation section. In

Chapter 4, Clocking, modified Introduction section. In Chapter 14, Register Organization, added new
section Register Side-Effects. In Chapter 15, Bridge Registers, modified description for DVADJ bit in the
Requester Metering Control register.

November 11, 2009: In Chapter 7, SerDes, deleted settings greater than 0x0F in Tables 7.7 and 7.8.

December 7, 2009: In Chapter 6, added reference in section Link width Negotiation to the MAXLNK-

WDTH field in the PCI Express Link Capabilities register. In Chapter 14, added new sub-section Limitations
under Register Side-Effects. In Chapter 15, modified Description for the MAXLNKWDTH field in the
PCIELCAP register and added field RCVD_OVRD to the SerDes Configuration register. In Chapter 16,
added field DDDNC to the Switch Control register and modified Description for the BLANK field in the
SMBus Status register.

PES48T12G2 User Manual 5 April 5, 2013

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Notes

December 14, 2009: Deleted all references to support for Weighted Round Robin arbitration.

January 21, 2010: Removed Preliminary from title.

February 10, 2010: In Chapter 5, added new Port Merging section. In Table 1.8, added reference to Port

Merging section in PxxMERGEN pin description.

March 31, 2010: In Chapter 14, Table 14.6, added the following register names and cross-references for
ports 8, 9, 12, 13: SWPORTxCTL, SWPORTxSTS, SxCTL, SxTXLCTL0, SxTXLCTL1, SxRXEQLCTL.

December 8, 2010: In Chapter 13, corrected ports specified for I/O Expander 10 in Table 12.3. In
Chapter 17, deleted PERSTN, GLK1, and SMODE from Table 17.1.

February 2, 2011: In Table 8.13, revised text in Action Taken column for ACS Source Validation. In
Chapter 15, added footnote to STAS bit in PCISTS and SECSTS registers.

May 18, 2011: In Chapter 7, section Low-Swing Transmitter Voltage Mode, the reference in the first
paragraph to the LSE bit being in the SerDes Control register was changed to the SerDes Configuration
register.

June 28, 2011: In Chapter 16, added bit 26,

register.

TX_SLEW_C, to the SerDes x Transmitter Lane Control 0

July 8, 2011: In Chapter 15, removed table footnotes from PCISTS and SECSTS registers, added
Reserved bits 31:24 to AERUEM and AERUESV registers, and added last sentence to each description in
the PCIESCTLIV register. In Chapter 16, added FEN and

FCAPSEL fields to SWPART[x]CTL register and

SWPORT[x]CTL registers, added PFAILOVER and SFAILOVER fields to SWPART[X]STS register and
SWPORT[x]STS register, adjusted bit fields in GPIOCFG1 and GPIOD1 registers.

August 31, 2011: In Chapter 2, page 2-1, added bullet to explain behavior of an odd numbered port
when it is merged with its even counterpart. In Chapter 6, revised text in section Link Width Negotiation in
the Presence of Bad Lanes. In Chapter 7, revised Table 7.1 and text under this table, revised text in section
Programmable De-emphasis Adjustment, added headings to Figures 7.1 through 7.3, and added paragraph
after Figure 7.3. In Chapter 13, revised text in the Introduction section. In Chapter 15, changed type of
MAXLNKSPD field in the PCIELCAP register from RWL to RO, revised Description for MAXGROUP field in
MCCAP register, changed lower to upper in Description for MCBLKALLH and MCBLKUTH registers. In
Chapter 17, deleted references to Failover capability from several registers.

September 9, 2011: In Chapter 7, added additional reference in last paragraph of section Driver Voltage
Level and Amplitude Boost.

February 7, 2012: In Chapter 12, added footnote for RERR and WERR bits in Table 12.13.

February 23, 2012: Added paragraph after Table 12.13 to explain use of DWord addresses.

January 31, 2013: In Figure 12.8, changed No-ack to Ack between DATALM and DATAUM.

April 5, 2013: In Chapter 16, added USSBRDELAY register.

PES48T12G2 User Manual 6 April 5, 2013

Notes

Table of Contents

®

About This Manual

Introduction ....................................................................................................................................1

Content Summary ..........................................................................................................................1

Signal Nomenclature .....................................................................................................................2

Numeric Representations ..............................................................................................................2

Data Units ...................................................................................................................................... 2

Register Terminology ..................................................................................................................... 3

Use of Hypertext ............................................................................................................................ 4

Reference Documents ................................................................................................................... 4

Revision History .............................................................................................................................4

PES48T12G2 Device Overview

Introduction .....................................................................................................................................1-1

Features.......................................................................................................................................... 1-1

Logic Diagram................................................................................................................................. 1-5

System Identification....................................................................................................................... 1-6

Vendor ID................................................................................................................................1-6

Device ID ................................................................................................................................1-6

Revision ID .............................................................................................................................1-6

JTAG ID..................................................................................................................................1-6

SSID/SSVID............................................................................................................................1-6

Device Serial Number Enhanced Capability........................................................................... 1-6

Pin Description................................................................................................................................ 1-7

Pin Characteristics........................................................................................................................1-13

Architectural Overview

Introduction .....................................................................................................................................2-1

Logical View.................................................................................................................................... 2-2

Switch Core

Introduction .....................................................................................................................................3-1

Switch Core Architecture ................................................................................................................3-1

Ingress Buffer .........................................................................................................................3-1

Egress Buffer.......................................................................................................................... 3-2

Crossbar Interconnect ............................................................................................................3-3

Datapaths ...............................................................................................................................3-3

Packet Ordering.............................................................................................................................. 3-3

Arbitration........................................................................................................................................3-4

Port Arbitration........................................................................................................................ 3-5

Cut-Through Routing ......................................................................................................................3-5

Request Metering............................................................................................................................3-7

Operation................................................................................................................................3-9

Completion Size Estimation.................................................................................................. 3-11

Internal Errors ...............................................................................................................................3-12

Switch Time-Outs .................................................................................................................3-13

Memory SECDED ECC Protection....................................................................................... 3-13

End-to-End Data Path Parity Protection ...............................................................................3-13

PES48T12G2 User Manual i April 5, 2013

IDT Table of Contents

Notes

Clocking

Introduction ..................................................................................................................................... 4-1

Port Clocking Mode ........................................................................................................................4-1

Reset and Initialization

Introduction ..................................................................................................................................... 5-1

Boot Configuration Vector............................................................................................................... 5-1

Switch Fundamental Reset............................................................................................................. 5-2

Hot Resets ...................................................................................................................................... 5-5

Hot Reset................................................................................................................................ 5-5

Upstream Secondary Bus Reset ............................................................................................5-5

Downstream Secondary Bus Reset........................................................................................ 5-6

Port Merging ................................................................................................................................... 5-6

Link Operation

Introduction ..................................................................................................................................... 6-1

Polarity Inversion ............................................................................................................................6-1

Lane Reversal................................................................................................................................. 6-1

Link Width Negotiation.................................................................................................................... 6-5

Link Width Negotiation in the Presence of Bad Lanes ...........................................................6-6

Dynamic Link Width Reconfiguration..............................................................................................6-6

Link Speed Negotiation................................................................................................................... 6-6

Link Speed Negotiation in the PES48T12G2 .........................................................................6-7

Software Management of Link Speed ....................................................................................6-9

Link Retraining.............................................................................................................................. 6-10

Link Down ..................................................................................................................................... 6-10

Slot Power Limit Support ..............................................................................................................6-11

Upstream Port ......................................................................................................................6-11

Downstream Port..................................................................................................................6-11

Link States .................................................................................................................................... 6-11

Active State Power Management .................................................................................................6-12

L0s ASPM............................................................................................................................. 6-12

L1 ASPM ..............................................................................................................................6-13

L1 ASPM Entry Rejection Timer ...................................................................................................6-14

Link Status .................................................................................................................................... 6-14

De-emphasis Negotiation .............................................................................................................6-15

Crosslink ....................................................................................................................................... 6-15

Hot Reset Operation on a Crosslink .................................................................................... 6-16

Link Disable Operation on a Crosslink .................................................................................6-16

Gen1 Compatibility Mode .............................................................................................................6-16

SerDes

Introduction ..................................................................................................................................... 7-1

SerDes Numbering and Port Association .......................................................................................7-1

SerDes Transmitter Controls ..........................................................................................................7-1

Driver Voltage Level and Amplitude Boost ............................................................................. 7-1

De-emphasis ..........................................................................................................................7-2

Slew Rate ............................................................................................................................... 7-2

PCI Express Low-Swing Mode ............................................................................................... 7-2

Receiver Equalization ..................................................................................................................... 7-3

Programming of SerDes Controls................................................................................................... 7-3

Programmable Voltage Margining and De-Emphasis..................................................................... 7-3

PES48T12G2 User Manual ii April 5, 2013

IDT Table of Contents

Notes

SerDes Transmitter Control Registers.................................................................................... 7-4

Transmit Margining using the PCI Express Link Control 2 Register............................................. 7-12

Low-Swing Transmitter Voltage Mode..........................................................................................7-13

Receiver Equalization Controls..................................................................................................... 7-14

SerDes Power Management.........................................................................................................7-15

Theory of Operation

Introduction ..................................................................................................................................... 8-1

Transaction Routing........................................................................................................................ 8-1

Interrupts......................................................................................................................................... 8-1

Downstream Port Interrupts.................................................................................................... 8-2

Legacy Interrupt Emulation..................................................................................................... 8-2

Access Control Services................................................................................................................. 8-3

Error Detection and Handling .........................................................................................................8-6

Physical Layer Errors .............................................................................................................8-7

Data Link Layer Errors............................................................................................................ 8-7

Transaction Layer Errors ........................................................................................................8-8

Routing Errors ......................................................................................................................8-16

Bus Locking .................................................................................................................................. 8-17

Hot-Plug and Hot-Swap

Introduction ..................................................................................................................................... 9-1

Hot-Plug Signals ............................................................................................................................. 9-3

Port Reset Outputs .........................................................................................................................9-4

Power Enable Controlled Reset Output.................................................................................. 9-5

Power Good Controlled Reset Output .................................................................................... 9-5

Hot-Plug Events.............................................................................................................................. 9-6

Legacy System Hot-Plug Support................................................................................................... 9-6

Hot-Swap ........................................................................................................................................ 9-8

Power Management

Introduction ................................................................................................................................... 10-1

PME Messages............................................................................................................................. 10-3

PCI Express Power Management Fence Protocol .......................................................................10-3

Upstream Switch Port or Downstream Switch Port Mode ....................................................10-3

Power Budgeting Capability.......................................................................................................... 10-4

General Purpose I/O

Introduction ................................................................................................................................... 11-1

GPIO Configuration ......................................................................................................................11-1

Configured as an Input .........................................................................................................11-1

Configured as an Output ......................................................................................................11-1

Configured as an Alternate Function .................................................................................... 11-1

SMBus Interfaces

Introduction ................................................................................................................................... 12-1

Master SMBus Interface ............................................................................................................... 12-1

Initialization...........................................................................................................................12-1

Serial EEPROM.................................................................................................................... 12-1

Initialization from Serial EEPROM........................................................................................ 12-2

Programming the Serial EEPROM .......................................................................................12-5

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IDT Table of Contents

Notes

I/O Expanders....................................................................................................................... 12-5

Slave SMBus Interface ...............................................................................................................12-13

Initialization.........................................................................................................................12-13

SMBus Transactions ..........................................................................................................12-13

Multicast

Introduction ................................................................................................................................... 13-1

Addressing and Routing ...............................................................................................................13-1

Multicast TLP Determination ................................................................................................13-1

Multicast TLP Routing ..........................................................................................................13-4

Multicast Egress Processing ................................................................................................13-4

Register Organization

Introduction ................................................................................................................................... 14-1

Partial-Byte Access to Word and DWord Registers .............................................................14-2

Register Side-Effects............................................................................................................14-2

Address Maps...............................................................................................................................14-2

PCI-to-PCI Bridge Registers................................................................................................. 14-2

Capability Structures ............................................................................................................14-3

IDT Proprietary Port Specific Registers.............................................................................. 14-10

Switch Configuration and Status Registers ........................................................................14-12

PCI to PCI Bridge and Proprietary Port Specific Registers

Type 1 Configuration Header Registers .......................................................................................15-1

PCI Express Capability Structure ...............................................................................................15-11

Power Management Capability Structure ...................................................................................15-27

Message Signaled Interrupt Capability Structure .......................................................................15-29

Subsystem ID and Subsystem Vendor ID ..................................................................................15-31

Extended Configuration Space Access Registers ......................................................................15-31

Advanced Error Reporting (AER) Enhanced Capability..............................................................15-32

Device Serial Number Enhanced Capability............................................................................... 15-41

PCI Express Virtual Channel Capability .....................................................................................15-42

Power Budgeting Enhanced Capability ......................................................................................15-47

ACS Extended Capability ...........................................................................................................15-49

Multicast Extended Capability..................................................................................................... 15-52

Proprietary Port Specific Registers............................................................................................. 15-56

Port Control and Status Registers ...................................................................................... 15-56

Internal Error Control and Status Registers........................................................................ 15-58

Physical Layer Control and Status Registers .....................................................................15-65

Power Management Control and Status Registers ............................................................15-68

Request Metering ...............................................................................................................15-69

Global Address Space Access Registers ........................................................................... 15-70

Switch Configuration and Status Registers

Switch Control and Status Registers ............................................................................................16-1

Internal Switch Timer .................................................................................................................... 16-3

Switch Port Registers ...................................................................................................................16-3

SerDes Control and Status Registers...........................................................................................16-4

General Purpose I/O Registers................................................................................................... 16-12

Hot-Plug and SMBus Interface Registers ................................................................................... 16-15

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Notes

JTAG Boundary Scan

Introduction ................................................................................................................................... 17-1

Test Access Point ......................................................................................................................... 17-1

Signal Definitions .......................................................................................................................... 17-1

Boundary Scan Chain...................................................................................................................17-2

Test Data Register (DR) ...............................................................................................................17-5

Boundary Scan Registers.....................................................................................................17-5

Instruction Register (IR)................................................................................................................17-7

EXTEST................................................................................................................................ 17-8

SAMPLE/PRELOAD............................................................................................................. 17-8

BYPASS ............................................................................................................................... 17-8

CLAMP ................................................................................................................................. 17-9

IDCODE................................................................................................................................ 17-9

VALIDATE ............................................................................................................................ 17-9

EXTEST_TRAIN................................................................................................................... 17-9

EXTEST_PULSE................................................................................................................ 17-10

RESERVED........................................................................................................................ 17-10

Usage Considerations ........................................................................................................17-10

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PES48T12G2 User Manual vi April 5, 2013

Notes

List of Tables

®

Table 1.1 Initial Configuration Register Settings for PES48T12G2 .....................................................1-3

Table 1.2 PES48T12G2 Device IDs ....................................................................................................1-6

Table 1.3 PES48T12G2 Revision ID ...................................................................................................1-6

Table 1.4 PCI Express Interface Pins.................................................................................................. 1-7

Table 1.5 Reference Clock Pins ..........................................................................................................1-8

Table 1.6 SMBus Interface Pins .......................................................................................................... 1-8

Table 1.7 General Purpose I/O Pins.................................................................................................... 1-9

Table 1.8 System Pins......................................................................................................................... 1-9

Table 1.9 Test Pins............................................................................................................................ 1-11

Table 1.10 Power, Ground, and SerDes Resistor Pins .......................................................................1-12

Table 1.11 Pin Characteristics.............................................................................................................1-13

Table 3.1 IFB Buffer Sizes................................................................................................................... 3-1

Table 3.2 EFB Buffer Sizes ................................................................................................................3-2

Table 3.3 Replay Buffer Storage Limit................................................................................................. 3-3

Table 3.4 Packet Ordering Rules in the PES48T12G2........................................................................3-4

Table 3.5 Conditions for Cut-Through Transfers ................................................................................. 3-6

Table 3.6 Request Metering Decrement Value..................................................................................3-10

Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State............................................ 4-2

Table 5.1 PES48T12G2 Reset Precedence........................................................................................5-1

Table 5.2 Boot Configuration Vector Signals....................................................................................... 5-2

Table 6.1 Crosslink Port Groups........................................................................................................6-15

Table 6.2 Gen1 Compatibility Mode: bits cleared in training sets...................................................... 6-17

Table 7.1 SerDes Transmit Level Controls in the S[x]TXLCTL0 and S[x]TXLCTL1 Registers............7-5

Table 7.2 SerDes Transmit Driver Settings in Gen1 Mode..................................................................7-6

Table 7.3 SerDes Transmit Driver Settings in Gen2 Mode with -3.5dB de-emphasis......................... 7-7

Table 7.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis......................... 7-8

Table 7.5 Transmitter Slew Rate Settings .........................................................................................7-11

Table 7.6 PCI Express Transmit Margining Levels supported by the PES48T12G2......................... 7-12

Table 7.7 SerDes Transmit Drive Swing in Low Swing Mode at Gen1 Speed ..................................7-13

Table 7.8 SerDes Transmit Drive Swing in Low Swing Mode at Gen2 Speed ..................................7-14

Table 8.1 Switch Routing Methods......................................................................................................8-1

Table 8.2 Downstream Port Interrupts................................................................................................. 8-2

Table 8.3 Downstream to Upstream Port Interrupt Routing Based on Device Number.......................8-3

Table 8.4 Prioritization of ACS Checks for Request TLPs...................................................................8-5

Table 8.5 Prioritization of ACS Checks for Completion TLPs.............................................................. 8-6

Table 8.6 TLP Types Affected by ACS Checks................................................................................... 8-6

Table 8.7 Physical Layer Errors...........................................................................................................8-7

Table 8.8 Data Link Layer Errors......................................................................................................... 8-7

Table 8.9 Transaction Layer Errors associated with the PCI-to-PCI Bridge Function......................... 8-9

Table 8.10 Conditions handled as Unsupported Requests (UR) by the PCI-to-PCI Bridge Function .8-11

Table 8.11 Ingress TLP Formation Checks Associated with the PCI-to-PCI Bridge Function.............8-11

Table 8.12 Egress Malformed TLP Error Checks................................................................................8-12

Table 8.13 ACS Violations for Ports Operating in Downstream Switch Port Mode ............................. 8-13

Table 8.14 Prioritization of Transaction Layer Errors ..........................................................................8-14

Table 9.1 Port Hot Plug Signals...........................................................................................................9-3

Table 9.2 Negated Value of Unused Hot-Plug Output Signals............................................................ 9-3

Table 10.1 PES48T12G2 Power Management State Transition Diagram...........................................10-2

Table 11.1 GPIO Pin Configuration..................................................................................................... 11-1

Table 11.2 General Purpose I/O Pin Alternate Function .....................................................................11-2

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Notes

Table 11.3 GPIO Alternate Function Pins ...........................................................................................11-2

Table 12.1 PES48T12G2 Compatible Serial EEPROMs..................................................................... 12-2

Table 12.2 Serial EEPROM Initialization Errors ..................................................................................12-5

Table 12.3 I/O Expander Function Allocation...................................................................................... 12-6

Table 12.4 I/O Expander Default Output Signal Value........................................................................ 12-7

Table 12.5 Pin Mapping for I/O Expanders 0 through 7 ......................................................................12-9

Table 12.6 Pin Mapping I/O Expander 8 ...........................................................................................12-10

Table 12.7 Pin Mapping I/O Expander 9 ...........................................................................................12-10

Table 12.8 Pin Mapping I/O Expander 10 .........................................................................................12-11

Table 12.9 I/O Expander 12 - Link Up Status.................................................................................... 12-12

Table 12.10 I/O Expander 13 - Link Activity Status ............................................................................. 12-12

Table 12.11 Slave SMBus Address..................................................................................................... 12-13

Table 12.12 Slave SMBus Command Code Fields ............................................................................. 12-14

Table 12.13 CSR Register Read or Write Operation Byte Sequence .................................................12-15

Table 12.14 CSR Register Read or Write CMD Field Description.......................................................12-16

Table 12.15 Serial EEPROM Read or Write Operation Byte Sequence .............................................12-16

Table 12.16 Serial EEPROM Read or Write CMD Field Description................................................... 12-17

Table 14.1 Global Address Space Organization .................................................................................14-1

Table 14.2 Default PCI Capability List Linkage ................................................................................... 14-3

Table 14.3 Default PCI Express Capability List Linkage .....................................................................14-4

Table 14.4 PCI-to-PCI Bridge Configuration Space Registers............................................................ 14-6

Table 14.5 Proprietary Port Specific Registers.................................................................................. 14-11

Table 14.6 Switch Configuration and Status .....................................................................................14-13

Table 17.1 JTAG Pin Descriptions ......................................................................................................17-2

Table 17.2 Boundary Scan Chain........................................................................................................ 17-3

Table 17.3 Instructions Supported by the JTAG Boundary Scan........................................................ 17-8

Table 17.4 System Controller Device Identification Register ..............................................................17-9

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Notes

List of Figures

®

Figure 1.1 PES48T12G2 Block Diagram ............................................................................................1-3

Figure 1.2 PES48T12G2 Logic Diagram .............................................................................................1-5

Figure 2.1 Transparent PCIe Switch ...................................................................................................2-2

Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers .................................................3-3

Figure 3.2 Architectural Model of Arbitration .......................................................................................3-5

Figure 3.3 PCIe Switch Static Rate Mismatch ....................................................................................3-8

Figure 3.4 PCIe Switch Static Rate Mismatch ....................................................................................3-8

Figure 3.5 Request Metering Count and Initial Value Loaded ............................................................3-9

Figure 3.6 Decrement Value and Decrement Value Adjustment .......................................................3-10

Figure 3.7 Request Metering Counter Decrement Operation ............................................................3-11

Figure 3.8 Non-Posted Read Request Completion Size Estimate Computation ...............................3-11

Figure 4.1 Logical Representation of the PES48T12G2 Clocking Architecture ..................................4-1

Figure 5.1 Switch Fundamental Reset with Serial EEPROM Initialization ..........................................5-4

Figure 5.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....................5-4

Figure 6.1 Unmerged Port Lane Reversal for Maximum Link Width of x4 ..........................................6-2

Figure 6.2 Unmerged Port Lane Reversal for Maximum Link Width of x2 ..........................................6-2

Figure 6.3 Merged Port Lane Reversal for Maximum Link Width of x2 ...............................................6-3

Figure 6.4 Merged Port Lane Reversal for Maximum Link Width of x4 ...............................................6-4

Figure 6.5 Merged Port Lane Reversal for Maximum Link Width of x8 ...............................................6-5

Figure 6.6 PES48T12G2 ASPM Link Sate Transitions .....................................................................6-12

Figure 7.1 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit

Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -3.5 dB

Nominal de-emphasis ......................................................................................................7-10

Figure 7.2 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit

Drive Level Controls, when the PHY Operates in Gen2 Data Rate with -3.5 dB

Nominal de-emphasis ......................................................................................................7-10

Figure 7.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit

Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB

Nominal de-emphasis ......................................................................................................7-11

Figure 8.1 ACS Source Validation Example .......................................................................................8-4

Figure 8.2 ACS Peer-to-Peer Request Re-direct at a Downstream Port ............................................8-4

Figure 8.3 ACS Upstream Forwarding Example .................................................................................8-5

Figure 8.4 Error Checking and Logging on a Received TLP .............................................................8-15

Figure 9.1 Hot-Plug on Switch Downstream Slots Application ............................................................9-1

Figure 9.2 Hot-Plug with Switch on Add-In Card Application ..............................................................9-2

Figure 9.3 Hot-Plug with Carrier Card Application ..............................................................................9-2

Figure 9.4 Power Enable Controlled Reset Output Mode Operation ..................................................9-5

Figure 9.5 Power Good Controlled Reset Output Mode Operation .....................................................9-5

Figure 9.6 PES48T12G2 Hot-Plug Event Signalling ...........................................................................9-7

Figure 10.1 PES48T12G2 Power Management State Transition Diagram .........................................10-2

Figure 12.1 Split SMBus Interface Configuration ................................................................................12-1

Figure 12.2 Single Double Word Initialization Sequence Format ........................................................12-3

Figure 12.3 Sequential Double Word Initialization Sequence Format .................................................12-3

Figure 12.4 Configuration Done Sequence Format ............................................................................12-4

Figure 12.5 Slave SMBus Command Code Format ..........................................................................12-14

Figure 12.6 CSR Register Read or Write CMD Field Format ............................................................12-15

Figure 12.7 Serial EEPROM Read or Write CMD Field Format ........................................................12-17

Figure 12.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled 12-18

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Notes

Figure 12.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC

Disabled .........................................................................................................................12-18

Figure 12.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled .........12-18

Figure 12.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled .....12-19

Figure 12.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ......12-19

Figure 12.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ..12-19

Figure 13.1 Multicast Group Address Ranges ....................................................................................13-2

Figure 13.2 Multicast Group Address Region Determination ..............................................................13-3

Figure 14.1 PCI-to-PCI Bridge Configuration Space Organization .....................................................14-5

Figure 14.2 Proprietary Port Specific Register Organization ............................................................14-10

Figure 14.3 Switch Configuration and Status Space Organization ...................................................14-12

Figure 17.1 Diagram of the JTAG Logic ..............................................................................................17-1

Figure 17.2 State Diagram of the TAP Controller ...............................................................................17-2

Figure 17.3 Diagram of Observe-only Input Cell .................................................................................17-6

Figure 17.4 Diagram of Output Cell ....................................................................................................17-6

Figure 17.5 Diagram of Bidirectional Cell ............................................................................................17-7

Figure 17.6 Device ID Register Format ...............................................................................................17-9

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Notes

Register List

®

ACSCAP - ACS Capability Register (0x324)........................................................................................ 15-49

ACSCTL - ACS Control Register (0x326)............................................................................................. 15-50

ACSECAPH - ACS Extended Capability Header (0x320) .................................................................... 15-49

ACSECV - ACS Egress Control Vector (0x328)................................................................................... 15-51

AERCAP - AER Capabilities (0x100) ................................................................................................... 15-32

AERCEM - AER Correctable Error Mask (0x114) ................................................................................ 15-38

AERCES - AER Correctable Error Status (0x110) ............................................................................... 15-37

AERCTL - AER Control (0x118)........................................................................................................... 15-40

AERHL1DW - AER Header Log 1st Doubleword (0x11C) ................................................................... 15-40

AERHL2DW - AER Header Log 2nd Doubleword (0x120)................................................................... 15-40

AERHL3DW - AER Header Log 3rd Doubleword (0x124).................................................................... 15-40

AERHL4DW - AER Header Log 4th Doubleword (0x128).................................................................... 15-41

AERUEM - AER Uncorrectable Error Mask (0x108) ............................................................................ 15-34

AERUES - AER Uncorrectable Error Status (0x104) ........................................................................... 15-32

AERUESV - AER Uncorrectable Error Severity (0x10C)...................................................................... 15-36

BAR0 - Base Address Register 0 (0x010).............................................................................................. 15-4

BAR1 - Base Address Register 1 (0x014).............................................................................................. 15-4

BCTL - Bridge Control Register (0x03E) .............................................................................................. 15-10

BCVSTS - Boot Configuration Vector Status (0x0004) .......................................................................... 16-2

BIST - Built-in Self Test Register (0x00F) .............................................................................................. 15-4

CAPPTR - Capabilities Pointer Register (0x034) ................................................................................... 15-9

CCODE - Class Code Register (0x009) ................................................................................................. 15-3

CLS - Cache Line Size Register (0x00C)............................................................................................... 15-4

DID - Device Identification Register (0x002) .......................................................................................... 15-1

ECFGADDR - Extended Configuration Space Access Address (0x0F8) ............................................. 15-31

ECFGDATA - Extended Configuration Space Access Data (0x0FC)................................................... 15-32

EEPROMINTF - Serial EEPROM Interface (0x0AD0).......................................................................... 16-19

EROMBASE - Expansion ROM Base Address Register (0x038)........................................................... 15-9

GASAADDR - Global Address Space Access Address (0xFF8).......................................................... 15-70

GASADATA - Global Address Space Access Data (0xFFC)................................................................ 15-70

GPECTL - General Purpose Event Control (0x0AE8).......................................................................... 16-21

GPESTS - General Purpose Event Status (0x0AEC) .......................................................................... 16-22

GPIOAFSEL0 - General Purpose I/O Alternate Function Select 0 (0x0A98) ....................................... 16-13

GPIOCFG0 - General Purpose I/O Configuration 0 (0x0AA8) ............................................................. 16-14

GPIOCFG1 - General Purpose I/O Configuration 1 (0x0AAC)............................................................. 16-14

GPIOD0 - General Purpose I/O Data 0 (0x0AB0) ................................................................................ 16-14

GPIOD1 - General Purpose I/O Data 1 (0x0AB4) ................................................................................ 16-15

GPIOFUNC0 - General Purpose I/O Function 0 (0x0A90)................................................................... 16-12

GPIOFUNC1 - General Purpose I/O Function 1 (0x0A94)................................................................... 16-13

HDR - Header Type Register (0x00E).................................................................................................... 15-4

HPCFGCTL - Hot-Plug Configuration Control (0x0ABC) ..................................................................... 16-16

HPSIGMAP - Hot-Plug GPIO Signal Map (0x0AB8) ............................................................................ 16-15

IERRORCTL - Internal Error Reporting Control (0x480) ...................................................................... 15-58

IERRORMSK - Internal Error Reporting Mask (0x488) ........................................................................ 15-59

IERRORSEV - Internal Error Reporting Severity (0x48C).................................................................... 15-61

IERRORSTS - Internal Error Reporting Status (0x484) ....................................................................... 15-58

IERRORTST - Internal Error Reporting Test (0x490)........................................................................... 15-64

INTRLINE - Interrupt Line Register (0x03C)........................................................................................... 15-9

INTRPIN - Interrupt PIN Register (0x03D) ............................................................................................. 15-9

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IDT Register List

Notes

IOBASE - I/O Base Register (0x01C)......................................................................................................15-5

IOBASEU - I/O Base Upper Register (0x030).........................................................................................15-8

IOEXPADDR0 - SMBus I/O Expander Address 0 (0x0AD8).................................................................16-20

IOEXPADDR1 - SMBus I/O Expander Address 1 (0x0ADC) ................................................................16-20

IOEXPADDR2 - SMBus I/O Expander Address 2 (0x0AE0) .................................................................16-21

IOEXPADDR3 - SMBus I/O Expander Address 3 (0x0AE4) .................................................................16-21

IOLIMIT - I/O Limit Register (0x01D).......................................................................................................15-6

IOLIMITU - I/O Limit Upper Register (0x032)..........................................................................................15-8

L1ASPMRTC - L1 ASPM Rejection Timer Control (0x710) ..................................................................15-68

LANESTS0 - Lane Status 0 (0x51C).....................................................................................................15-66

LANESTS1 - Lane Status 1 (0x520) .....................................................................................................15-66

MBASE - Memory Base Register (0x020)...............................................................................................15-7

MCBARH- Multicast Base Address High (0x33C).................................................................................15-53

MCBARL- Multicast Base Address Low (0x338)...................................................................................15-53

MCBLKALLH- Multicast Block All High (0x34C)....................................................................................15-54

MCBLKALLL- Multicast Block All Low (0x348)......................................................................................15-54

MCBLKUTH - Multicast Block Untranslated High (0x354) ....................................................................15-55

MCBLKUTL- Multicast Block Untranslated Low (0x350).......................................................................15-55

MCCAP - Multicast Capability (0x334)..................................................................................................15-52

MCCAPH - Multicast Enhanced Capability Header (0x330) .................................................................15-52

MCCTL- Multicast Control (0x336)........................................................................................................15-52

MCOVRBARH- Multicast Overlay Base Address High (0x35C)............................................................15-55

MCOVRBARL- Multicast Overlay Base Address Low (0x358)..............................................................15-55

MCRCVH- Multicast Receive High (0x344)...........................................................................................15-54

MCRCVL- Multicast Receive Low (0x340) ............................................................................................15-53

MLIMIT - Memory Limit Register (0x022)................................................................................................15-7

MSIADDR - Message Signaled Interrupt Address (0x0D4)...................................................................15-30

MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) ...............................................15-29

MSIMDATA - Message Signaled Interrupt Message Data (0x0DC)......................................................15-30

MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) .....................................................15-30

PBUSN - Primary Bus Number Register (0x018)....................................................................................15-5

PCICMD - PCI Command Register (0x004)............................................................................................15-1

PCIECAP - PCI Express Capability (0x040) .........................................................................................15-11

PCIEDCAP - PCI Express Device Capabilities (0x044) ........................................................................15-11

PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ...................................................................15-24

PCIEDCTL - PCI Express Device Control (0x048)................................................................................15-13

PCIEDCTL2 - PCI Express Device Control 2 (0x068)...........................................................................15-24

PCIEDSTS - PCI Express Device Status (0x04A) ................................................................................15-14

PCIEDSTS2 - PCI Express Device Status 2 (0x06A) ...........................................................................15-24

PCIELCAP - PCI Express Link Capabilities (0x04C) ............................................................................15-14

PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) .......................................................................15-24

PCIELCTL - PCI Express Link Control (0x050).....................................................................................15-16

PCIELCTL2 - PCI Express Link Control 2 (0x070)................................................................................15-25

PCIELSTS - PCI Express Link Status (0x052)......................................................................................15-17

PCIELSTS2 - PCI Express Link Status 2 (0x072).................................................................................15-27

PCIESCAP - PCI Express Slot Capabilities (0x054) .............................................................................15-19

PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) ........................................................................15-27

PCIESCTL - PCI Express Slot Control (0x058).....................................................................................15-20

PCIESCTL2 - PCI Express Slot Control 2 (0x078)................................................................................15-27

PCIESCTLIV - PCI Express Slot Control Initial Value (0x420)..............................................................15-56

PCIESSTS - PCI Express Slot Status (0x05A) .....................................................................................15-22

PCIESSTS2 - PCI Express Slot Status 2 (0x07A) ................................................................................15-27

PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) ..............................................15-42

PCISTS - PCI Status Register (0x006) ...................................................................................................15-2

PHYLCFG0 - Phy Link Configuration 0 (0x530)....................................................................................15-67

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IDT Register List

Notes

PHYLSTATE0 - Phy Link State 0 (0x540).............................................................................................15-67

PHYPRBS - Phy PRBS Seed (0x55C)..................................................................................................15-68

PLTIMER - Primary Latency Timer (0x00D)............................................................................................15-4

PMBASE - Prefetchable Memory Base Register (0x024) .......................................................................15-7

PMBASEU - Prefetchable Memory Base Upper Register (0x028)..........................................................15-8

PMCAP - PCI Power Management Capabilities (0x0C0)......................................................................15-27

PMCSR - PCI Power Management Control and Status (0x0C4) ..........................................................15-28

PMLIMIT - Prefetchable Memory Limit Register (0x026) ........................................................................15-7

PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) ..........................................................15-8

PVCCAP1- Port VC Capability 1 (0x204)..............................................................................................15-42

PVCCAP2- Port VC Capability 2 (0x208)..............................................................................................15-42

PVCCTL - Port VC Control (0x20C) ......................................................................................................15-43

PVCSTS - Port VC Status (0x20E) .......................................................................................................15-43

PWRBCAP - Power Budgeting Capabilities (0x280).............................................................................15-47

PWRBD - Power Budgeting Data (0x288).............................................................................................15-48

PWRBDSEL - Power Budgeting Data Select (0x284)...........................................................................15-48

PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) ...................................................15-48

PWRBPBC - Power Budgeting Power Budget Capability (0x28C) .......................................................15-48

RID - Revision Identification Register (0x008) ........................................................................................15-3

RMCOUNT - Requester Metering Count (0x88C).................................................................................15-69

RMCTL - Requester Metering Control (0x880) .....................................................................................15-69

S[13:12, 9:0]CTL - SerDes x Control.......................................................................................................16-5

S[13:12, 9:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control............................................16-12

S[13:12, 9:0]TXLCTL0 - SerDes x Transmitter Lane Control 0...............................................................16-6

S[13:12, 9:0]TXLCTL1 - SerDes x Transmitter Lane Control 1...............................................................16-9

SBUSN - Secondary Bus Number Register (0x019) ...............................................................................15-5

SECSTS - Secondary Status Register (0x01E) ......................................................................................15-6

SERDESCFG - SerDes Configuration (0x510) .....................................................................................15-65

SLTIMER - Secondary Latency Timer Register (0x01B).........................................................................15-5

SMBUSCTL - SMBus Control (0x0ACC)...............................................................................................16-19

SMBUSSTS - SMBus Status (0x0AC8) ................................................................................................16-17

SNUMCAP - Serial Number Capabilities (0x180) .................................................................................15-41

SNUMLDW - Serial Number Lower Doubleword (0x184) .....................................................................15-41

SNUMUDW - Serial Number Upper Doubleword (0x188).....................................................................15-41

SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) .........................................................15-31

SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) .................................15-31

SUBUSN - Subordinate Bus Number Register (0x01A)..........................................................................15-5

SWCTL - Switch Control (0x0000) ..........................................................................................................16-1

SWPORT[13:12, 9:0]CTL - Switch Port x Control ...................................................................................16-3

SWPORT[13:12, 9:0]STS - Switch Port x Status ....................................................................................16-4

USSBRDELAY - Upstream Secondary Bus Reset Delay (0x008C)........................................................16-3

VCR0CAP- VC Resource 0 Capability (0x210).....................................................................................15-43

VCR0CTL- VC Resource 0 Control (0x214)..........................................................................................15-44

VCR0STS - VC Resource 0 Status (0x218)..........................................................................................15-44

VCR0TBL0 - VC Resource 0 Port Arbitration Table Entry 0 (0x240) ....................................................15-45

VCR0TBL1 - VC Resource 0 Port Arbitration Table Entry 1 (0x244) ....................................................15-46

VCR0TBL2 - VC Resource 0 Port Arbitration Table Entry 2 (0x248) ....................................................15-46

VCR0TBL3 - VC Resource 0 Port Arbitration Table Entry 3 (0x24C) ...................................................15-47

VID - Vendor Identification Register (0x000)...........................................................................................15-1

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IDT Register List

Notes

PES48T12G2 User Manual xiv April 5, 2013

Notes

®

Chapter 1

PES48T12G2 Device

Overview

Introduction

The 89HPES48T12G2 is a member of the IDT PRECISE™ family of PCI Express® switching solutions.
The PES48T12G2 is a 48-lane, 12-port system interconnect switch optimized for PCI Express Gen2 packet
switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows.
Target applications include servers, storage, communications, embedded systems, and multi-host or intelli­gent I/O based systems with inter-domain communication.

Utilizing standard PCI Express interconnect, the PES48T12G2 provides the most efficient fan-out solu­tion for applications requiring high throughput, low latency, and simple board layout with a minimum number
of board layers. It provides 48 GBps (384 Gbps) of aggregated, full-duplex switching capacity through 48
integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 Gbps of bandwidth in
both directions and is fully compliant with PCI Express Base Specification, Revision 2.0.

Features



High Performance Non-Blocking Switch Architecture

– 48-lane 12-port PCIe switch

• Six x8 ports switch ports each of which can bifurcate to two x4 ports (total of twelve x4 ports)

– Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Gen1 operation
– Delivers up to 48 GBps (384 Gbps) of switching capacity
– Supports 128 Bytes to 2 KB maximum payload size
– Low latency cut-through architecture

– Supports one virtual channel and eight traffic classes



Standards and Compatibility

– PCI Express Base Specification 2.0 compliant
– Implements the following optional PCI Express features

• Advanced Error Reporting (AER) on all ports

• End-to-End CRC (ECRC)

• Access Control Services (ACS)

• Power Budgeting Enhanced Capability

• Device Serial Number Enhanced Capability

• Sub-System ID and Sub-System Vendor ID Capability

• Internal Error Reporting ECN

• Multicast ECN

• VGA and ISA enable

• L0s and L1 ASPM

•ARI ECN



Port Configurability

– x4 and x8 ports

• Ability to merge adjacent x4 ports to create a x8 port

– Automatic per port link width negotiation

(x8  x4  x2  x1)

– Crosslink support
– Automatic lane reversal

– Autonomous and software managed link width and speed control
– Per lane SerDes configuration

PES48T12G2 User Manual 1 - 1 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

• De-emphasis

• Receive equalization

• Drive strength



Initialization / Configuration

– Supports Root (BIOS, OS, or driver), Serial EEPROM, or SMBus switch initialization
– Common switch configurations are supported with pin strapping (no external components)
– Supports in-system Serial EEPROM initialization/programming



Quality of Service (QoS)

– Port arbitration

• Round robin

• Weighted Round Robin (WRR)

– Request metering

• IDT proprietary feature that balances bandwidth among switch ports for maximum system
throughput

– High performance switch core architecture

• Combined Input Output Queued (CIOQ) switch architecture with large buffers



Multicast

– Compliant to the PCI-SIG multicast ECN
– Supports arbitrary multicasting of Posted transactions
– Supports 64 multicast groups
– Multicast overlay mechanism support
– ECRC regeneration support



Clocking

– Supports 100 MHz and 125 MHz reference clock frequencies
– Flexible clocking modes

• Common clock

• Non-common clock



Hot-Plug and Hot Swap

– Hot-plug controller on all ports

• Hot-plug supported on all downstream switch ports

– All ports support hot-plug using low-cost external I
– Configurable presence detect supports card and cable applications
– GPE output pin for hot-plug event notification

• Enables SCI/SMI generation for legacy operating system support

– Hot swap capable I/O



Power Management

– Supports D0, D3hot and D3 power management states
– Active State Power Management (ASPM)

• Supports L0, L0s, L1, L2/L3 Ready and L3 link states

• Configurable L0s and L1 entry timers allow performance/power-savings tuning

– Supports PCI Express Power Budgeting Capability
– SerDes power savings

• Supports low swing / half-swing SerDes operation

• SerDes optionally turned-off in D3hot

• SerDes associated with unused ports are turned-off

• SerDes associated with unused lanes are placed in a low power state



9 General Purpose I/O



Reliability, Availability and Serviceability (RAS)

– ECRC support
– AER on all ports

2

C I/O expanders

PES48T12G2 User Manual 1 - 2 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

48 PCI Express Lanes

Up to 6 x8 ports or 12 x4 Ports

12-Port Switch Core

Frame Buffer

Route Table

Port

Arbitration

Scheduler

DL/Transaction Layer

SerDes

x8/x4/x2/x1

DL/Transaction Layer

SerDes

x8/x4/x2/x1

DL/Transaction Layer

SerDes

x8/x4/x2/x1

DL/Transaction Layer

SerDes

x8/x4/x2/x1

DL/Transaction Layer

SerDes

x8/x4/x2/x1

DL/Transaction Layer

SerDes

x8/x4/x2/x1

– SECDED ECC protection on all internal RAMs
– End-to-end data path parity protection
– Checksum Serial EEPROM content protected
– Autonomous link reliability (preserves system operation in the presence of faulty links)
– Ability to generate an interrupt (INTx or MSI) on link up/down transitions



Test and Debug

– On-chip link activity and status outputs available for Port 0 (upstream port)
– Per port link activity and status outputs available using external I

– SerDes test modes
– Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG



Power Supplies

– Requires only two power supply voltages (1.0 V and 2.5 V)
– No power sequencing requirements



Packaged in a 27mm x 27mm 676-ball Flip Chip BGA with 1mm ball spacing

2

C I/O expander for all other ports

Figure 1.1 PES48T12G2 Block Diagram

P o r t

PCIELCAP

MAXLNKWDTH

00x4

10x4

20x4

30x4

PES48T12G2 User Manual 1 - 3 April 5, 2013

Table 1.1 Initial Configuration Register Settings for PES48T12G2 (Part 1 of 2)

40x4

IDT PES48T12G2 Device Overview

Notes

P o r t

50x4

60x4

70x4

80x4

90x4

12 0x4

13 0x4

Table 1.1 Initial Configuration Register Settings for PES48T12G2 (Part 2 of 2)

PCIELCAP

MAXLNKWDTH

Note: There are no ports 10 and 11 in the PES48T12G2 device.

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IDT PES48T12G2 Device Overview

PE00TP[3:0]

Global

Reference Clocks

GCLKN[1:0]
GCLKP[1:0]

JTAG_TCK

GPIO[8:0]

9

General Purpose

I/O

VDDCORE

V

DD

I/O

V

DD

PEA

Power/Ground

MSMBCLK
MSMBDAT

SSMBADDR[2,1]

SSMBCLK
SSMBDAT

2

Master

SMBus Interface

Slave

SMBus Interface

GCLKFSEL

RSTHALT

System

Pins

JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

JTAG Pins

V

SS

SWMODE[3:0]

4

CLKMODE[1:0]

PERSTN

PE00RP[3:0]
PE00RN[3:0]

PCI Express

Switch

SerDes Input

PE00TN3:[0]

PCI Express

Switch

SerDes Output

Port 0

Port 0

PE09RP[3:0]
PE09RN[3:0]

PCI Express

Switch

SerDes Input

PE09TP[3:0]
PE09TN[3:0]

PCI Express

Switch

SerDes Output

Port 9

Port 9

......

PE13RP[3:0]
PE13RN[3:0]

PCI Express

Switch

SerDes Input

PE12TP[3:0]
PE12TN[3:0]

PCI Express

Switch

SerDes Output

Port 13

Port 12

PES48T12G2

REFRES[13,12,9:0]

SerDes

Reference

Resistors

VDDPEHA

VDDPETA

......

2

P01MERGEN

P23MERGEN
P45MERGEN
P67MERGEN

P89MERGEN

P1213MERGEN

PE12RP[3:0]
PE12RN[3:0]

PCI Express

Switch

SerDes Input

Port 12

PE13TP[3:0]
PE13TN[3:0]

PCI Express

Switch

SerDes Output

Port 13

PE01RP[3:0]
PE01RN[3:0]

PCI Express

Switch

SerDes Input

Port 1

PE02RP[3:0]
PE02RN[3:0]

PCI Express

Switch

SerDes Input

Port 2

PE03RP[3:0]
PE03RN[3:0]

PCI Express

Switch

SerDes Input

Port 3

REFRESPLL

Logic Diagram

PES48T12G2 User Manual 1 - 5 April 5, 2013

Figure 1.2 PES48T12G2 Logic Diagram

IDT PES48T12G2 Device Overview

Notes

System Identification

Vendor ID

All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech-

nology, Inc.

Device ID

The PES48T12G2 device ID is shown in Table 1.2.

Revision ID

The revision ID in the PES48T12G2 is set to the same value in all mode. The value of the revision ID is
determined in one place and is easily modified during a metal mask change. The revision ID will start at 0x0
and will be incremented with each all-layer or metal mask change.

PCIe Device Device ID

0x11 0x807B

Table 1.2 PES48T12G2 Device IDs

Revision ID Description

0x0 Corresponds to ZA silicon

0x1 Corresponds to ZB silicon

0x2 Corresponds to ZC silicon

Table 1.3 PES48T12G2 Revision ID

JTAG ID

The JTAG ID is:

– Version: Same value as Revision ID. See Table 1.3
– Part number: Same value as base Device ID. See Table 1.2.
– Manufacture ID: 0x33
– LSB: 0x1

SSID/SSVID

The PES48T12G2 contains the mechanisms necessary to implement the PCI-to-PCI bridge Subsystem
ID and Subsystem Vendor ID capability structure. However, in the default configuration the Subsystem ID
and Subsystem Vendor ID capability structure is not enabled. To enable this capability, the SSID and SSVID
fields in the Subsystem ID and Subsystem Vendor ID (SSIDSSVID) register must be initialized with the
appropriate ID values. the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be
initialized to point to this capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted
to point to the next capability if necessary.

Device Serial Number Enhanced Capability

The PES48T12G2 contains the mechanisms necessary to implement the PCI express device serial
number enhanced capability. However, in the default configuration this capability structure is not enabled.
To enable the device serial number enhanced capability, the Serial Number Lower Doubleword
(SNUMLDW) and the Serial Number Upper Doubleword (SNUMUDW) registers should be initialized. The
Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to this
capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted to point to the next capa­bility if necessary.

PES48T12G2 User Manual 1 - 6 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

Pin Description

The following tables list the functions of the pins provided on the PES48T12G2. Some of the functions
listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals
ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals
(including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic
one (high) level. Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the
positive portion of the differential pair and the differential signal ending in “N” is the negative portion of the
differential pair.

Signal Type Name/Description

PE00RP[3:0]
PE00RN[3:0]

PE00TP[3:0]
PE00TN[3:0]

PE01RP[3:0]
PE01RN[3:0]

PE01TP[3:0]
PE01TN[3:0]

PE02RP[3:0]
PE02RN[3:0]

PE02TP[3:0]
PE02TN[3:0]

PE03RP[3:0]
PE03RN[3:0]

PE03TP[3:0]
PE03TN[3:0]

PE04RP[3:0]
PE04RN[3:0]

PE04TP[3:0]
PE04TN[3:0]

PE05RP[3:0]
PE05RN[3:0]

PE05TP[3:0]
PE05TN[3:0]

PE06RP[3:0]
PE06RN[3:0]

PE06TP[3:0]
PE06TN[3:0]

PE07RP[3:0]
PE07RN[3:0]

I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pairs for port 0.

O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 0.

I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive

pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.

O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.

I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pairs for port 2.

O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 2.

I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive

pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.

O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.

I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pairs for port 4.

O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 4.

I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive

pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.

O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 5. When port 4 is merged with port 5, these signals
become port 4 transmit pairs for lanes 4 through 7.

I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive

pairs for port 6.

O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 6.

I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive

pairs for port 7. When port 6 is merged with port 7, these signals become
port 6 receive pairs for lanes 4 through 7.

Table 1.4 PCI Express Interface Pins (Part 1 of 2)

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IDT PES48T12G2 Device Overview

Notes

Signal Type Name/Description

PE07TP[3:0]
PE07TN[3:0]

PE08RP[3:0]
PE08RN[3:0]

PE08TP[3:0]
PE08TN[3:0]

PE09RP[3:0]
PE09RN[3:0]

PE09TP[3:0]
PE09TN[3:0]

PE12RP[3:0]
PE12RN[3:0]

PE12TP[3:0]
PE12TN[3:0]

PE13RP[3:0]
PE13RN[3:0]

PE13TP[3:0]
PE13TN[3:0]

O PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.

I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive

pairs for port 8.

O PCI Express Port 8 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 8.

I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive

pairs for port 9. When port 8 is merged with port 9, these signals become
port 8 receive pairs for lanes 4 through 7.

O PCI Express Port 9 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 9. When port 8 is merged with port 9, these signals
become port 8 transmit pairs for lanes 4 through 7.

I PCI Express Port 12 Serial Data Receive. Differential PCI Express

receive pairs for port 12.

O PCI Express Port 12 Serial Data Transmit. Differential PCI Express

transmit pairs for port 12.

I PCI Express Port 13 Serial Data Receive. Differential PCI Express

receive pairs for port 13. When port 12 is merged with port 13, these sig­nals become port 12 receive pairs for lanes 4 through 7.

O PCI Express Port 13 Serial Data Transmit. Differential PCI Express

transmit pairs for port 13. When port 12 is merged with port 13, these sig­nals become port 12 transmit pairs for lanes 4 through 7.

Table 1.4 PCI Express Interface Pins (Part 2 of 2)

Signal Type Name/Description

GCLKN[1:0]

GCLKP[1:0]

Signal Type Name/Description

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

SSMBADDR[2,1] I Slave SMBus Address. These pins determine the SMBus address to

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

I Global Reference Clock. Differential reference clock input pair. This clock

is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.

Table 1.5 Reference Clock Pins

transfers on the master SMBus.

ter SMBus.

which the slave SMBus interface responds.

fers on the slave SMBus.

SMBus.

Table 1.6 SMBus Interface Pins

PES48T12G2 User Manual 1 - 8 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

GPIO[1] I/O General Purpose I/O.

GPIO[2] I/O General Purpose I/O.

GPIO[3] I/O General Purpose I/O.

GPIO[4] I General Purpose I/O.

GPIO[5] O General Purpose I/O.

GPIO[6] I General Purpose I/O.

GPIO[7] I/O General Purpose I/O.

GPIO[8] I General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin.
1st Alternate function — Reserved
2nd Alternate function pin name: P0LINKUPN
2nd Alternate function pin type: Output
2nd Alternate function: Port 0 Link Up Status output.

This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: GPEN
1st Alternate function pin type: Output
1st Alternate function: Hot-plug general purpose even output.
2nd Alternate function pin name: P0ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 0 Link Active Status Output.

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN
Alternate function pin type: Input
Alternate function: IO expander interrupt.

Table 1.7 General Purpose I/O Pins

Signal Type Name/Description

CLKMODE[1:0] Clock Mode. These signals determine the port clocking mode used by

ports of the device.

GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of

the GCLKP and GCLKN signals.
0x0 100 MHz
0x1 125 MHz

P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low

internally.
When this pin is low, port 0 is merged with port 1 to form a single x8 port.
The Serdes lanes associated with port 1 become lanes 4 through 7 of port

0. Refer to section Port Merging on page 5-6 for details.
When this pin is high, port 0 and port 1 are not merged, and each operates
as a single x4 port.

Table 1.8 System Pins (Part 1 of 3)

PES48T12G2 User Manual 1 - 9 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

Signal Type Name/Description

P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low

P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low

P67MERGEN I Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low

P89MERGEN I Port 8 and 9 Merge. P89MERGEN is an active low signal. It is pulled low

P1213MERGEN I Port 12 and 13 Merge. P1213MERGEN is an active low signal. It is pulled

internally.
When this pin is low, port 2 is merged with port 3 to form a single x8 port.
The Serdes lanes associated with port 3 become lanes 4 through 7 of port

2. Refer to section Port Merging on page 5-6 for details.
When this pin is high, port 2 and port 3 are not merged, and each operates
as a single x4 port.

internally.
When this pin is low, port 4 is merged with port 5 to form a single x8 port.
The Serdes lanes associated with port 5 become lanes 4 through 7 of port

4. Refer to section Port Merging on page 5-6 for details.
When this pin is high, port 4 and port 5 are not merged, and each operates
as a single x4 port.

internally.
When this pin is low, port 6 is merged with port 7 to form a single x8 port.
The Serdes lanes associated with port 7 become lanes 4 through 7 of port

6. Refer to section Port Merging on page 5-6 for details.
When this pin is high, port 6 and port 7 are not merged, and each operates
as a single x4 port.

internally.
When this pin is low, port 8 is merged with port 9 to form a single x8 port.
The Serdes lanes associated with port 9 become lanes 4 through 7 of port

8. Refer to section Port Merging on page 5-6 for details.
When this pin is high, port 8 and port 9 are not merged, and each operates
as a single x4 port.

low internally.
When this pin is low, port 12 is merged with port13 to form a single x8 port.
The Serdes lanes associated with port 13 become lanes 4 through 7 of port

12. Refer to section Port Merging on page 5-6 for details.
When this pin is high, port 12 and port 13 are not merged, and each oper­ates as a single x4 port.

Table 1.8 System Pins (Part 2 of 3)

PES48T12G2 User Manual 1 - 10 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

Signal Type Name/Description

PERSTN I Global Reset. Assertion of this signal resets all logic inside PES48T12G2.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental

SWMODE[3:0] I Switch Mode. These configuration pins determine the PES48T12G2

reset, PES48T12G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera­tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.

switch operating mode. Note: These pins should be static and not change
following the negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-

abled)

0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-

abled)

0xA - Single partition with Serial EEPROM initialization and port 0 selected

as the upstream port (port 2 disabled)

0xB - Single partition with Serial EEPROM initialization and port 2 selected

as the upstream port (port 0 disabled)
0xE - Reserved
0xF - Reserved

Table 1.8 System Pins (Part 3 of 3)

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 1.9 Test Pins

PES48T12G2 User Manual 1 - 11 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

Signal Type Name/Description

REFRES[13,12,9:0] I/O External Reference Resistors. Provides a reference for the SerDes bias

REFRESPLL I/O PLL External Reference Resistor. Provides a reference for the PLL bias

CORE I Core V

V

DD

V

DD

PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).

V

DD

PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).

V

DD

V

PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog

DD

V

SS

currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be
connected from these pins to ground.

currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be
connected from this pin to ground.

I/O I I/O V

power supply (1.0V).

I Ground.

Table 1.10 Power, Ground, and SerDes Resistor Pins

Power supply for core logic (1.0V).

DD.

LVTTL I/O buffer power supply (2.5V or preferred 3.3V).

DD.

PES48T12G2 User Manual 1 - 12 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

Pin Characteristics

Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus
and System inputs should be tied off to appropriate levels. This is especially critical for unused control
signal inputs which, if left floating, could adversely affect operation. Also, floating pins can cause a
slight increase in power consumption. Unused Serdes (Rx and Tx) pins should be left floating. Finally,
No Connection pins should not be connected.

Function Pin Name Type Buffer

PCI Express
Interface

PE00RN[3:0] I PCIe

PE00RP[3:0] I

PE00TN[3:0] O

PE00TP[3:0] O

PE01RN[3:0] I

PE01RP[3:0] I

PE01TN[3:0] O

PE01TP[3:0] O

PE02RN[3:0] I

PE02RP[3:0] I

PE02TN[3:0] O

PE02TP[3:0] O

PE03RN[3:0] I

PE03RP[3:0] I

PE03TN[3:0] O

PE03TP[3:0] O

PE04RN[3:0] I

PE04RP[3:0] I

PE04TN[3:0] O

PE04TP[3:0] O

PE05RN[3:0] I

PE05RP[3:0] I

PE05TN[3:0] O

PE05TP[3:0] O

PE06RN[3:0] I

PE06RP[3:0] I

PE06TN[3:0] O

PE06TP[3:0] O

PE07RN[3:0] I

PE07RP[3:0] I

PE07TN[3:0] O

PE07TP[3:0] O

PE08RN[3:0] I

PE08RP[3:0] I

PE08TN[3:0] O

Differential

2

I/O

Type

Serial Link

Internal

Resistor

Notes

1

Table 1.11 Pin Characteristics (Part 1 of 3)

PES48T12G2 User Manual 1 - 13 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

Function Pin Name Type Buffer

PCI Express
Interface (Cont.)

SMBus MSMBCLK I/O LVTTL STI

General Pur­pose I/O

System Pins CLKMODE[1:0] I LVTTL Input pull-up

EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up

PE08TP[3:0] O PCIe

PE09RN[3:0] I

PE09RP[3:0] I

PE09TN[3:0] O

PE09TP[3:0] O

PE12RN[3:0] I

PE12RP[3:0] I

PE12TN[3:0] O

PE12TP[3:0] O

PE13RN[3:0] I

PE13RP[3:0] I

PE13TN[3:0] O

PE13TP[3:0] O

GCLKN[1:0] I HCSL Diff. Clock

GCLKP[1:0] I

MSMBDAT I/O STI pull-up on board

SSMBADDR[2:1] I Input pull-up

SSMBCLK I/O STI pull-up on board

SSMBDAT I/O STI pull-up on board

GPIO[8:0] I/O LVTTL STI,

GCLKFSEL I pull-down

P01MERGEN I pull-down

P23MERGEN I pull-down

P45MERGEN I pull-down

P67MERGEN I pull-down

P89MERGEN I pull-down

P1213MERGEN I pull-down

PERSTN I STI

RSTHALT I Input pull-down

SWMODE[3:0] I pull-down

JTAG_TDI I STI pull-up

JTAG_TDO O

JTAG_TMS I STI pull-up

JTAG_TRST_N I STI pull-up

Differential

I/O

Type

Serial Link

Input

High Drive

Internal

Resistor

3

pull-up

1

Refer to Table 9

PES48T12G2

Data Sheet

pull-up on board

Notes

in the

Table 1.11 Pin Characteristics (Part 2 of 3)

PES48T12G2 User Manual 1 - 14 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

Function Pin Name Type Buffer

SerDes Refer­ence Resistors

REFRES00 I/O Analog

REFRES01 I/O

I/O

Type

Internal

Resistor

1

REFRES02 I/O

REFRES03 I/O

REFRES04 I/O

REFRES05 I/O

REFRES06 I/O

REFRES07 I/O

REFRES08 I/O

REFRES09 I/O

REFRES12 I/O

REFRES13 I/O

REFRESPLL I/O

Table 1.11 Pin Characteristics (Part 3 of 3)

1.

Internal resistor values under typical operating conditions are 92K  for pull-up and 91K for pull-down.

2.

All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.

3.

Schmitt Trigger Input (STI).

Notes

PES48T12G2 User Manual 1 - 15 April 5, 2013

IDT PES48T12G2 Device Overview

Notes

PES48T12G2 User Manual 1 - 16 April 5, 2013

Notes

®

Chapter 2

Port

SerDes

Switch Core

GPIO

Controller

Ma ster

SM Bus

Interface

Slave

SM Bus

Interface

Reset

Controller

GPIO

Master SMBus

Slave SM Bus

Reset and Bo ot
Conf ig uration Ve ctor

Port

SerDes

Port

SerD es

Port Port Port

SerDes SerD es SerDes

PCI Ex pr es s P ort s

PCI E xpr ess Port s

….

….

Port

SerDes

Switch Core

GPIO

Controller

Ma ster

SM Bus

Interface

Slave

SM Bus

Interface

Reset

Controller

GPIO

Master SMBus

Slave SM Bus

Reset and Bo ot
Conf ig uration Ve ctor

Port

SerDes

Port

SerD es

Port Port Port

SerDes SerD es SerDes

PCI Ex pr es s P ort s

PCI E xpr ess Port s

….

….

Architectural Overview

Introduction

This section provides a high level architectural overview of the PES48T12G2. An architectural block

diagram of the PES48T12G2 is shown in .

PES48T12G2 User Manual 2 - 1 April 5, 2013

The PES48H12G2 contains twelve x4 ports labeled port 0 through port 13 (omitting ports 10 and 11

which do not exist in this device). An even port n and its odd counterpart, port n+1, may be merged to
create a single x8 port.

– When ports are merged, the odd numbered port is not logically visible in the PCI Express hier-

archy associated with the port.

All ports support 2.5 GT/s (i.e., Gen1) and 5.0 GT/s (i.e., Gen2) operation.

At a high level, the PES48H12G2 consists of ports and a switch core. A port consists of a logic that
performs functions associated with the physical, data link, and transactions layers described in the PCIe
base 2.0 specification. In addition, a port performs switch application layer functions such as TLP routing
using route map tables, processing configuration read and write requests, etc.

The switch core is responsible for transferring TLPs between ports. Its main functions are: input buff­ering, maintaining per port ingress and egress flow control information, port and VC arbitration, scheduling,
and forwarding TLPs between ports.

Since the PES48H12G2 represents a single architecture optimized for both fan-out and system inter­connect applications, its switch core is based on a non-blocking crossbar.

IDT Architectural Overview

Notes

Virtual PCI Bus

P2P

Bridge

Upstream

Port

P2P

Bridge

P2P

Bridge

P2P

Bridge

P2P

Bridge

Downstream Ports

P2P

Bridge

Logical View

The logical view of a PCIe switch is shown in Figure 2.1. A PCI switch contains one upstream port and
one or more downstream ports. Each port is associated with a PCI-to-PCI bridge. All PCI-to-PCI bridges
associated with a PCIe switch are interconnected by a virtual PCI bus.

– The primary side of the upstream port’s PCI-to-PCI bridge is associated with the external link,

while the secondary side connects to the virtual PCI bus.

– The primary side of a downstream port’s PCI-to-PCI bridge is connected to the virtual PCI bus,

while the secondary side is associated with the external link.

Figure 2.1 Transparent PCIe Switch

PES48T12G2 User Manual 2 - 2 April 5, 2013

Notes

®

Chapter 3

Switch Core

Introduction

This chapter provides an overview of the PES48T12G2’s Switch Core. As shown in Figure 2.1 in the
Architectural Overview chapter, the Switch Core interconnects switch ports. The Switch Core’s main func­tion is to transfer TLPs among these ports efficiently and reliably. In order to do so, the Switch Core
provides buffering, ordering, arbitration, and error detection services.

Switch Core Architecture

The Switch Core is based on a non-blocking crossbar design optimized for system interconnect (i.e.,
peer-to-peer) as well as fanout (i.e., root-to-endpoint) applications. At a high level, the Switch Core is
composed of ingress buffers, a crossbar fabric interconnect, and egress buffers. These blocks are comple­mented with ordering, arbitration, and error handling logic (not shown in the figure).

Each port has dedicated ingress and egress buffer. The ingress buffer stores data received or generated
by the port. The egress buffer stores data that will be sent to the port. The crossbar interconnect is a matrix
of pathways, capable of concurrently transferring data among all possible port pairs (e.g., port 0 can
transfer data to port 1 at the same time port 2 transfers data to port 3).

As packets are received from the link they are stored in the corresponding ingress buffer. After under­going ordering and arbitration, they are transferred to the corresponding egress buffer via the crossbar
interconnect. The presence of egress buffers provides head-of-line-blocking (HOLB) relief when an egress
port is congested. For example, a packet received on port 0 that is destined to port 1 may be transferred
from port 0’s ingress buffer to port 1’s egress buffer even if port 1 does not have sufficient egress link
credits. This transfer allows subsequent packets received on port 0 to be transmitted to their destination.

Ingress Buffer

When a packet is received from the link, the ingress port’s Application Layer determines the packet’s
route and subjects it to TC/VC mapping. The packet is then stored in the appropriate IFB, together with its
routing and handling information (i.e., the packet’s descriptor). The IFB consists of three queues. These
queues are the posted transaction queue (PT queue), the non-posted transaction queue (NP queue), and
the completion transaction queue (CP queue).

– The queues for the IFB are implemented using a descriptor memory and a data memory.
– When two x4 ports are merged to create a x8 port, the descriptor and data memories for both x4

ports are merged.

The default size of each of these queues is shown in Table 3.1.

Port

Mode

x4

Bifurcated

IFB

Queue

Posted 6176 Bytes and up to 64

Non Posted 1024 Bytes and up to 64

Completion 6176 Bytes and up to 64

Total Size and

Limitations

(per-port)

TLPs

TLPs

TLPs

Table 3.1 IFB Buffer Sizes (Part 1 of 2)

Advertised

Data

Credits

386 64

64 64

386 64

Advertised

Header
Credits

PES48T12G2 User Manual 3 - 1 April 5, 2013

IDT Switch Core

Notes

Port

Mode

x8

Merged

IFB

Queue

Posted 12352 Bytes and up to 127

Non Posted 2048 Bytes and up to 127

Completion 12352 Bytes and up to 127

Total Size and

Limitations

(per-port)

TLPs

TLPs

TLPs

Table 3.1 IFB Buffer Sizes (Part 2 of 2)

Advertised

Data

Credits

772 127

128 127

772 127

Advertised

Header
Credits

Egress Buffer

The EFBs provide head-of-line-blocking (HOLB) relief to the IFBs by allowing packets to be stored in an
egress port’s EFB even if the port’s link does not have sufficient credits to accept the packet. HOLB relief
allows subsequent packets in the IFB to be transferred to their destinations efficiently. As packets are trans­ferred from an IFB to an EFB, they are subjected to the egress port’s TC/VC mapping and stored in the
EFB.

Each EFB consists of three queues. These are the posted queue, non-posted queue, and completion
queue. The use of these queues allows for packet re-ordering to improve transmission efficiency on the
egress link. Refer to section Packet Ordering on page 3-3 for details.

– The queues for both EFBs are implemented using a descriptor memory and a data memory.
– When two x4 ports are merged to create a x8 port, the descriptor and data memories for both x4

ports are merged.

The default size of each of these queues is shown in Table 3.2.

Port

Mode

x4

Bifurcated

x8

Merged

EFB

Queue

Posted 6176 Bytes and up to 64 TLPs

Non Posted 1024 Bytes and up to 64 TLPs

Completion 6176 Bytes and up to 64 TLPs

Posted 12352 Bytes and up to 128 TLPs

Non Posted 2048 Bytes and up to 128 TLPs

Completion 12352 Bytes and up to 128 TLPs

Table 3.2 EFB Buffer Sizes

Total Size and Limitations

(per-port)

In addition to providing HOLB relief, the EFB is used as a dynamically sized replay buffer. This allows for
efficient use of the egress buffer space: when transmitted packets are not being acknowledged by the link
partner the replay buffer grows to allow further transmission; when transmitted packets are successfully
acknowledged by the link partner the replay buffer shrinks and this space is used as egress buffer space to
provide maximum HOLB relief to the IFBs. Assuming a link partner issues acknowledges at the rates
recommended in the PCI Express 2.0 spec, the replay buffer naturally grows to the optimal size for the
port’s link width and speed. Table 3.3 shows the maximum number of TLPs that may be stored in the EFB’s
replay buffer.

PES48T12G2 User Manual 3 - 2 April 5, 2013

IDT Switch Core

Notes

Port

Mode

x4

Bifurcated

x8

Merged

Table 3.3 Replay Buffer Storage Limit

Replay Buffer Storage

Limit

32 TLPs

64 TLPs

Crossbar Interconnect

The crossbar is an 12x12 matrix of pathways, capable of concurrently transferring data between a
maximum of 12 port pairs. The crossbar interconnects the port ingress buffers to the egress buffers. It
provides two data-interfaces per port, one for the port’s ingress buffers and one for the port’s egress
buffers.

Figure 3.1 shows the interface between the crossbar and a port’s ingress and egress buffers. The
crossbar is able to support 12 simultaneous data transfers. This architecture is well suited for system inter­connect applications, as it allows simultaneous full-duplex communication between up to 12 peer devices.
Note there are no ports 10 and 11 in this device.

Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers

Datapaths

As mentioned earlier, the Switch Core interfaces with 12 ports. The interface between each port and the
switch core can be logically divided into ingress data interface, egress data interface.

The ingress data interface transfers data received by the port from the PCIe link into the switch-core.
The egress data interface transfers data from the switch-core to the port. All data paths through the ingress
data interface, crossbar interconnect and egress data interface are 160-bits wide instead of the required
128-bits (i.e., a x8 Gen2 port requires a throughput of 128-bits per clock cycle). On the ingress data inter­face, the Switch Core receives data from the port at a rate determined by the operational mode of the port
(merged or bifurcated) and the width and speed of the port’s link. Packets received from the port are stored

in the appropriate IFB queue. After being queued in an IFB

1

and undergoing ordering and arbitration, all
data transferred through the crossbar interconnect is transferred in a continuous TLP manner (i.e., the data
path is never multiplexed).

This choice of datapath width implies that the crossbar has 20% higher throughput than the throughput
required to service all ports. This “over-speed” ensures that inter-port messages (i.e., internal messages
exchanged by ports for switch management) do not affect the throughput of the PCIe links.

On the egress interface, data in the EFB is read by the port’s data link layer (i.e., DL) when it is chosen
to be transmitted on the link. If the port is in merged mode, the DL allocates all clock cycles to read data
from the EFB. However, depending on the negotiated link width not all clock cycles may be used to transfer
data. If the port is in bifurcated mode, the DL reads data from the appropriate EFB (i.e., each port has a
dedicated EFB). Again, depending on the negotiated link width, not all clock cycles may be used to transfer
data.

Packet Ordering

The PCI Express specification 2.0 contains packet ordering rules to ensure the producer/consumer
model is honored across a PCIe hierarchy and to prevent deadlocks. The Switch Core performs packet
ordering on a per-port basis, at the output of the ingress and egress buffers of each port (refer to Figure

3.1).

1.

Please refer to section Cut-Through Routing on page 3-5 for further information on conditions for cut-through

transfers to occur.

PES48T12G2 User Manual 3 - 3 April 5, 2013

IDT Switch Core

Notes

Applying ordering rules at the output of the ingress buffer (i.e., before the crossbar) is done to ensure
that packets are ordered regardless of their destination port. This guarantees that the producer/consumer
model is met when the data transfer involves any number of peers.

Applying ordering rules at the output of the egress buffer is done to allow packets in the EFB to be re­ordered for deadlock prevention and efficient transmission on the link without violating the PCIe ordering
rules. Without this ordering logic, packets in the EFB would need to be transmitted in the order they were
received by the EFB. If the oldest packet in the EFB lacked sufficient link credits for its departure, head-of­line blocking would occur at the EFB. The presence of ordering logic at the EFB reliefs potential head-of­line blocking by allowing other packets to be transmitted, as long as ordering rules are not violated.

Table 3.4 shows the ordering rules honored by the Switch Core. Note that the PES48T12G2 honors the
relaxed-ordering attribute in packets as shown in the table.

Row Pass Column?

Posted

Request

Non Posted

Request

Completion

Request

Memory

Write or

Message

Request

Read

Request

IO or Config­uration Write

Request

Read Com-

pletion

IO or Config­uration Write

Completion

Posted

Request

Memory

Write or

Message

Request

No YesYesYesYes

No No No Yes Yes

No No No Yes Yes

‘Yes’ if packet

has RO bit

set; Else ‘No’

Non-Posted Request Completion

IO or

Read

Request

Yes Yes No No

Yes Yes No No

Configur

ation

Write

Request

Read

Comple-

tion

IO or

Configur

ation

Write

Comple-

tion

Table 3.4 Packet Ordering Rules in the PES48T12G2

Arbitration

Packets stored in the ingress buffers are subject to arbitration as they are moved towards the egress
port. The switch core performs all packet arbitration functions in the switch. Architecturally, arbitration is
done at the egress ports. Each port has a dedicated arbitration configuration as programmed in the port’s
VC Capability Structure.

Packets undergo two levels of arbitration at an egress port:

– Port arbitration within a VC
– VC arbitration for access to the egress link

Figure 3.2 shows the architectural model of arbitration. The following sub-sections describe arbitration in
detail.

Note: There are no ports 10 and 11 in this device.

PES48T12G2 User Manual 3 - 4 April 5, 2013

IDT Switch Core

Notes

Port 0 IFB

VC 0

Port 1 IFB

VC 0

Port 13 IFB

VC 0

EFB

VC 0

VC 0

Port

Arbitration

VC

Arbitration

(not

applicable)

Port 0 Egress Arbitration

TC/
VC

Map

EFB

VC 0

VC 0

Port

Arbitration

VC

Arbitration

(not

applicable)

Port 13 Egress Arbitration

TC/

VC

Map

Figure 3.2 Architectural Model of Arbitration

Port Arbitration

Each egress port does port arbitration among multiple ingress ports for packets. Each egress port
contains a port arbiter. Ingress port(s) that wish to transfer one or more packets to the egress port partici­pate in arbitration.

Prior to participating in port arbitration, each ingress port does packet ordering. Based on this, each
ingress port selects zero, one, or multiple packets as candidates for transfer towards the EFBs.Port arbitra­tion is done according to the configuration of the egress port’s VC Capability Structure. The PES48T12G2
ports operating in upstream switch port or downstream switch port mode support port arbitration using

Hardware Fixed Round-Robin (default) and 32-phase Weighted Round-Robin (WRR) algorithms

1

. The arbi­tration algorithm and WRR arbitration parameters are programmed independently for each of the ports via
the VC Capability Structure located in the port’s configuration space.

Cut-Through Routing

The PES48T12G2 utilizes a combined input and output buffered cut-through switching architecture to
forward PCIe TLPs between switch ports. Cut-through means that while a TLP is being received on an
ingress link, it can be simultaneously routed across the switch and transferred on the egress link. The entire
TLP need not be received and buffered prior to starting the routing process (i.e., store-and-forward). This
reduces the latency experienced by packets as they are transferred across the switch.

Typically, cut-through occurs when a TLP is received on an ingress link whose bandwidth is greater than
or equal to the bandwidth of the egress link. For example, a TLP received on a x4 Gen2 port and destined
to a x1 Gen2 port is cut-through the switch. This rule ensures that the ingress link has enough bandwidth to
prevent ‘underflow’ of the egress link. In addition to this, the PES48T12G2 does “adaptive cut-through”,
meaning that packets are cut-through even if the egress link bandwidth is greater than the ingress link
bandwidth. In this case, the cut-through transfer starts when the ingress port has received enough quantity
of the packet such that the packet can be sent to the egress link without underflowing this link.

1.

Weighted round robin arbitration with 32-phases is implemented by converting the PCIe port arbitration table
into weighted round robin counts. Therefore, over short intervals grants may not match the phase table configura­tion.

PES48T12G2 User Manual 3 - 5 April 5, 2013

IDT Switch Core

Notes

The ingress and egress link bandwidth is determined by the negotiated speed and width of the links.

Table 3.5 shows the conditions under which cut-through and adaptive-cut-through occur. When the condi-

1

tions are met, cut-through is performed across the IFB, crossbar

, and EFB. Note that a packet undergoing
a cut-through transfer across the Switch Core may be temporarily delayed by the presence of prior packets
in the IFB and/or EFB. In this case, the packet starts cutting-through as soon as it becomes unblocked by
prior packets.

When cut-through routing of a packet is not possible, the packet is fully buffered in the appropriate IFB
prior to being transferred to the EFB and towards the egress link (i.e., store-and-forward operation). Once
the packet is stored in the IFB, there is no necessity to fully store it in the EFB as it is transferred towards
the egress link.

Ingress

Link

Speed

2.5 Gbps x8 2.5 x8, x4, x2, x1 Always

Ingress

Link

Width

x4 2.5 x4, x2, x1 Always

x2 2.5 x2, x1 Always

x1 2.5 x1 Always

Egress

Link

Speed

5.0 x4, x2, x1 Always

5.0 x2, x1 Always

5.0 x1 Always

Egress

Link

Width

x8 At least 50% of packet is in IFB

x8 At least 50% of packet is in IFB

x4 At least 50% of packet is in IFB

x8 At least 75% of packet is in IFB

x4 At least 50% of packet is in IFB

x8 At least 75% of packet is in IFB

x2 At least 50% of packet is in IFB

x4 At least 75% of packet is in IFB

x8 At least 100% of packet is in IFB

Conditions for Cut-

Through

x2 At least 50% of packet is in IFB

x4 At least 75% of packet is in IFB

x8 Never (100% of packet is in IFB)

5.0 x1 At least 50% of packet is in IFB

x2 At least 75% of packet is in IFB

x4 Never (100% of packet is in IFB)

x8

Table 3.5 Conditions for Cut-Through Transfers (Part 1 of 2)

1.

During cut-through transfers, the crossbar maintains the connection between the appropriate IFB and EFB

through-out the duration of the transfer.

PES48T12G2 User Manual 3 - 6 April 5, 2013

IDT Switch Core

Notes

Ingress

Link

Speed

5.0 Gbps x8 2.5 x8, x4, x2, x1 Always

Ingress

Link

Width

x4 2.5 x8, x4, x2, x1 Always

x2 2.5 x8 At least 50% of packet is in IFB

x1 2.5 x8 At least 75% of packet is in IFB

Egress

Link

Speed

5.0 x8, x4, x2, x1 Always

5.0 x8 At least 50% of packet is in IFB

5.0 x8 At least 75% of packet is in IFB

5.0 x8 Never (100% of packet is in IFB)

Egress

Link

Width

x4, x2, x1 Always

x4, x2, x1 Always

x4 At least 50% of packet is in IFB

x2, x1 Always

x4 At least 50% of packet is in IFB

x2, x1 Always

x4 At least 75% of packet is in IFB

x2 At least 50% of packet is in IFB

Conditions for Cut-

Through

x1 Always

Table 3.5 Conditions for Cut-Through Transfers (Part 2 of 2)

Request Metering

Request metering may be used to reduce congestion in PCI express switches caused by a static rate
mismatch. Request metering is available on all PES48T12G2 switch ports but is disabled by default. A
static rate mismatch is a mismatch in the capacity of the path from a component injecting traffic into the
fabric (e.g., a Root Complex) and the ultimate destination (e.g., an Endpoint).

An example of a static rate mismatch in a PCIe fabric is a x8 root injecting traffic destined to a x1
endpoint. PCIe fabrics are typically no more than one switch deep. Therefore, static rate mismatches typi­cally occur within a switch due to asymmetric link rates. Figure 3.3 illustrates the effect of congestion on
PCIe fabric caused by a static rate mismatch. In this example there are two endpoints issuing memory read
requests to a root. Endpoint A has a x1 link to the switch, while endpoint B and the root complex have a x8
link.

Memory read request TLPs are three or four DWords in size. A single memory read request may result
in up to 4 KB of completion data being returned to the requester. Depending on system architecture and
configured maximum payload size, this completion data may be returned as a single completion TLP or
may be returned as a series of small (e.g., 64B data) TLPs.

Consider an example where Endpoints A and B are injecting read request to the root at a high rate and
the root is able to inject completion data into the fabric at a rate higher than which may be supported by
endpoint A’s egress link. The result is that the endpoint A’s EFB and the root’s IFB may become filled with
queued completion data blocking completion data to endpoint B.

PES48T12G2 User Manual 3 - 7 April 5, 2013

IDT Switch Core

Notes

Root Port

IFB

Switch Core

Endpoint A

EFB

Endpoint B

EFB

Root

(x8)

Endpoint A

(x1)

Endpoint B

(x8)

Request

1

Request

2

Request

3

Time

Request

1

Request

2

Request

3

Time

Estimate of Request 1

Completion Transfer Time

Estimate of Request 2

Completion Transfer Time

(a) Request Injection without Request Metering

(b) Request Injection with Request Metering

If read requests are injected sporadically or at a low rate, then buffering within the switch may be used to
accommodate short lived contention and allow completions to endpoints to proceed without interfering. If
read requests are injected at a high rate, then no amount of buffering in the switch will prevent completions
from interfering.

PCIe has no end-to-end QoS mechanisms. Therefore, it is common for Endpoints to be designed to
inject requests into a fabric at high rates. Request metering is a congestion avoidance mechanism that
limits the request injection rate into a fabric. Although this example illustrates the effect of a static rate
mismatch in an I/O connectivity application, similar situations may occur in system interconnect applica­tions.

Figure 3.3 PCIe Switch Static Rate Mismatch

The request metering operation is illustrated Figure 3.4. Figure 3.4(a) shows requests injection without
request metering. Figure 3.4(b) shows requests injection with request metering. Request metering is imple­mented by logic at the interface between the IFB and the switch core arbiter. When a request reaches the
head of the non-posted IFB queue, request metering logic examines the request and estimates the amount
of time that the associated completion TLPs will consume on the endpoint link (i.e., completion transfer
time). The request is then allowed to proceed and a timer is initiated with the estimated completion transfer
time. The next request from that IFB is not allowed to proceed until the timer has expired.

PES48T12G2 User Manual 3 - 8 April 5, 2013

Figure 3.4 PCIe Switch Static Rate Mismatch

IDT Switch Core

Notes

0 DW ords Fractional Part

Sign 13 bits 11 bits

Request Metering C ount
(24 bits)

0 DW ords Nibbles

Init ial V alu e L oa d e d into
Request Metering C ounter

0000 0000

Sign 13 bits 8 bits

3 bits

The request metering implementation in the PES48T12G2 makes a number of simplifying assumptions
that may or may not be true in all systems. Therefore, it should be expected that some amount of parameter
tuning may be required to achieve optimum performance.

Note that tuning of the request metering mechanism should take into account the completion timeout
value of the associated requesters (i.e., request metering should be tuned such that a requester’s comple­tion timeout value is not violated).

Operation

The completion transfer timer is implemented using a counter. The counter is loaded with an estimate of
the number of DWords that will be transferred on the link in servicing the completion and is decremented at
a rate that corresponds to the number of DWords that will be transferred on the link in a 4ns period.

Request metering is enabled on an input port when the Enable (EN) bit is set in the Requester Metering
Control (RMCTL) register. An non-posted request TLP is allowed to be transferred into the switch core
when the request metering counter is zero.

When a request is transferred into the switch core, the request metering counter is loaded with a value
that estimates the number of DWords associated with the corresponding completion(s). The method for
determining this value is described in section Completion Size Estimation on page 3-11.

– The request metering counter is a 24-bit counter. The count represents a signed-magnitude fixed-

point 0:13:11 number (i.e., a positive number with 13 integer bits and 11 fractional bits) but is
treated by the logic as a 24-bit unsigned integer.

– The value loaded into the request metering counter for the last non-posted request is available in

the Count (COUNT) field of the Request Metering Counter (RMCOUNT) register.

The requester metering initial counter value computed as described in section Comple­tion Size Estimation on page 3-11 is a sign-magnitude fixed point 0:13:3 number (i.e., a
positive number with 13 integer bits and 3 fractional bits).

The least significant eight fractional bits of the initial counter value are always implicitly
zero.

Figure 3.5 shows the request metering count and its initial value.

PES48T12G2 User Manual 3 - 9 April 5, 2013

Figure 3.5 Request Metering Count and Initial Value Loaded

The request metering counter is decremented by a value that corresponds to the number of DWords
transferred on the link per 4ns period. The value is equal to the sum of the decrement value plus the value
of the Decrement Value Adjustment (DVADJ) field in the RMCTL register.

The decrement value is a sign-magnitude fixed-point 0:4:3 number (i.e., an positive number with 4
integer bits and 3 fractional bits), determined by the port’s negotiated link width and speed as shown in
Table 3.6.

– The least significant eight fractional bits of the decrement value are always implicitly zero.

IDT Switch Core

Notes

0 DWords Nibbles

Sign 4 bits 3 bits

Fixed Decrement Value

0 DWords Fractional Part

Sign 4 bits 11 bits

Decrement Value Adjustment

0000 0000

8 bits

0 DWords Fractional Part

Sign 4 bits 11 bits

Actual Decrement Value

The Decrement Value Adjustment (DVADJ) field represents a sign-magnitude fixed point 0:4:11 number
(i.e., a positive fixed-point number with 4 integer bits and 11 fractional bits).

– DVADJ field provides fine grain programmable adjustment of the value by which the counter is

decremented.

– The sign bit in the DVADJ field should not be set to negative (i.e., 0b1).

Figure 3.6 shows the decrement value and the decrement value adjustment.

The counter stops decrementing when it reaches zero or when a rollover occurs (i.e., the decrement
causes it to become negative).

The computation that occurs on each clock tick by the request metering counter is shown Figure 3.7.

Figure 3.6 Decrement Value and Decrement Value Adjustment

Link

Width

Link

Speed

Decrement Value Notes

x1 Gen 1 0x02 Corresponds to 1 Byte per clock tick

x2 Gen 1 0x04 Corresponds to 2 Bytes per clock tick

x4 Gen 1 0x08 Corresponds to 4 Bytes per clock tick

x8 Gen 1 0x10 Corresponds to 8 Bytes per clock tick

x1 Gen 2 0x04 Corresponds to 2 Bytes per clock tick

x2 Gen 2 0x08 Corresponds to 4 Bytes per clock tick

x4 Gen 2 0x10 Corresponds to 8 Bytes per clock tick

x8 Gen 2 0x20 Corresponds to 16 Bytes per clock tick

Table 3.6 Request Metering Decrement Value

PES48T12G2 User Manual 3 - 10 April 5, 2013

IDT Switch Core

Notes

tmp = RequestMeteringCounter

RequestMeteringCounter -= (DecrementValue[LinkSpeed,LinkWidth] +
RMCTL.DVADJ)

if (tmp < RequestMeteringCounter) {

RequestMeteringCounter = 0

DataDWords = Length / 4 *4

If (DataDWords == 0) {

CompletionSizeEstimate = 3

} else if (DataDWords <= CnstLimit) {

CompletionSizeEstimate = DataDWords + 1

} else {

OverheadDWords = (DataDWords >> OverheadFactor)

CompletionSizeEstimate = DataDWords + OverheadDWords

}

Figure 3.7 Request Metering Counter Decrement Operation

Completion Size Estimation

This section describes the value that is loaded into the request metering counter when a request is
transferred into the switch core. This value is referred to as the completion size estimate. The completion
size estimate is based on the type of non-posted request as described below. The request metering counter
is a 24-bit counter that represents a fixed point 0:13:11 number (i.e., an unsigned number with 13 integer
bits and 11 fractional bits).

The completion size estimate is a 0:13:3 number. The least significant eight fractional bits of the comple­tion size estimate are always implicitly zero.

Non-Posted Writes

The completion size estimate is 0x0018 which corresponds to 3 DWords (3 DWord header)

Non-Posted Reads

The completion size estimate is based on the Length field in the read request header and is computed
as shown in Figure 3.8. All arithmetic in this section is performed using an implicit 0:13:3 representation and
all values are implicitly converted to this value.

Figure 3.8 Non-Posted Read Request Completion Size Estimate Computation

The number of data DWords in a non-posted request TLP is estimated by the number of PCI Express
data credits required by the corresponding completion(s). Each PCI Express data credit is 4 DWords or 16
bytes.

– The first line in Figure 3.8 computes the number of DWords required by the completion(s) using

the number of required PCI Express data credits. This corresponds to PCI Express completion
data credits multiplied by 4.

PES48T12G2 User Manual 3 - 11 April 5, 2013

If the number of data DWords is zero, then the completion size is estimated to be three DWords (i.e., a
0:13:3 representation value of 0x0018).

– Otherwise, if the number of required data DWords is less than the Constant Limit (CNSTLIMIT)

field in the RMCTL register, then the completion size is estimated as the number of required data
DWords plus one.

IDT Switch Core

Notes

– Otherwise, if the number of required data DWords is greater than CNSTLIMIT, then the completion

size is estimated using OverheadDWords as described below.

OverheadDWords represents the number of DWords of link overhead. This includes the header, data
link layer overhead, and physical layer overhead of the completion TLP(s) associated with this request.
Ideally, OverheadDWords would be set to the number of completion TLPs associated with the request
multiplied by the TLP overhead. Unfortunately, this requires a multiplication. Therefore, the following esti­mate may be used.

A completion header is 3 DWords. There are 2 DWords of additional overhead associated with a TLP.
Therefore a reasonable estimate of the overhead is 5 DWords. In many systems, completions are 64-bytes
in size (i.e., 16 DWords in size).

OverheadDWords = (Length / 16) * 5.

– This is approximately equal to OverheadDWords = (Length / 16) * 4.
– This may be simplified to (Length / 4) and may be computed as (Length >> 2).

Thus, an acceptable value for OverheadFactor in many systems is 2. The OverheadFactor value used in
computing the completion size estimate is contained in the Overhead Factor (OVRFACTOR) field in the
RMCTL register.

Internal Errors

Internal errors are errors associated with a PCI Express interface that occurs within a component and
which may not be attributable to a packet or event on the PCI Express interface itself or on behalf of trans­actions initiated on PCI Express.

The PES48T12G2 classifies the following IDT proprietary switch errors as internal errors.

– Switch core time-outs
– Single and double bit internal memory ECC errors
– End-to-end data path parity protection errors

Internal errors are reported by the port in which they are detected through AER as outlined in the PCI­SIG Internal Error Reporting ECN. The reporting of internal errors may be disabled by clearing the Internal
Error Reporting Enable (IERROREN) bit in the port’s Internal Error Reporting Control (IERRORCTL)
register. When internal error reporting is disabled, the following AER fields become read-only:

– Uncorrectable Internal Error Mask (UIE) field in the AERUEM register
– Uncorrectable Internal Error Severity (UIE) field in the AERUESV register
– Correctable Internal Error Mask (CIE) field in the AERCEM register
– Header Log Overflow Mask (HLO) field in the AERCEM register

The PES48T12G2 does not support recording of headers for uncorrectable internal errors. When an
uncorrectable internal error is reported by AER, a header of all ones is recorded.

Corresponding to each possible internal error source is a status bit in the Internal Error Reporting Status
(IERRORSTS) register. A bit is set in the status register when the corresponding internal error is detected.
Associated with each internal error status bit in the IERRORSTS register is a mask bit in the Internal Error
Reporting Mask (IERRORMSK) register. When a mask bit is set in this register, the setting of the corre­sponding status bit is masked from generating an internal error.

Each internal error status bit has an associated severity bit in the IERRORSEV register. When an
unmasked internal error is detected, the error is reported as dictated by the corresponding severity bit (i.e.,
either an Uncorrectable Internal Error or a Correctable Internal Error). When an uncorrectable or correct­able internal error is reported, the corresponding AER status bit is set and process as dictated by the PCIe
base specification and Internal Error Reporting ECN.

To facilitate testing of software error handlers, any bit in the IERRORSTS register may be set by writing
a one to the corresponding bit position in the Internal Error Test (IERRORTST) register. Once a bit is set in
the ERRORSTS register, it is processed as though the actual error occurred (e.g., reported by AER).

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IDT Switch Core

Notes

Switch Time-Outs

The switch core discards any TLP that reaches the head of an IFB or EFB queue and is more than 64
seconds old. This includes posted, non-posted, completion and inserted TLPs. If during processing of a
TLP with broadcast routing a switch core time-out occurs, then the switch core will abort processing of the
TLP. This may result in the broadcast TLP being transmitted on some but not all downstream pots.

Memory SECDED ECC Protection

PCI Express provides reliable hop-by-hop communication between interconnected devices, such as
roots, switches, and endpoints, by utilizing a 32-bit Link CRC (LCRC), sequence numbers, and a link level
retransmission protocol. While this mechanism provides reliable communication between interconnected
devices, it does not protect against corruption that may occur inside of a device. PCI Express defines an
optional end-to-end data integrity mechanism that consists of appending a 32-bit end-to-end CRC (ECRC)
computed at the source over the invariant fields of a Transaction Layer Packet (TLP) that is checked at the
ultimate destination of the TLP. While this mechanism provides end-to-end error detection, unfortunately it
is an optional PCI Express feature and has not been implemented in many North-Bridges and endpoints. In
addition, the ECRC mechanism does not cover variant fields within a TLP.

Since deep sub-micron devices are known to be susceptible to single-event-upsets, a mechanism is
desired that detects errors that occur within a PCI Express switch.

The PES48T12G2 protects all memories (i.e., both data and control structures) with a Single Error
Correction with Double Error Detection (SECDED) Error Correcting Code (ECC). The objective of this
memory protection is to prevent silent data corruption. Single bit errors are automatically corrected and
optionally reported while double bit errors are optionally reported.

Double bit errors are uncorrectable memory errors that may compromise the integrity of control and data
structures. Detection of a double bit error may result in further modification of one or more memory bits in
the data quantity in which the error was detected (i.e., single bit error correction is not disabled when a
double bit error is detected and a double bit error may result in one or more single bit corrections).

Associated with each port are five memories: IFB control, IFB data, and EFB control, EFB data, and
Replay Buffer Control. Each port contains memory error control and status registers that are used to
manage memory errors associated with that port.

When a single or double bit error is detected in a memory, the status bit corresponding to the memory in
which the error was detected is set in the Internal Error Reporting Status (IERRORSTS) register.

A double bit error detected by a memory associated with TLP data (i.e., IFB or EFB data) results in the
TLP being nullified when it reaches the DL layer of an egress port. The TLP is nullified by inverting the
computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by a link partner are
discarded. Although the TLP is nullified, flow control credits associated with the egress port may not be
correctly updated. Thus, double bit errors could result in a flow control credit leak.

The DL layer never replays a TLP with a sequence number different from that initially used. If a double
bit error is detected during a DL layer replay, then all TLPs in the replay buffer are flushed.

If a double bit error is detected by an internal memory in a TLP that targets a function in the switch (e.g.,
a configuration read or write request to the PCI-to-PCI bridge function), then the TLP is discarded.

End-to-End Data Path Parity Protection

In addition to memory ECC protection, the PES48T12G2 supports end-to-end data path parity protec­tion. Data flowing into the PES48T12G2 is protected by the LCRC. Within the Data Link (DL) layer of the
switch ingress port, the LCRC is checked and a 32-bit DWord even parity is computed on the received TLP
data. If an LCRC error is detected at this point, the link level retransmission protocol is used to recover from
the error by forcing a retransmission by the link partner.

As the TLP flows through the switch, its alignment or contents may be modified. In all such cases, parity
is updated and not recomputed. Hence, any error that occurs is propagated and not masked by a parity
regeneration. When the TLP reaches the DL layer of the switch egress port, parity is checked and in parallel

PES48T12G2 User Manual 3 - 13 April 5, 2013

IDT Switch Core

Notes

an LCRC is computed. If the TLP is parity error free, then the LCRC and TLP contents are known to be
correct and the LCRC is used to protect the packet through the lower portion of the DL layer, PHY layer, and
link transmission.

If a parity error is detected by the DL layer of an egress port, then the TLP is nullified by inverting the
computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by the link-partner are
discarded. In addition to nullifying the TLP, the End-to-End Parity Error (E2EPE) bit is set in the Internal
Error Status (IERRORSTS) register. The DL layer never replays a TLP with a sequence number different
from that initially used. If a parity error is detected during a DL layer replay, then all TLPs in the replay buffer
are flushed.

In addition to TLPs that flow through the switch, cases exist in which TLPs are produced and consumed
by the switch (e.g., configuration requests and responses). Whenever a TLP is produced by the switch,
parity is computed as the TLP is generated. Thus, error protection is provided on produced TLPs as they
flow through the switch. In addition, parity is checked on all consumed TLPs. If an error is detected, the TLP
is discarded and an error is reported by setting the E2EPE bit in the IERRORSTS register.

A parity error reported at a switch port cannot be definitively used to identify the location within the
device at which the fault occurred as the fault may have occurred at another port, in the switch core, or may
have been generated locally (i.e., for ingress TLPs to the switch core which are consumed by the port such
as Type 0 configuration read requests on the upstream port).

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Notes

®

Chapter 4

SerDes

Quad

Port 0
Stack

SerDes

Quad

Port 1
Stack

SerDes

Quad

Port 9
Stack

SerDes

Quad

Port 12

Stack

SerDes

Quad

Port 13

Stack

Switch Core

PLL

GCLK

Port 0Port 1

Port 9 Port 12

Port 13

...

Clocking

Introduction

Figure 4.1 provides a logical representation of the PES48T12G2 clocking architecture. The
PES48T12G2 has a single differential global reference clock input (GCLK).

Figure 4.1 Logical Representation of the PES48T12G2 Clocking Architecture

The differential global reference clock input (GCLK) is driven into the device on the GCLKP[1:0] and
GCLKN[1:0] pins.

– The nominal frequency of the global reference clock input may be selected by the Global Clock

Frequency Select (GCLKFSEL) pin to be either 100 MHz or 125 MHz.

– Both global reference clock differential inputs should be driven with the same frequency. There

are no skew requirements between the GCLKP[0]/GCLKN[0] and GCLKP[1]/GCLKN[1] inputs.
Any constant phase difference is acceptable.

– The Global Clock supports Spread Spectrum Clocking (SSC).
– The global reference clock input is provided to each SerDes quad and to an on-chip PLL.

• The on-chip PLL uses this clock to generate a 250 MHz core clock that is used by internal switch

logic (e.g., switch core, portion of a stack, etc.).

• The PLL within each SerDes quad generates a 5.0 GHz clock used by the SerDes analog
portion (PMA) and a 250 MHz clock used by the digital portion (PCS).

Port Clocking Mode

Port clocking refers to the clock that a port uses to receive and transmit serial data. All ports in the switch
use the global reference clock (GCLK) input for receiving and transmitting serial data. The switch does not
introduce any requirements on the global reference clock input beyond those imposed by PCI express.
Depending on the system configuration, a port may employ the common Refclk or separate Refclk architec­tures defined by the PCIe Base specification.

PES48T12G2 User Manual 4 - 1 April 5, 2013

IDT Clocking

Notes

The port clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the boot
configuration vector as shown in Table 4.1. This field determines the initial value of the Slot Clock Configu­ration (SCLK) field in each port’s PCI Express Link Status (PCIELSTS) register. The SCLK field controls the
advertisement of whether or not the port uses the same reference clock source as the link partner. A one in
the SCLK field indicates that the port and its link partner use the same reference clock source. This is
defined as Common Clock Configuration by the PCI Express Base Specification. A zero in the SCLK field
indicates that the port and its link partner do not use the same reference clock source.

CLKMODE[1:0] Value in

Boot Configuration Vector

000

110

201

311

Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State

Port 0

SCLK

SCLK for Ports other

than Port 0

PES48T12G2 User Manual 4 - 2 April 5, 2013

Notes

®

Chapter 5

Reset and Initialization

Introduction

This chapter describes the PES48T12G2 reset and initialization.

When multiple resets are initiated concurrently, the precedence shown in Table 6.1 is used to determine
which one is acted upon.

– Reset types and causes are described in detail in the following sections.

• A switch fundamental reset affects the entire device

• A port reset affects only that one port

– When a high priority and low priority reset are initiated concurrently and the condition causing the

high priority reset ends prior to that causing the low priority reset, then the device/port immediately
transitions to the reset associated with low priority reset condition.

• If the high priority and low priority resets share the same reset type, then the device/port remains
in the corresponding reset when the high priority reset condition ends.

• If the high priority and low priority reset have different reset types, then the device/port transi­tions to the low priority reset type when the high priority reset condition ends.

Priority Reset Type Reset cause

1 (Highest) Switch fundamental reset Global reset pin (PERSTN) assertion

2 Hot reset Reception of TS1 ordered sets on upstream port indicat-

ing a hot reset

3 Hot reset Data link layer of the upstream port transitioning to

DL_Down state

4 Upstream secondary bus reset Setting of the SRESET bit in the switch’s upstream port

PCI-to-PCI bridge BCTL register

5 (Lowest) Downstream secondary bus

reset

Table 5.1 PES48T12G2 Reset Precedence

Registers and fields designated as Switch Sticky (SWSticky) or Sticky (Sticky) take on their initial value
as a result of the Switch Fundamental Reset. Other resets have no effect on registers and fields with these
designations.

All fields designated as Read Write when Unlocked (RWL) are implicitly SWSticky. Their value is
preserved across all resets except a switch fundamental reset.

Setting of the SRESET bit in the corresponding port’s
PCI-to-PCI bridge BCTL register

Boot Configuration Vector

A boot configuration vector consisting of the signals listed in Table 5.2 is sampled during a switch funda­mental reset. Since the boot configuration vector is only sampled during a switch fundamental reset, the
value of signals that make up the boot configuration vector is ignored and their state outside of a switch
fundamental reset sequence has no effect on the operation of the device.

While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require more complex initialization. This initialization may be performed by an external
SMBus device via the slave SMBus interface or may be performed automatically via the serial EEPROM.

See Chapter 12, SMBus Interfaces, for a description of the slave SMBus interface and serial EEPROM
operation.

PES48T12G2 User Manual 5 - 1 April 5, 2013

IDT Reset and Initialization

Notes

As noted in Table 5.2, some of the initial values specified by the boot configuration vector may be over­ridden by software, serial EEPROM, or an external SMBus device. The state of all of the boot configuration
signals in Table 5.2 sampled during a switch fundamental reset may be determined from the Boot Configu­ration Status (BCVSTS) register.

Signal

GCLKFSEL N Global Clock Frequency Select.

CLKMODE[1:0] Y Clock Mode.

P01MERGEN N Ports 0 and 1 Merge.

P23MERGEN N Ports 2 and 3 Merge.

P45MERGEN N Ports 4 and 5 Merge.

P67MERGEN N Ports 6 and 7 Merge.

P89MERGEN N Ports 8 and 9 Merge.

P1213MERGEN N Ports 12 and 13 Merge.

May Be

Overridden

Name/Description

This pin specifies the frequency of the GCLKP and GCLKN
signals.

These pins specify the clocking mode used by switch ports.
See Table 4.1 for a definition of the encoding of these signals.
The value of these signals may be overridden by modifying
the Port Clocking Mode (PCLKMODE) register.

This pin specifies whether ports 0 and 1 are merged.

This pin specifies whether ports 2 and 3 are merged.

This pin specifies whether ports 4 and 5 are merged.

This pin specifies whether ports 6 and 7 are merged.

This pin specifies whether ports 6 and 8 are merged.

This pin specifies whether ports 12 and 13 are merged.

RSTHALT Y Reset Halt.

When this pin is asserted during a switch fundamental reset
sequence, the PES48T12G2 remains in a reset state with the
Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal
device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the SWCTL register by
an SMBus master.

SSMBADDR[2,1] N Slave SMBus Address.

SMBus address of the switch on the slave SMBus.

SWMODE[3:0] N Switch Mode.

These pins specify the switch operating mode.

Table 5.2 Boot Configuration Vector Signals

Switch Fundamental Reset

A switch fundamental reset may be cold or warm. A cold switch fundamental reset occurs following a
device being powered-on and assertion of the global reset (PERSTN) signal. A warm switch fundamental
reset occurs when a switch fundamental reset is initiated while power remains applied. The PES48T12G2
behaves in the same manner regardless of whether the switch fundamental reset is cold or warm.

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IDT Reset and Initialization

Notes

A switch fundamental reset may be initiated by any of the following conditions.

When a switch fundamental reset is initiated, the following sequence is executed.

1. Wait for the switch fundamental reset condition to clear (e.g., negation of PERSTN).

2. On negation of PERSTN, sample the boot configuration vector signals shown in Table 5.2.

3. If the sampled Switch Mode (SWMODE[3:0]) state corresponds to a test mode, then skip the

4. All registers are initialized to their default value.

5. The Register Unlock (REGUNLOCK) bit is set in the Switch Control (SWCTL) register.

6. The PLL and SerDes are initialized (i.e., PLL lock and CDR reset).

7. Within 20 ms after the switch fundamental reset condition clears, the reset signal to the stacks is

8. Within 100 ms following clearing of the switch fundamental reset condition, the stacks enter a quasi-

– A cold switch fundamental reset initiated by application of power (i.e., a power-on) followed by

assertion of the global reset (PERSTN) signal.

– A warm switch fundamental reset initiated by assertion of PERSTN while power remains applied.

remainder of this reset sequence and execute the reset sequence outlined in tbd.

negated and link training begins on all ports. While link training takes place, execution of the reset
sequence continues.

reset state.

– All stacks that have PCIe base specification compliant link partners have completed link training.
– All stacks are able to receive and process TLPs.
– Stacks respond to configuration request TLPs with a configuration request retry status completion.

All other TLPs are ignored (i.e., flow control credits are returned but the TLP is discarded).

9. The master SMBus operating frequency is 100kH.

10. The slave SMBus is taken out of reset and initialized. The slave SMBus address is specified by the
SSMBADDR[2,1] signals in the boot configuration vector.

11. If the sampled Switch Mode (SWMODE[3:0]) state corresponds to a mode that supports serial
EEPROM initialization, then the contents of the serial EEPROM are read and appropriate switch
registers are updated.

– If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State

0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using the
current link parameters.

– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM

is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the
SMBUSSTS register.

– When serial EEPROM initialization completes or when an error is detected, the EEPROM Done

(EEPROMDONE) bit in the SMBUSSTS register is set.

12. All stacks remain in a quasi reset state while the Reset Halt (RSTHALT) bit is set in the SWCTL
register.

– In this state the entire device is operational except that the stacks remain in quasi-reset and

respond to configuration request TLPs with a configuration request retry completion status.

– This provides a synchronization point for a device on the slave SMBus to initialize the device.

When device initialization is completed, the slave SMBus device clears the RSTHALT bit allowing
the device to begin normal operation.

13. The Register Unlock (REGUNLOCK) bit is cleared in the Switch Control (SWCTL) register.

14. Normal device operation begins as dictated by the SWMODE value in the boot configuration vector.

The PCIe specification indicates that a device must respond to Configuration Request transactions
within 100ms from the end of Conventional Reset (cold, warm, or hot). Additionally, the PCIe specification
indicates that a device must respond to Configuration Requests with a Successful Completion within 1.0

PES48T12G2 User Manual 5 - 3 April 5, 2013

IDT Reset and Initialization

Notes

GCLK*

Vdd

PERSTN

SerDes

Master SMBus

Slave SMBus

CDR Lock

Link Ready

Ready for Normal Operation

Ready

Serial EEPROM Initiali zation

1. Clock not shown to scale

~285 s

Switch Ports held in Quasi-Reset Mode

Link Training

PLL Reset & Lock

> 100ns

Stable
Power

Stable
GCLK

~2 s

< 100 ms

< 200 ms

Switch ports begin to process TLPs normally

SerDes

Slave SMBus

CDR Lock

Link Ready

Ready for Normal Operation

Switch Ports held in Quasi-Reset Mode

Link Training

PLL Reset & Lock

RSTHALT

Boot Vector sampled and RSTHALT bit in SWCTL register is set

RSTHALT bit in SWCTL cleared (e.g., via slave SMBus)

GCLK*

Vdd

PERSTN

1. Clock not shown to scale

> 100ns

Stable
Power

Stable
GCLK

~285 s ~2 s

< 100 ms

Switch ports begin to process TLPs normally

second after Conventional Reset of a device. The reset sequence above guarantees that the switch will be
ready to respond successfully to configuration requests within the 1.0 second period as long as the serial
EEPROM initialization process completes within 200 ms.

Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.

The operation of a switch fundamental reset with serial EEPROM initialization is illustrated in Figure 5.1.

– During EEPROM initialization, the switch responds to a Configuration Request with Configuration-

Request-Retry-Status Completion.

– Under normal circumstances, 200 ms is more than adequate to initialize registers in the device

even with a Master SMBus operating frequency of 100 KHz.

Figure 5.1 Switch Fundamental Reset with Serial EEPROM Initialization

The operation of a switch fundamental reset using RSTHALT is illustrated in Figure 5.2.

PES48T12G2 User Manual 5 - 4 April 5, 2013

Figure 5.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State

IDT Reset and Initialization

Notes

Hot Resets

Hot resets may be subdivided into three subcategories: switch hot reset, upstream secondary bus reset,
and downstream secondary bus reset. These subcategories correspond to resets defined by the PCI
Express architecture.

Hot Reset

A switch hot reset is initiated by any of the following events.

When a switch hot reset is initiated, the following sequence of actions take place.

1. The upstream port (i.e., configured as Upstream Switch Port) transitions its PHY LTSSM

2. Each downstream switch port whose link is up propagates a hot reset by transmitting TS1 ordered

3. All register fields and registers associated with the switch except those designated Sticky and

4. As long as the condition that initiated the switch hot reset persists, logic associated with the switch

5. Ports begin to link train and normal switch operation begins.

– A fundamental reset logically causes all logic associated with the switch to take on its initial state.
– A hot reset logically causes all logic to be returned to an initial state, but does not cause the state

of register fields denoted as Sticky or SWSticky to be modified.

– An upstream secondary bus reset logically causes all devices on the virtual PCI bus of the switch

to be hot reset except the upstream port (e.g., upstream PCI to PCI bridge).

– A downstream secondary bus reset causes a hot reset to be propagated on the corresponding

external link.

– Reception of TS1 ordered-sets on the switch’s upstream port indicating a hot reset.
– Data link layer of the switch’s upstream port transitions to the DL_Down state.

1

state to
the appropriate state (i.e., the Hot-Reset state on reception of TS1 ordered-sets indicating hot-reset
or else the Detect state).

sets with the hot reset bit set. All logic associated with the switch (i.e., switch ports, switch core, etc.)
is logically reset to its initial state.

• If the link associated with a downstream port is in the Disabled LTSSM state, then a hot reset
will not be propagated out on that port. The port will instead transition to the Detect LTSSM state.
Although not a hot reset, this has the same functional effect on downstream components.

SWSticky, are reset to their initial value. The value of Sticky and SWSticky registers and fields is
preserved across a hot reset.

remains at this step.

Upstream Secondary Bus Reset

An upstream secondary bus reset is initiated by any of the following events.

– A one is written to the Secondary Bus Reset (SRESET) bit in the switch’s upstream port Bridge

Control (BCTL) register

2

.

When an Upstream Secondary Bus Reset occurs, the following sequence of actions take place on logic

associated with the switch.

1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with
the hot reset bit set.

• If the link associated with a downstream port is in the Disabled LTSSM state, then a hot reset
will not be propagated out on that port. The port will instead transition to the Detect LTSSM state.
Although not a hot reset, this has the same functional effect on downstream components.

2. All registers fields in all registers associated with downstream ports, except those designated Sticky
and SWSticky, are reset to their initial value. The value of fields designated Sticky or SWSticky is
unaffected by an Upstream Secondary Bus Reset.

1.

The term ‘LTSSM’ refers to a port’s Link Training and Status State Machine in the Physical Layer.

2.

Note that the Bridge Control Register is only present in Type 1 Configuration Headers (i.e., PCI-to-PCI Bridge

functions).

PES48T12G2 User Manual 5 - 5 April 5, 2013

IDT Reset and Initialization

Notes

3. All TLPs received from downstream ports and queued in the switch are discarded.

4. Logic in the stack and switch core associated with the downstream ports are gracefully reset.

5. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge

6. Normal downstream port operation begins.

The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and

Type 0 configuration read and write transactions that target the upstream port complete normally.

During an Upstream Secondary Bus Reset, all TLPs destined to the secondary side of the upstream

port’s PCI-to-PCI bridge are treated as unsupported requests.

The operation of the slave SMBus interface is unaffected by an Upstream Secondary Bus Reset. Using
the slave SMBus to access a register that is reset by an Upstream Secondary Bus Reset causes the
register’s default value to be returned on a read and written data to be ignored on writes.

Downstream Secondary Bus Reset

A downstream secondary bus reset may be initiated by the following condition:

When a Downstream Secondary Bus Reset occurs, the following sequence of actions take place.

The operation of the upstream port is unaffected by a downstream secondary bus reset. The operation
of other downstream ports is unaffected by a downstream secondary bus reset. During a downstream
secondary bus reset, Type 0 configuration read and write transactions that target the downstream port
complete normally, and all TLPs destined to the secondary side of the downstream port’s PCI-to-PCI bridge
are treated as unsupported requests.

Control Register (BCTL).

– A one is written to the Secondary Bus Reset (SRESET) bit in a downstream port’s Bridge Control

Register (BCTL).

– If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are

transmitted

– All TLPs received from corresponding downstream port and queued are discarded.
– Wait for software to clear the Secondary Bus Reset (SRESET) bit in the downstream port’s Bridge

Control Register (BCTL).

– Normal downstream port operation begins.

Port Merging

The switch allows merging of ports to form a single port whose link width is the aggregate sum of the
individual port widths. Port merging is only supported between an even numbered port and its subsequent
odd numbered port. The PxyMERGEN signals, sampled during switch fundamental reset, select which
ports are merged. For example, if the P45MERGEN signal is driven asserted (i.e., low) at switch funda­mental reset, then ports 4 and 5 are merged. It is not possible to change this port configuration until a
subsequent switch fundamental reset.

When two ports are merged, the even numbered port is active and its odd-numbered pair is de-acti­vated. For example, when ports 4 and 5 are merged, port 4 remains active and port 5 is de-activated. A de­activated port has the following behavior:

– All output signals associated with the port are placed in a negated state (e.g., link status and hot-

plug signals).

• The negated value of PxAIN, PxILOCKP, PxPEP, PxPIN, and PxRSTN is determined as shown
in Table 9.2.

• PxACTIVEN and PxLINKUPN are negated.

– All input signals associated with the port are ignored and have no effect on the operation of the

device.

PES48T12G2 User Manual 5 - 6 April 5, 2013

IDT Reset and Initialization

Notes

• The state of the following hot-plug input signals is ignored: PxAPN, PxMRLN, PxPDN, PxPFN,
and PxPWRGDN.

– The port is not associated with a PCI Express link. PCI Express configuration requests targeting

the port are not possible and the port is not part of the PCI Express hierarchy.

– The port is not associated with any switch partition. The port is unaffected by the state of any

switch partition, and vice-versa.

– Unused logic is placed in a low power state.
– All registers associated with the port remain accessible from the global address space.

1

– The port remains in this state regardless of the setting of the port’s operating mode (i.e., via the

port’s SWPORTxCTL register).

1.

Refer to Chapter 14, Register Organization, for details on the switch’s global address space.

PES48T12G2 User Manual 5 - 7 April 5, 2013

IDT Reset and Initialization

Notes

PES48T12G2 User Manual 5 - 8 April 5, 2013

Notes

®

Chapter 6

Link Operation

Introduction

Link operation in the PES48T12G2 adheres to the PCI Express 2.0 Base Specification, supporting
speeds of 2.5 GT/s and 5.0 GT/s. The PES48T12G2 contains sixteen x4 ports which may be merged in
pairs to form x8 ports. The default link width of each port is x4 and the SerDes lanes are statically assigned
to a port.

Each port supports upstream and downstream link behavior. The behavior is determined dynamically by
the port’s operating state (i.e., upstream switch port, downstream switch port). A full link retrain is defined as

retraining of a link that transitions through the Detect LTSSM

Polarity Inversion

Each port of the PES48T12G2 supports automatic polarity inversion as required by the PCIe specifica­tion. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its
data. During link training, the receiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for
inversion of the PExRP[n] and PExRN[n] signals. If an inversion is detected, then logic for the receiving
lane automatically inverts received data. Polarity inversion is a lane and not a link function. Therefore, it is
possible for some lanes of link to be inverted and for others not to be inverted.

1

state.

Lane Reversal

The PCIe specification describes an optional lane reversal feature. The PES48T12G2 supports the
automatic lane reversal feature outlined in the PCIe specification. The operation of lane reversal is depen­dent on the maximum link width determined dynamically by the PHY. The maximum link width is the
minimum of:

– The value of the MAXLNKWDTH field in the port’s PCI Express Link Capabilities (PCIELCAP)

register.

– The number of consecutive lanes detected during the Detect state on which valid training sets are

received.

Lane reversal mapping for the various non-trivial maximum link width configurations supported by the
PES48T12G2 is illustrated in Figures 6.1 and 6.5.

1.

The term ‘LTSSM’ refers to a port’s Link Training and Status State Machine in the Physical Layer.

PES48T12G2 User Manual 6 - 1 April 5, 2013

IDT Link Operation

Notes

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 0
lane 1
lane 2
lane 3

(a) x4 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 3
lane 2
lane 1
lane 0

(b) x4 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 0
lane 1

(a) x2 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 1
lane 0

(b) x2 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 0

(a) x1 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 0

(b) x1 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 0
lane 1

(a) x2 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 1
lane 0

(b) x2 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 0

(c) x1 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES48T12G2

lane 0

(d) x1 Port with lane reversal

Figure 6.1 Unmerged Port Lane Reversal for Maximum Link Width of x4

Figure 6.2 Unmerged Port Lane Reversal for Maximum Link Width of x2

PES48T12G2 User Manual 6 - 2 April 5, 2013

IDT Link Operation

Notes

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0
lane 1

(a) x2 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 1
lane 0

(b) x2 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0

(c) x1 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0

(d) x1 Port with lane reversal

Figure 6.3 Merged Port Lane Reversal for Maximum Link Width of x2

PES48T12G2 User Manual 6 - 3 April 5, 2013

IDT Link Operation

Notes

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0
lane 1
lane 2
lane 3

(a) x4 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 3
lane 2
lane 1
lane 0

(b) x4 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0
lane 1

(c) x2 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 1
lane 0

(d) x2 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0

(e) x1 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0

(f) x1 Port with lane reversal

PES48T12G2 User Manual 6 - 4 April 5, 2013

Figure 6.4 Merged Port Lane Reversal for Maximum Link Width of x4

IDT Link Operation

Notes

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0
lane 1
lane 2
lane 3
lane 4
lane 5
lane 6
lane 7

(a) x8 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 7
lane 6
lane 5
lane 4
lane 3
lane 2
lane 1
lane 0

(b) x8 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0
lane 1
lane 2
lane 3

(c) x4 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 3
lane 2
lane 1
lane 0

(d) x4 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0
lane 1

(e) x2 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 1
lane 0

(f) x2 Port with lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0

(g) x1 Port without lane reversal

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

PES48T12G2

lane 0

(h) x1 Port with lane reversal

Figure 6.5 Merged Port Lane Reversal for Maximum Link Width of x8

Link Width Negotiation

The PES48T12G2 ports support the optional link variable width negotiation feature outlined in the PCI
Express 2.0 specification. The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link
Capabilities (PCIELCAP) register contains the maximum link width that the port can achieve. This field is of
RWL type and may be modified when the REGUNLOCK bit is set in the SWCTL register. Modification of
this field allows the maximum link width of the port to be configured. The new link width takes effect the next
time full link training occurs.

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IDT Link Operation

Notes

The actual link width is determined dynamically during link training. Ports limited to a maximum link
width of x8 are capable of negotiating to a x8, x4, x2, or x1 link width. The current negotiated width of a link
may be determined from the Negotiated Link Width (NLW) field in the corresponding port’s PCI Express
Link Status (PCIELSTS) register.

To force a link width to a smaller width than the default value, the MAXLNKWDTH field could be config­ured through Serial EEPROM initialization and full link retraining forced by setting the Full Link Retrain
(FLRET) bit in the port’s PHYLSTATE0 register.

For details, refer to the description of the MAXLNKWDTH field in the PCIELCAP register in Chapter 15.

Link Width Negotiation in the Presence of Bad Lanes

In an effort to maximize the link width when one or more lanes of a multi-lane link are not functioning
correctly (i.e., reliable communication of training sets across the lane is not possible), PES48T12G2 down­stream switch ports automatically attempt a lane reversed configuration when doing so has the potential to
enhance the achievable link width.

For example, if lane 1 of a x4 link is not operating correctly, the device’s downstream switch port
attached to the link attempts a lane reversed configuration to form a x2 link using lanes 2 and 3 (Figure 6.4
(d)). If the link partner accepts the lane reversed configuration, the optimal x2 link will be formed using lanes
2 and 3. If the link partner does not accept the lane reversed configuration, but instead requests a lane
configuration supported by the PES48T12G2 (e.g., x1 link using lane 0), the device accepts the configura­tion and forms the reduced width link. Otherwise, if the lane numbering agreement fails, the device auto­matically re-trains the link from the Detect state. During this re-training, the PES48T12G2 port does not re­attempt a lane reversed configuration, but rather tries to form the link without reversing the lanes. As a
result, a x1 link is formed using lane 0 (Figure 6.4 (e)).

Dynamic Link Width Reconfiguration

PES48T12G2 ports support dynamic link width upconfiguration and downconfiguration in response to
link partner requests. This capability is honored for regular links and crosslinks.

PES48T12G2 ports do not initiate autonomous link width upconfiguration and downconfiguration of
links, except for downconfiguration due to link reliability reasons. Therefore, the Hardware Autonomous
Width Disable (HAWD) bit in the ports PCIELCTL register has no effect and is hardwired to 0x0. Addition­ally, the PES48T12G2 port’s never set the ‘Autonomous Change’ bit in the training sets exchanged with the

link partner during link training.

1

A downstream port link partner may autonomously change link width. When this occurs, the
PES48T12G2 downstream port sets the Link Autonomous Bandwidth Status (LABWSTS) bit in the
PCIELSTS register.

Link Speed Negotiation

The PCI Express 2.0 specification introduces support for 5.0 GT/s data rates per lane (a.k.a., Gen2), in
addition to the 2.5 GT/s data rates (a.k.a, Gen1) mandated in previous versions of the specification. Per the
PCIe specification, all lanes of a link must operate at the same data rate. During full link training (i.e., from
the Detect state), links initially operate at 2.5 GT/s. Once the LTSSM on both components of the link reach
the L0 state and the data-link layer enters the DL_Active state, the link speed may be upgraded to 5.0 GT/s
if this capability is advertised by both components. The process of upgrading the link speed does not result
in a DL_Down state.

1.

Note that the ‘Autonomous Change’ bit is located in bit 6 of the fourth symbol in the training sets. This bit has
multiple meanings depending on the LTSSM state in which it is issued. PES48T12G2 never sets this bit in LTSSM
states in which this bit carries the ‘autonomous change’ meaning.

PES48T12G2 User Manual 6 - 6 April 5, 2013

IDT Link Operation

Notes

A component advertises its supported speeds via the Data Rate Identifier bits in the TS1 and TS2
training sets transmitted to its link partner during link training. The PCIe spec permits a component to
change its supported speeds dynamically. It is allowed for a component to advertise supported link speeds
without necessarily changing the link speed, via the Recovery LTSSM state.

A component determines the supported speeds of its link partner by examining the Data Rate Identifier
bits in the TS1/TS2 training sets received during link training, specifically in the Configuration.Complete and
Recovery.RcvrCfg states. The last advertisement received overrides any previously recorded value.

Either link component may request a link speed change due to software requests or link reliability
reasons (i.e., speed downgrade). Downstream components are further permitted to request link speed
changes due to autonomous hardware initiated mechanisms. A component must only initiate a link speed
change when it knows that its link partner supports the target speed via prior exchange of Training Sets.
Gen2 support is optional while Gen1 support is mandatory.

If neither component in the link advertises support for Gen2, then the link remains operating in Gen1
speed. If one component has advertised support for Gen1 and Gen2, and the other has advertised support
for Gen1 only, then the link will remain operating in Gen1 speed until the lesser speed component decides
to:

– Advertise support for Gen2 via the Recovery state without modifying the link speed. The link

remains operating at Gen1 speed.

– Transition the link speed to Gen2 via the Recovery.Speed state. The link will operate at Gen2

speed. In this case, the advertisement of Gen2 speed by both components is done implicitly in the
Recovery substates entered while modifying the link speed.

It is the responsibility of the upstream component of the link (i.e., switch downstream ports) to keep the
link at the target link speed or at the highest common speed supported by both components of the link,
whichever is lower. In addition, the upstream component must initiate a link speed upgrade if it has
recorded support for the higher speed by its link partner and software sets the Link Retrain bit in the
PCIELCTL register with a target link speed which is not equal to the current link speed. The upstream
component (i.e., switch downstream port) is capable of notifying software of link speed changes via the Link
Bandwidth Notification mechanism described in the PCI Express 2.0 specification.

Link Speed Negotiation in the PES48T12G2

PES48T12G2 ports support data rates of 5.0 GT/s and 2.5 GT/s. The highest data rate of each link is
determined dynamically, and depends on the following factors:

– Maximum link data rate supported by both components of the link
– The Target Link Speed set via the Link Control 2 Register (PCIELCTL2)
– The reliability of the link at 5.0 GT/s

By default, the Target Link Speed (TLS) of each port is set to 5.0 GT/s. Therefore, the PES48T12G2
ports advertise support for 2.5 GT/s and 5.0 GT/s during the link training process via training-sets.

– During normal operation, the TLS field should not be modified in an upstream port.

After a fundamental reset, each port link trains to the L0 state at 2.5 GT/s (Gen1). Once the data-link
layer reaches the DL_Active state, if the Target Link Speed indicates 5.0 GT/s (default value), the switch’s
downstream ports automatically initiate link speed upgrade to 5.0 GT/s (Gen2) using the link speed change
mechanism described in PCI Express 2.0 specification. Upstream ports do not automatically initiate link
speed upgrade to Gen2.

– The Initial Link Speed Change Control (ILSCC) bit in a port’s PHYLCFG0 register controls whether

the port automatically initiates a speed upgrade to Gen2. If the ILSCC bit is set, the port does not
automatically initiate a speed change to Gen2. Software may modify this bit to change the default
behavior.

– The Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register of downstream

ports is not set since the initial link speed upgrade is not caused by a software directed link retrain
or due to link reliability issues.

PES48T12G2 User Manual 6 - 7 April 5, 2013

IDT Link Operation

Notes

The current link speed of each port is reported via the Current Link Speed (CLS) field of the port’s Link
Status Register (PCIELSTS). The above behavior applies after full link retrain (i.e., when the LTSSM transi­tions through the ‘Detect’ state). Assuming the target link speed is set to 5.0 GT/s, a PES48T12G2 port initi­ates a link speed upgrade in the following cases:

– Link speed upgrade after initial link train (i.e., from the Detect state) to L0 at 2.5 GT/s, when the

link partner advertised support for the higher speed.

– Link speed upgrade after full link retrain (i.e., via the Detect state) to L0 at 2.5 GT/s, when the link

partner advertised support for the higher speed.

PES48T12G2 User Manual 6 - 8 April 5, 2013

IDT Link Operation

Notes

– When software sets the Link Retrain (LRET) bit in the PCIELCTL register and the PES48T12G2

port has recorded support for the higher speed by its link partner.

1

When operating at 5.0 GT/s, a PES48T12G2 port initiates a link speed downgrade in the following
cases:

– When the PHY layer cannot achieve reliable operation at the higher speed. In this case, the

switch’s port continues to support the higher speed in the training-sets it transmits during link
training.

– When software sets the target link speed to 2.5 GT/s and sets the LRET bit in the PCIELCTL

register. In this case, the switch’s port removes support for the higher speed in the training-sets it
transmits during link training.

Additionally, the PES48T12G2 ports always respond to link partner requests to change speed. In this
case, the speed change is only successful when both components in the link advertise support the target
speed. When a link speed upgrade operation fails, the PHY LTSSM reverts back to the speed before the
upgrade (i.e., 2.5 GT/s) and does not autonomously initiate a subsequent link speed upgrade. In this case,
the PHY continues to support Gen1 and Gen2 data rates and therefore responds to link partner requests for
link speed upgrade, or to link speed upgrades triggered by software setting the LRET bit in the port’s
PCIELCTL register.

The PES48T12G2 ports do not have a mechanism to autonomously regulate link speed. As a result, the
Hardware Autonomous Speed Disable (HASD) bit in the PCIELCTL2 register has no effect and is hardwired
to 0x0. Additionally, PES48T12G2 ports never set the ‘Autonomous Change’ bit in the training sets

exchanged with the link partner during link training

2

. Still, a link partner connected to a PES48T12G2 down­stream port may autonomously change link speed. When this occurs, the PES48T12G2 downstream port
sets the Link Autonomous Bandwidth Status (LABWSTS) bit in the PCIELSTS register.

A system designer may limit the maximum speed at which each port operates by changing the target
link speed via software or EEPROM and forcing link retraining. Refer to section Link Retraining on page 6­10 for further details.

Software Management of Link Speed

Software can interact with the link control and status registers of downstream ports to set the link speed,
as well as receive notification of link speed changes. This gives software the capability to choose the
desired link speed based on system specific criteria. For example, depending on the traffic load expected
on a link, software can choose to downgrade link speed to 2.5 GT/s in order to reduce power on a low-traffic
link, and later upgrade the link to 5.0 GT/s when the bandwidth is required. Software may also choose to
change the link speed due to link reliability reasons (i.e., a link that has reliability problems at 5.0 GT/s may
be downgraded to 2.5 GT/s).

As mentioned above, the Target Link Speed (TLS) field of the port’s Link Control 2 Register
(PCIELCTL2) sets the preferred link speed. By default, the Target Link Speed of each PES48T12G2 port is
set to 5.0 GT/s. During normal operation, the link speed of a downstream port may be modified by setting
the TLS field of the port’s PCIELCTL2 register to the desired speed and initiating link retraining by writing a
one to the Link Retrain (LRET) bit in the Link Control (PCIELCTL) register.

– The port will only initiate a change to a higher speed if the link partner advertised support for the

higher speed in its latest entry to the Configuration.Complete or Recovery.RcvrCfg states.

– If a speed change is initiated to a speed not supported by the link partner, then the port will remain

at the current speed by transitioning through the Recovery state without the “Speed_Change” bit
set.

1.

The speed advertisement of the link partner is noted by PES48T12G2 in the latest LTSSM entry to the Configu-

ration.Complete or Recovery.RcvrCfg sub-states.

2.

Note that the ‘Autonomous Change’ bit is located in bit 6 of the fourth symbol in the training sets. This bit has
multiple meanings depending on the LTSSM state in which it is issued. PES48T12G2 never sets this bit in LTSSM
states in which this bit carries the ‘autonomous change’ meaning.

PES48T12G2 User Manual 6 - 9 April 5, 2013

IDT Link Operation

Notes

Notification of link speed changes if provided through the link bandwidth notification mechanism
described in the PCIe specification. This mechanism is enabled by setting the Link Bandwidth Management
Interrupt Enable (LBWINTEN) bit in the PCIELCTL register of switch downstream ports. For downstream
ports, the Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register is set when the link
speed is changed due to the following reasons:

– Link speed downgrade initiated by a PES48T12G2 port when the PHY layer cannot achieve reli-

able operation at the higher speed. Note that this does not include link speed downgrading due to
failure to achieve symbol lock while trying to upgrade link speed via the Recovery state.

– Link speed change initiated by the link partner that was not indicated as an autonomous change.

Also, the LBWSTS bit is set whenever software sets the LRET bit in the PCIELCTL register, even if the
link speed is not changed. Note that the LBWSTS bit is not set during the initial link speed change (i.e., the
speed change from Gen1 to Gen2 after fundamental reset or a full-link-retrain via the ‘Detect’ state). Soft­ware can verify the link speed by reading the Current Link Speed (CLS) field of the port’s Link Status
Register (PCIELSTS).

Link Retraining

Per the PCI Express 2.0 specification, link retraining can be done autonomously in response to link
problems (i.e., repeated TLP replay attempts), or as a result of software setting the link retrain (LRET) bit in
the PCI Express Link Control (PCIELCTL) register.

Writing a one to the Full Link Retrain (FLRET) bit in the Phy Link State 0 (PHYLSTATE0) register of any
port forces that port’s PCIe link to retrain. When this occurs, the LTSSM transitions directly to the Detect
state.

Link retraining does not result in the link going down, unless the LTSSM transitions through the Detect
state in its retraining attempt. The speed of the link is not necessarily changed as a result of link retraining.
A link that operates at 5.0 GT/s will continue to operate at that speed if the link retraining attempt is
successful at that speed. Else, the link speed is changed to 2.5 GT/s.

When link retraining results in the speed of the link being downgraded from 5.0 GT/s to 2.5 GT/s, the
Link Bandwidth Management Status (LBWSTS) bit is set in the PCI Express Link Status (PCIELSTS)
register. Additionally, the PHY LTSSM remains at the downgraded speed until the link partner requests a
link speed upgrade, software sets the LRET bit in the PCIELCTL register, or the link is fully retained via the
FLRET bit in the PHYLSTATE0 register.

In addition to link retrain (via the Recovery state), the link may be fully retrained by writing a one to the
Full Link Retrain (FLRET) bit in a port’s Phy Link State 0 (PHYLSTATE0) register. When this occurs the
LTSSM transitions directly to the Detect state. This causes the data-link to go down (refer to the Link Down
section below).

Note that the LBWSTS bit in the PCIELSTS register is not affected by a full link retrain (i.e., since the
data-link transitioned to the DL_Down state).

Link Down

When an upstream port’s link goes down, it triggers a hot reset, as described in section Switch Funda­mental Reset on page 5-2. In addition:

– All TLPs queued in the port’s ingress frame buffer (IFB) are silently discarded.
– All TLPs queued in the port’s replay buffer (EFB) are silently discarded.

When a downstream port’s link goes down (i.e., the data-link layer transitions to the DL_Down state), the
following occurs:

– All TLPs queued in the port’s ingress frame buffer (IFB) are silently discarded.
– All TLPs queued in the port’s replay buffer (EFB) are silently discarded.
– Request TLPs received by other ports and destined to the logical bus number associated with the

link that is down are treated as Unsupported Requests (UR).

– All other TLPs received by the other ports and destined to the logical bus number associated with

the link that is down are silently discarded.

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IDT Link Operation

Notes

– The port handles all TLPs that target the port’s function(s) normally.

• It is possible to perform configuration read and write operations to port.

When a link comes up, flow control credits for the configured size of the port’s IFB queues are adver­tised. A link down condition on a downstream port’s link may cause the Surprise Down Error Status
(SDOENERR) bit to be set in the port’s AER Uncorrectable Error Status (AERUES) register. The conditions
under which surprise down is reported are described in Section 3.2.1 of the PCI Express 2.0 Specification.

In addition to the exception conditions listed in Section 3.2.1of the PCI Express 2.0 specification, the
SDOENERR bit in a port’s AERUES register is not set in the following cases:

– The port’s link is fully retrained via the FLRET bit in the PHYLSTATE0 register.
– The port’s clocking mode is modified (see section Port Clocking Mode on page 4-1).

Slot Power Limit Support

The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream
switch port or root port to the upstream port of a connected device or switch.

Upstream Port

When a Set_Slot_Power_Limit message is received by an upstream port, then the fields in the message
are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.

– Byte 0 bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale

(CSPLS) field.

– Byte 1 bits 1:0 of the message payload are written to the Captured Slot Power Limit Value

(CSPLV) field.

Downstream Port

A Set_Slot_Power_Limit message is sent by downstream switch ports when either of the following
events occur.

– A configuration write is performed to the corresponding PCIESCAP register when the link associ-

ated with the downstream port is up.

– A link associated with the downstream port transitions from a non-operational state to an opera-

tional (i.e., data-link layer up) state.

Link States

PES48T12G2 ports support the following link states:

– L0

Fully operational link state

– L0s

Automatically entered low power state with shortest exit latency

– L1

Lower power state than L0s

May be automatically entered or directed by software by placing the device in the D3

– L2/L3 Ready

The L2/L3 state is entered after the acknowledgement of a PME_Turn_Off Message.

There is no TLP or DLLP communications over a link in this state.

Note that in this state, the link is considered ‘up’.

– L3

Link is completely unpowered and off

– Link Down

A transitional link down pseudo-state prior to L0. This pseudo-state is associated with the
LTSSM Detect, Polling, Configuration, Disabled, Loopback and Hot-Reset states.

hot

state

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IDT Link Operation

Notes

L0

L0s L1

L2/L3 Ready

L3

Link Down

Fundamental Reset

Hot Reset

Etc.

Figure 6.6 PES48T12G2 ASPM Link Sate Transitions

Active State Power Management

The operation of link Active State Power Management (ASPM) is orthogonal to device power manage­ment. Once ASPM is enabled, ASPM link state transitions are initiated by hardware without software
involvement.

The PES48T12G2 ASPM supports the required receiver L0s state as well as the optional transmitter
L0s and L1 states. ASPM is enabled via the ASPM field in the function’s link control register (PCIELCTL).

L0s ASPM

L0s entry/exit operates independently for each direction of the link. On the receive side, the
PES48T12G2 upstream and downstream ports always respond to L0s entry/exit requests from the link
partner. On the transmit side, the L0s entry conditions must be met for 7us before the hardware transitions
the transmit link to the L0s state.

L0s Entry Conditions

The transmit side L0s entry conditions depend on the port’s operational state. A port configured in
‘Upstream Switch Port’ mode initiates L0s entry when all of the conditions listed below are met:

– L0s ASPM is enabled via the port’s PCIELCTL register.
– The following conditions are met for the amount of time specified in the above field:

A port configured in ‘Downstream Switch Port’ mode initiates L0s entry when all of the conditions listed
below are met:

– L0s ASPM is enabled via the port’s PCIELCTL register.
– The following conditions are met for the amount of time specified in the above field:

• The receive lanes of all of the switch downstream ports which are not in a low power state (i.e.,

D3) and whose link is not down are in the L0s state.

• The port has no TLPs to transmit or there are no available flow control credits to transmit a TLP.

• The port has no DLLPs pending for transmission.

• The receive lanes of the switch’s upstream port are in the L0s state.

• The switch has no TLPs to transmit on the downstream port or there are no available flow control

credits to transmit a TLP.

• There are no DLLPs pending for transmission on the downstream port.

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IDT Link Operation

Notes

L0s Exit Conditions

The transmit side L0s exit conditions depend on the port’s operational state. A port configured in
‘Upstream Switch Port’ mode initiates exit from L0s when any of the conditions listed below are met:

– The port has a TLP or DLLP scheduled for transmission.
– A downstream port in the switch has initiated exit from L0s.

A port configured in ‘Downstream Switch Port’ mode initiates exit from L0s when any of the conditions
listed below are met:

– The port has a TLP or DLLP scheduled for transmission.
– The upstream port in the switch has initiated exit from L0s.

L1 ASPM

L1 entry/exit is initiated by downstream link components (i.e., upstream ports) and affects both direc­tions of the link. Upstream link components (i.e., downstream ports) accept or reject L1 entry requests from
the link partner.

L1 Entry Conditions

The PES48T12G2 downstream ports may accept or reject L1 entry requests sent by the link partner. A
port configured in ‘Downstream Switch Port’ mode accepts L1 entry requests when all of the conditions
listed below are met. Else, the L1 entry request is rejected.

– L1 ASPM is enabled via the port’s PCIELCTL register.
– The port has no TLPs pending for transmission.
– The port has no ACK or NAK DLLPs pending for transmission.

The PES48T12G2 upstream ports request entry into L1 based on the criteria defined below. The L1
entry conditions must be met for 1 ms before the upstream port transitions the link to the L1 state. If these
conditions are met and the link is in the L0 or L0s states, then the hardware will request a transition to the
L1 state from its link partner. If the link partner acknowledges the transition, then the L1 state is entered.

Otherwise, L0s entry is attempted

1

A port configured in ‘Upstream Switch Port’ mode initiates L1 entry

when all of the conditions listed below are met:

– L1 ASPM is enabled via the port’s PCIELCTL register.
– All of the downstream ports which are not in a low power state (i.e., D3) and whose link is not down

are in the L1 state.

– The port has no TLPs pending for transmission.

The port’s replay-buffer is empty.

– The port has no DLLPs pending for transmission.
– The port’s receiver is idle (i.e., no TLPs or DLLPs are received) for the amount of time specified

above.

– The port has accumulated enough flow-control header and data credits to transmit the largest

possible packet of each type (i.e., posted, non-posted, or completion).

L1 Exit Conditions

The L1 exit conditions depend on the port’s operational state. A port configured in ‘Upstream Switch
Port’ mode initiates exit from L1 when any of the conditions listed below are met:

– The port has a TLP scheduled for transmission.
– A downstream port in the switch has initiated exit from L1.

The latency between the downstream port’s initiated exit from L1 and the upstream port’s initi­ated exit from L1 must not exceed 1 µs.

A port configured in ‘Downstream Switch Port’ mode initiates exit from L1 when any of the conditions
listed below are met:

– The port has a TLP scheduled for transmission.
– The upstream port in the switch has initiated exit from L1.

The latency between the upstream port’s initiated exit from L1 and the downstream port’s initi­ated exit from L1 must not exceed 1 µs.

1.

L0s entry is subject to the rules specified in section L0s ASPM on page 6-12.

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IDT Link Operation

Notes

L1 ASPM Entry Rejection Timer

When enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, PES48T12G2
downstream ports respond to link partner requests to enter the L1 ASPM state. In order to enter the L1
ASPM link state, a downstream device (i.e., endpoint) sends continuous PM_Active_State_Request_L1
DLLPs to its link partner (i.e., a downstream switch port). This process continues until the downstream
device receives an acceptance or rejection from its link partner.

A PES48T12G2 downstream port can choose to accept or reject the request, depending on a variety of
conditions (refer to section L1 Entry Conditions on page 6-13). When accepting a request, the
PES48T12G2 downstream port sends continuous PM_Request_Ack DLLPs until the downstream device
receives these and sends an electrical idle ordered set, effectively placing the link in L1 state.

When rejecting a request, the PES48T12G2 downstream port sends a single PM_Active_State_Nak
TLP. The downstream device, upon reception of this TLP, should place its transmitter into the L0s state, and
exit this state prior to sending a new L1 ASPM entry request. Optionally, the downstream device may keep
the link in L0 state, in which case it must wait at least 10 µs before sending a new L1 ASPM entry request.

Some endpoint devices do not meet the required 10 µs gap between consecutive L1 ASPM entry
requests. A live-lock situation can develop in the following scenario:

– The Endpoint sends continuous PM_Active_State_Request_L1 DLLPs to the downstream port of

a switch.

– The switch receives the request but decides to reject (i.e., due to a TLP already queued for trans-

mission on this link). The switch sends a PM_Active_State_Nak TLP to the endpoint device.

– The endpoint device notices the rejection, waits an amount of time (i.e., 8 µs) and resumes trans-

mission of PM_Active_State_Request_L1 DLLPs.

– The switch receives PM_Active_State_Request_L1 DLLPs, but does not recognize them as a

new L1 ASPM entry request, since there was a violation of the 10 µs gap between L1 ASPM entry
requests.

– The switch does not respond with an acceptance or rejection. Therefore, the endpoint keeps

waiting for an acceptance or rejection. A live-lock condition develops.

To avoid this live-lock condition, PES48T12G2 downstream ports allow programmability of a timer that
checks for the 10 µs gap between L1 ASPM entry requests. There is a timer per port. The Minimum Time
between L1 Entry Requests (MTL1ER) field in the L1 ASPM Rejection Timer Control (Px_L1ASPMRTC)
register may be programmed for this purpose.

This timer may be programmed from the nano-second range (i.e., 100 ns) up to the micro-second range
(i.e., 64 µs). By default, the timer is set to 9.5 µs (refer to the Implementation note in Section 5.4.1.2 of the
PCI Express 2.0 spec).

Normally, this timer starts its count after the switch downstream port issues an L1 ASPM rejection (i.e.,
PM_Active_State_Nak TLP), without checking activity on the link. The PES48T12G2 also provides an
option to start the timer after the downstream port issues an L1 ASPM rejection (i.e., PM_Active_State_Nak
TLP) and no activity is detected on the receive-lanes. The Timer Start Control (TSCTL) in the L1ASPMRTC
register controls this behavior. This feature allows the PES48T12G2 downstream ports to enter L1 ASPM
with a variety of endpoints, even those that don’t meet the 10 µs gap between subsequent L1 ASPM entry
requests.

Link Status

Associated with each PES48T12G2 port is a Port Link Up (PxLINKUPN) status output and a Port
Activity (PxACTIVEN) status output. These outputs are provided on an I/O expander. The PxLINKUPN and
PxACTIVEN status outputs may be used to provide a visual indication of system state and activity or for
debug. The PxLINKUPN output is asserted when the port’s data link layer is up (i.e., when the LTSSM is in
the L0, L0s, L1 or recovery states). When the data link layer is down, this output is negated.

The PxACTIVEN output is asserted whenever any TLP, other than a vendor defined message, is trans­mitted or received on the corresponding port’s link. Whenever a PxACTIVEN output is asserted, it remains
asserted for at least 200 ms. Since an I/O expander output may change no more frequently than once every
40 ms, this translates into five I/O expander update periods.

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IDT Link Operation

Notes

De-emphasis Negotiation

The PCI Express 2.0 specification requires that components support the following levels of de­emphasis, depending on the link data rate:

– 2.5 GT/s (Gen1): De-emphasis = -3.5dB
– 5.0 GT/s (Gen2): De-emphasis = -3.5dB or -6.0dB

When operating at 5.0 GT/s, the de-emphasis is selected by programming the Selectable De-emphasis
(SDE) field in the port’s PCI Link Control 2 Register (PCIELCTL2). The chosen de-emphasis for the link is
the result of a negotiation between the two components of the link. Both components must operate with the
same de-emphasis across all lanes of the link.

During normal operation (i.e, not polling.compliance), de-emphasis selection is done during the
Recovery state. The downstream component of the link (i.e., switch upstream port or endpoint) advertises
its desired de-emphasis by transmission of training sets. The upstream component of the link (i.e., switch
downstream port or root-complex port) notes its link partner desired de-emphasis, and makes a decision
about the de-emphasis to be used in the link.

The PES48T12G2’s upstream port physical layer advertises its desired de-emphasis based on the
setting of the port’s SDE field in the PCIELCTL2 register. The upstream port always accepts the link-part­ners decision on the de-emphasis to be used in the link. The PES48T12G2’s downstream ports ignore the
link partner’s desired de-emphasis, and always choose the de-emphasis setting in the SDE field of the
port’s PCIELCTL2 register.

Crosslink

The PES48T12G2 ports support the optional crosslink capability specified in the PCI Express Base
Specification 2.0. Per this specification, a crosslink is established between two downstream ports or two
upstream ports. The PES48T12G2 ports are capable of establishing crosslink with any link partner,
including another PES48T12G2 port.

When crosslink is formed between two ports, the physical layer of one of the ports operates as an
upstream component (e.g., downstream lanes) while the physical layer of the other port operates as a
downstream component (e.g., upstream lanes). The determination of which of the two ports that form the
crosslink operates with upstream or downstream lanes depends on the link training process as specified in
the PCI Express Base Specification.

The Link Mode (LINKMODE) field in the SWPORTxSTS register associated with the PES48T12G2 port
indicates the current link mode (i.e., upstream or downstream lanes) of the port’s physical layer. When two
PES48T12G2 ports are crosslinked to each other, it is recommended that the crosslink connection be done
among ports in different port groups, as shown in Table 6.1. In order for ports in the same port group (e.g.,
port 0 and port 4, port 3 and port 7, etc.) to form a crosslink, software must set the SEED field in the cross­linked port’s Phy PRBS Seed (PHYPRBS) register to different values.

Port Groups

Group 0 Group 1 Group 2 Group 3

0123

4567

8 9 10 11

12 13 14 15

Table 6.1 Crosslink Port Groups

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IDT Link Operation

Notes

Note that when a PES48T12G2 upstream port is crosslinked to a link-partner’s upstream port, neither
port may automatically initiate a link speed change to Gen 2, thereby resulting in a Gen 1 link. It is possible
to overcome this by setting the ILSCC bit in the PES48T12G2 upstream port’s PHYLCFG0 register. By
setting this bit, the PES48T12G2 upstream port will initiate the link transition to Gen 2 speed.

Crosslink is enabled by default. Crosslink may be disabled by setting the Crosslink Disable (CLINKDIS)
bit in the port’s Phy Link Configuration 0 (PHYLCFG0) register.

Hot Reset Operation on a Crosslink

When a PES48T12G2 port forms a crosslink, hot reset operates as follows.

– For a port operating in downstream switch port mode:

• Regardless of the physical layer’s mode of operation (i.e., upstream or downstream lanes), the

physical layer responds to the reception of training sets with the hot reset bit set by transitioning
to the hot reset state as specified in the PCI Express Base Specification. The hot reset does not
reset the configuration registers of the port and does not affect other ports in the partition.

• If the port’s physical layer operates as ‘downstream lanes’ and a higher layer directs the port to
the hot reset state (e.g., partition hot reset, upstream secondary hot reset, downstream
secondary hot reset), the physical layer enters the recovery state and proceeds to the hot reset
state, as specified in the PCI Express Base Specification.

• If the port’s physical layer operates as ‘upstream lanes’, the PES48T12G2 provides no higher
layer mechanism to direct the physical layer to enter the hot reset state. This implies that in a
crosslink formed by a PES48T12G2 downstream port whose physical layer has trained as
‘upstream lanes’, hot reset across the link may only be propagated by the link partner’s port
(which must have trained as a downstream port with downstream lanes).

– For a port operating in upstream switch port mode:

• There is no higher layer mechanism to place the port in hot reset state.

• Regardless of the physical layer’s mode of operation (i.e., upstream or downstream lanes), the

physical layer responds to the reception of training sets with the hot reset bit set by transitioning
to the hot reset state. The hot reset has the effect described in section Hot Resets on page 5-5.

Link Disable Operation on a Crosslink

When a port is crosslinked, link disable operates as follows.

– For a port operating in downstream switch port mode:

• Regardless of the port’s physical layer mode of operation (i.e., downstream lanes or upstream

lanes):

If a higher layer directs the port to disable the link (i.e., the Link Disable (LDIS) bit is set in
the port’s PCIELCTL register), the physical layer enters the recovery state and proceeds
to the disabled state, as specified in the PCI Express Base Specification.

The physical layer responds to the reception of training sets with the disabled bit set by
transitioning to the disabled state as specified in the PCI Express Base Specification.

– For a port operating in upstream switch port mode:

• There is no higher layer mechanism to place the port’s link in the disabled state.

• Regardless of the port’s physical layer mode of operation (i.e., downstream lanes or upstream

lanes), the physical layer responds to the reception of training sets with the disabled bit set by
transitioning to the disabled state as specified in the PCI Express Base Specification.

Gen1 Compatibility Mode

The PES48T12G2 ports may be configured to operate in ‘Gen1 Compatibility Mode’. The intent of this
mode is to overcome interoperability problems that arise when PCI Express 2.0 devices link train with
devices that conform to the PCIe 1.1 or earlier specifications (a.k.a., Gen1 devices). Specifically, this mode
overcomes the problem in which Gen1 devices react incorrectly to newly defined bits in the PCI Express 2.0
specification for the PHY training sets. Such bits include bits 2, 6, and 7 in symbol four of the TS1 and TS2
training sets.

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IDT Link Operation

Notes

A PES48T12G2 port is placed in Gen1 Compatibility Mode by setting the Gen1 Compatibility Mode
Enable (G1CME) bit in the PHYLCFG0 register and fully retraining the link (i.e., via the FLRET bit the
PHYLSTATE0 register).

When a PES48T12G2 port operates in Gen1 Compatibility Mode, the PHY does not set

the following

bits in Table 6.2 in the training sets that it transmits

Training

Set

TS1 4 2 Reserved 5.0 GT/s Data Rate Support

TS2 4 2 Reserved 5.0 GT/s Data Rate Support

Symbol Bit

Table 6.2 Gen1 Compatibility Mode: bits cleared in training sets

PCIe 1.1 and

earlier

Definition

6 Multiple meanings (refer to PCI Express

7 Speed Change

6 Multiple meanings (refer to PCI Express

7 Speed Change

PCI Express 2.0 Definition

2.0 Specification)

2.0 Specification)

A PES48T12G2 port exits Gen1 Compatibility Mode by clearing the G1CME field in the PHYLCFG0
register and fully retraining the link (i.e., via the FLRET bit the PHYLSTATE0 register). When this occurs,
the training set bits listed in Table 6.2 behave per the PCI Express 2.0 definition.

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IDT Link Operation

Notes

PES48T12G2 User Manual 6 - 18 April 5, 2013

Notes

®

Chapter 7

SerDes

Introduction

This chapter describes the controllability of the Serialiazer-Deserializer (SerDes) block associated with
each PES48T12G2 port. A SerDes block is composed of the serializing/deserializing logic for four PCI
Express lanes (i.e., a SerDes “quad”), plus a central block that controls the quad as a whole. This central
block is called CMU, and contains functionality such as a PLL to generate a high-speed clock used by each
lane, initialization of the quad, etc.

In order to improve signal integrity across the high-speed PCI Express links, the PES48T12G2 allows
per-lane programmability of several SerDes settings. These include the following.

– Transmitter drive level
– Transmitter de-emphasis level
– Transmitter slew rate
– Receiver equalization

In addition, the PES48T12G2 supports the optional “low-swing mode” specified by the PCI Express 2.0
specification. This mode is intended for power-sensitive applications.

This chapter describes these controls, their intended use, and the manner in which they are
programmed. Before this is discussed, the topic of SerDes numbering and port association is introduced. To
modify the SerDes driver and receiver settings for a port, the SerDes quad and specific lanes associated
with the port must be identified as described in the next section.

SerDes Numbering and Port Association

The PES48T12G2 contains twelve SerDes quads, numbered zero to 13 (omitting ports 10 and 11 which
do not exist in this device). A SerDes quad is normally associated with its corresponding numbered port
(i.e., SerDes quad 0 is associated with port 0, SerDes quad 1 is associated with Port 1, and so on).

A x4 port is always associated with its corresponding SerDes quad.

A x8 (merged) port is composed of an even numbered port and its odd counterpart. This port is always
associated with the two corresponding SerDes quads (i.e., a merged port 0 is associated with SerDes 0 and
SerDes 1, merged port 2 is associated with SerDes 2 and SerDes 3, etc.).

SerDes Transmitter Controls

The PES48T12G2 allows programmability of SerDes transmitter voltage level, de-emphasis, and slew
(i.e., signal rise and fall times), including support for the PCI Express optional low-swing mode, as well as a
proprietary “amplitude boost” feature to increase the drive strength above its normal operating level (e.g.,
for operation across long traces).

Except for low-swing mode, which is defined by PCI Express as a per-link function, all the other controls
are proprietary and provided on a per-lane basis. This allows a system designer to customize the SerDes
transmitter settings for each lane independently. At the 5.0 GT/s speed (i.e., Gen2) and above, small differ­ences in the channel characteristics among lanes may result in noticeable differences in the quality of the
signal at the receiver and per-lane controllability is an important tool in improving the bit-error rate on the
link.

Driver Voltage Level and Amplitude Boost

The PCI Express 2.0 specification requires that each port support the ‘transmit margining’ feature. This
feature allows the selection of several voltage settings across the link and is intended for compliance testing
and debug.

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IDT SerDes

Notes

In addition to this, the PES48T12G2 offers proprietary fine grain controllability of the SerDes transmitter
voltage level, across a wide range of settings. The PES48T12G2 places no restrictions on the time at which
these settings can be modified (e.g., they can be modified during normal operation of the link or while the
link is being tested).

By default, the SerDes transmit level can be programmed in the range from 950 mV to 120 mV, at steps

of ~40 mV each

1

. In addition, there is an “amplitude-boost” control that monotonically increases the drive
level by ~5% for each of four settings. By default, this control is set to the second level (out of four),
meaning that the range shown above can be increased by up to 10% when the maximum boost setting is
used, or decreased by 5% when the minimum boost setting is used.

Together, the controls for drive-level and amplitude boost allow the system designer to select, on a per­lane basis if desired, the appropriate drive strength for the channel. For power sensitive applications, the
drive level can be reduced with fine granularity to the desired level, without compromising link reliability.

Note that the PCI Express specification requires that, at 5.0 GT/s, receivers accept incoming signals in
the range 1.2 V to 0.120 V. Thus, the transmitter voltage settings may be modified without requiring any
modification of the link partner’s receiver settings. Refer to section Programming of SerDes Controls on
page 7-3 for procedural details on modifying the default SerDes settings and to section SerDes Transmitter
Control Registers on page 7-4 for details on programming the transmitter voltage level and amplitude boost
controls.

De-emphasis

The PCI Express 2.0 specification supports three de-emphasis levels: -3.5 dB (at 2.5 GT/s or 5.0 GT/s
speeds), -6.0 dB (only for 5.0 GT/s), and 0 dB (low-swing mode). The de-emphasis selected for the link is

controlled by the Selectable De-emphasis bit in each port’s PCI Express Link Control 2 register

2

. This field
is set by hardware or firmware (e.g., EEPROM) during boot time and remains unchanged during normal
system operation.

To allow the de-emphasis setting to be modified and customized on the link, the PES48T12G2 contains
proprietary per-lane coarse and fine de-emphasis adjustment controls. Together, these controls allow the
nominal de-emphasis setting (i.e., -3.5 dB or -6.0 dB) to be modified with a granularity of ~0.3 dB per

3

setting

. The desired de-emphasis setting can be achieved across the range of driver level settings
described in the previous section. The PES48T12G2 places no restrictions on the time at which the de­emphasis setting can be modified.

Refer to section SerDes Transmitter Control Registers on page 7-4 for details on programming the

transmitter de-emphasis.

Slew Rate

In addition to transmitter drive level and de-emphasis controls, the PES48T12G2 ports also contain
proprietary fine and coarse slew rate controls. These provide controllability over the rise and fall times of the
transmitted differential signal, and are useful in scenarios where slow rise and fall times negatively affect
the signal eye. The controls for the slew rate are provided on a per-lane basis, and the PES48T12G2
places no restrictions on the time at which they can be modified. Refer to section SerDes Transmitter
Control Registers on page 7-4 for details on programming the slew rate controls.

PCI Express Low-Swing Mode

The PES48T12G2 ports support the optional low-swing transmit voltage mode defined in the PCI
Express 2.0 specification. In this mode, the port’s transmitter voltage level is set to approximately half the
value of the full-swing (default) mode, which results in reduced power consumption in the SerDes. In addi-

1.

Values are based on HSPICE simulation results, assuming typical conditions, as measured at the pin of the

device.

2.

In low-swing mode, de-emphasis is automatically set to 0 dB and the Selectable De-emphasis bit in the port’s

PCI Express Link Control 2 register is ignored.

3.

Note that the PCI Express specification allows a deviation of +/- 0.5 dB from the nominal setting.

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IDT SerDes

Notes

tion, signal de-emphasis is turned off. Low-swing mode is a per-link feature, meaning that all lanes of the
port operate low-swing simultaneously. Refer to section Low-Swing Transmitter Voltage Mode on page 7-13
for details on enabling low-swing mode on a port.

Receiver Equalization

In addition to the transmitter controls described above, the PES48T12G2 SerDes also contains a
receiver equalizer to compensate for effects of channel loss on received signal (i.e., high-speed signal
degradation due to the combined effects of board traces, vias, connectors, and cables in the physical link).
In general, the channel has low-pass filter characteristics, which results in the degradation of high speed
signals. Receiver equalization may be used to compensate for the lossy attenuation effects of the channel
on high-speed signals.

Receiver equalization can be controlled on a per-lane basis. Each SerDes lane contains a receiver
equalization circuit. This circuit is a multi-stage programmable amplifier, where each stage is a peaking
equalizer with a different center frequency and programmable gain. Varying amounts of gain may be
applied depending on the overall frequency response of the channel loss.

For details on programming the receiver equalizer, refer to section Receiver Equalization Controls on
page 7-14. The PES48T12G2 places no restrictions on the time at which the equalizer settings may be
modified (e.g., the settings can be modified during normal operation of the link or while the link is being
tested).

Programming of SerDes Controls

The SerDes controls described above may be programmed by accessing IDT proprietary registers
within the PES48T12G2 switch. The registers may be programmed via any of the mechanisms allowed by
the PES48T12G2 (i.e., via PCI Express configuration accesses from a root, via EEPROM loading at boot­time, or via the PES48T12G2’s SMBus slave interface).

The following sections describe in detail the control registers associated with the SerDes and the
manner in which the SerDes controls are programmed.

Programmable Voltage Margining and De-Emphasis

The PES48T12G2 contains SerDes transmitter voltage controls on a per-port, per-SerDes, and per-lane
basis. There are two mechanisms to control the SerDes transmitter voltage level:

– Via the Transmit Margin (TM) field of the associated port’s Link Control 2 Register (PCIELCTL2).
– Via the SerDes transmitter control registers

• Each SerDes quad has independent transmitter control registers

• The SerDes Lane Transmitter Control Registers (S[x]TXLCTL0 and S[x]TXLCTL1) provide

transmit driver controls per-lane.

• S[0]TXLCTL0 and S[0]TXLCTL1 are associated with SerDes 0, S[1]TXLCTL0 and
S[1]TXLCTL1 are associated with SerDes 1, and so on.

The selection of which of the two mechanism controls the SerDes transmit voltage is based on the
setting of the TM field in the associated port’s PCIELCTL2 register. The port associated with a SerDes quad
is subject to the rules in section SerDes Numbering and Port Association on page 7-1.

1

1.

The S[x]TXLCTL0 and S[x]TXLCTL1 registers are used in conjunction with the SerDes Control (S[x]CTL)
register in order to apply the settings to a particular lane or all lanes of the SerDes. Please refer to the description
of the S[x]CTL register for further details.

PES48T12G2 User Manual 7 - 3 April 5, 2013

IDT SerDes

Notes

When the Transmit Margin (TM) field in the port’s PCIELCTL2 register is set to ‘Normal Operating
Range’, the transmitter voltage level for each SerDes lane of the port is controlled via the S[x]TXLCTL0 and
S[x]TXLCTL1 registers. Otherwise, the TM field controls the SerDes voltage directly for all SerDes lanes of
the port.

– For instance, port 0 is associated with SerDes quad 0.

1

If the TM field in the port’s PCIELCTL2
register is set to ‘Normal Operating Range’, then the S[0]TXLCTL0 and S[0]TXLCTL1 registers
control the operating voltage of the port’s SerDes. If the TM field is set to another value, the
SerDes voltage is set to the value in the port’s PCIELCTL2.TM field.

– Also, if port 4 operates in merged mode, it is associated with SerDes quads 4 and 5. If the TM field

in the port’s PCIELCTL2 register is set to ‘Normal Operating Range’, then the S[4:5]TXLCTL0 and
S[4:5]TXLCTL1 registers control the operating voltage of the port’s SerDes. If the TM field is set
to another value, the SerDes voltage of both SerDes quad 4 and SerDes quad 5 is set to the value
in the PCIELCTL2.TM field of port 4.

De-emphasis levels may also be adjusted on a per-lane basis, using the above mentioned transmitter
control registers. Nominally, de-emphasis levels are set to -3.5 dB, -6.0 dB, or 0 dB (in low-swing mode).
The S[x]TXLCTL0 and S[x]TXLCTL1 registers can be used to modify the nominal values by coarse or fine
steps.

SerDes Transmitter Control Registers

As described above, each SerDes quad is associated with two transmitter control registers
(S[x]TXLCTL0 and S[x]TXLCTL1). Together, these registers allow full programmability of the SerDes trans­mitter voltage levels and de-emphasis. These registers are segmented into fields that allow programma­bility of the transmit driver levels under the following PHY operating modes:

– Full-Swing Mode, in Gen1 data rate, with -3.5 dB de-emphasis
– Full-Swing Mode, in Gen2 data rate, with -3.5 dB de-emphasis
– Full-Swing Mode, in Gen2 data rate, with -6.0 dB de-emphasis
– Low-Swing Mode, in Gen1 data rate (no de-emphasis)
– Low-Swing Mode, in Gen2 data rate (no de-emphasis)

The S[x]TXLCTL0 and S[x]TXLCTL1 registers have default values that select the appropriate transmit
driver settings for each of the above modes. These default values may be modified to adjust the drive
levels.

When the Physical layer of the port associated with the SerDes transitions dynamically across these
operating modes, the appropriate driver settings are applied to the SerDes automatically. For example,
when the PHY operates in Full-swing mode at Gen1 data rate with -3.5 dB de-emphasis, the SerDes
transmit settings are set to the values specified in the S[x]TXLCTL0 and S[x]TXLCTL1 registers corre­sponding to that operating mode. As the PHY changes data rate to Gen2, the SerDes transmit settings are
automatically modified to the values specified in the S[x]TXLCTL0 and S[x]TXLCTL1 registers corre­sponding to the new operating mode (e.g., Full-Swing mode at Gen2 data rate with -3.5 dB de-emphasis).

Table 7.1 shows the register fields that control the SerDes transmit levels for the operation modes listed
above.

1.

SerDes and Port association are subject to the rules outlined in section SerDes Numbering and Port Association

on page 7-1.

PES48T12G2 User Manual 7 - 4 April 5, 2013

IDT SerDes

Notes

PHY Operation Mode

Voltage

Swing

Full-Swing 2.5 GT/s -3.5 dB CDC_FS3DBG1

Full-Swing 5.0 GT/s -3.5 dB CDC_FS3DBG2

Full-Swing 5.0 GT/s -6.0 dB CDC_FS6DBG2

Low-Swing 2.5 GT/s 0 dB N/A TX_SLEW_G1 &

Low-Swing 5.0 GT/s 0 dB N/A TX_SLEW_G2 &

Data
Rate

Table 7.1 SerDes Transmit Level Controls in the S[x]TXLCTL0 and S[x]TXLCTL1 Registers

De-

emphasis

Relevant fields in

S[x]TXLCTL0

Coarse De-

emphasis
Control &

Transmitter

Equalization

TX_EQ_3DBG1

TX_EQ_3DBG2

TX_EQ_6DBG2

Slew Rate

Control

(Course & Fine)

TX_SLEW_G1 &

TX_FSLEW_G1

TX_SLEW_G2 &

TX_FSLEWG2

TX_FSLEW_G1

TX_FSLEW_G2

Relevant fields in

S[x]TXLCTL1

Drive Level / Fine-De-

emphasis Control

TDVL_FS3DBG1 /

FDC_FS3DBG1

TDVL_FS3DBG2 /

FDC_FS3DBG2

TDVL_FS6DBG2 /

FDC_FS6DBG2

TDVL_LSG1

TDVL_LSG2

As shown in Table 7.1, there are six parameters that may be programmed to adjust the transmitter drive
levels. These are:

– Coarse Slew Rate Control (in the S[x]TXLCTL0 register).
– Transmitter Equalization Control (in the S[x]TXLCTL0 register).
– Fine Slew Rate Control (in the S[x]TXLCTL0 register).
– Coarse De-emphasis Control (in the S[x]TXLCTL0 register).
– Fine De-emphasis Control (in the S[x]TXLCTL1 register).
– Drive Level Control (in the S[x]TXLCTL1 register).

Modification of these settings take an immediate effect on the SerDes. Therefore, the link does not need
to be retrained explicitly (i.e., by setting the link-retrain (LRET) bit in the PCIELCTL) in order for these
settings to take effect. Still, the user must be careful when changing the transmit voltage margin while the
port is in normal operating mode, as this may result in the link instability.

Table 7.2 shows a number of possible settings for the drive, de-emphasis, and slew rate controls in

Gen1 mode

1

. These can be used as guidance when adjusting the SerDes transmit levels. The default
setting is highlighted. Note that in Gen1 mode, de-emphasis is ideally -3.5dB with +/- 0.5dB error (refer to
Section 4.3.3.5 of the PCI Express 2.0 Specification). All settings listed in the table ensure that the de­emphasis is kept within the allowable range.

1.

Table values are based on simulations using the Snowbush SerDes HSPICE model and device package s­parameters. Values are sampled at the device pins. The simulation assumes typical conditions, with VddPEA =
VddPETA = 1.0V, VddPEHA = 2.5V, and TX_AMPBOOST = 0x1. Please refer to the device data sheet for post­silicon device characterization data.

PES48T12G2 User Manual 7 - 5 April 5, 2013

IDT SerDes

Notes

Transmit Levels

Drive
Level

De-

empha-

sis

De-

empha-

sized
Level

Settings of Relevant Fields in the S[x]TXLCTL0 &

S[x]TXLCTL1 registers

TDVL_

FS3DBG1

TX_EQ_

3DBG1

CDC_

FS3DBG1

FDC_

FS3DBG1

TX_SLEW

959 -3.6 636 0x1C 0x2 0x3 0x3 0x2

959 -3.6 636 0x1B 0x2 0x3 0x4 0x2

958 -3.6 636 0x1A 0x2 0x3 0x4 0x2

957 -3.6 635 0x19 0x2 0x3 0x4 0x2

956 -3.6 635 0x18 0x2 0x3 0x4 0x2

949 -3.5 631 0x17 0x2 0x3 0x4 0x2

942 -3.5 628 0x16 0x2 0x3 0x4 0x2

935 -3.5 624 0x15 0x2 0x3 0x4 0x2

928 -3.5 620 0x14 0x2 0x3 0x4 0x2

902 -3.5 602 0x13 0x2 0x3 0x4 0x2

877 -3.5 584 0x12 0x2 0x3 0x4 0x2

851 -3.6 566 0x11 0x2 0x3 0x4 0x2

825 -3.6 547 0x10 0x2 0x3 0x4 0x2

789 -3.5 525 0x0F 0x2 0x3 0x3 0x2

_G1

753 -3.5 503 0x0E 0x2 0x3 0x3 0x2

716 -3.5 481 0x0D 0x2 0x3 0x3 0x2

680 -3.4 459 0x0C 0x2 0x3 0x3 0x2

638 -3.4 431 0x0B 0x2 0x3 0x2 0x2

596 -3.4 403 0x0A 0x2 0x3 0x2 0x2

554 -3.4 374 0x09 0x2 0x3 0x2 0x2

512 -3.4 346 0x08 0x2 0x3 0x2 0x2

465 -3.4 314 0x07 0x2 0x3 0x2 0x2

419 -3.5 281 0x06 0x2 0x3 0x2 0x2

372 -3.5 248 0x05 0x2 0x3 0x2 0x2

325 -3.6 216 0x04 0x2 0x3 0x2 0x2

274 -3.6 182 0x03 0x2 0x3 0x1 0x2

224 -3.6 148 0x02 0x2 0x3 0x1 0x2

173 -3.6 115 0x01 0x2 0x3 0x1 0x2

122 -3.6 81 0x00 0x2 0x3 0x1 0x2

Table 7.2 SerDes Transmit Driver Settings in Gen1 Mode

Table 7.3 shows a number of possible settings for the drive, de-emphasis, and slew rate controls in

1

Gen2 mode with -3.5dB de-emphasis.

PES48T12G2 User Manual 7 - 6 April 5, 2013

The default setting is highlighted.

IDT SerDes

Notes

Transmit Levels

Drive
Level

De-

emphas

is

De-

emphas

ized

Level

Settings of Relevant Fields in the S[x]TXLCTL0 &

S[x]TXLCTL1 registers

TDVL_

FS3DBG2

TX_EQ_

3DBG2

CDC_

FS3DBG2

FDC_

FS3DBG2

TX_SLEW

898 -3.5 603 0x1C 0x1 0x1 0x3 0x0

891 -3.5 596 0x1B 0x1 0x1 0x4 0x0

884 -3.5 589 0x1A 0x1 0x1 0x4 0x0

878 -3.6 581 0x19 0x1 0x1 0x4 0x0

871 -3.6 574 0x18 0x1 0x1 0x4 0x0

854 -3.6 562 0x17 0x1 0x1 0x4 0x0

837 -3.7 549 0x16 0x1 0x1 0x4 0x0

819 -3.7 537 0x15 0x1 0x1 0x4 0x0

802 -3.7 525 0x14 0x1 0x1 0x4 0x0

777 -3.7 509 0x13 0x1 0x1 0x3 0x0

752 -3.7 494 0x12 0x1 0x1 0x3 0x0

727 -3.6 478 0x11 0x1 0x1 0x3 0x0

702 -3.6 463 0x10 0x1 0x1 0x3 0x0

672 -3.6 446 0x0F 0x1 0x1 0x1 0x0

_G2

641 -3.5 428 0x0E 0x1 0x1 0x1 0x0

610 -3.4 411 0x0D 0x1 0x1 0x1 0x0

579 -3.4 393 0x0C 0x1 0x1 0x1 0x0

546 -3.4 370 0x0B 0x1 0x1 0x0 0x0

512 -3.4 346 0x0A 0x1 0x1 0x0 0x0

479 -3.4 323 0x09 0x1 0x1 0x0 0x0

445 -3.4 300 0x08 0x1 0x1 0x0 0x0

406 -3.4 274 0x07 0x1 0x0 0x7 0x0

367 -3.4 248 0x06 0x1 0x0 0x7 0x0

328 -3.4 222 0x05 0x1 0x0 0x7 0x0

289 -3.4 196 0x04 0x1 0x0 0x7 0x0

246 -3.5 166 0x03 0x1 0x0 0x5 0x0

203 -3.5 136 0x02 0x1 0x0 0x5 0x0

160 -3.6 107 0x01 0x1 0x0 0x5 0x0

118 -3.7 77 0x00 0x1 0x0 0x5 0x0

Table 7.3 SerDes Transmit Driver Settings in Gen2 Mode with -3.5dB de-emphasis

1.

Table values are based on simulations using the Snowbush SerDes HSPICE model and device package s­parameters. Values are sampled at the device pins. The simulation assumes typical conditions, with VddPEA =
VddPETA = 1.0V, VddPEHA = 2.5V, and TX_AMPBOOST = 0x1. Please refer to the device data sheet for post­silicon device characterization data.

PES48T12G2 User Manual 7 - 7 April 5, 2013

IDT SerDes

Notes

Table 7.4 shows a number of possible settings for the drive, de-emphasis, and slew rate controls in

Gen2 mode with -6.0dB de-emphasis

1

. The default setting is highlighted. As mentioned above, the PCI
Express 2.0 spec allows an error of up to +/- 0.5dB on the de-emphasis. All settings listed in the table
ensure that the de-emphasis is kept within the allowable range.

Transmit Levels

Drive
Level

De-

empha-

sis

De-

empha-

sized
Level

TDVL_

FS6DBG2

Settings of Relevant Fields in the

S[x]TXLCTL0 & S[x]TXLCTL1 registers

TX_EQ_

6DBG2

CDC_

FS6DBG2

FDC_

FS6DBG2

TX_SLEW

903 -5.8 461 0x1C 0x1 0x3 0x1 0x0

901 -5.8 460 0x1B 0x1 0x3 0x2 0x0

899 -5.8 459 0x1A 0x1 0x3 0x2 0x0

897 -5.8 458 0x19 0x1 0x3 0x2 0x0

895 -5.8 456 0x18 0x1 0x3 0x2 0x0

884 -5.9 447 0x17 0x1 0x3 0x3 0x0

874 -6.0 438 0x16 0x1 0x3 0x3 0x0

864 -6.1 429 0x15 0x1 0x3 0x3 0x0

853 -6.2 420 0x14 0x1 0x3 0x3 0x0

853 -6.2 420 0x13 0x1 0x3 0x2 0x0

853 -6.2 420 0x12 0x1 0x3 0x2 0x0

853 -6.2 420 0x11 0x1 0x3 0x2 0x0

853 -6.2 420 0x10 0x1 0x3 0x2 0x0

800 -6.2 394 0x0F 0x1 0x3 0x1 0x0

_G2

748 -6.2 368 0x0E 0x1 0x3 0x1 0x0

695 -6.2 342 0x0D 0x1 0x3 0x1 0x0

642 -6.2 316 0x0C 0x1 0x3 0x1 0x0

605 -6.1 298 0x0B 0x1 0x1 0x7 0x0

568 -6.1 280 0x0A 0x1 0x1 0x7 0x0

530 -6.1 262 0x09 0x1 0x1 0x7 0x0

493 -6.1 244 0x08 0x1 0x1 0x7 0x0

450 -6.1 224 0x07 0x1 0x1 0x5 0x0

407 -6.0 203 0x06 0x1 0x1 0x5 0x0

363 -5.9 183 0x05 0x1 0x1 0x5 0x0

320 -5.9 162 0x04 0x1 0x1 0x5 0x0

Table 7.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis (Part 1 of 2)

1.

Table values are based on simulations using the Snowbush SerDes HSPICE model and device package s­parameters. Values are sampled at the device pins. The simulation assumes typical conditions, with VddPEA =
VddPETA = 1.0V, VddPEHA = 2.5V, and TX_AMPBOOST = 0x1. Please refer to the device data sheet for post­silicon device characterization data.

PES48T12G2 User Manual 7 - 8 April 5, 2013

IDT SerDes

Notes

Transmit Levels

Drive
Level

272 -6.0 138 0x03 0x1 0x1 0x3 0x0

225 -6.1 113 0x02 0x1 0x1 0x3 0x0

177 -6.2 88 0x01 0x1 0x1 0x3 0x0

130 -6.3 63 0x00 0x1 0x1 0x3 0x0

Table 7.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis (Part 2 of 2)

De-

empha-

sis

De-

empha-

sized
Level

TDVL_

FS6DBG2

Settings of Relevant Fields in the

S[x]TXLCTL0 & S[x]TXLCTL1 registers

TX_EQ_

6DBG2

CDC_

FS6DBG2

FDC_

FS6DBG2

TX_SLEW

_G2

When the PHY operates in low-swing mode, de-emphasis is automatically turned off. Therefore, the fine
and coarse de-emphasis controls in the S[x]TXLCTL0 and S[x]TXLCTL1 registers have no effect. In this
mode, the TDVL_LSG1 and TDVL_LSG2 fields in the S[x]TXLCTL1 register control the transmitter voltage
swing for Gen1 and Gen2 modes respectively. Please refer to section Low-Swing Transmitter Voltage Mode
on page 7-13 for further details.

In addition to the SerDes settings described above, the user may apply an amplitude boost to the drive
swing by setting the TX_AMPBOOST field in the S[x]TXLCTL0 register. Amplitude boost may be applied on
a per-lane basis. Amplitude boost may be applied to increase the drive swings above the values shown in
Tables 7.2, 7.3, and 7.4. Refer to the description of the TX_AMPBOOST field for further details.

Programmable De-emphasis Adjustment

The tables shown in the previous section list different settings to control the SerDes drive swing while
keeping the de-emphasis within the allowable range, depending on the PHY operating mode (e.g., Gen1
data rate, Gen2 data rate and -3.5 dB de-emphasis, or Gen2 data rate with -6.0 dB de-emphasis).

It is possible to modify the de-emphasis in fine or coarse increments on a per-lane basis, using the
appropriate fields in the S[x]TXLCTL0 and S[x]TXLCTL1 registers. Table 7.1 shows the register fields that
control fine and coarse de-emphasis for each PHY operating mode.

When using the de-emphasis controls, it is important to understand that the actual deemphasis applied
on the link is a function of the de-emphasis controls, the transmitter equalization control, the transmit drive
swing controls, and the data rate of the SerDes.

The coarse de-emphasis controls should generally be set as shown in Tables 7.2, 7.3, and 7.4. Note that
there are separate coarse de-emphasis and transmit equalization controls per PHY operating mode. The
settings shown in the above tables ensure that the de-emphasis falls within the nominal range mandated by
the PCI Express Specification. The coarse de-emphasis settings shown in the above tables ensure that the
de-emphasis falls within the nominal range mandated by the PCI Express specification 2.0. As shown in the
tables, the coarse de-emphasis setting is dependent on the transmit drive swing setting. Therefore, modi­fying the transmit drive swing must be done in conjunction with modifying the coarse de-emphasis setting.

The fine de-emphasis registers allow modification of the de-emphasis in fine steps. There is a fine de­emphasis control per PHY operating mode.

When the PHY operates in Gen1 data rate with -3.5 dB de-emphasis, the fine de-emphasis control
(FDC_FS3DBG1 field in the S[x]TXLCTL1 register) has the effect shown in Figure 7.1. In the figure,
TXLEV[4:0] refers to the TDVL_FS3DBG1 field in the S[x]TXLCTL1 register.

When the PHY operates in Gen2 data rate with -3.5 dB de-emphasis, the fine de-emphasis control
(FDC_FS3DBG2 field in the S[x]TXLCTL1 register) has the effect shown in Figure 7.2. In the figure,
TXLEV[4:0] refers to the TDVL_FS3DBG2 field in the S[x]TXLCTL1 register.

PES48T12G2 User Manual 7 - 9 April 5, 2013

IDT SerDes

Notes

When the PHY operates in Gen2 data rate with -6.0 dB de-emphasis, the fine de-emphasis control
(FDC_FS6DBG2 field in the S[x]TXLCTL1 register) has the effect shown in Figure 7.3. In the figure,
TXLEV[4:0] refers to the TDVL_FS6DBG2 field in the S[x]TXLCTL1 register.

As shown in these figures, the de-emphasis applied on the line varies depending on the setting of the
transmit drive level field. Thus, when modifying the transmit drive level of the SerDes, the fine de-emphasis
control must be adjusted appropriately to ensure that the de-emphasis on the line falls within the range
mandated by the PCI Express specification.

Note: It is possible to turn off the de-emphasis (i.e., 0 db de-emphasis) by setting the coarse de­emphasis setting to a value of 0x3 and the fine de-emphasis setting to a value of 0x7.

Figure 7.1 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit Drive Level

Controls, when the PHY Operates in Gen1 Data Rate with -3.5 dB Nominal de-emphasis

Figure 7.2 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit Drive Level

Controls, when the PHY Operates in Gen2 Data Rate with -3.5 dB Nominal de-emphasis

PES48T12G2 User Manual 7 - 10 April 5, 2013

IDT SerDes

Notes

Figure 7.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit Drive Level

Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB Nominal de-emphasis

Finally, note that it is possible to turn off de-emphasis (i.e., 0 dB de-emphasis) for a given PHY operating
mode by setting the corresponding transmitter equalization control to 0x0, the coarse de-emphasis control
to a value of 0x3, and the fine de-emphasis control to a value of 0x7.

Programmable Slew Adjustment

The transmitter’s slew rate is controlled by fields in the S[x]TXLCTL0 register. It is possible to select
different settings for Gen1 operation and Gen2 operation. The S[x]TXLCTL0 register contains the following
slew rate controls:

At Gen1 data rate:

TX_SLEW_G1: transmit driver coarse slew control

TX_FSLEW_G1: transmit driver fine slew control

At Gen2 data rate:

TX_SLEW_G2: transmit driver coarse slew control

TX_FSLEW_G2: transmit driver fine slew control

Table 7.5 shows the slew rate settings. The values shown apply to both Gen1 and Gen2 data rates.

Rise/Fall Times

TX_SLEW TX_FSLEW

35 326

4266

2141

089

(20% to 80%)

in Picoseconds

Table 7.5 Transmitter Slew Rate Settings (Part 1 of 2)

PES48T12G2 User Manual 7 - 11 April 5, 2013

IDT SerDes

Notes

25 337

4269

2120

060

1 5 340

4272

2123

050

0 5 342

4273

2127

048

Table 7.5 Transmitter Slew Rate Settings (Part 2 of 2)

Transmit Margining using the PCI Express Link Control 2 Register

When the Transmit Margin (TM) field in the port’s PCIELCTL2 register is set to a value other than
‘Normal Operating Range’, the transmitter voltage levels are controlled by hardware based on the setting of
the TM field, and not by the S[x]TXLCTL0 and S[x]TXLCTL1 registers. Per the PCI Express 2.0 specifica­tion, transmit margining may be done in full-swing mode or in low-swing mode. Table 7.6 shows the transmit

margining settings supported by the switch.

1

Full Swing

Mode

(mV)

900 500

700 400

500 300

300 200

200 100

Table 7.6 PCI Express Transmit Margining Levels supported by the PES48T12G2

Low Swing

Mode

(mV)

Note that in compliance mode (i.e., when the associated port’s PHY LTSSM is in the Polling.Compliance
state), the SerDes transmit level is controlled by the TM field in the associated port’s PCIELCTL2 register,
and the de-emphasis setting is controlled by the LTSSM based on the rules described in Section 4.2.6.2.2
of the PCI Express 2.0 specification.

– When the LTSSM enters the Polling.Compliance state in full-swing mode, the values for full-swing

margining are applied.

– When the LTSSM enters the Polling.Compliance state in low-swing mode, the values for low-

swing margining are applied.

1.

The TX_AMPBOOST field in the S[x]TXLCTL0 register does have an effect during transmit margining.

PES48T12G2 User Manual 7 - 12 April 5, 2013

IDT SerDes

Notes

Finally, when the TM field is modified, the newly selected value is not applied until the PHY LTSSM tran­sitions through the states in which it is allowed to modify the transmit margin setting on the line (e.g.,
Recovery.RcvrLock). Therefore, after modifying this field, it is recommended that the link be retrained by
setting the LRET bit in the port’s PCIELCTL register.

Low-Swing Transmitter Voltage Mode

The PES48T12G2 ports support the optional low-swing transmit voltage mode defined in the PCI
Express 2.0 specification. In this mode, the transmitter’s voltage level is set to approximately half the value
of the full-swing (default) mode, which reduces power consumption in the SerDes. This mode is enabled by
setting the Low-Swing Enable (LSE) bit in the SerDes Configuration register.

– For a merged port, the LSE bit must be set in the SerDes Configuration register of both of the

SerDes associated with the port.

When Low-Swing mode is enabled, the transmitter drive level is reduced and de-emphasis is automati­cally turned off. Therefore, the Selectable De-emphasis (SDE) and Compliance De-emphasis (CDE) fields
in the PCIELCTL2 register have no effect. Additionally, the Current De-emphasis (CDE) field in the
PCIELSTS2 register becomes invalid.

The low-swing mode transmitter voltage swing may be adjusted via the TDVL_LSG1 (when operating in
Gen1 mode) and TDVL_LSG2 (when operating in Gen2 mode) fields in the S[x]TXLCTL1 register. Table 7.7
shows the transmitter’s drive swing for different values of TDVL_LSG1, when the port operates in low swing

mode at Gen1 speed
when the port operates in low swing mode at Gen2 speed. The default setting is highlighted.

1

. Table 7.8 shows the transmitter’s drive swing for different values of TDVL_LSG2,

Drive Level TDVL_LSG1

820 0x0F

785 0x0E

750 0x0D

714 0x0C

673 0x0B

632 0x0A

590 0x09

549 0x08

499 0x07

449 0x06

399 0x05

350 0x04

296 0x03

242 0x02

188 0x01

134 0x00

Table 7.7 SerDes Transmit Drive Swing in Low Swing Mode at Gen1 Speed

1.

Table values are based on simulations using the Snowbush SerDes HSPICE model and device package s­parameters. The simulation assumes typical conditions, with VddPEA = VddPETA = 1.0V, VddPEHA = 2.5V, and
TX_AMPBOOST = 0x2. Please refer to the device data sheet for post-silicon device characterization data.

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IDT SerDes

Notes

Drive Level TDVL_LSG2

764 0x0F

737 0x0E

709 0x0D

682 0x0C

649 0x0B

616 0x0A

583 0x09

550 0x08

506 0x07

462 0x06

418 0x05

374 0x04

320 0x03

266 0x02

212 0x01

158 0x00

Table 7.8 SerDes Transmit Drive Swing in Low Swing Mode at Gen2 Speed

When the PHY enters the Polling.Compliance state and low-swing mode is enabled, the following

occurs:

– The transmit drive level is selected by the Transmit Margin (TM) field in the PCIELCTL2 register.

This field has specific transmit margin levels for full-swing and low-swing mode. The values corre­sponding to low-swing mode are applied.

– De-emphasis is turned off.

Receiver Equalization Controls

The switch contains SerDes receiver equalization controls on a per-lane basis. The receiver equaliza­tion circuit has two controls which may be programmed via the SerDes Receiver Equalization Lane Control
(S[x]RXEQLCTL) register. These are:

– Receiver Equalization Zero (RXEQZ): Increases the high-frequency gain of the equalizer.
– Receiver Equalization Boost (RXEQB): Reduces the low-frequency gain of the equalizer.

Together, RXEQZ and RXEQB provide wide programmability and fine grain control over the equalizer’s
boost. Refer to the definition of the S[x]RXEQLCTL register for further details on programming these
controls.

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IDT SerDes

Notes

SerDes Power Management

In order to maximize power savings in the SerDes, the PES48T122G2 adheres to the following guide­lines. For SerDes quads that are used, their power state depends on the state of the port(s) associated with
the SerDes, as described below.

1. When a port is disabled:
– For a x4 or x8 port, the SerDes quad(s) associated with the port are placed in a deep low power

state.

• There is one SerDes quad associated with a x4 port.

• There are two SerDes quads associated with a x8 port.

– For a x1 or x2 port, the SerDes lanes associated with the port are placed in a deep low power

state.

• If all lanes of a SerDes quad are associated with disabled ports, the entire SerDes quad is
placed in a deep low power state.

2. When a port is not disabled:

– The SerDes quad(s) associated with the port are turned-on.
– Unused lanes are powered down.

• Lanes that form the initial link width (i.e., lanes on which the PHY LTSSM detected the presence

of a link partner in the Detect state) are considered used. All other lanes associated with the port
are unused.

– Used lanes are active and fully powered.
– Dynamic link width downconfigure (i.e., change of link width while the link is up) is handled per the

rules in the PCI Express 2.0 specification. In this case, inactive lanes place their transmitter in
electrical idle and enable receiver termination

It is possible to explicitly power-down a SerDes quad by setting the POWERDN bit in the corresponding
SerDes Control (S[x]CTL) register. Refer to the definition of this field for further details. Powering-down a
SerDes shared by multiple ports results in all such ports being affected.

1

2

.

1.

Note that unused lanes may become used when the PHY LTSSM transitions to the Detect state and retrains the

link.

2.

In the PES48T12G2, these lanes are placed in the P1 power state.

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IDT SerDes

Notes

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Notes

®

Chapter 8

Theory of Operation

Introduction

This chapter describes the PES48T12G2-specific architectural behavior of the PCI Express switch.

Transaction Routing

The switch supports routing of all transaction types defined in PCI Express Base Specification Revision

2.0. This includes routing of specification defined transactions as well as those that may be used in vendor
defined messages and in future revisions of the PCI Express specification. Specifically, the PES48T12G2
supports the following type of routing:

– Address routing with 32-bit or 64-bit format
– ID based routing using bus, device and function numbers.
– Implicit routing utilizing

• Route to root

• Broadcast from root

• Local - terminate at receiver

• Gathered and routed to root

A summary of TLP types that use the above routing methods is provided in Table 8.1.

Routing Method TLP Type Using Routing Method

Route by Address MRd, MrdLk, MWr, IORd, IOWr, Msg, MsgD

ID Based Routing CfgRd0, CfgWr0, CfgRd1, CfgWr1, TCfgRd, TCfgWr, Cpl,

CpdD, CplLk, CplDLk, Msg, MsgD

Imlicit Routing - Route to Root Msg, MsgD

Implicit Routing - Broadcast from Root Msg, MsgD

Implicit Routing - Local Msg, MsgD

Implicit Routing - Gathered and Routed to

1

Root

1.

The only Gathered and Routed to Root message supported is a PME_TO_Ack message received on a downstream

port.

Only supported for PME_TO_Ack messages in response to a
root initiated PME_Turn_Off message.

Table 8.1 Switch Routing Methods

Interrupts

When an unmasked interrupt condition occurs, an MSI or interrupt message is generated by the corre­sponding port as described in Table 8.2. The removal of the interrupt condition occurs when unmasked
status bit(s) causing the interrupt are masked or cleared. The PES48T12G2 assumes that all generated
MSIs target the root and routes these transactions to the upstream port. Configuring the address contained
in a downstream port’s MSIADDR and MSIADDRU registers to an address that does not route to the
upstream port and generating an MSI produces undefined results.

It follows that MSIs generated by the switch’s ports can’t fall within the multicast BAR aperture in the
partition. When this occurs, the behavior is undefined.

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IDT Theory of Operation

Notes

Unmasked

Interrupt

Asserted 1 X MSI message generated

Negated 1 X None

EN bit in

MSICAP

Register

0 0 Assert_INTA message request generated to switch

0 1 None

0 0 Deassert_INTA message request generated to

0 1 None

INTXD bit

in PCICMD

Register

core

switch core

Table 8.2 Downstream Port Interrupts

Action

Downstream Port Interrupts

Downstream ports support generation of legacy interrupts and MSIs. The following are sources of down­stream port interrupts and MSIs.

– Downstream port’s hot-plug controller
– Link bandwidth notification capability (i.e., assertion of the LBWSTS or LABWSTS bits in the

PCIELSTS register when interrupt notification is enabled for these bits)

When a port is configured to generate INTx messages, only INTA is used.

Legacy Interrupt Emulation

PES48T12G2 supports legacy PCI INTx emulation. Rather than use sideband INTx signals, PCIe
defines two messages that indicate the assertion and negation of an interrupt signal. An Assert_INTx
message is used to signal the assertion of an interrupt signal and an Deassert_INTx message is used to
signal its negation.

The PES48T12G2 maintains an aggregated INTx state for each of the four interrupt signals (i.e., A
through D) at each port. An Assert_INTx message is sent to the root by the upstream port when the aggre­gated state of the corresponding interrupt in the upstream port transitions from a negated to an asserted
state. A Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the
corresponding interrupt in the upstream port transitions from an asserted to a negated state.

PCI to PCI bridges must map interrupts on the secondary side of the bridge according to the device
number of the device on the secondary side of the bridge. No mapping is performed for the PCI to PCI
bridges corresponding to downstream ports as these ports only connect to device zero. A mapping is
performed for the upstream port. This mapping is summarized in Table 8.3.

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