Page 1
®
IDT™ 89HPES34H16
PCI Express® Switch
User Manual
October 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284- 2775
©2008 Integrated Device Technology, Inc.
Printed in U.S.A.
Page 2
Integrated Device Technology, Inc. reserves t he right to make changes to its produc ts or specifications at any time, without notice, in order to improve design or perf or mance
and to supply th e best possible product. IDT does not assume any responsibility for use of any circui try described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use . N o license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
GENERAL DISCLAIMER
Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
at your own risk. IDT MA KES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY
OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITA T ION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REP RESENTA TI ONS OR W ARRANTI ES AS T O THE TRUT H, ACCURACY OR COMPLETENES S
OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR
THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR
SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code
examples also ma y b e s ubj ec t t o Uni te d S ta tes ex po rt c on trol l aw s an d m ay b e s ubj ect t o the e xpo r t or im por t la ws of ot her co un tries and it i s your re sponsi bilit y to comply with
any applicable l aws or regulations .
Integrated Device Technology's products are not authorized for use as cr itical components in life support devi ces or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intend ed for su rgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly us ed in accordance with instructions for use provid ed in the labeling, can be reasonably expected to res ult in a significant injury to the user.
2. A critical co mpo nent is an y com pon en ts of a lif e sup por t dev ice or system whose fai lu re t o perform can be re aso na bl y exp ect ed to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trade m arks or registered trademarks of Integrated Device Technology , Inc.
CODE DISCLAIMER
LIFE SUPPORT POLICY
Page 3
Notes
®
About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES34H16, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical characteristics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES34H16 Device Overview,” provides a complete introduction to the performance capabilities of the 89HPES34H16. Included in this chapter is a summary of features for the device as well as a
system block diagram and pin description.
Chapter 2, “Upstream Port Failover,” describes upstream port failover mechanism in the PES34H16
that enables the construction of fault tolerant systems.
Chapter 3, “Clocking, Reset, and Initialization,” provides a description of the two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 4, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 5, “General Purpose I/O,” describes how the 32 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 6, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES34H16.
Chapter 7, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-PCI bridge in the PES34H16.
Chapter 8, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in
the PES34H16.
Chapter 9, “Configuration Registers,” discusses the base addresses, PCI configuration space, and
registers associated with the PES34H16.
Chapter 10, “JT AG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. T he term negate or negation
is used to indicate that a signal is inactive or false.
To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N ’ s hould be i nterpreted as being active, or asserted, when at a logic z ero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
PES34H16 User Manual 1 October 30, 2008
Page 4
IDT
Notes
1 2 3 4
high-to-low
transition
low-to-high
transition
single clock cycle
To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
Data Units
The following data unit terminology is used in this document.
Term Words Bytes Bits
Byte 1/2 1 8
Word 1 2 16
Doubleword (Dword) 2 4 32
Quadword (Qword) 4 8 64
Table 1 Data Unit Terminology
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In doublewords, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the leas t significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
PES34H16 User Manual 2 October 30, 2008
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
Page 5
IDT
Notes
0 1 2 3
bit 0bit 31
Address of Bytes within Words: Big Endian
3 2 1 0
bit 0bit 31
Address of Bytes within Words: Little Endian
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications made by PCIe root configuration writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initialization. See Table 2.
Type Abbreviation Description
Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hardware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit positions and then written back.
Read Only RO Software can only read registers/bits with this attribute. Contents
are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.
Read and Write RW Software can both read and write bits with this attribute.
Table 2 Register Terminology (Sheet 1 of 2)
PES34H16 User Manual 3 October 30, 2008
Page 6
IDT
Notes
Type Abbreviation Description
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.
However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.
Read and Write when
Unlocked
Write Transient WT The zero is always read from a bit/field of this type. Writing of a
Zero Zero A zero register or bit must be written with a value of zero and
RWL Software can read the register/bits with this attribute. Writing to
register/bits with this attribute will only cause the value to be modified if the REGUNLOCK bit in the SWCTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the register/bits are effectively read-only
one is used to quality the writing of other bits/fields in the same
register.
returns a value of zero when read.
Table 2 Register Terminology (Sheet 2 of 2)
Use of Hypertext
In Chapter 9, Tables 9.2 and 9.3 contain register nam es and page numbers highlighted in blue under the
Register Definition column. In pdf files, users can jump from this source table directly to the registers by
clicking on the register name in the source table. Each register name in the table is linked directly to the
appropriate register in the register section of the chapter. To return to the source table after having jumped
to the register section, click on the same register name (in blue) in the register section.
Reference Documents
PCI Express Base Specification, Revision 1.1, PCI Special Interest Group.
PCI Power Management Interface Specification, Revision 1.1, PCI Special Interest Group.
PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group.
SMBus Specification, Revision 2.0.
Revision History
October 17, 2007: Initial Publication.
December 14, 2007: In Chapter 1, added second virtual channel capability and changed Device ID to
0x8034.
December 26, 2007: Changed device number from 34T16 to 34H16.
April 15, 2008: In Chapter 9, changed 0x0 definition for bit EEPE in SWPERCTL register from “time-out”
to “end-to-end parity error”.
October 30, 2008: Updated the following Description fields: LDIS in the PCIELCTL register, INTXD in
PCICMD register, changed RO to RW for bits 10:9 in the HPCFGCTL register, SDOENERR in the AERUES
register, DLLLA in both the PCIESTS and PCIELCAP registers, and added note in Description field for
SWMODE field.
PES34H16 User Manual 4 October 30, 2008
Page 7
Notes
Table of Contents
®
About This Manual
Introduction ....................................................................................................................................1
Content Summary ..........................................................................................................................1
Signal Nomenclature .....................................................................................................................1
Numeric Representations ..............................................................................................................2
Data Units ......................................................................................................................................2
Register Terminology .....................................................................................................................3
Use of Hypertext ............................................................................................................................4
Reference Documents ...................................................................................................................4
Revision History .............................................................................................................................4
PES34H16 Device Overview
Introduction.....................................................................................................................................1-1
List of Features...............................................................................................................................1-1
Logic Diagram.................................................................................................................................1-3
System Identification.......................................................................................................................1-4
Vendor ID................................................................................................................................1-4
Device ID................................................................................................................................1-4
Revision ID.............................................................................................................................1-4
JTAG ID..................................................................................................................................1-4
SSID/SSVID............................................................................................................................1-4
Device Serial Number Enhanced Capability...........................................................................1-4
Pin Description................................................................................................................................1-5
Pin Characteristics........................................................................................................................1-12
Port Configuration.........................................................................................................................1-15
Disabled Ports......................................................................................................................1-16
Upstream Port Failover
Introduction.....................................................................................................................................2-1
Failover...........................................................................................................................................2-2
Static Upstream Port Failover.................................................................................................2-3
Dynamic Upstream Port Failover............................................................................................2-3
Clocking, Reset, and Initialization
Introduction.....................................................................................................................................3-1
Initialization.....................................................................................................................................3-3
Reset...............................................................................................................................................3-4
Fundamental Reset................................................................................................................3-5
Hot Reset................................................................................................................................3-6
Upstream Secondary Bus Reset............................................................................................3-7
Downstream Secondary Bus Reset........................................................................................3-8
Downstream Port Reset Outputs....................................................................................................3-8
Power Enable Controlled Reset Output..................................................................................3-9
Power Good Controlled Reset Output....................................................................................3-9
PES34H16 User Manual i October 30, 2008
Page 8
IDT Table of Contents
Notes
Link Operation
Introduction.....................................................................................................................................4-1
Polarity Inversion............................................................................................................................4-1
Link Width Negotiation....................................................................................................................4-1
Lane Reversal.................................................................................................................................4-1
Link Retraining................................................................................................................................4-4
Link Down.......................................................................................................................................4-5
Slot Power Limit Support................................................................................................................4-5
Upstream Port ........................................................................................................................4-5
Downstream Port....................................................................................................................4-5
Link States......................................................................................................................................4-5
Active State Power Management ...................................................................................................4-6
Link Status......................................................................................................................................4-6
General Purpose I/O
Introduction.....................................................................................................................................5-1
GPIO Configuration ........................................................................................................................5-2
GPIO Pin Configured as an Input...........................................................................................5-2
GPIO Pin Configured as an Output........................................................................................5-2
GPIO Pin Configured as an Alternate Function......................................................................5-2
SMBus Interfaces
Introduction.....................................................................................................................................6-1
Master SMBus Interface.................................................................................................................6-2
Initialization.............................................................................................................................6-2
Serial EEPROM......................................................................................................................6-2
I/O Expanders.........................................................................................................................6-6
Slave SMBus Interface.................................................................................................................6-17
Initialization...........................................................................................................................6-17
SMBus Transactions ............................................................................................................6-18
Power Management
Introduction.....................................................................................................................................7-1
PME Messages...............................................................................................................................7-2
Power Express Power Management Fence Protocol.....................................................................7-2
Power Budgeting Capability ...................................................................................................7-3
Hot-Plug and Hot-Swap
Introduction.....................................................................................................................................8-1
Hot-Plug I/O Expander ...........................................................................................................8-4
Hot-Plug Interrupts and Wake-up...........................................................................................8-4
Legacy System Hot-Plug Support ..........................................................................................8-4
Hot-Swap........................................................................................................................................8-6
Configuration Registers
Configuration Space Organization..................................................................................................9-1
Upstream Port (Port 0) ...........................................................................................................9-3
Downstream Ports (Ports 1 through 15).................................................................................9-8
Register Definitions.......................................................................................................................9-11
Type 1 Configuration Header Registers...............................................................................9-11
PCI Express Capability Structure.........................................................................................9-22
PES34H16 User Manual ii October 30, 2008
Page 9
IDT Table of Contents
Notes
Power Management Capability Structure.............................................................................9-35
Message Signaled Interrupt Capability Structure.................................................................9-36
Subsystem ID and Subsystem Vendor ID............................................................................9-38
Extended Configuration Space Access Registers................................................................9-38
Advanced Error Reporting (AER) Enhanced Capability.......................................................9-39
Device Serial Number Enhanced Capability.........................................................................9-45
PCI Express Virtual Channel Capability...............................................................................9-46
Power Budgeting Enhanced Capability................................................................................9-57
Switch Control and Status Registers....................................................................................9-59
Internal Switch Error Control and Status Registers..............................................................9-76
JTAG Boundary Scan
Introduction...................................................................................................................................10-1
Test Access Point.........................................................................................................................10-1
Signal Definitions..........................................................................................................................10-1
Boundary Scan Chain...................................................................................................................10-3
Test Data Register (DR)...............................................................................................................10-5
Boundary Scan Registers.....................................................................................................10-5
Instruction Register (IR)................................................................................................................10-7
EXTEST................................................................................................................................10-8
SAMPLE/PRELOAD.............................................................................................................10-8
BYPASS...............................................................................................................................10-8
CLAMP.................................................................................................................................10-9
IDCODE................................................................................................................................10-9
VALIDATE............................................................................................................................10-9
RESERVED..........................................................................................................................10-9
Usage Considerations........................................................................................................10-10
PES34H16 User Manual iii October 30, 2008
Page 10
IDT Table of Contents
Notes
PES34H16 User Manual iv October 30, 2008
Page 11
Notes
List of Tables
®
Table 1.1 PES34H16 Device IDs.........................................................................................................1-4
Table 1.2 PES34H16 Revision ID........................................................................................................1-4
Table 1.3 PCI Express Interface Pins..................................................................................................1-5
Table 1.4 SMBus Interface Pins..........................................................................................................1-7
Table 1.5 General Purpose I/O Pins....................................................................................................1-7
Table 1.6 System Pins.......................................................................................................................1-10
Table 1.7 Test Pins............................................................................................................................1-11
Table 1.8 Power and Ground Pins.....................................................................................................1-12
Table 1.9 Pin Characteristics.............................................................................................................1-12
Table 3.1 Reference Clock Mode Encoding........................................................................................3-1
Table 3.2 Boot Configuration Vector Signals.......................................................................................3-3
Table 5.1 General Purpose I/O Pin Alternate Function.......................................................................5-1
Table 5.2 GPIO Pin Configuration.......................................................................................................5-2
Table 6.1 Serial EEPROM SMBus Address........................................................................................6-2
Table 6.2 PES34H16 Compatible Serial EEPROMs...........................................................................6-3
Table 6.3 I/O Expander 0 Signals......................................................................................................6-10
Table 6.4 I/O Expander 1 Signals......................................................................................................6-11
Table 6.5 I/O Expander 2 Signals......................................................................................................6-11
Table 6.6 I/O Expander 3 Signals......................................................................................................6-12
Table 6.7 I/O Expander 4 Signals......................................................................................................6-13
Table 6.8 I/O Expander 5 Signals......................................................................................................6-13
Table 6.9 I/O Expander 6 Signals......................................................................................................6-14
Table 6.10 I/O Expander 7 Signals......................................................................................................6-15
Table 6.11 I/O Expander 8 Signals......................................................................................................6-15
Table 6.12 I/O Expander 9 Signals......................................................................................................6-16
Table 6.13 I/O Expander 10 Signals....................................................................................................6-17
Table 6.14 Slave SMBus Address When a Static Address is Selected...............................................6-17
Table 6.15 Slave SMBus Command Code Fields...............................................................................6-18
Table 6.16 CSR Register Read or Write Operation Byte Sequence...................................................6-19
Table 6.17 CSR Register Read or Write CMD Field Description.........................................................6-20
Table 6.18 Serial EEPROM Read or Write Operation Byte Sequence................................................6-21
Table 6.19 Serial EEPROM Read or Write CMD Field Description.....................................................6-21
Table 7.1 PES34H16 Power Management State Transition Diagram.................................................7-2
Table 8.1 Downstream Port Hot-Plug Signals.....................................................................................8-3
Table 9.1 Base Addresses for Port Configuration Space Registers....................................................9-1
Table 9.2 Upstream Port 0 Configuration Space Registers.................................................................9-3
Table 9.3 Downstream Ports 1 through 15 Configuration Space Registers........................................9-8
Table 10.1 JTAG Pin Descriptions.......................................................................................................10-2
Table 10.2 Boundary Scan Chain........................................................................................................10-3
Table 10.3 Instructions Supported by PES34H16’s JTAG Boundary Scan.........................................10-8
Table 10.4 System Controller Device Identification Register...............................................................10-9
PES34H16 User Manual v October 30, 2008
Page 12
IDT List of Tables
Notes
PES34H16 User Manual vi October 30, 2008
Page 13
Notes
List of Figures
®
Figure 1.1 PES34H16 Architectural Block Diagram ............................................................................1-2
Figure 1.2 PES34H16 Logic Diagram .................................................................................................1-3
Figure 1.3 All Ports Unmerged Configuration ...................................................................................1-15
Figure 1.4 Three Ports Merged Configuration ...................................................................................1-16
Figure 2.1 Upstream Port Failover Architecture ..................................................................................2-1
Figure 2.2 Upstream Failover Mode Data Configurations ...................................................................2-2
Figure 3.1 Common Clock on Upstream and Downstream (option to enable or disable Spread
Spectrum Clock) ................................................................................................................3-1
Figure 3.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable
Spread Spectrum Clock) ....................................................................................................3-2
Figure 3.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable
Spread Spectrum Clock) ....................................................................................................3-2
Figure 3.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum
Clock) .................................................................................................................................3-3
Figure 3.5 Fundamental Reset in Transparent Mode with Serial EEPROM Initialization ....................3-6
Figure 3.6 Power Enable Controlled Reset Output Mode Operation ..................................................3-9
Figure 3.7 Power Good Controlled Reset Output Mode Operation .....................................................3-9
Figure 4.1 Unmerged Port Lane Reversal for Maximum Link Width of x4
(MAXLNKWDTH[5:0]=0x4) ................................................................................................4-2
Figure 4.2 Unmerged Port Lane Reversal for Maximum Link Width of x2
(MAXLNKWDTH[5:0]=0x2) ................................................................................................4-2
Figure 4.3 Merged Port Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[5:0]=0x2) ...4-3
Figure 4.4 Merged Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[5:0]=0x4) ...4-3
Figure 4.5 Merged Port Lane Reversal for Maximum Link Width of x8 (MAXLNKWDTH[5:0]=0x8) ...4-4
Figure 4.6 PES34H16 ASPM Link Sate Transitions ...........................................................................4-6
Figure 6.1 SMBus Interface Configuration Examples .........................................................................6-1
Figure 6.2 Sequential Double Word Initialization Sequence Format ...................................................6-4
Figure 6.3 Configuration Done Sequence Format ..............................................................................6-4
Figure 6.4 Serial EEPROM Initialization Errors ...................................................................................6-5
Figure 6.5 I/O Expander Function Allocation ......................................................................................6-6
Figure 6.6 I/O Expander Default Output Signal Value ........................................................................6-7
Figure 6.7 Slave SMBus Command Code Format ............................................................................6-18
Figure 6.8 CSR Register Read or Write CMD Field Format ..............................................................6-20
Figure 6.9 Serial EEPROM Read or Write CMD Field Format ..........................................................6-21
Figure 6.10 CSR Register Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................6-22
Figure 6.11 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................6-23
Figure 6.12 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........6-23
Figure 6.13 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........6-23
Figure 6.14 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........6-23
Figure 6.15 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....6-24
Figure 7.1 PES34H16 Power Management State Transition Diagram ...............................................7-1
Figure 8.1 Hot-Plug on Switch Downstream Slots Application ............................................................8-1
Figure 8.2 Hot-Plug with Switch on Add-In Card Application ..............................................................8-2
Figure 8.3 Hot-Plug with Carrier Card Application ..............................................................................8-2
Figure 8.4 PES34H16 Hot-Plug Event Signalling ...............................................................................8-5
Figure 9.1 Port Configuration Space Organization .............................................................................9-2
PES34H16 User Manual vii October 30, 2008
Page 14
IDT List of Figures
Notes
Figure 10.1 Diagram of the JTAG Logic ..............................................................................................10-1
Figure 10.2 State Diagram of PES34H16’s TAP Controller ................................................................10-2
Figure 10.3 Diagram of Observe-only Input Cell .................................................................................10-6
Figure 10.4 Diagram of Output Cell ....................................................................................................10-6
Figure 10.5 Diagram of Output Enable Cell ........................................................................................10-7
Figure 10.6 Device ID Register Format ...............................................................................................10-9
PES34H16 User Manual viii October 30, 2008
Page 15
Notes
Register List
®
AERCAP - AER Capabilities (0x100)..................................................................................................... 9-39
AERCEM - AER Correctable Error Mask (0x114).................................................................................. 9-44
AERCES - AER Correctable Error Status (0x110)................................................................................. 9-43
AERCTL - AER Control (0x118)............................................................................................................. 9-44
AERHL1DW - AER Header Log 1st Doubleword (0x11C)..................................................................... 9-45
AERHL2DW - AER Header Log 2nd Doubleword (0x120)..................................................................... 9-45
AERHL3DW - AER Header Log 3rd Doubleword (0x124)...................................................................... 9-45
AERHL4DW - AER Header Log 4th Doubleword (0x128)...................................................................... 9-45
AERUEM - AER Uncorrectable Error Mask (0x108).............................................................................. 9-40
AERUES - AER Uncorrectable Error Status (0x104)............................................................................. 9-40
AERUESV - AER Uncorrectable Error Severity (0x10C)........................................................................ 9-42
BAR0 - Base Address Register 0 (0x010).............................................................................................. 9-15
BAR1 - Base Address Register 1 (0x014).............................................................................................. 9-15
BCTL - Bridge Control Register (0x03E)................................................................................................9-21
BIST - Built-in Self Test Register (0x00F).............................................................................................. 9-15
CAPPTR - Capabilities Pointer Register (0x034)................................................................................... 9-20
CCODE - Class Code Register (0x009)................................................................................................. 9-14
CLS - Cache Line Size Register (0x00C)............................................................................................... 9-14
DID - Device Identification Register (0x002).......................................................................................... 9-12
ECFGADDR - Extended Configuration Space Access Address (0x0F8)............................................... 9-38
ECFGDATA - Extended Configuration Space Access Data (0x0FC)..................................................... 9-39
EEPROMINTF - Serial EEPROM Interface (0x42C).............................................................................. 9-66
EROMBASE - Expansion ROM Base Address Register (0x038)........................................................... 9-20
GPECTL - General Purpose Event Control (0x450)............................................................................... 9-70
GPESTS - General Purpose Event Status (0x454)................................................................................ 9-72
GPIOCFG - General Purpose I/O Configuration (0x41C)....................................................................... 9-63
GPIOD - General Purpose I/O Data (0x420).......................................................................................... 9-64
GPIOFUNC - General Purpose I/O Control Function (0x418)................................................................ 9-63
GPR - General Purpose Register (0x40C).............................................................................................9-63
HDR - Header Type Register (0x00E).................................................................................................... 9-15
HPCFGCTL - Hot-Plug Configuration Control (0x408)........................................................................... 9-62
INTRLINE - Interrupt Line Register (0x03C)........................................................................................... 9-20
INTRPIN - Interrupt PIN Register (0x03D)............................................................................................. 9-21
IOBASE - I/O Base Register (0x01C)..................................................................................................... 9-16
IOBASEU - I/O Base Upper Register (0x030)........................................................................................ 9-19
IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434)..................................................................... 9-68
IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438)..................................................................... 9-69
IOEXPADDR2 - SMBus I/O Expander Address 2 (0x43C).................................................................... 9-69
IOEXPINTF - I/O Expander Interface (0x430)........................................................................................ 9-67
IOLIMIT - I/O Limit Register (0x01D)...................................................................................................... 9-17
IOLIMITU - I/O Limit Upper Register (0x032)......................................................................................... 9-20
MBASE - Memory Base Register (0x020).............................................................................................. 9-18
MLIMIT - Memory Limit Register (0x022)............................................................................................... 9-18
MSIADDR - Message Signaled Interrupt Address (0x0D4).................................................................... 9-37
MSICAP - Message Signaled Interrupt Capability and Control (0x0D0)................................................ 9-36
MSIMDATA - Message Signaled Interrupt Message Data (0x0DC)....................................................... 9-38
MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8)...................................................... 9-37
PBUSN - Primary Bus Number Register (0x018)................................................................................... 9-15
PCICMD - PCI Command Register (0x004)...........................................................................................9-12
PES34H16 User Manual ix October 30, 2008
Page 16
IDT Register List
Notes
PCIECAP - PCI Express Capability (0x040) ...........................................................................................9-22
PCIEDCAP - PCI Express Device Capabilities (0x044)..........................................................................9-23
PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064).....................................................................9-33
PCIEDCTL - PCI Express Device Control (0x048)..................................................................................9-24
PCIEDCTL2 - PCI Express Device Control 2 (0x068).............................................................................9-33
PCIEDSTS - PCI Express Device Status (0x04A) ..................................................................................9-25
PCIEDSTS2 - PCI Express Device Status 2 (0x06A) .............................................................................9-34
PCIELCAP - PCI Express Link Capabilities (0x04C) ..............................................................................9-26
PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) .........................................................................9-34
PCIELCTL - PCI Express Link Control (0x050).......................................................................................9-27
PCIELCTL2 - PCI Express Link Control 2 (0x070)..................................................................................9-34
PCIELSTS - PCI Express Link Status (0x052)........................................................................................9-28
PCIELSTS2 - PCI Express Link Status 2 (0x072)...................................................................................9-34
PCIESCAP - PCI Express Slot Capabilities (0x054)...............................................................................9-29
PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074)..........................................................................9-34
PCIESCTL - PCI Express Slot Control (0x058).......................................................................................9-31
PCIESCTL2 - PCI Express Slot Control 2 (0x078)..................................................................................9-34
PCIESSTS - PCI Express Slot Status (0x05A) .......................................................................................9-32
PCIESSTS2 - PCI Express Slot Status 2 (0x07A) ..................................................................................9-35
PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200)................................................9-46
PCISTS - PCI Status Register (0x006) ...................................................................................................9-13
PLTIMER - Primary Latency Timer (0x00D)............................................................................................9-15
PMBASE - Prefetchable Memory Base Register (0x024).......................................................................9-18
PMBASEU - Prefetchable Memory Base Upper Register (0x028)..........................................................9-19
PMCAP - PCI Power Management Capabilities (0x0C0)........................................................................9-35
PMCSR - PCI Power Management Control and Status (0x0C4) ............................................................9-36
PMLIMIT - Prefetchable Memory Limit Register (0x026)........................................................................9-19
PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)..........................................................9-19
PVCCAP1- Port VC Capability 1 (0x204)................................................................................................9-46
PVCCAP2- Port VC Capability 2 (0x208)................................................................................................9-47
PVCCTL - Port VC Control (0x20C)........................................................................................................9-47
PVCSTS - Port VC Status (0x20E) .........................................................................................................9-48
PWRBCAP - Power Budgeting Capabilities (0x280)...............................................................................9-57
PWRBD - Power Budgeting Data (0x288)...............................................................................................9-57
PWRBDSEL - Power Budgeting Data Select (0x284).............................................................................9-57
PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300)...................................................................9-58
PWRBPBC - Power Budgeting Power Budget Capability (0x28C) .........................................................9-58
RID - Revision Identification Register (0x008) ........................................................................................9-14
SBUSN - Secondary Bus Number Register (0x019)...............................................................................9-16
SECSTS - Secondary Status Register (0x01E) ......................................................................................9-17
SLTIMER - Secondary Latency Timer Register (0x01B).........................................................................9-16
SMBUSCTL - SMBus Control (0x428)....................................................................................................9-65
SMBUSSTS - SMBus Status (0x424) .....................................................................................................9-64
SNUMCAP - Serial Number Capabilities (0x180) ...................................................................................9-45
SNUMLDW - Serial Number Lower Doubleword (0x184) .......................................................................9-46
SNUMUDW - Serial Number Upper Doubleword (0x188).......................................................................9-46
SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4)...........................................................9-38
SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0)...................................9-38
SUBUSN - Subordinate Bus Number Register (0x01A)..........................................................................9-16
SWCTL - Switch Control (0x404)............................................................................................................9-61
SWPECNT - Switch Parity Error Count (0x74C).....................................................................................9-77
SWPECTL - Switch Parity Error Control (0x740)....................................................................................9-76
SWPERCTL - Switch Parity Error Reporting Control (0x748).................................................................9-77
SWPESTS - Switch Parity Error Status (0x744) .....................................................................................9-76
SWSTS - Switch Status (0x400) .............................................................................................................9-59
PES34H16 User Manual x October 30, 2008
Page 17
IDT Register List
Notes
SWTOCNT - Switch Time-Out Count (0x75C)........................................................................................9-79
SWTORCTL - Switch Time-Out Reporting Control (0x758)....................................................................9-78
SWTOSTS - Switch Time-Out Status (0x754) ........................................................................................9-77
USPFCTL - Upstream Port Failover Control (0x474)..............................................................................9-75
USPFSTS - Upstream Port Failover Status (0x470)...............................................................................9-74
USPFTIMER - Upstream Port Failover Watchdog Timer (0x478)...........................................................9-75
VCR0CAP- VC Resource 0 Capability (0x210).......................................................................................9-48
VCR0CTL- VC Resource 0 Control (0x214)............................................................................................9-49
VCR0STS - VC Resource 0 Status (0x218)............................................................................................9-50
VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x230)..............................................................9-52
VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x234)..............................................................9-53
VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x238)..............................................................9-53
VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x23C).............................................................9-54
VCR1CAP- VC Resource 1 Capability (0x21C)......................................................................................9-50
VCR1CTL- VC Resource 1 Control (0x220)............................................................................................9-51
VCR1STS - VC Resource 1 Status (0x224)............................................................................................9-51
VCR1TBL0 - VC Resource 1 Arbitration Table Entry 0 (0x240)..............................................................9-54
VCR1TBL1 - VC Resource 1 Arbitration Table Entry 1 (0x244)..............................................................9-55
VCR1TBL2 - VC Resource 1 Arbitration Table Entry 2 (0x248)..............................................................9-55
VCR1TBL3 - VC Resource 1 Arbitration Table Entry 3 (0x24C).............................................................9-56
VID - Vendor Identification Register (0x000)...........................................................................................9-11
PES34H16 User Manual xi October 30, 2008
Page 18
IDT Register List
Notes
PES34H16 User Manual xii October 30, 2008
Page 19
Notes
®
Chapter 1
PES34H16 Device Overview
Introduction
The 89HPES34H16 is a member of the IDT PRECISE™ family of PCI Express® switching solutions.
The PES34H16 is a 34-lane, 16-port peripheral chip that performs PCI Express packet switching with a
feature set optimized for high-performance applications such as servers, storage, and communications/
networking. It provides connectivity and switching functions between a PCI Express upstream port and up
to fifteen downstream ports and supports switching between downstream ports.
List of Features
– Sixteen maximum switch ports
• Up to three x8 ports that bifurcate up to six x4 ports
• Ten x1 ports
– Thirty-four 2.5 Gbps embedded SerDes
• Supports pre-emphasis and receive equalization on per-port basis
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin algorithms
– Automatic per port link width negotiation from x8 to x4 to x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy software
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and queueing
– Integrates thirty-four 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no sepa-
rate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Redundant upstream port failover capability
– Supports optional PCI Express end-to-end CRC checking
PES34H16 User Manual 1 - 1 October 30, 2008
Page 20
IDT PES34H16 Device Overview
Reset
Controller
Bifurcating PCI Express
Stack 0 Ingress
Port 0
Port 1
Bifurcating PCI Express
Stack 1 Ingress
Port 2
Port 3
Bifurcating PCI Express
Stack 2 Ingress
Port 4
Port 5
Bifurcating PCI Express
Stack 3 Ingress
Port 6
Port 7
Bifurcating PCI Express
Stack 4 Ingress
Port 8
Port 9
Bifurcating PCI Express
Stack 5 Ingress
Port 10
Port 11
Bifurcating PCI Express
Stack 6 Ingress
Port 12
Port 13
Bifurcating PCI Express
Stack 7 Ingress
Port 14
Port 15
Credit Based Queue (CBQ)
.
.
.
Credit Based Queue (CBQ)
.
.
.
Credit Based Queue (CBQ)
.
.
.
Credit Based Queue (CBQ)
.
.
.
Credit Based Queue (CBQ)
.
.
.
Credit Based Queue (CBQ)
.
.
.
Credit Based Queue (CBQ)
.
.
.
Credit Based Queue (CBQ)
.
.
.
Shared Memory Queue (SMQ)
Memory and Scheduler (MAS)
Destination
Scheduler
Destination
Scheduler
Shared Memory Queue (SMQ)
Shared Memory Queue (SMQ)
Shared Memory Queue (SMQ)
Bifurcating PCI Express
Stack 0 Egress
Port 0
Bifurcating PCI Express
Stack 1 Egress
Port 1
Port 2
Port 3
Shared Memory Queue (SMQ)
Memory and Scheduler (MAS)
Destination
Scheduler
Destination
Scheduler
Shared Memory Queue (SMQ)
Shared Memory Queue (SMQ)
Shared Memory Queue (SMQ)
Bifurcating PCI Express
Stack 2 Egress
Port 4
Bifurcating PCI Express
Stack 3 Egress
Port 5
Port 6
Port 7
Shared Memory Queue (SMQ)
Memory and Scheduler (MAS)
Destination
Scheduler
Destination
Scheduler
Shared Memory Queue (SMQ)
Shared Memory Queue (SMQ)
Shared Memory Queue (SMQ)
Bifurcating PCI Express
Stack 4 Egress
Port 8
Bifurcating PCI Express
Stack 5 Egress
Port 9
Port 10
Port 11
Shared Memory Queue (SMQ)
Memory and Scheduler (MAS)
Destination
Scheduler
Destination
Scheduler
Shared Memory Queue (SMQ)
Shared Memory Queue (SMQ)
Shared Memory Queue (SMQ)
Bifurcating PCI Express
Stack 6 Egress
Port 12
Bifurcating PCI Express
Stack 7 Egress
Port 13
Port 14
Port 15
Switch Core
Master
SMBus
Interface
Slave
SMBus
Interface
GPIO
Controller
– Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC)
– Supports optional PCI Express Advanced Error Reporting
– Supports PCI Express Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC
motherboards
– Supports Hot-Swap
Power Management
– Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM)
• Supports powerdown modes at the link level (L0, L0s, L1, L2/L3 Ready and L3) and at the device level (D0, D3
hot
)
– Unused SerDes disabled
Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Thirty-two General Purpose Input/Output pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with 1mm ball spacing
PES34H16 User Manual 1 - 2 October 30, 2008
Figure 1.1 PES34H16 Architectural Block Diagram
Page 21
IDT PES34H16 Device Overview
Reference
Clock
PEREFCLKP[3:0]
PEREFCLKN[3:0]
JTAG_TCK
GPIO[31:0]
32
General Purpose
I/O
VDDCORE
V
DD
I/O
V
DD
PE
V
DD
APE
Power/Ground
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
Master
SMBus Interface
CCLKUS
RSTHALT
System
Pins
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
V
SS
SWMODE[3:0]
4
4
4
CCLKDS
PERSTN
REFCLKM
MSMBSMODE
VTTPE
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PE0TP[0]
PE0TN[0]
PE0TP[3]
PE0TN[3]
...
...
PE1RP[0]
PE1RN[0]
PE1RP[3]
PE1RN[3]
PCIe Switch
SerDes Input
PE1TP[0]
PE1TN[0]
PE1TP[3]
PE1TN[3]
...
Port 1
...
PE2RP[0]
PE2RN[0]
PE2RP[3]
PE2RN[3]
PE2TP[0]
PE2TN[0]
PE2TP[3]
PE2TN[3]
...
...
PE5RP[0]
PE5RN[0]
PE5RP[3]
PE5RN[3]
PE5TP[0]
PE5TN[0]
PE5TP[3]
PE5TN[3]
...
...
PE6RP[0]
PE6RN[0]
PE15RP[0]
PE15RN[0]
PCIe Switch
SerDes Input
PE6TP[0]
PE6TN[0]
PE15TP[0]
PE15TN[0]
PCIe Switch
SerDes Output
...
Port 15
Port 15
...
PES34H16
...
P01MERGEN
P23MERGEN
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
4
Slave
SMBus Interface
P45MERGEN
PCIe Switch
SerDes Input
Port 6
PCIe Switch
SerDes Input
Port 5
PCIe Switch
SerDes Input
Port 2
PCIe Switch
SerDes Input
Port 0
PCIe Switch
SerDes Output
Port 6
PCIe Switch
SerDes Output
Port 1
PCIe Switch
SerDes Output
Port 0
PCIe Switch
SerDes Output
Port 2
PCIe Switch
SerDes Output
Port 5
...
Logic Diagram
Figure 1.2 PES34H16 Logic Diagram
PES34H16 User Manual 1 - 3 October 30, 2008
Page 22
IDT PES34H16 Device Overview
Notes
System Identification
Vendor ID
All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech-
nology, Inc.
Device ID
The PES34H16 device ID is shown in Table 1.1.
Revisio n ID
The revision ID in the PES34H16 is set to the same value in all mode. The value of the revision ID is
determined in one place and is easily modified during a metal mask change.
The revision ID will start at 0x0 and will be incremented with each all-layer or metal mask change.
PCIe Device Device ID
0x4 0x8034
Table 1.1 PES34H16 Device IDs
Revision ID Description
0x0 Corresponds to ZA silicon
Table 1.2 PES34H16 Revision ID
JTAG ID
The JTAG ID is:
– Version: Same value as Revision ID. See Table 1.2
– Part number: Same value as base Device ID. See Table 1.1.
– Manufacture ID: 0x33
– LSB: 0x1
SSID/SSVID
The PES34H16 contains the mechanisms necessary to implement the PCI-to-PCI bridge Subsystem ID
and Subsystem Vendor ID capability structure. However, in the default configuration the Subsystem ID and
Subsystem Vendor ID capability structure is not enabled. To enable this capability, the SSID and SSVID
fields in the Subsystem ID and Subsystem Vendor ID (SSIDSSVID) register must be initialized with the
appropriate ID values. the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be
initialized to point to this capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted
to point to the next capability if necessary.
Device Serial Nu m ber E nha nced Capability
The PES34H16 contains the mechanisms necessary to implement the PCI express device serial
number enhanced capability. However, in the default configuration this capability structure is not enabled.
To enable the device serial number enhanced capability, the Serial Number Lower Doubleword
(SNUMLDW) and the Serial Number Upper Doubleword (SNUMUDW) registers should be initialized. The
Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to this
capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted to point to the next capability if necessary.
PES34H16 User Manual 1 - 4 October 30, 2008
Page 23
IDT PES34H16 Device Overview
Notes
Pin Description
The following tables lists the functions of the pins provided on the PES34H16. Some of the functions
listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals
ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals
(including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic
one (high) level. Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the
positive portion of the differential pair and the differential signal ending in “N” is the negative portion of the
differential pair.
Signal Type Name/Description
PE0RP[3:0]
PE0RN[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1RN[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE2RP[3:0]
PE2RN[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3RN[3:0]
PE3TP[3:0]
PE3TN[3:0]
PE4RP[3:0]
PE4RN[3:0]
PE4TP[3:0]
PE4TN[3:0]
PE5RP[3:0]
PE5RN[3:0]
PE5TP[3:0]
PE5TN[3:0]
PE6RP[0]
PE6RN[0]
PE6TP[0]
PE6TN[0]
PE7RP[0]
PE7RN[0]
PE7TP[0]
PE7TN[0]
I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit
pairs for port 0. Port 0 is the upstream port.
I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become port
0 receive pairs for lanes 4 through 7.
O PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit
pairs for port 1. When port 0 is merged with port 1, these signals become port
0 transmit pairs for lanes 4 through 7.
I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit
pairs for port 2.
I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become port
2 receive pairs for lanes 4 through 7.
O PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit
pairs for port 2. When port 2 is merged with port 3, these signals become port
2 transmit pairs for lanes 4 through 7.
I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit
pairs for port 4.
I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become port
4 receive pairs for lanes 4 through 7.
O PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit
pairs for port 5. When port 4 is merged with port 5, these signals become port
4 transmit pairs for lanes 4 through 7.
I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pair for port 6.
O PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit
pair for port 6.
I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive
pair for port 7.
O PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit
pair for port 7.
Table 1.3 PCI Express Interface Pins (Part 1 of 2)
PES34H16 User Manual 1 - 5 October 30, 2008
Page 24
IDT PES34H16 Device Overview
Notes
Signal Type Name/Description
PE8RP[0]
PE8RN[0]
PE8TP[0]
PE8TN[0]
PE9RP[0]
PE9RN[0]
PE9TP[[0]
PE9TN[0]
PE10RP[0]
PE10RN[0]
PE10TP[0]
PE10TN[0]
PE11RP[0]
PE11RN[0]
PE11TP[0]
PE11TN[0]
PE12RP[0]
PE12RN[0]
PE12TP[0]
PE12TN[0]
PE13RP[0]
PE13RN[0]
PE13TP[0]
PE13TN[0]
PE14RP[0]
PE14RN[0]
PE14TP[0]
PE14TN[0]
PE15RP[0]
PE15RN[0]
PE15TP[0]
PE15TN[0]
REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre-
PEREFCLKP[3:0]
PEREFCLKN[3:0]
I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive
pair for port 8.
O PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit
pair for port 8.
I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive
pair for port 9.
O PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit
pair for port 9.
I PCI Express Port 10 Serial Data Receive. Differential PCI Express receive
pair for port 10.
O PCI Express Port 10 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 10.
I PCI Express Port 11 Serial Data Receive. Differential PCI Express receive
pair for port 11.
O PCI Express Port 11 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 11.
I PCI Express Port 12 Serial Data Receive. Differential PCI Express receive
pair for port 12.
O PCI Express Port 12 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 12.
I PCI Express Port 13 Serial Data Receive. Differential PCI Express receive
pair for port 13.
O PCI Express Port 13 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 13. W
I PCI Express Port 14 Serial Data Receive. Differential PCI Express receive
pair for port 14.
O PCI Express Port 14 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 14.
I PCI Express Port 15 Serial Data Receive. Differential PCI Express receive
pair for port 15.
O PCI Express Port 15 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 15.
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
I PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal.
Table 1.3 PCI Express Interface Pins (Part 2 of 2)
PES34H16 User Manual 1 - 6 October 30, 2008
Page 25
IDT PES34H16 Device Overview
Notes
Signal Type Name/Description
MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize trans-
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master
SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
Signal Type Name/Description
serial EEPROM from which configuration information is loaded.
fers on the master SMBus. It is active and generating the clock only when the
EEPROM or I/O Expanders are being accessed.
SMBus.
the slave SMBus interface responds.
fers on the slave SMBus.
SMBus.
Table 1.4 SMBus Interface Pins
GPIO[0] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[1] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[2] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[3] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[4] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[5] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
GPIO[6] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
GPIO[7] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[8] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
Table 1.5 General Purpose I/O Pins (Part 1 of 4)
PES34H16 User Manual 1 - 7 October 30, 2008
Page 26
IDT PES34H16 Device Overview
Notes
Signal Type Name/Description
GPIO[9] I/O General Purpose I/O.
GPIO[10] I/O General Purpose I/O.
GPIO[11] I/O General Purpose I/O.
GPIO[12] I/O General Purpose I/O.
GPIO[13] I/O General Purpose I/O.
GPIO[14] I/O General Purpose I/O.
GPIO[15] I/O General Purpose I/O.
GPIO[16] I/O General Purpose I/O.
GPIO[17] I/O General Purpose I/O.
GPIO[18] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P7RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 7
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P8RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 8
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P9RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 9
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P10RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 10
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P11RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 11
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P12RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 12
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P13RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 13
Table 1.5 General Purpose I/O Pins (Part 2 of 4)
PES34H16 User Manual 1 - 8 October 30, 2008
Page 27
IDT PES34H16 Device Overview
Notes
Signal Type Name/Description
GPIO[19] I/O General Purpose I/O.
GPIO[20] I/O General Purpose I/O.
GPIO[21] I/O General Purpose I/O.
GPIO[22] I/O General Purpose I/O.
GPIO[23] I/O General Purpose I/O.
GPIO[24] I/O General Purpose I/O.
GPIO[25] I/O General Purpose I/O.
GPIO[26] I/O General Purpose I/O.
GPIO[27] I/O General Purpose I/O.
GPIO[28] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P14RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 14
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P15RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 15
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 0
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN1
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 1
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 2
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN3
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 3
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN4
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 4
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN5
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 5
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN6
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 6
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN7
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 7
Table 1.5 General Purpose I/O Pins (Part 3 of 4)
PES34H16 User Manual 1 - 9 October 30, 2008
Page 28
IDT PES34H16 Device Overview
Notes
Signal Type Name/Description
GPIO[29] I/O General Purpose I/O.
GPIO[30] I/O General Purpose I/O.
GPIO[31] I/O General Purpose I/O.
Signal Type Name/Description
CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi-
CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indicates
MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the mas-
P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low
P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low
This pin can be configured as a general purpose I/O pin.
This pin can be configured as a general purpose I/O pin.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN10
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 10
Table 1.5 General Purpose I/O Pins (Part 4 of 4)
cates that a common clock is being used between the downstream device
and the downstream port.
that a common clock is being used between the upstream device and the
upstream port.
ter SMBus should operate at 100 KHz instead of 400 KHz. This value may not
be overridden.
internally via a 251K ohm resistor.
When this pin is low, port 0 is merged with port 1 to form a single x8 port. The
Serdes lanes associated with port 1 become lanes 4 through 7 of port 0.
When this pin is high, port 0 and port 1 are not merged, and each operates as
a single x4 port
internally via a 251K ohm resistor.
When this pin is low, port 2 is merged with port 3 to form a single x8 port. The
Serdes lanes associated with port 3 become lanes 4 through 7 of port 2.
When this pin is high, port 2 and port 3 are not merged, and each operates as
a single x4 port.
internally via a 251K ohm resistor.
When this pin is low, port 4 is merged with port 5 to form a single x8 port. The
Serdes lanes associated with port 5 become lanes 4 through 7 of port 4.
When this pin is high, port 4 and port 5 are not merged, and each operates as
a single x4 port.
Table 1.6 System Pins (Part 1 of 2)
PES34H16 User Manual 1 - 10 October 30, 2008
Page 29
IDT PES34H16 Device Overview
Notes
Signal Type Name/Description
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the
RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental
SWMODE[3:0] I Switch Mode. These configuration pins determine the PES34H16 switch
PES34H16 and initiates a PCI Express fundamental reset.
reset, the PES34H16 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to read
and write registers internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT bit is cleared in
the PA_SWCTL register by an SMBus master.
operating mode. These pins should be static and not change following the
negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0 selected as
the upstream port)
0x9 - Normal switch mode with upstream port failover (port 2 selected as
the upstream port)
0xA - Normal switch mode with Serial EEPROM initialization and upstream
port failover (port 0 selected as the upstream port)
0xB - Normal switch mode with Serial EEPROM initialization and upstream
port failover (port 2 selected as the upstream port)
0xC through 0xF - Reserved
Table 1.6 System Pins (Part 2 of 2)
Signal Type Name/Description
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into
or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan
logic or JTAG Controller. When no data is being shifted out, this signal is tristated.
JTAG_TMS I JTA G Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can
access this signal. However, for systems running in functional mode, one of
the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 1.7 Test Pins
PES34H16 User Manual 1 - 11 October 30, 2008
Page 30
IDT PES34H16 Device Overview
Notes
Signal Type Name/Description
VDDCORE I Core VDD. Power supply for core logic.
V
V
VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL
V
Pin Characteristics
Note: Some input pads of the PES34H16 do not contain internal pull-ups or pull-downs. Unused
inputs should be tied off to appropriate levels. This is especially critical for unused control signal
inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can
cause a slight increase in power consumption.
I/O I I/O VDD. LVTTL I/O buffer power supply.
DD
PE I PCI Express Digital Power. PCI Express digital power used by the digital
DD
V
SS
PE PCI Express Serial Data Transmit Termination Voltage. This pin allows
TT
power of the SerDes.
and bias generator.
I Ground.
the driver termination voltage to be set, enabling the system designer to control the Common Mode Voltage and output voltage swing of the corresponding PCI Serial Data Transmit differential pair.
Table 1.8 Power and Ground Pins
Function Pin Name Type Buffer
PCI Express Interface PE0RN[3:0] I CML Serial Link
PE0RP[3:0] I
PE0TN[3:0] O
PE0TP[3:0] O
PE1RN[3:0] I
PE1RP[3:0] I
PE1TN[3:0] O
PE1TP[3:0] O
PE2RN[3:0] I
PE2RP[3:0] I
PE2TN[3:0] O
PE2TP[3:0] O
PE3RN[3:0] I
PE3RP[3:0] I
PE3TN[3:0] O
PE3TP[3:0] O
PE4RN[3:0] I
PE4RP[3:0] I
I/O
Type
Internal
Resistor
Notes
Table 1.9 Pin Characteristics (Part 1 of 3)
PES34H16 User Manual 1 - 12 October 30, 2008
Page 31
IDT PES34H16 Device Overview
Notes
Function Pin Name Type Buffer
PCI Express Interface
(cont.)
PE4TN[3:0] O CML Serial Link
PE4TP[3:0] O
PE5RN[3:0] I
PE5RP[3:0] I
PE5TN[3:0] O
PE5TP[3:0] O
PE6RN[0] I
PE6RP[0] I
PE6TN[0] O
PE6TP[0] O
PE7RN[0] I
PE7RP[0] I
PE7TN[0] O
PE7TP[0] O
PE8RN[0] I
PE8RP[0] I
PE8TN[0] O
PE8TP[0] O
PE9RN[0] I
PE9RP[0] I
PE9TN[0] O
PE9TP[0] O
PE10RN[0] I
PE10RP[0] I
PE10TN[0] O
PE10TP[0] O
PE11RN[0] I
PE11RP[0] I
PE11TN[0] O
PE11TP[0] O
PE12RN[0] I
PE12RP[0] I
PE12TN[0] O
PE12TP[0] O
PE13RN[0] I
PE13RP[0] I
PE13TN[0] O
PE13TP[0] O
I/O
Type
Internal
Resistor
Notes
Table 1.9 Pin Characteristics (Part 2 of 3)
PES34H16 User Manual 1 - 13 October 30, 2008
Page 32
IDT PES34H16 Device Overview
Notes
Function Pin Name Type Buffer
PCI Express Interface
(cont.)
SMBus MSMBADDR[4:1
General Purpose I/O GPIO[31:0] I/O LVTTL pull-up
System Pins CCLKDS I LVTTL Input pull-up
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up
PE14RN[0] I CML Serial Link
PE14RP[0] I
PE14TN[0] O
PE14TP[0] O
PE15RN[0] I
PE15RP[0] I
PE15TN[0] O
PE15TP[0] O
PEREF-
CLKN[3:0]
PEREF-
CLKP[3:0]
REFCLKM I LVTTL Input pull-down
]
MSMBCLK I/O STI
MSMBDAT I/O STI
SSMBADDR[5,3:
1]
SSMBCLK I/O STI
SSMBDAT I/O STI
CCLKUS I pull-up
MSMBSMODE I pull-down
P01MERGEN I pull-down
P23MERGEN I pull-down
P45MERGEN I pull-down
PERSTN I
RSTHALT I pull-down
SWMODE[3:0] I pull-down
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up External pull-
I LVPECL/
CML
I
I LVTTL pull-up
I pull-up
I/O
Type
Diff. Clock
Input
Internal
Resistor
1
Notes
Refer to
Table 9 in the
PES34H16
Data Sheet
down
1.
Schmitt Trigger Input (STI).
PES34H16 User Manual 1 - 14 October 30, 2008
Table 1.9 Pin Characteristics (Part 3 of 3)
Page 33
IDT PES34H16 Device Overview
Notes
PES34H16
PCI to PCI
Bridge
PCI to PCI
Bridge
Dev. 1
PCI to PCI
Bridge
Dev. 5
PCI to PCI
Bridge
Dev. 6
PCI to PCI
Bridge
Dev. 15
Dev. 0
Port 0
Virtual PCI Bus
x4
Port 1
x4
Port 5
x4
Port 6
x1
Port 15
x1
...
...
...
...
Port Configuration
The PES34H16 contains up to 6 x4 ports and ten x1 ports labeled 0 through 15. Port 0 is always the
upstream port and ports 1 through 15 are always downstream ports. An even port n and its odd counterpart,
port n+1, may be merged into a single x8 port (ports 0 through 3 only). When this occurs, port n is said to be
a merged port. When an even port n and its odd counterpart, port n+1, operate independently, then ports n
and n+1 are said to be unmerged.
The PES34H16 supports port merging in a static manner during a fundamental reset. If the Port x and y
Merge (PxyMERGEN) signal is asserted, then the two x4 ports x and y are merged into a single x8 merged
port called port x. When ports x and y are merged, the switch port, the PCI-to-PCI bridge, and all associated
resources associated with port y are disabled and the following modifications are made to the default
PES34H16 configuration.
– All of the output signals associated with port y remain in a negated state (e.g., hot-plug outputs,
link status signals, port reset output, etc.)
– All input signals associated with port y are ignored by the PES34H16 and have no effect on its
operation.
– Configuration read or write transactions to device y on the PES34H16’s virtual PCI bus are treated
by the upstream port (port 0) as unsupported requests (i.e., the device no longer exists).
• This renders the registers in port y’s configuration space inaccessible to the root.
– All registers associated with port y become inaccessible via the SMBus. Reading or writing an
inaccessible register has an undefined effect.
• Reading a port y register returns an undefined value and writing a port y register has an unde-
– All of the SerDes lanes associated with port y become part of port x and are managed by port x as
native SerDes lanes (i.e., port x operates as though it were a x8 port).
– The initial value of the MAXLNKWDTH field in port x’s PCIELCAP register defaults to x8 mode.
Figures 1.3 and 1.4 illustrate two possible PES34H16 configurations. In Figure 1.3, all of the ports are
unmerged. In this configuration, the PES34H16 operates as a 16-port switch with all ports 0 through 5
having a x4 width, and ports 6 through 15 having a x 1 width. In Figure 1.4, even ports 0, 2, and 4 are
merged with their corresponding odd ports, and ports 6 through 15 remain x1 width. In this configuration,
the PES34H16 operates as a 13-port.
fined effect.
PES34H16 User Manual 1 - 15 October 30, 2008
Figure 1.3 All Ports Unmerged Configuration
Page 34
IDT PES34H16 Device Overview
Notes
PES34H16
PCI to PCI
Bridge
PCI to PCI
Bridge
PCI to PCI
Bridge
Dev. 2
Dev. 4
PCI to PCI
Bridge
PCI to PCI
Bridge
Dev. 6
Dev. 7
PCI to PCI
Bridge
Dev. 8
PCI to PCI
Bridge
Dev. 15
Dev. 0
Port 0
Virtual PCI Bus
x8
Port 2
x8
Port 4
x8
Port 6
x1
Port 7
x1
Port 8
x1
Port 15
x1
...
...
Disabled Ports
The PES34H16 may be configured to disable one or more ports. Disabling a port has the following
effect.
– All of the output signals associated with a disabled port remain in a negated state (e.g., hot plug
– All input signals associated with a disabled port are ignored by the PES34H16 and have no effect
– Configuration read or write transactions to a device that corresponds to a disabled port on the
All registers associated with a disabled port become inaccessible via the SMBus. Reading or writing a
disabled port’s register has an undefined effect.
Figure 1.4 Three Ports Merged Configuration
outputs, link status signals, port reset output, etc.)
on its operation. For example, if port 5 is disabled, the P45MERGEN has no effect on the
PES34H16.
PES34H16’s virtual PCI bus are treated by the upstream port (port 0) as an unsupported request
(i.e., the device no longer exists).
PES34H16 User Manual 1 - 16 October 30, 2008
Page 35
Notes
®
Chapter 2
Stack 1
Table
Route Map
Processor
Ingress
Checker
TLP
Processor
Egress
Processor
Completion
Processor
Message
Generator
TLP
Controller
Hot-Plug
Application Layer
Data Link Layer
Physical Layer and Port Bifurcation Mux/Demux
SerDesSerDes
Output &
Replay Buffer
Port 0 Port 1
Data Link Layer
Physical Layer and Port Bifurcation Mux/Demux
SerDesSerDes
Output &
Replay Buffer
Port 2 Port 3
Stack 0
Switch Core
Processor
Ingress
Checker
TLP
Processor
Completion
Processor
Message
Generator
TLP
Controller
Hot-Plug
Application Layer
Table
Route Map
Processor
Egress
Upstream Port Failover
Introduction
The PES34H16 supports an upstream port failover mechanism that enables the construction of fault
tolerant systems. Upstream port failover allows port 0 or port 2 to be selected as the upstream switch port.
The failover feature is disabled by default. To enable upstream port failover, an upstream port failover
switch mode must be selected in the boot configuration vector during a fundamental reset. The following
switch modes (SWMODE[3:0]) enable this feature.
– Normal switch mode with upstream port failover (port 0 selected as the upstream port)
– Normal switch mode with upstream port failover (port 2 selected as the upstream port)
– Normal switch mode with Serial EEPROM initialization and upstream port failover (port 0 selected
as the upstream port)
– Normal switch mode with Serial EEPROM initialization and upstream port failover (port 2 selected
as the upstream port)
A graphical representation of the upstream port failover architecture is shown in Figure 2.1.
PES34H16 User Manual 2 - 1 October 30, 2008
Stack 0 is always associated with the upstream port. In normal mode, SerDes lanes associated with port
0 are fed into stack zero. In failover mode, the SerDes lanes associated with port 0 or port 2 may be fed into
stack zero. Thus, from an external perspective, it appears as though the upstream port can be moved from
port 0 to port 2; however, in reality, all that is occurring is that the SerDes lanes associated with port 0 or
Figure 2.1 Upstream Port Failover Architecture
port 2 are multiplexed into stack zero (i.e., the stack associated with the upstream port).
Page 36
IDT Upstream Port Failover
Notes
Stack 0
SerDes
Port 0
SerDes
Port 1
SerDes
Port 2
SerDes
Port 3
Stack 1
(a) x8 Upstream Failover Mode with
Port 0 Selected
Stack 0
SerDes
Port 0
SerDes
Port 1
SerDes
Port 2
SerDes
Port 3
Stack 1
(b) x8 Upstream Failover Mode with
Port 2 Selected
Stack 0
SerDes
Port 0
SerDes
Port 1
SerDes
Port 2
SerDes
Port 3
Stack 1
(c) x4 Upstream Failover Mode with
Port 0 Selected
Stack 0
SerDes
Port 0
SerDes
Port 1
SerDes
Port 2
SerDes
Port 3
Stack 1
(d) x4 Upstream Failover Mode with
Port 2 Selected
When the PES34H16 is configured to operate in an upstream port failover switch mode, port 2 is always
disabled. If the upstream port is configured to operate in x8 merged mode, then both ports two and three
are disabled. The behavior of a disabled port is described in the section entitled section Disabled Ports on
page 1-16.
Upstream port resources (e.g., link status control LED outputs) are always associated with port 0
regardless of the external PES34H16 port associated with the upstream port. The PES34H16 consists of
eight bifurcating PCIe stacks. A PES34H16 stack may be configured to operate as two x4 ports (bifurcated
mode) or as one x8 port (merged mode).
Upstream port failover is supported in both x4 and x8 upstream port modes. However, both ports 0 and
2 must be configured to operate in the same mode (i.e., if port 0 is configured to operate in x8 merged
mode, then port 2 must also be configured to operate in x8 merged mode). Configuring ports 0 and 2 to
operate in different modes produces an undefined behavior.
If the PES34H16 is configured to operate in an upstream failover mode and the upstream port is configured to operate in x4 bifurcated mode, then ports 1 and 3 operate as normal. While upstream port failover
mode disables port 2, in bifurcated mode it has no effect on the operation of ports 1 and 3.
If the PES34H16 is configured to operate in an upstream failover mode and the upstream port is configured to operate in x8 merged mode, then ports 1, 2, and 3 are disabled. The behavior of a disabled port is
described in section Disabled Ports on page 1-16. x8 merged mode and x4 bifurcated mode data paths for
upstream port failover are illustrated in Figure 2.2. The red lines show the upstream port data path. The
green lines show the data paths for other ports.
PES34H16 User Manual 2 - 2 October 30, 2008
Figure 2.2 Upstream Failover Mode Data Configurations
Failover
An upstream port failover may be initiated statically through a fundamental reset or dynamically while
the system is running.
Page 37
IDT Upstream Port Failover
Notes
At a system level, a dynamic upstream port failover appears as a full link retrain of the upstream port,
i.e., the Link State Sequence State Machine (LTSSM) transitions to the Detect state, and the data link layer
transitions to a DL_Down state. This typically results in a hot-reset of the PES34H16 and devices below the
PES34H16 in the PCIe hierarchy. A hot-reset due to a DL_Down state may be disabled by setting the
Disable Link Down Hot Reset (DLDHRST) bit in the Switch Control (SWCTL) register. With this bit set, an
upstream port failover does not reset the PES34H16 or the PCIe hierarchy and system state is preserved.
When a dynamic upstream port failover occurs, upstream port data queued in the switch, data being
transmitted, and data in the replay buffer may be lost. Thus, some interruption of PCIe traffic should be
expected with an upstream port failover. When the switch is configured to operate in a mode that supports
upstream port failover, the Upstream Port Failover Enabled (USPFEN) bit is set in the Upstream Port
Failover Status (USPFSTS) register.
In all switch modes, the current external PES34H16 switch port associated with the upstream port may
be determined by reading the Current Upstream Port (CUSP) field in the USPFSTS register. Whenever a
dynamic upstream port failover occurs, the Upstream Port Change (USPC) bit is set in the USPFSTS
register. This bit is sticky and thus its status is preserved across a hot-reset.
The operation of the upstream port failover mechanism is unaffected by a hot-reset. Fields in the
USPFEN register have no effect on system operation when an upstream port failover switch mode has not
been selected during a fundamental reset.
Static Upstream Port Failover
A static upstream port failover requires a fundamental reset to be initiated whenever the upstream port
is changed. Since the initial upstream port is selected by the switch mode in the boot configuration vector,
the static upstream port failover feature may be viewed as nothing more than the ability to select the
upstream port during a fundamental reset.
A static upstream port failover consists of the following steps:
The following switch modes select port 0 as the upstream port during a fundamental reset:
The following switch modes select port 2 as the upstream port during a fundamental reset:
Since initiation of an upstream port failover requires a fundamental reset of the PCIe hierarchy, many
systems may require the use of dynamic upstream port failover.
– Assert the PCIe fundamental reset signal (PERSTN)
– Modify the switch mode (SWMODE) signals to select the external PES34H16 port associated with
the upstream port.
– Negate the PCIe fundamental reset signal (PERSTN).
– Normal switch mode
– Normal switch mode with Serial EEPROM initialization
– Normal switch mode with upstream port failover (port 0 selected as the upstream port)
– Normal switch mode with Serial EEPROM initialization and upstream port failover (port 0 selected
as the upstream port).
– Normal switch mode with upstream port failover (port 2 selected as the upstream port)
– Normal switch mode with Serial EEPROM initialization and upstream port failover (port 2 selected
as the upstream port)
Dynamic Upstream Port Failover
Dynamic upstream port failover allows the external PES34H16 port associated with the upstream port to
be modified while the system is live and in a manner which preserves the system state.
PES34H16 User Manual 2 - 3 October 30, 2008
Page 38
IDT Upstream Port Failover
Notes
When a dynamic upstream port failover is initiated, the PES34H16 takes the following actions:
The following sections describe the manner in which a dynamic upstream port failover may be initiated.
In most systems it is expected that only one upstream failover mechanism will be enabled at a time. If a
failover of the same type (i.e., software, signal, or watchdog timer) is initiated while one is already in progress, then the second initiation will be lost. If a failover of a different type is initiated while one is in progress,
then the second failover will be performed when the one in progress is completed. Software may utilize the
Upstream Failover Change (USPC) and Upstream Failover Change Initiated (USPCI) bits in the Upstream
Port Failover Status (USPFSTS) register to avoid failover race conditions.
Software Initiated Failover
An upstream port failover may be initiated by modifying the state of the Upstream Port Software Select
(USPSEL) field in the Upstream Port Failover Control (USPFCTL) register when the switch is selected to
operate in an upstream failover mode. A software initiated failover may be instituted by software running on
the root or software running on the device that writes to the USPSEL field via the SMBus. The USPSEL
field should not be modified during an upstream port failover (i.e., failover requests are not queued).
Signal Initiated Failover
An upstream port failover may be initiated by a change in the state of the Upstream Port Select
(USPSEL) signal. Such a failover is initiated when:
– The LTSSM associated with the upstream port immediately transitions to the Detect state and the
data link layer transitions to the DL_Down state. This causes data in the replay buffer associated
with the upstream port and upstream port data queued in the switch core to be discarded.
– The state of the SerDes multiplexors are modified to select the new upstream port.
– The LTSSM initiates link training with the upstream port.
1. the Upstream Port Signal Failover Enable (SIGFEN) bit is set in the Upstream Port Failover Control
(USPFCTL) register
2. the switch i s selected to operate in an upstream failover mode, and
3. the upstream port selected by the USPSEL signal differs from the current upstream port.
The USPSEL signal is an alternate function of GPIO[4]. The state of the USPSEL signal always reflects
the state of the GPIO[4] pin regardless of whether or not GPIO[4] is configured to operate as an alternate
function. When USPSEL is negated (low), port 0 is selected as the upstream port. When USPSEL is
asserted (high), port 2 is selected as the upstream port. The state of the USPSEL signal should not be
modified more frequently than once per second. The behavior of the PES34H16 is undefined when the
USPSEL signal is modified more frequently than this rate.
Watchdog Timer Initiated Failover
An upstream port failover may be initiated as the result of an expiration of a watchdog timer. Such a
failover is initiated when:
1. the Upstream Port Timer Failover Enable (TIMFEN) bit is set in the Upstream Port Failover Control
(USPFCTL) register
2. the switch i s selected to operate in an upstream failover mode, and
3. the Watchdog Timer Count (COUNT) field in the Upstream Port Failover Watchdog Timer
(USPFTIMER) transitions from a one to a zero.
When non-zero, the COUNT field in the US PFTIMER is decremented once per microsecond (1 µ S).
This provides a maximum watchdog timer interval of over one hour. Decrementing of the COUNT field
ceases when zero is reached. The COUNT fi eld may be written by software at any time. Modifying the
count field is used to rearm the watchdog timer. If not expired, the watchdog timer continues to decrement
across a hot-reset.
PES34H16 User Manual 2 - 4 October 30, 2008
Page 39
IDT Upstream Port Failover
Notes
When a watchdog timer failover is initiated, the new upstream port becomes the one that is not selected
by the CUSP field in the USPFSTS register. For example, if the current upstream port is port 0, then the
new upstream port following the failover is port 2.
When the count reaches zero, it remains at zero and no switchover will occur. When the count is
updated with a non-zero value, switchover is again enabled.
PES34H16 User Manual 2 - 5 October 30, 2008
Page 40
IDT Upstream Port Failover
Notes
PES34H16 User Manual 2 - 6 October 30, 2008
Page 41
Notes
®
Chapter 3
PES34H16
Port 0
CCLKDS
CCLKUS
REFCLK0
Root Complex
Hi
Hi
Clock Generator
Port 1
Port 15
EP
EP
...
...
REFCLK1 REFCLK2 REFCLK3
Clocking, Reset, and
Initialization
Introduction
The PES34H16 has four differential reference clock inputs that are used internally to generate all of the
clocks required by the internal switch logic and the SerDes. It is recommended that all reference clock input
pairs be driven from a common clock source. The frequency of the reference clock inputs may be selected
by the Reference Clock Mode Select (REFCLKM) input.
REFCLKM Description
0 100 MHz reference clock input.
1 125 MHz reference clock input.
Table 3.1 Reference Clock Mode Encoding
Each PES34H16 port has an associated PLL. Each of the reference clock differential inputs feeds four
on-chip PLLs (i.e., one quarter of the ports). Each PLL generates a 2.5 GHz clock which is used by four
SerDes lanes and produces a 250 MHz core clock. The 250 MHz core clock output from the upstream port
(i.e., port 0) is used as the system clock for internal switch logic
test mode via the SWMODE pins, the 250 MHz clock generated by the PLL is bypassed and the reference
clock input on REFCLKP[0]/REFCLKN[0] is used for the core logic.
1
. When the switch is placed in PLL Bypass
Clock Operation
When the CCLKUS and CCLKDS pins are asserted, they indicate that a common clock is being used
between the upstream device and the upstream port, as well as between the downstream devices and the
downstream ports. The Spread Spectrum Clock (SSC) must be disabled when the non-common clock is
used on either the upstream port or downstream port. Figures 3.1 through 3.4 illustrate the operation of the
CCLKUS and CCLKDS clocks using a common clock and a non-common clock.
PES34H16 User Manual 3 - 1 October 30, 2008
Figure 3.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock)
1.
The port 0 PLL is used to generate the 250 MHz core clock even when upstream port failover is enabled and
regardless of the selected upstream port.
Page 42
IDT Clocking, Reset, and Initialization Clock Operation
Notes
PES34H16
Port 0
CCLKDS
CCLKUS
Root Complex
Hi
Low
Clock Generator
Clock Generator
Port 1
Port 15
EP
EP
...
...
REFCLK0
REFCLK1 REFCLK2 REFCLK3
PES34H16
Port 0
CCLKDS
CCLKUS
Root Complex
Low
Hi
Clock Generator
Clock Generator
Port 1
Port 15
EP
EP
...
...
REFCLK0
REFCLK1 REFCLK2 REFCLK3
Figure 3.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum
Clock)
Figure 3.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable Spread Spectrum
Clock)
PES34H16 User Manual 3 - 2 October 30, 2008
Page 43
IDT Clocking, Reset, and Initialization Clock Operation
Notes
PES34H16
Port 0
CCLKDS
CCLKUS
Root Complex
Low
Low
Clock Generator
Clock Generator
Clock Generator
Port 1
Port 15
EP
EP
...
...
REFCLK0
REFCLK1 REFCLK2 REFCLK3
Figure 3.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock)
Initialization
A boot configuration vector consisting of the signals listed in Table 3.2 is sampled by the PES34H16
during a fundamental reset when PERSTN is negated. The boot configuration vector defines essential
parameters for switch operation. Since the boot configuration vector is sampled only during a fundamental
reset sequence, the value of signals which make up the boot configuration vector is ignored during other
times and their state outside of a fundamental reset has no effect on the operation of the PES34H16.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require configuration via an external serial EEPROM. The external serial EEPROM allows
modification of any bit in any software visible register. See Chapter 6, SMBus Interfaces, for more information on the serial EEPROM.
The external serial EEPROM and slave SMBus interface may be used to override the function of some
of the signals in the boot configuration vector during a fundamental reset. The signals that may be overridden are noted in Table 3.2. The state of all of the boot configuration signals in Table 3.2 sampled during
the most recent cold reset may be determined by reading the SWSTS register.
Signal
CCLKDS Y Common Cloc k Downstream. When the CCLKDS pin is asserted,
CCLKUS Y Common Cloc k Upstr ea m. When the CCLKUS pin is asserted, it
MSMBSMODE N Master SMBus Slow Mode. The assertion of this pin indicates that
P01MERGEN N Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with
May Be
Overridden
Description
it indicates that a common clock is being used between the downstream device and the downstream port.
indicates that a common clock is being used between the upstream
device and the upstream port.
the master SMBus should operate at 100 KHz instead of 400 kHz.
port 0 to form a single x8 port. The SerDes lanes associated with
port 1 become lanes 4 through 7 of port 0.
Table 3.2 Boot Configuration Vector Signals
PES34H16 User Manual 3 - 3 October 30, 2008
Page 44
IDT Clocking, Reset, and Initialization Clock Operation
Notes
Signal
P23MERGEN N Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with
P45MERGEN N Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside
RSTHALT Y Reset Halt. When this signal is asserted during a PCI Express fun-
SWMODE[3:0] N Switch Mode. These configuration pins determine the PES34H16
May Be
Overridden
Description
port 2 to form a single x8 port. The SerDes lanes associated with
port 3 become lanes 4 through 7 of port 2.
port 4 to form a single x8 port. The SerDes lanes associated with
port 5 become lanes 4 through 7 of port 4.
the PES34H16 and initiates a PCI Express fundamental reset.
damental reset, the PES34H16 executes the reset procedure and
remains in a reset state with the Master and Slave SMBuses active.
This allows software to read and write registers internal to the device
before normal device operation begins. The device exits the reset
state when the RSTHALT bit is cleared in the SWCTL register
through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the
SWCTL register.
switch operating mode. These pins should be static and not change
following the negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0
selected as the upstream port)
0x9 - Normal switch mode with upstream port failover (port 2
selected as the upstream port)
0xA - Normal switch mode with Serial EEPROM initialization and
upstream port failover (port 0 selected as the upstream port)
0xB - Normal switch mode with Serial EEPROM initialization and
upstream port failover (port 2 selected as the upstream port)
0xC through 0xF - Reserved
Table 3.2 Boot Configuration Vector Signals
Reset
The PES34H16 defines four reset categories: fundamental reset, hot reset, upstream secondary bus
reset, and downstream secondary bus reset.
– A fundamental reset causes all logic in the PES34H16 to be returned to an initial state.
– A hot reset causes all logic in the PES34H16 to be returned to an initial state, but does not cause
the state of register fields denoted as “sticky” to be modified.
– An upstream secondary bus reset causes all devices on the virtual PCI bus to be hot reset except
the upstream port (i.e., upstream PCI to PCI bridge).
– A downstream secondary bus reset causes a hot reset to be propagated on the corresponding
external secondary bus link.
There are two sub-categories of fundamental reset: cold reset and warm reset. A cold reset occurs
following a device being powered on and assertion of PERSTN. A warm reset i s a fundamental reset that
occurs without removal of power.
PES34H16 User Manual 3 - 4 October 30, 2008
Page 45
IDT Clocking, Reset, and Initialization Clock Operation
Notes
Fundamental R eset
A fundamental reset may be initiated by any of the following conditions:
– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input
pin.
– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power
is on.
– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch
Control (SWCTL) register.
The following reset sequence is executed.
1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN).
2. On negation of PERSTN, sample the boot configuration signals listed in Table 3.2. If PERSTN was
not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental
reset is the result of a one being written to the FRST bit in the SWCTL register).
– Examine the state of the sampled SWMODE[3:0] signals to determine the switch operating mode.
3. The PLL and SerDes are initialized.
4. Link training begins. Wh ile link training is in progress, proceed to step 5.
5. If the Reset Hal t (RSTHA LT) pin is asserted, the RSTHALT bit in the SWSTS register is set.
6. If the switch operating mode is not a test mode, then the reset signal to the PCI Express stacks and
associated logic is negated but they are held in a quasi-reset state in which the following actions
occur.
– All links enter an active link training state within 20ms of the clearing of the fundamental reset
condition.
– Within 100ms of the clearing of the fundamental reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration request
retry status completion. All other transactions are ignored.
7. The master SMBus operating frequency is determined.
– The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is
initialized to operate at 100 KHz rather than 400 KHz.
8. The slave SM Bus is taken out of reset and initialized. The slave SMBus address specified by the
SSMBADDR[5,3:1] pins is used.
9. The master SMBus is taken out of reset and initialized.
10. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then
the contents of the serial EEPROM are read and the appropriate P ES34H16 registers are upda ted.
– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the
SMBUSSTS register.
– When serial EEPROM initialization completes or when an error is detected, the EEPROMDONE
bit in the SMBUSSTS register is set.
11. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state
except the master and slave SMBuses, the control/status registers, and the stacks which continue
to be held in a quasi-reset state and respond to configuration transactions with a retry. The device
remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an external
agent may read and write any internal control and status registers and may access the external
serial EEPROM via the EEPROMINTF register.
12. Normal device operation begins.
PES34H16 User Manual 3 - 5 October 30, 2008
Page 46
IDT Clocking, Reset, and Initialization Clock Operation
Notes
REFCLK
Vdd
PERSTN
SerDes
Master SMBus
Slave SMBus
Tpvperl
PLL Reset and Lock CDR Reset & Lock Ready for Normal Operation
Ready for Normal Operation
ReadyIdle Serial E EPROM Initia lization
11μs
20ms max.
50
μ
s max.
Link Training
RSTHALT bit cleared
in SWCTL
Stacks in Quasi Reset State
Notes:
1) Reference Clock (REFCLK) not shown to scale.
2) The PES34H16 requires a minimum time for Tperst-clk of 1µs. The PES34H16 requires a minimum time for Tpvperl of 1ms.
3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PES34H16 is used. For example,
the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.
The PCIe base specification indicates that normal operation should begin within 1.0 second after a
fundamental reset of a device. The reset sequence above guarantees that normal operation will begin
within this period as long as the serial EEPROM initialization process completes within 200 ms. Under
normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a Master
SMBus operating frequency of 100 KHz.
Serial EEPROM initialization may cause writes to register fiel ds that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch Control
(SWCTL) register always results in the PES34H16 returning a completion
to the requester before the warm
reset process begins.
The PES34H16 provides a reset output signal for each downstream port implemented as a GPIO alternate function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the
downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they
are used as reset outputs.
The operation of a fundamental reset with serial EEPROM initialization (i.e., SWMODE[3:0] = 0x1) is
illustrated in Figure 3.5.
Figure 3.5 Fundamental Reset in Transparent Mode with Serial EEPROM Initialization
Hot Reset
A hot reset may be initiated by any of the following conditions:
– Reception of TS1 ordered-sets on the upstream port indicating a hot reset.
PES34H16 User Manual 3 - 6 October 30, 2008
– Data link layer of the upstream port transitions to the DL_Down state.
– Writing a one to the Hot Reset (HRST) bit in the System Control (SWCTL) register.
Page 47
IDT Clocking, Reset, and Initialization Clock Operation
Notes
The initiation of a hot reset due to the data l ink layer of the upstream port transitioni ng to the DL_D own
state may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the Switch Control
(SWCTL) register. Other hot reset conditions are unaffected by this bit. When a hot reset occurs, the
following sequence is executed.
1. Each downstream port whose link is up propagates the hot reset by transmitting TS1 ordered sets
with the hot reset bit set.
2. All of the logic associated with the PES34H16 except the PLLs, SerDes, master SMBus interface,
and slave SMBus interface is reset.
3. All registers fields in all registers, except those denoted as “sticky” or Read and Write when Unlocked
(i.e, RWL), are reset to their initial value. The value of fields denoted as “sticky” or RWL is preserved
across a hot reset.
4. Link training begins. Wh ile link training is in progress, proceed to step 5.
5. The PCI Express stacks and associated logic are held in a quasi-reset state in which the following
actions occur.
– All links enter an active link training state within 20ms of the clearing of the hot reset condition.
– Within 100ms of the clearing of the fundamental reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration request
retry status completion. All other transactions are ignored.
6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and
the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control
(SWCTL) register, then the contents of the serial EEPROM are read and the appropriate PES34H16
registers are updated. In addition, if the Reset Halt (RSTHALT) pin is asserted, the RSTHALT bit in
the SWSTS register is set.
– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the
SMBUSSTS register.
– When serial EEPROM initialization completes or when an error is detected, the DONE bit in the
SMBUSSTS register is set.
7. If the Res et Halt (RST HALT) bit is set in the SWCTL register, all of the logic is held in a reset state
except the master and slave SMBuses. The RSTHALT bit is set only under the following two conditions:
– serial EEPROM initialization is enabled in step 6 and an error is detected during loading of the
serial EEPROM or
– the user intentionally sets this bit through the EEPROM code.
8. Normal device operation begins.
The operation of the slave SMBus interface is unaffected by a hot reset. Using the slave SMBus to
access a register that is reset by a hot reset causes zero to be returned on a read and written data to be
ignored on writes.
A hot reset initiated by the writing of a one to the Hot Reset (HRS T) bit in the S witch Control (SWCTL)
register always results in the PES34H16 returning a completion
process begins.
Upstream Secondary Bus Reset
An upstream secondary bus reset may be initiated by the following condition:
– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (i.e., port 0)
Bridge Control Register (BRCTL).
to the requester before the hot reset
PES34H16 User Manual 3 - 7 October 30, 2008
Page 48
IDT Clocking, Reset, and Initialization Clock Operation
Notes
When an upstream secondary bus reset occurs, the following sequence is executed.
1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with
the hot reset bit set.
2. All registers fields in all registers associated with downstream ports, except those denoted as “sticky”
or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields
denoted as “sticky” or RWL is unaffected by an upstream secondary bus reset.
3. All TLPs received from downstream ports and queued in the PES34H16 are discarded.
4. Logic in the stack, application layer and switch core associated with the downstream ports are gracefully reset.
5. Wait for the Secondary Bus Reset (SRESET) bit in the upstream port’s Switch Control Register
(SWCTRL) to clear.
6. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and
Type 0 configuration read and write transactions that target the upstream port complete normally. During an
upstream secondary bus reset, all TLPs destined to the secondary side of the upstream port’s PCI-to-PCI
bridge are treated as unsupported requests. The operation of the slave SMBus interface is unaffected by an
upstream secondary bus reset. Using the slave SMBus to access a register that is reset by an upstream
secondary bus reset causes zero to be returned on a read and written data to be ignored on writes.
Downstream Secondary Bus Reset
A downstream secondary bus reset may be initiated by the following condition:
– A one is written to the Secondary Bus Reset (SRESET) bit in a downstream port’s (i.e., port 0)
Bridge Control Register (BCTRL).
When a downstream secondary bus reset occurs, the following sequence is executed.
1. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are
transmitted
2. All TLPs received from corresponding downstream port and queued in the PES34H16 are discarded.
3. Wait for the Secondary Bus Reset (SRESET) bit in the upstream port’s Switch Control Register
(SWCTRL) to clear.
4. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a downstream secondary bus reset. The operation
of other downstream ports is unaffected by a downstream secondary bus reset. During a downstream
secondary bus reset, Type 0 configuration read and write transactions that target the downstream port
complete normally. During a downstream secondary bus reset, all TLPs destined to the secondary side of
the downstream port’s PCI-to-PCI bridge are treated as unsupported requests. The operation of the slave
SMBus interface is unaffected by a downstream secondary bus reset.
Downstream Port Reset Outputs
Individual downstream port reset outputs (P1RSTN through P15RSTN) are provided as GPIO pin alternate functions. Following a fundamental reset, all of the GPIO pins default to GPIO inputs. Therefore, the
downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they
are used as reset outputs. The PES34H16 ensures through hardware that the minimum PxRSTN assertion
pulse width is no less than 200 µS.
Downstream port reset outputs can be configured to operate in one of three modes. These modes are:
power enable controlled reset output, power good controlled reset output, and hot reset controlled output.
The downstream port reset output mode is determined by the Reset Mode (RSTMODE) field in the HotPlug Configuration Control (HPCFGCTL) register.
PES34H16 User Manual 3 - 8 October 30, 2008
Page 49
IDT Clocking, Reset, and Initialization Clock Operation
Notes
PxPEP
PxRSTN
T
PWR2RST
T
RST2PWR
PxPEP
PxPWRGDN
T
PWR2RST
PxRSTN
T
RST2PWR
Power Enable Controlled Reset Output
In this mode a downstream port reset output state is controlled as a side effect of slot power being
turned on or off. The operation of this mode is illustrated in Figure 3.6. A downstream port’s slot power is
controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register
Figure 3.6 Power Enable Controlled Reset Output Mode Operation
While slot power is disabled, the corresponding downstream port reset output is asserted.
When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is
asserted and then power to the slot is enabled and the corresponding downstream port reset output is
negated. The time between the assertion of the PxPEP signal and the negation of the PxRSTN signal is
controlled by the value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.
While slot power is enabled, the corresponding downstream port reset output is negated.
When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset
output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.
Power Good Controlled Reset Output
As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is
controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on
the power good state of the slot’s power supply. The operation of this mode is illustrated in Figure 3.7.
Figure 3.7 Power Good Controlled Reset Output Mode Operation
The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that
when power is enabled, the negation of the corresponding port reset output occurs as a result of and after
assertion of the slot’s Power Good (PxPWRGDN) signal is observed. The time between the assertion of the
PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to
Reset Negation (PWR2RST) field in the HPCFGCTL register.
When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset
output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.
If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is
detected (i.e., PxPWRGDN is negated), then the corresponding port reset output is immediately asserted.
PES34H16 User Manual 3 - 9 October 30, 2008
Page 50
IDT Clocking, Reset, and Initialization Clock Operation
Notes
Since the PxPWRGDN signal is an I/O expander i nput, it may not be possibl e to meet a profile’s power
level invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a
shorter time interval may implement this functionality external to the PES34H16.
PES34H16 User Manual 3 - 10 October 30, 2008
Page 51
Notes
Chapter 4
Link Operation
Introduction
The PES34H16 contains six x4 ports which may be merged in pairs to form up to three x8 ports. The
remaining 10 ports are x1. The default link width for ports zero through five is x4 and the SerDes lanes are
statically assigned to a port.
Polarity Inversion
Each port of the PES34H16 supports automatic polarity inversion as required by the PCIe specification.
Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its data.
During link training, the receiver examines symbols six through 16 of the TS1 and TS2 ordered sets for
inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receiving lane
automatically inverts received data. Polarity inversion is a lane and not a link function. Therefore, it is
possible for some lanes of link to be inverted and for others to not be inverted.
Link Width Negotiation
The PES34H16 supports the optional link variable width negotiation feature outlined in the PCIe specification. During link training, Each merged x8 port is capable of negotiating to a x8, x4, x2 or x1 link width and
each unmerged x4 port is capable of negotiating to a x4, x2 or x1 link width.
The negotiated width of each link may be determined from the Link Width (LW) field in the corresponding
port’s PCI Express Link Status (PCIELSTS) register. The Maximum Link Width (MAXLNKWDTH) field in a
port’s PCI Express Link Capabilities (PCIELCAP) register contains the maximum link width of the port. This
field is of RWL type and may be modified when the REGUNLOCK bit is set in the SWCTL register. Modification of this field allows the maximum link width of the port to be configured. The new l ink width takes effect
the next time link training occurs.
The initial value of the MAXLNKWDTH field defaults to x4 mode. To force a link width to a smaller width
than the default value, the MAXLNKWDTH field could be configured through Serial EEPROM initialization
and full link retraining forced. When merged port link negotiates to a width less than x8, then the unused
group of four lanes are powered down to save power. In addition, unused S erDes in a four lane group are
put in a low power state (i.e. L1 state).
When an unmerged port negotiates to a width less than x4, the unused SerDes lanes are put in a low
power state (i.e., L1 state). When a merged or unmerged port is disabled, all SerDes lanes associated with
that port are powered down.
Lane Reversal
The PCIe specification describes an optional lane reversal feature. The PES34H16 supports the automatic lane reversal feature outlined in the PCIe specification. The operation of lane reversal is dependant
on the maximum link width selected by the MAXLNKWDTH field. Lane reversal mapping for the various
non-trivial x4 non-merged port maximum link width configurations supported by the PES34H16 are illustrated in Figures 4.1 and 4.2. Lane reversal mapping for the various non-trivial x8 merged port maximum
link width configurations supported by the PES34H16 are illustrated in Figures 4.3 through 4.5.
PES34H16 User Manual 4 - 1 October 30, 2008
Page 52
IDT Link Operation
Notes
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 0
lane 1
lane 2
lane 3
(a) x4 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 3
lane 2
lane 1
lane 0
(b) x4 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 0
lane 1
(a) x2 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 1
lane 0
(b) x2 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 0
(a) x1 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 0
(b) x1 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 0
lane 1
(a) x2 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 1
lane 0
(b) x2 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 0
(c) x1 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES34H16
lane 0
(d) x1 Port with lane reversal
Figure 4.1 Unmerged Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[5:0]=0x4)
Figure 4.2 Unmerged Port Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[5:0]=0x2)
PES34H16 User Manual 4 - 2 October 30, 2008
Page 53
IDT Link Operation
Notes
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
lane 1
(a) x2 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 1
lane 0
(b) x2 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
(c) x1 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
(d) x1 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
lane 1
lane 2
lane 3
(a) x4 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 3
lane 2
lane 1
lane 0
(b) x4 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
lane 1
(c) x2 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 1
lane 0
(d) x2 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
(e) x1 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
(f) x1 Port with lane reversal
Figure 4.3 Merged Port Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[5:0]=0x2)
PES34H16 User Manual 4 - 3 October 30, 2008
Figure 4.4 Merged Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[5:0]=0x4)
Page 54
IDT Link Operation
Notes
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
lane 1
lane 2
lane 3
lane 4
lane 5
lane 6
lane 7
(a) x8 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 7
lane 6
lane 5
lane 4
lane 3
lane 2
lane 1
lane 0
(b) x8 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
lane 1
lane 2
lane 3
(c) x4 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 3
lane 2
lane 1
lane 0
(d) x4 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
lane 1
(e) x2 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 1
lane 0
(f) x2 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
(g) x1 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES34H16
lane 0
(h) x1 Port with lane reversal
PES34H16 User Manual 4 - 4 October 30, 2008
Figure 4.5 Merged Port Lane Reversal for Maximum Link Width of x8 (MAXLNKWDTH[5:0]=0x8)
Link Retraining
Link retraining should not cause either a downstream component or an upstream component to reset or
revert to default values. Writing a one to the Link Retrain (LRET) bit in the upstream port’s PCI Express Link
Control (PCIELCTL) register when the REGUNLOCK bit is set in the SYSCTL register forces the upstream
PCIe link to retrain. When this occurs the LTSSM transitions directly to the Recovery state.
Writing a
one to the Link Retrain (LRET) bit in a downstream port’s PCI Express Link Control (PCIELCTL) register
regardless of the REGUNLOCK bit state in the SYSCTL register forces the downstream PCIe link to retrain.
When this occurs the LTSSM transitions directly to the Recovery state.
Page 55
IDT Link Operation
Notes
Link Down
When a link goes down, all TLPs received by that port and queued in the switch are discarded and all
TLPs received by other ports and destined to the port whose link is down are treated as Unsupported
Requests (UR). While a downstream link is down, it is possible to perform configuration read and write
operations to the PCI-PCI bridge associated with that link. When a link comes up, flow control credits for the
configured size of the input buffer queues are advertised.
Slot Power Limit Support
The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream
switch port or root port to the upstream port of a connected device or switch.
Upstream Port
When a Set_Slot_Power_Limit message is received by the upstream switch port, then the fields in the
message are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.
– Byte 0 bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale
(CSPLS) field.
– Byte 1 bits 1:0 of the message payload are written to the Captured Slot Power Limit Value
(CSPLV) field.
Downstream Port
A Set_Slot_Power_Limit message is sent by downstream switch ports when either of the following
events occur.
– A configuration write is performed to the corresponding PCIESCAP register when the link associ-
ated with the downstream port is up.
– A link associated with the downstream port transitions from a non-operational state to an opera-
tional (i.e., up) state.
Link States
The PES34H16 supports the following link states
– L0
• Fully operational link state
– L0s
• Automatically entered low power state with shortest exit latency
– L1
• Lower power state than L0s
• May be automatically entered or directed by software by placing the device in the D3
– L2/L3 Ready
• The L2/L3 state is entered after the acknowledgement of a PM_Turn_Off Message.
• There is no TLP or DLLP communications over a link in this state.
– L3
• Link is completely unpowered and off
hot
state
PES34H16 User Manual 4 - 5 October 30, 2008
Page 56
IDT Link Operation
Notes
L0
L0s L1
L2/L3 Ready
L3
Figure 4.6 PES34H16 ASPM Link Sate Transitions
Active State Power Management
The operation of Active State Power Management (ASPM) is orthogonal to power management. Once
enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transitions are initiated by hardware without software involvement. The PES34H16 ASPM supports the required
L0s state as well as the optional L1 state.
The L0s Entry Timer (L0ET) field in the PCI Power Management Proprietary Control (PMPC) register
controls the amount of time L0s entry conditions must be met before the hardware transitions the link to the
L0s state. The L1 Entry Timer (L1ET) field in the PCI Power Management Proprietary Control (PMPC)
register controls the amount of time L1 entry conditions must be met before the hardware transitions the link
to the L1 state. If these conditions are met and the link is in the L0 or L0s states, then the hardware will
request a transition to the L1 state from its link partner. Note that L1 entry requests are only made by the
PES34H16 upstream port. If the link partner acknowledges the transition, then the L1 state is entered.
Otherwise the L0s state is entered.
Link Status
Associated with each port is a Port Link Up (PxLINK UPN) status output and a Port Activity (PxACTIVEN) status output. These outputs are provided on I/O expander tbd. See section I/O Expanders on page
6-6 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins. The
PxLINKUPN and PxACTIVEN status outputs may be used to provide a visual indication of system state and
activity or for debug.
The PxLINKUPN output is asserted when the PCI Express data link layer is up (i.e., when the LTSSM is
in the L0, L0s, L1 or recovery states). When the data link layer is down, this output is negated.
The PxACTIVEN output is asserted whenever any TLP, other than a vendor defined message, is transmitted or received on the corresponding port’s link. Whenever a PxACTIVEN output is asserted, it remains
asserted for at least 200 ms. Since an I/O expander output may change no more frequently than once every
PES34H16 User Manual 4 - 6 October 30, 2008
40 ms, this translates into five I/O expander update periods.
Page 57
Notes
®
Chapter 5
General Purpose I/O
Introduction
The PES34H16 has 32 General Purpose I/O (GPIO) pins that may be individually configured as: general
purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General
Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose
I/O Data (GPIOD) registers in the upstream port’s PCI configuration space. As shown in Table 5.1, many
GPIO pins are shared with other on-chip functions. The GPIO Function (GPIOFUNC) register whether a
GPIO bit operates as a general purpose I/O or as the specified alternate function.
GPIO
Pin
10 P5RSTN Reset output for downstream port 5 Output
11 P6RSTN Reset output for downstream port 6 Output
12 P7RSTN Reset output for downstream port 7 Output
13 P8RSTN Reset output for downstream port 8 Output
14 P9RSTN Reset output for downstream port 9 Output
15 P10RSTN Reset output for downstream port 10 Output
16 P11RSTN Reset output for downstream port 11 Output
17 P12RSTN Reset output for downstream port 12 Output
18 P13RSTN Reset output for downstream port 13 Output
19 P14RSTN Reset output for downstream port 14 Output
Alternate
Function
Pin Name
5 GPEN General purpose event output Output
6 P1RSTN Reset output for downstream port 1 Output
7 P2RSTN Reset output for downstream port 2 Output
8 P3RSTN Reset output for downstream port 3 Output
9 P4RSTN Reset output for downstream port 4 Output
Alternate Function Description
Alternate
Function
Pin Type
20 P15RSTN Reset output for downstream port 15 Output
21 IOEXPINTN0 SMBus I/O expander interrupt 0 Input
22 IOEXPINTN1 SMBus I/O expander interrupt 1 Input
23 IOEXPINTN2 SMBus I/O expander interrupt 2 Input
24 IOEXPINTN3 SMBus I/O expander interrupt 3 Input
25 IOEXPINTN4 SMBus I/O expander interrupt 4 Input
26 IOEXPINTN5 SMBus I/O expander interrupt 5 Input
Table 5.1 General Purpose I/O Pin Alternate Function (Part 1 of 2)
PES34H16 User Manual 5 - 1 October 30, 2008
Page 58
IDT General Purpose I/O
Notes
GPIO
Pin
27 IOEXPINTN6 SMBus I/O expander interrupt 6 Input
28 IOEXPINTN7 SMBus I/O expander interrupt 7 Input
31 IOEXPINTN10 SMBus I/O expander interrupt 10 Input
Alternate
Function
Pin Name
Table 5.1 General Purpose I/O Pin Alternate Function (Part 2 of 2)
Alternate Function Description
Alternate
Function
Pin Type
After reset, all GPIO pins default to the GPIO input function. GPIO pins configured as GPIO inputs are
sampled no more frequently than once every 128ns and may be treated as asynchronous inputs. When a
GPIO pin is configured to use the GPIO function, the unneeded alternate function associated with the pin is
held in an inactive state by internal logic. Care should be exercised when configuring the GPIO pins as
outputs since an incorrect configuration could cause damage to external components as well as the
PES34H16.
GPIO Configuration
Associated with each GPIO pin is a bit in the GPIOFUNC, GPIOCFG and GPIOD registers. Table 5.2
summarizes the configuration of GPIO pins.
GPIOFUNC GPIOCFG Pin Function
0 0 GPIO input
0 1 GPIO output
1 don’t care Alternate function
Table 5.2 GPIO Pin Configuration
GPIO Pin Config ured as an Inpu t
When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC
register, the GPIO pin is sampled and registered in the GPIOD register. The value of the input pin can be
determined at any time by reading the GPIOD register. Note that the value in this register corresponds to
the value of the pin irrespective of whether the pin is configured as a GPIO input, GPIO output or alternate
function.
GPIO Pin Configured as an Output
When configured as an output in the GPIOCFG register and as a GPIO function in the GPIOFUNC
register, the value in the corresponding bit position of the GPIOD register is driven on the pin. System
designers should treat the GPIO outputs as asynchronous outputs. The actual value of the output pin can
be determined by reading the GPIOD register.
GPIO Pin Configured as an Alternat e Function
When configured as an alternate function in the GPIOFUNC register, the pin behaves as described by
the section associated with that function. The value of the alternate function pin can be determined at any
time by reading the GPIOD register.
PES34H16 User Manual 5 - 2 October 30, 2008
Page 59
Notes
®
Chapter 6
Processor
PES34H16
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES34H16
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
...
(a) Unified Configuration
(b) Split Configuration
Hot-Plug
I/O
Expander
Hot-Plug
I/O
Expander
SMBus Interfaces
Introduction
The PES34H16 contains two SMBus interfaces. The slave SMBus interface provides full access to all
software visible registers in the PES34H16, allowing every register in the device to be read or written by an
external SMBus master. The slave SMBus may also be used to initialize the serial EEPROM used for initialization.
The Master SMBus interface provides connection for an optional external serial EEPROM used for
initialization and optional external I/O expanders. Six pins make up each of the two SMBus interfaces.
These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. As shown in
Figure 6.1, the master and slave SMBuses may be used in a unified or split configuration.
Figure 6.1 SMBus Interface Configuration Examples
In the unified configuration, shown in Figure 6.1(a), the master and slave SMBuses are tied together and
PES34H16 User Manual 6 - 1 October 30, 2008
the PES34H16 acts both as an SMBus master as well as an SMBus slave on this bus. This requires that the
external SMBus master or processor that has access to the PES34H16 registers support SMBus arbitration. In some systems, this external SMBus master interface may be implemented using general purpose I/
O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these
systems, the PES34H16 may be configured to operate in a split configuration as shown in Figure 6.1(b).
Page 60
IDT SMBus Interfaces
Notes
In the split configuration, the master and slave SMBuses operate as two independent buses and thus
multi-master arbitration is not required.
Master SMBus Interface
The master SMBus interface is used during a fundamental reset to load configuration values from an
optional serial EEPROM. It is also used to support optional I/O expanders used for hot-plug and other
status signals.
Initialization
Master SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
3-5).
During a fundamental reset initialization sequence, the state of the Master SMBus Slow Mode (MSMBSMODE) signal is examined. If this signal is asserted, then the Master SMBus Clock Prescalar (MSMBCP)
field in the SMBus Control (SMBUSCTL) register is initialized to support 100 KHz SMBus operation. If the
signal is negated, then the MSMBCP field is initialized for 400 KHz SMBus operation.
Serial EEPROM
During a fundamental or hot reset, an optional serial EEPROM may be used to initialize any software
visible register in the device. Serial EEPROM loading occurs if the Switch Mode (SWMODE[3:0]) field
selects an operating mode that performs serial EEPROM initialization. The address used by the SMBus
interface to access the serial EEPROM is specified by the MSMBADDR[4:1] signals as shown in Table 6.1.
Address
Bit
1 MSMBADDR[1]
2 MSMBADDR[2]
3 MSMBADDR[3]
4 MSMBADDR[4]
51
60
71
Table 6.1 Serial EEPROM SMBus Address
Address Bit Value
Device Initialization from a Serial EEPROM
During initialization from the optional serial EEPROM, the master SMBus interface reads configuration
blocks from the serial EEPROM and updates corresponding registers in the PES34H16. Any PES34H16
software visible register in any port may be initialized with values stored in the serial EEPROM.
Each software visible register in the PES34H16 has a CSR sys tem address which is formed by adding
the PCI configuration space offset value of the register to the base address of the configuration space in
which the register is located. Configuration blocks stored in the serial EEPROM use this CSR system
address shifted right two bits (i.e., configuration blocks in the serial EEPROM use doubleword CSR system
addresses and not byte CSR system addresses).
Base addresses for the PCI configuration spaces in the PES34H16 are listed in Table 9.1. Since configuration blocks are used to store only the value of those registers that are initialized, a serial EEPROM much
smaller than the total size of all of the configuration spaces may be used to initialize the device.
PES34H16 User Manual 6 - 2 October 30, 2008
Page 61
IDT SMBus Interfaces
Notes
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Byte 0 CSR_SYSADDR[7:0]
CSR_SYSADDR[13:8]
TYPE
0x0
Byte 1
Byte 2 DATA[ 7:0]
Byte 3 DATA[15:8]
Byte 4 DATA[23:16]
Byte 5 DATA[31:24]
Any serial EEPROM compatible with those listed in Table 6.2 may be used to store the PES34H16
initialization values. Some of these devices are larger than the total size of all of the PCI configuration
spaces in the PES34H16 that may be initialized and thus may not be fully utilized.
Serial EEPROM Size
24C32 4 KB
24C64 8 KB
24C128 16 KB
24C256 32 KB
24C512 64 KB
Table 6.2 PES34H16 Compatible Serial EEPROMs
During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial
EEPROM address zero. These bytes are interpreted as configuration blocks and sequential reading of the
serial EEPROM continues until the end of a configuration done block is reached or the serial EEPROM
address rolls over from 0xFFFF to 0x0.
All register initialization performed by the serial EEPROM is performed in double word quantities. There
are three configuration block types that may be stored in the serial EEPROM. The first type is a single
double word initialization sequence. A double word initialization sequence occupies six bytes in the serial
EEPROM and is used to initialize a single double word quantity in the PES34H16.
A single double word initialization sequence consists of three fields and its format is shown in Figure 6.1.
The CSR_SYSADDR field contains the double word C SR system address of the double word to be initialized. The actual CSR system address, which is a by te address, equals this value w ith two lower zero bits
appended. The next field is the TYPE field that indicates the type of the configuration block. For single
double word initialization sequence, this value is always 0x0. The final DATA field contains the double word
initialization value.
Figure 6.1 Single Double Word Initialization Sequence Format
The second type of configuration block is the sequential double word initialization sequence. It is similar
to a single double word initialization sequence except that it contains a double word count that allows
multiple sequential double words to be initialized in one configuration block.
A sequential double word initialization sequence consists of four required fields and one to 65535
PES34H16 User Manual 6 - 3 October 30, 2008
shown in Figure 6.2. The CSR_SYSADDR field contains the starting double word CSR system address to
be initialized. The next field is the TYPE field that indicates the type of the configuration block. For sequential double word initialization sequences, this value is always 0x1. The NUMDW field specifies the number
of double words initialized by the configuration block. This is followed by the number of DATA fields specified in the NUMDW field.
double word initialization data fields. The format of a sequential double word initialization sequence is
Page 62
IDT SMBus Interfaces
Notes
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Byte 0 CSR_SYSADDR[7:0]
CSR_SYSADDR[13:8]
TYPE
0x1
Byte 1
Byte 2 NUMDW[7:0]
Byte 3 NUMDW[15:8]
Byte 4 DATA0[7:0]
Byte 5 DATA0[15:8]
Byte 6 DATA0[23:16]
Byte 7 DATA0[31:24]
Byte 4n+4 DATAn[7:0]
Byte 4n+ 5 DATAn[15:8]
Byte 4n+6 DATAn[23:16]
Byte 4n+7 DATAn[31:24]
...
...
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Byte 0 CHECKSUM[7:0]
ReservedTYPE
0x3
Byte 1
(must be zero)
PES34H16 User Manual 6 - 4 October 30, 2008
Figure 6.2 Sequential Double Word Initialization Sequence Format
The final type of configuration block is the configuration done sequence w hich is used to signify the end
of a serial EEPROM initialization sequence.
If during serial EEPROM initialization, an attempt is made to initialize a register that is not defined in a
configuration space (i.e., not defined in Chapter 9), then the Unmapped Register Initialization Attempt
(URIA) bit is set in the SMBUSSTS register and the write is ignored.
The configuration done sequence consists of two fields and its format is shown in Figure 6.3. The
CHECKSUM field contains the checksum of all of the bytes in all of the fields read from the serial EEPROM
from the first configuration block to the end of this done sequence. The second field is the TYPE field which
is always 0x3 for configuration done sequences.
Figure 6.3 Configuration Done Sequence Format
The checksum in the configuration done sequence enables the integrity of the serial EEPROM initialization to be verified. Since uninitialized EEPROMs typically have a value of all ones, initialization from an
uninitialized serial EEPROM will result in a checksum mismatch.
The checksum is computed in the following manner. An 8-bit counter is initialized to zero and the 8-bit
sum is computed over the configuration bytes stored in the serial EEPROM, including the entire contents of
the configuration done sequence, with the checksum field initialized to zero.
1.
This includes the byte containing the TYPE field.
1
The 1’s complement of this
Page 63
IDT SMBus Interfaces
Notes
sum is placed in the checksum field. The checksum is verified in the following manner. An 8-bit counter is
cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire
contents of the configuration done sequence.
1
The correct result should always be 0xFF (i.e., all ones).
Checksum checking may be disabled by setting the Ignore Checksum Errors (ICHEC KSUM) bit in the
SMBus Control (SMBUSCTL) register. If an error is detected during loading of the serial EEPROM, then
loading of the serial EEPROM is aborted and the RSTHALT bit is set in the SWCTL register. This allows
debugging of the error condition via the slave SMBus interface but prevents normal system operation with a
potentially incorrectly initialized device. Error information is recorded in the SMBUSSTS register.
Once serial EEPROM initialization completes, or when an error is detected, the EEPROM Done
(EEPROMDONE) bit is set in the SMBus S tatus (SMBSTS) register. A summary of possible errors during
serial EEPROM initialization and specific action taken when detected is summarized in Figure 6.4.
Error Action Taken
Configuration Done Sequence checksum mismatch with that computed by the PES34H16
Invalid configuration block type
(only invalid type is 0x2)
An unexpected NACK is observed during a
master SMBus transaction
Master SMBus interface loses 16 consecutive
arbitration attempts
A misplaced START or STOP condition is
detected by the master SMBus interface
Figure 6.4 Serial EEPROM Initialization Errors
- Set RSTHALT bit in SWCTL register
- ICSERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
- Set RSTHALT bit in SWCTL register
- ICSERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
- Set RSTHALT bit in SWCTL register
- NAERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
- Set RSTHALT bit in SWCTL register
- LAERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
- Set RSTHALT bit in SWCTL register
- OTHERERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
Programming the Serial EEPROM
The serial EEPROM may be programmed prior to board assembly or in-system via the slave SMBus
interface or a PCIe root. Programming the serial EEPROM via the slave SMBus is described in section
Serial EEPROM Read or Write Operation on page 6-20. A PCIe root may read and write the serial
EEPROM by performing configuration read and write transactions to the Serial EEPROM Interface
(EEPROMINTF) register.
To read a byte from the serial EEPROM, the root should configure the Address (ADDR) field in the
EEPROMINTF register with the byte address of the serial EEPROM location to be read and the Operation
(OP) field to “read.” The Busy (BUSY) bit should then be checked. If the EEPROM is not busy, then the read
operation may be initiated by performing a write to the Data (DATA) field. When the serial EEPROM read
operation completes, the Done (DONE) bit in the EEPROMINTF register is set and the busy bit is cleared.
When this occurs, the DATA field contains the byte data of the value read from the serial EEPROM.
To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of
the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy
(i.e., the BUSY bit is cleared), then the write operation may be initiated by writing the val ue to be w ritten to
the DATA field. When the write operation completes, the DONE bit is set and the busy bit is cleared. Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results.
1.
This includes the checksum byte as well as the byte that contains the type and reserved field.
PES34H16 User Manual 6 - 5 October 30, 2008
Page 64
IDT SMBus Interfaces
Notes
SMBus errors may occur when accessing the serial EEPROM. If an error occurs, then it is reported in
the SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial
EEPROM access.
I/O Expanders
The PES34H16 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus interface for hot-plug and port status signals.
The PES34H16 is designed to work with Phillips PCA9555 compatible I/O expanders (i.e., PCA9555,
PCA9535, and PCA9539). See the Phillips PCA9555 data sheet for details on the operation of this device.
An external SMBus I/O expander provides 16 bit I/O pins that may be configured as inputs or outputs.
PES34H16 supports up to 11 external I/O expanders. Figure 6.5 summarizes the allocation of functions
to I/O expanders. I/O expanders zero through seven are used to provide general hot-plug I/O signals. I/O
expander eight provides link status outputs while I/O expander nine provides link activity LED status
outputs. I/O expander ten provides hot-plug power good status inputs.
I/O expander signals associated with LED control (i.e., link status and activity) are active low (i.e., driven
low when an LED should be turned on).
I/O expander signals associated with hot-plug signals are not inverted.
SMBus I/O
Expander
0 Lower Port 1 hot-plug
1 Lower Port 2 hot-plug
2 Lower Port 5 hot-plug
3 Lower Port 6 hot-plug
4 Lower Port 9 hot-plug
5 Lower Port 10 hot-plug
6 Lower Port 13 hot-plug
7 Lower Port 14 hot-plug
8 Lower Link status (ports 0 through 7)
Section Function
Upper Port 3 hot-plug
Upper Port 4 hot-plug
Upper Port 7 hot-plug
Upper Port 8 hot-plug
Upper Port 11 hot-plug
Upper Port 12 hot-plug
Upper Port 15 hot-plug
Upper reserved
Upper Link status (ports 8 through 15)
Figure 6.5 I/O Expander Function Allocation (Part 1 of 2)
PES34H16 User Manual 6 - 6 October 30, 2008
Page 65
IDT SMBus Interfaces
Notes
SMBus I/O
Expander
9 Lower Link activity (ports 0 through 7)
10 Lower Power good inputs (ports 0 through 7)
Figure 6.5 I/O Expander Function Allocation (Part 2 of 2)
Section Function
Upper Link activity (ports 8 through 15)
Upper Power good inputs (ports 8 through 15)
During the PES34H16 initialization, the SMBus/I2C-bus address allocated each I/O expander used in
that system configuration should be written to the corresponding IO Expander Address (IOE[0:10]ADDR)
field. The IOE[0:3]ADDR fields are contained in the I/O Expander Address 0 (IOEXPADDR0) register, the
IOE[4:7]ADDR fields are contained in the SMBus I/O Expander Address 1 (IOEXPADDR1) register , and the
IOE[8:10]ADDR fields are contained in the SMBus I/O Expander Address 2 (IOEXPADDR2) register.
Hot-plug outputs and I/O expanders may be initialized via serial EEPROM. Since the I/O expanders and
serial EEPROM both utilize the master SMBus, no I/O expander transactions are initiated until serial
EEPROM initialization completes.
– Since no I/O expander transactions are initiated until serial EEPROM initialization completes, it is
not possible to toggle a hot-plug output through serial EEPROM initialization (i.e., it is not possible
to cause a 0 -> 1 -> 0 transition or a 1 -> 0 -> 1 transition).
Whenever the value of an IOEXPADDR field is written, SMBus write transactions are issued to the
corresponding I/O expander by the PES34H16 to configure the device. This configuration initializes the
direction of each I/O expander signal and sets outputs to their default value.
Outputs for ports that are disabled or are not implemented in that configuration or bo nd option, are set to
their negated value (e.g., the power indicator is turned off, the link is down, there is no activity, etc.).
The default value of I/O expander outputs is shown in Figure 6.6. Note that this default value may be
modified via serial EEPROM or SMBus configuration prior to SMBus initialization by changing the state of
the PCI Express Slot Control Register (PCIESCTL) or Hot-Plug Configuration Control (HPCFGCTL).
SMBus I/O
Expander
Bit
(I/O-x.4) P2AIN Attention indicator output (off) 1
(I/O-x.5) P2PIN Power indicator output (on) 0
(I/O-x.6) P2PEP Power enable output (on) 1
(I/O-x.7) P2ILOCKP Electromechanical interlock (negated - off) 0
Signal Description
Figure 6.6 I/O Expander Default Output Signal Value
Default
Value
PES34H16 User Manual 6 - 7 October 30, 2008
Page 66
IDT SMBus Interfaces
Notes
The following I/O expander configuration sequence is issued by the PES34H16 to I/O expanders zero
through seven (i.e., the ones that contain hot-plug signals).
– Write the default value of the outputs bits on the lower eight I/O expander pins (i.e., I/O-0.0 through
I/O-0.7) to I/O expander register 2.
– Write the default value of the outputs bits on the upper eight I/O expander pins (i.e., I/O-1.0
through I/O-1.7) to I/O expander register 3.
– write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– write value 0x0 to I/O expander register 5 (no inversion in IO-1)
– Write the configuration value to select inputs/outputs in the lower eight I/O expander bits (i.e., I/O-
0.0 through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select inputs/outputs in the upper eight I/O expander bits (i.e., I/
O-1.0 through I/O-1.7) to I/O expander register 7.
– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander
bits (i.e., I/O-0.0 through I/O-0.7)
– Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander
bits (i.e., I/O-1.0 through I/O-1.7)
The following I/O expander configuration sequence is issued by the PES34H16 to I/O expanders eight
and nine (i.e., the one that contains link up and link activity status).
– Write link up or activity status for ports 0 through 7 to the lower eight I/O expander pins (i.e., I/O-
0.0 through I/O-0.7) to I/O expander register 2.
– Write link up or activity status for ports 8 through 15 to the upper eight I/O expander pins (i.e., I/
O-1.0 through I/O-1.7) to I/O expander register 3.
– Write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– Write value 0x0 to I/O expander register 5 (no inversion in IO-1)
– Write the configuration value to select all outputs in the lower eight I/O expander bits (i.e., I/O-0.0
through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select all outputs in the upper eight I/O expander bits (i.e., I/O-1.0
through I/O-1.7) to I/O expander register 7.
The following I/O expander configuration sequence is issued by the PES34H16 to I/O expander ten (i.e.,
the one that contains power good inputs).
– Write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– Write value 0x0 to I/O expander register 5 (no inversion in IO-1)
– Write the configuration value to select all inputs in the lower eight I/O ex pander bits (i.e., I/O-0.0
through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select all inputs in the upper eight I/O expander bits (i.e., I/O-1.0
through I/O-1.7) to I/O expander register 7.
– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander
bits (i.e., I/O-0.0 through I/O-0.7)
– Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander
bits (i.e., I/O-1.0 through I/O-1.7)
While the I/O expander is enabled, the PES34H16 maintains the I/O bus expander signals and the
PES34H16 internal view of the hot-plug signals in a consistent state. This means that whenever that I/O
bus expander state and the PES34H16 internal view of the signal state differs, an SMBus transaction is
initiated by the PES34H16 to resolve the state conflict.
– An example of an event that may lead to a state conflict is a hot reset. When a hot reset occurs,
one or more hot-plug register control fields may be re-initialized to its default value. When this
occurs, the internal PES34H16 state of the hot-plug signals is in conflict with the state of I/O
expander hot-plug output signals. In such a situation, the PES34H16 will initiate an SMBus transaction to modify the state of the I/O expander hot-plug outputs.
PES34H16 User Manual 6 - 8 October 30, 2008
Page 67
IDT SMBus Interfaces
Notes
Each I/O expander has an open drain interrupt output that is asserted when a pin configured as an input
changes state from the value previously read. Each interrupt output from an I/O expander should be
connected to the corresponding PES34H16 I/O expander interrupt input. Since the PES34H16 I/O
expander interrupt inputs are GPIO alternate functions, the corresponding GPIOs should be initialized
during configuration to operate in alternate function mode. See Chapter 5, General Purpose I/O.
Whenever the PES34H16 needs to change the state of an I/O expander signal output, a master SMBus
transaction is initiated to update the state of the I/O expander. This write operation causes the corresponding I/O expander to change the state of its output(s). The PES34H16 will not update the state of an I/
O expander output more frequently than once every 40 milliseconds. This 40 millisecond time interval is
referred to as the I/O expander update period.
Whenever an input to the I/O expander changes state from the value previously read, the interrupt
output of the I/O expander is asserted. This causes the PES34H16 to issue a master SMBus transaction to
read the updated state of the I/O expander inputs. Regardless of the state of the interrupt output of the I/O
expander, the PES34H16 will not issue a master SMBus transaction to read the updated state of the I/O
expander inputs more frequently than once every 40 milliseconds (i.e., the I/O expander update period).
This delay in sampling may be used to eliminate external debounce circuitry.
The I/O expander interrupt request output is negated whenever the input values are read or w hen the
input pin changes state back to the value previously read. The PES34H16 ensures that I/O expander transactions are initiated on the master SMBus in a fair manner. This guarantees that all I/O expanders have
equal service latencies. Any errors detected during I/O expander SMBus read or write transactions is
reflected in the status bits of the SMBus Status (SMBUSSTS) register.
The I/O Expander Interface (IOEXPINTF) register allows direct testing and debugging of the I/O
expander functionality. The Select (SEL) field in the IOEXPINTF register selects the I/O expander number
on which other fields in the register operate. The I/O Expander Data field in the IOEXPINTF register reflect
the current state, as viewed by the PES34H16, of the I/O expander inputs and outputs selected by the SEL
field.
Writing a one to the Reload I/O Expander Signals (RELOADIOEX) bit in the IOEXPINTF register causes
the PES34H16 to generate SMBus write and read transactions to the I/O expander number selected in the
SEL field. This results in the value of the IOEDATA field being updated to reflect the current state of the
corresponding I/O expander signals. This feature may be used to aid in debugging I/O expander operation.
For example, a user who neglects to configure a GPIO as an alternate function may use this feature to
determine that master SMBus transactions to the I/O expander function properly and that the issue is with
the interrupt logic.
The IO Expander Test Mode (IOEXTM) bit in the IOEXPTINF register allows an I/O expander test mode
to be entered. When this bit is set, the PES34H16 core logic outputs are ignored and the values written to
the I/O expander for output bits are the values in the IOEDATA field. In this mode, the PES34H16 issues a
transaction to update the state of the I/O expander whenever a bit corresponding to an I/O expander output
changes state due to a write to the IOEDATA field and the RELOADIOEX bit is set. Bits in the IOEDATA
field that correspond to outputs are dependent on the I/O expander number selected in the SEL field in the
IOEXPINTF register. The outputs for each I/O expander number are shown in Table 6.3 through 6.13.
PES34H16 User Manual 6 - 9 October 30, 2008
Page 68
IDT SMBus Interfaces
Notes
System design recommendations
– I/O expander addresses and default output values may be configured during serial EEPROM
initialization. If I/O expander addresses are configured via the serial EEPROM, then the
PES34H16 will initialize the I/O expanders when normal device operation begins following the
completion of the fundamental reset sequence.
– If the I/O expanders are initialized via serial EEPROM, then the data value for output signals
during the SMBus initialization sequence will correspond to those at the time the SMBus transactions are initiated. It is not possible to toggle SMBus I/O expander outputs by modifying data
values during serial EEPROM initialization.
– During a fundamental reset and before the I/O expander outputs are initialized, all I/O expander
output signals default to inputs. Therefore, pull-up or pull-down resistors should be placed on
outputs to ensure that they are held in the desired state during this period.
– All hot-plug data value modifications that correspond to hot-plug outputs result in SMBus transac-
tions. This includes modifications due to upstream secondary bus resets and hot-resets.
– The standard PCA9555 I/O expander is not able to support the number of unique addresses
required by all of the PES34H16 hot-plug I/O expanders. Therefore, it is recommended that a
MAX7313 be used instead. The MAX7313 is software and pin compatible with the PCA9555
– I/O expander outputs are not modified when the device transitions from normal operation to a
fundamental reset. In systems where I/O expander output values must be reset during a fundamental reset, an I/O expander reset circuit may be used to reset the I/O expanders. Contact IDT
for more information.
I/O Expander 0
SMBus I/O
Expander
Bit
0 (I/O-0.0)
1 (I/O-0.1) I P1PDN Port 1 presence detect input
2 (I/O-0.2) I P1PFN Port 1 power fault input
3 (I/O-0.3) I P1MRLN Port 1 manually-operated retention latch (MRL)
4 (I/O-0.4) O P1AIN Port 1 attention indicator output
5 (I/O-0.5) O P1PIN Port 1 power indicator output
6 (I/O-0.6) O P1PEP Port 1 power enable output
7 (I/O-0.7) O P1ILOCKP Port 1 electromechanical interlock
8 (I/O-1.0) I P3APN Port 3 attention push button input
9 (I/O-1.1) I P3PDN Port 3 presence detect input
10 (I/O-1.2) I P3PFN Port 3 power fault input
11 (I/O-1.3) I P3MRLN Port 3 manually-operated retention latch (MRL)
12 (I/O-1.4) O P3AIN Port 3 attention indicator output
13 (I/O-1.5) O P3PIN Port 3 power indicator output
14 (I/O-1.6) O P3PEP Port 3 power enable output
1
Type Signal Description
I P1APN Port 1 attention push button input
input
input
15 (I/O-1.7) O P3ILOCKP Port 3 electromechanical interlock
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
PES34H16 User Manual 6 - 10 October 30, 2008
Table 6.3 I/O Expander 0 Signals
Page 69
IDT SMBus Interfaces
Notes
I/O Expander 1
SMBus I/O
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) I P2PDN Port 2 presence detect input
2 (I/O-0.2) I P2PFN Port 2 power fault input
3 (I/O-0.3) I P2MRLN Port 2 manually-operated retention latch (MRL)
4 (I/O-0.4) O P2AIN Port 2 attention indicator output
5 (I/O-0.5) O P2PIN Port 2 power indicator output
6 (I/O-0.6) O P2PEP Port 2 power enable output
7 (I/O-0.7) O P2ILOCKP Port 2 electromechanical interlock
8 (I/O-1.0) I P4APN Port 4 attention push button input
9 (I/O-1.1) I P4PDN Port 4 presence detect input
10 (I/O-1.2) I P4PFN Port 4 power fault input
11 (I/O-1.3) I P4MRLN Port 4 manually-operated retention latch (MRL)
Type Signal Description
I P2APN Port 2 attention push button input
input
input
12 (I/O-1.4) O P4AIN Port 4 attention indicator output
13 (I/O-1.5) O P4PIN Port 4 power indicator output
14 (I/O-1.6) O P4PEP Port 4 power enable output
15 (I/O-1.7) O P4ILOCKP Port 4 electromechanical interlock
Table 6.4 I/O Expander 1 Signals
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
I/O Expander 2
SMBus I/O
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) I P5PDN Port 5 presence detect input
2 (I/O-0.2) I P5PFN Port 5 power fault input
3 (I/O-0.3) I P5MRLN Port 5 manually-operated retention latch (MRL)
4 (I/O-0.4) O P5AIN Port 5 attention indicator output
5 (I/O-0.5) O P5PIN Port 5 power indicator output
Type Signal Description
I P5APN Port 5 attention push button input
input
6 (I/O-0.6) O P5PEP Port 5 power enable output
7 (I/O-0.7) O P5ILOCKP Port 5 electromechanical interlock
Table 6.5 I/O Expander 2 Signals (Part 1 of 2)
PES34H16 User Manual 6 - 11 October 30, 2008
Page 70
IDT SMBus Interfaces
Notes
SMBus I/O
Expander
Type Signal Description
Bit
8 (I/O-1.0) I P7APN Port 7 attention push button input
9 (I/O-1.1) I P7PDN Port 7 presence detect input
10 (I/O-1.2) I P7PFN Port 7 power fault input
11 (I/O-1.3) I P7MRLN Port 7 manually-operated retention latch (MRL)
input
12 (I/O-1.4) O P7AIN Port 7 attention indicator output
13 (I/O-1.5) O P7PIN Port 7 power indicator output
14 (I/O-1.6) O P7PEP Port 7 power enable output
15 (I/O-1.7) O P7ILOCKP Port 7 electromechanical interlock
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
I/O Expander 3
SMBus I/O
Table 6.5 I/O Expander 2 Signals (Part 2 of 2)
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) I P6PDN Port 6 presence detect input
2 (I/O-0.2) I P6PFN Port 6 power fault input
3 (I/O-0.3) I P6MRLN Port 6 manually-operated retention latch (MRL)
4 (I/O-0.4) O P6AIN Port 6 attention indicator output
5 (I/O-0.5) O P6PIN Port 6 power indicator output
6 (I/O-0.6) O P6PEP Port 6 power enable output
7 (I/O-0.7) O P6ILOCKP Port 6 electromechanical interlock
8 (I/O-1.0) I P8APN Port 8 attention push button input
9 (I/O-1.1) I P8PDN Port 8 presence detect input
10 (I/O-1.2) I P8PFN Port 8 power fault input
Type Signal Description
I P6APN Port 6 attention push button input
input
11 (I/O-1.3) I P8MRLN Port 8 manually-operated retention latch (MRL)
input
12 (I/O-1.4) O P8AIN Port 8 attention indicator output
13 (I/O-1.5) O P8PIN Port 8 power indicator output
14 (I/O-1.6) O P8PEP Port 8 power enable output
15 (I/O-1.7) O P8ILOCKP Port 8 electromechanical interlock
Table 6.6 I/O Expander 3 Signals
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
PES34H16 User Manual 6 - 12 October 30, 2008
Page 71
IDT SMBus Interfaces
Notes
I/O Expander 4
SMBus I/O
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) I P9PDN Port 9 presence detect input
2 (I/O-0.2) I P9PFN Port 9 power fault input
3 (I/O-0.3) I P9MRLN Port 9 manually-operated retention latch (MRL)
4 (I/O-0.4) O P9AIN Port 9 attention indicator output
5 (I/O-0.5) O P9PIN Port 9 power indicator output
6 (I/O-0.6) O P9PEP Port 9 power enable output
7 (I/O-0.7) O P9ILOCKP Port 9 electromechanical interlock
8 (I/O-1.0) I P11APN Port 11 attention push button input
9 (I/O-1.1) I P11PDN Port 11 presence detect input
10 (I/O-1.2) I P11PFN Port 11 power fault input
11 (I/O-1.3) I P11MRLN Port 11 manually-operated retention latch (MRL)
Type Signal Description
I P9APN Port 9 attention push button input
input
input
12 (I/O-1.4) O P11AIN Port 11 attention indicator output
13 (I/O-1.5) O P11PIN Port 11 power indicator output
14 (I/O-1.6) O P11PEP Port 11 power enable output
15 (I/O-1.7) O P11ILOCKP Port 11 electromechanical interlock
Table 6.7 I/O Expander 4 Signals
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
I/O Expander 5
SMBus I/O
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) I P10PDN Port 10 presence detect input
2 (I/O-0.2) I P10PFN Port 10 power fault input
3 (I/O-0.3) I P10MRLN Port 10 manually-operated retention latch (MRL)
4 (I/O-0.4) O P10AIN Port 10 attention indicator output
5 (I/O-0.5) O P10PIN Port 10 power indicator output
Type Signal Description
I P10APN Port 10 attention push button input
input
6 (I/O-0.6) O P10PEP Port 10 power enable output
7 (I/O-0.7) O P10ILOCKP Port 10 electromechanical interlock
Table 6.8 I/O Expander 5 Signals (Part 1 of 2)
PES34H16 User Manual 6 - 13 October 30, 2008
Page 72
IDT SMBus Interfaces
Notes
SMBus I/O
Expander
Type Signal Description
Bit
8 (I/O-1.0) I P12APN Port 12 attention push button input
9 (I/O-1.1) I P12PDN Port 12 presence detect input
10 (I/O-1.2) I P12PFN Port 12 power fault input
11 (I/O-1.3) I P12MRLN Port 12 manually-operated retention latch (MRL)
input
12 (I/O-1.4) O P12AIN Port 12 attention indicator output
13 (I/O-1.5) O P12PIN Port 12 power indicator output
14 (I/O-1.6) O P12PEP Port 12 power enable output
15 (I/O-1.7) O P12ILOCKP Port 12 electromechanical interlock
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
I/O Expander 6
SMBus I/O
Table 6.8 I/O Expander 5 Signals (Part 2 of 2)
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) I P13PDN Port 13 presence detect input
2 (I/O-0.2) I P13PFN Port 13 power fault input
3 (I/O-0.3) I P13MRLN Port 13 manually-operated retention latch (MRL)
4 (I/O-0.4) O P13AIN Port 13 attention indicator output
5 (I/O-0.5) O P13PIN Port 13 power indicator output
6 (I/O-0.6) O P13PEP Port 13 power enable output
7 (I/O-0.7) O P13ILOCKP Port 13 electromechanical interlock
8 (I/O-1.0) I P15APN Port 15 attention push button input
9 (I/O-1.1) I P15PDN Port 15 presence detect input
10 (I/O-1.2) I P15PFN Port 15 power fault input
Type Signal Description
I P13APN Port 13 attention push button input
input
11 (I/O-1.3) I P15MRLN Port 15 manually-operated retention latch (MRL)
input
12 (I/O-1.4) O P15AIN Port 15 attention indicator output
13 (I/O-1.5) O P15PIN Port 15 power indicator output
14 (I/O-1.6) O P15PEP Port 15 power enable output
15 (I/O-1.7) O P15ILOCKP Port 15 electromechanical interlock
Table 6.9 I/O Expander 6 Signals
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
PES34H16 User Manual 6 - 14 October 30, 2008
Page 73
IDT SMBus Interfaces
Notes
I/O Expander 7
SMBus I/O
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) I P14PDN Port 14 presence detect input
2 (I/O-0.2) I P14PFN Port 14 power fault input
3 (I/O-0.3) I P14MRLN Port 14 manually-operated retention latch (MRL)
4 (I/O-0.4) O P14AIN Port 14 attention indicator output
5 (I/O-0.5) O P14PIN Port 14 power indicator output
6 (I/O-0.6) O P14PEP Port 14 power enable output
7 (I/O-0.7) O P14ILOCKP Port 14 electromechanical interlock
8 (I/O-1.0) I - Unused
9 (I/O-1.1) I - Unused
10 (I/O-1.2) I - Unused
11 (I/O-1.3) I - Unused
Type Signal Description
I P14APN Port 14 attention push button input
input
12 (I/O-1.4) O - Unused
13 (I/O-1.5) O - Unused
14 (I/O-1.6) O - Unused
15 (I/O-1.7) O - Unused
Table 6.10 I/O Expander 7 Signals
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
I/O Expander 8
SMBus I/O
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) O P1LINKUPN Port 1 link up status output
2 (I/O-0.2) O P2LINKUPN Port 2 link up status output
3 (I/O-0.3) O P3LINKUPN Port 3 link up status output
4 (I/O-0.4) O P4LINKUPN Port 4 link up status output
5 (I/O-0.5) O P5LINKUPN Port 5 link up status output
Type Signal Description
O P0LINKUPN Port 0 link up status output
6 (I/O-0.6) O P6LINKUPN Port 6 link up status output
7 (I/O-0.7) O P7LINKUPN Port 7 link up status output
8 (I/O-1.0) O P8LINKUPN Port 8 link up status output
Table 6.11 I/O Expander 8 Signals (Part 1 of 2)
PES34H16 User Manual 6 - 15 October 30, 2008
Page 74
IDT SMBus Interfaces
Notes
SMBus I/O
Expander
Type Signal Description
Bit
9 (I/O-1.1) O P9LINKUPN Port 9 link up status output
10 (I/O-1.2) O P10LINKUPN Port 10 link up status output
11 (I/O-1.3) O P11LINKUPN Port 11 link up status output
12 (I/O-1.4) O P12LINKUPN Port 12 link up status output
13 (I/O-1.5) O P13LINKUPN Port 13 link up status output
14 (I/O-1.6) O P14LINKUPN Port 14 link up status output
15 (I/O-1.7) O P15LINKUPN Port 15 link up status output
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
I/O Expander 9
SMBus I/O
Table 6.11 I/O Expander 8 Signals (Part 2 of 2)
Expander
Bit
0 (I/O-0.0)
1
1 (I/O-0.1) O P1ACTIVENN Port 1 active status output
2 (I/O-0.2) O P2ACTIVENN Port 2 active status output
3 (I/O-0.3) O P3ACTIVENN Port 3 active status output
4 (I/O-0.4) O P4ACTIVENN Port 4 active status output
5 (I/O-0.5) O P5ACTIVENN Port 5 active status output
6 (I/O-0.6) O P6ACTIVENN Port 6 active status output
7 (I/O-0.7) O P7ACTIVENN Port 7 active status output
8 (I/O-1.0) O P8ACTIVENN Port 8 active status output
9 (I/O-1.1) O P9ACTIVENN Port 9 active status output
10 (I/O-1.2) O P10ACTIVENN Port 10 active status output
Type Signal Description
O P0ACTIVENN Port 0 active status output
11 (I/O-1.3) O P11ACTIVENN Port 11 active status output
12 (I/O-1.4) O P12ACTIVENN Port 12 active status output
13 (I/O-1.5) O P13ACTIVENN Port 13 active status output
14 (I/O-1.6) O P14ACTIVENN Port 14 active status output
15 (I/O-1.7) O P15ACTIVENN Port 15 active status output
Table 6.12 I/O Expander 9 Signals
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
PES34H16 User Manual 6 - 16 October 30, 2008
Page 75
IDT SMBus Interfaces
Notes
I/O Expander 10
SMBus I/O
Expander
Bit
0 (I/O-0.0)
1 (I/O-0.1) I P1PWRGDN Port 1 power good input
2 (I/O-0.2) I P2PWRGDN Port 2 power good input
3 (I/O-0.3) I P3PWRGDN Port 3 power good input
4 (I/O-0.4) I P4PWRGDN Port 4 power good input
5 (I/O-0.5) I P5PWRGDN Port 5 power good input
6 (I/O-0.6) I P6PWRGDN Port 6 power good input
7 (I/O-0.7) I P7PWRGDN Port 7 power good input
8 (I/O-1.0) I P8PWRGDN Port 8 power good input
9 (I/O-1.1) I P9PWRGDN Port 9 power good input
10 (I/O-1.2) I P10PWRGDN Port 10 power good input
11 (I/O-1.3) I P11PWRGDN Port 11 power good input
12 (I/O-1.4) I P12PWRGDN Port 12 power good input
1
Type Signal Description
-Unused
13 (I/O-1.5) I P13PWRGDN Port 13 power good input
14 (I/O-1.6) I P14PWRGDN Port 14 power good input
15 (I/O-1.7) I P15PWRGDN Port 15 power good input
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
Table 6.13 I/O Expander 10 Signals
Slave SMBus Interface
The slave SMBus interface provides the PES34H16 with a configuration, management and debug inter-
face.
Using the slave SMBus interface, an external master can read or write any software visible register in
the device.
Initialization
Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
3-5).
During the fundamental reset initialization sequence, the slave SMBus address is initialized. The
address is specified by the SSMBADDR[5,3:1] signals as shown in Table 6.14.
Address
Bit
Address Bit Value
1 SSMBADDR[1]
2 SSMBADDR[2]
3 SSMBADDR[3]
Table 6.14 Slave SMBus Address When a Static Address is Selected (Part 1 of 2)
PES34H16 User Manual 6 - 17 October 30, 2008
Page 76
IDT SMBus Interfaces
Notes
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
ENDSTARTFUNCTIONSIZEPEC
Address
Bit
Address Bit Value
40
5 SSMBADDR[5]
61
71
Table 6.14 Slave SMBus Address When a Static Address is Selected (Part 2 of 2)
SMBus Transactions
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
See the SMBus 2.0 specification for a detailed description of these transactions.
– Byte and Word Write/Read
– Block Write/Read
Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces
undefined results.
Associated with each of the above transactions is a command code. The command code format for
operations supported by the slave SMBus interface is shown in Figure 6.7 and described in Table 6.15.
Figure 6.7 Slave SMBus Command Code Format
Bit
Field
Name
Description
0 END End of transaction indicator. Setting both START and END signifies a
single transaction sequence
0 - Current transaction is not the last read or write sequence.
1 - Current transaction is the last read or write sequence.
1 START Start of transaction indicator. Setting both START and END signifies
a single transaction sequence
0 - Current transaction is not the first of a read or write sequence.
1 - Current transaction is the first of a read or write sequence.
Table 6.15 Slave SMBus Command Code Fields (Part 1 of 2)
PES34H16 User Manual 6 - 18 October 30, 2008
Page 77
IDT SMBus Interfaces
Notes
Bit
Field
4:2 FUNCTION This field encodes the type of SMBus operation.
6:5 SIZE This field encodes the data size of the SMBus transaction.
7 PEC This bit controls whether packet error checking is enabled for the cur-
Name
0 - CSR register read or write operation
1 - Serial EEPROM read or write operation
2 through 7 - Reserved
0 - Byte
1 - Word
2 - Block
3 - Reserve d
rent SMBus transaction.
0 - Packet error checking disabled for the current SMBus transaction.
1 - Packet error checking enabled for the current SMBus transaction.
Table 6.15 Slave SMBus Command Code Fields (Part 2 of 2)
Description
The FUNCTION field in the command code indicates if the SMBus operation is a CSR register read/
write or a serial EEPROM read/write operation. Since the format of these transactions is different. They will
be described individually in the following sections.
If a command is issued while one is already in progress or if the slave is unable to supply data associated with a command, then the command is NACKed. This indicates to the master that the transaction
should be retried.
CSR Register Read or Write Operation
Table 6.16 indicates the sequence of data as it is presented on the slave SMBus following the byte
address of the Slave SMBus interface.
Byte
Positio
n
0 CCODE Command Code. Slave Command Code field described in Table
1 BYTCNT Byte Count. The byte count field is only transmitted for block type
2CMDCommand. This field encodes fields related to the CSR register read
3 ADDRL Address Low. Lower 8-bits of the doubleword CSR system address
4 ADDRU Address Upper. Upper 6-bits of the doubleword CSR system
Field
Name
Description
6.15.
SMBus transactions. SMBus word and byte accesses do not contain
this field. The byte count field indicates the number of bytes following
the byte count field when performing a write or setting up for a read.
The byte count field is also used when returning data to indicate the
number of following bytes (including status). Note that the byte count
field does not include the PEC byte if PEC is enabled.
or write operation.
of register to access.
address of register to access. Bits 6 and 7 in the byte must be zero
and are ignored by the hardware.
5 DATALL Data Lower. Bits [7:0] of data doubleword.
Table 6.16 CSR Register Read or Write Operation Byte Sequence (Part 1 of 2)
PES34H16 User Manual 6 - 19 October 30, 2008
Page 78
IDT SMBus Interfaces
Notes
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
BELLBELMWERR BEUMBEUUOPRERR 0
Byte
Positio
n
Field
Name
Description
6 DATALM Data Lower Middle. Bits [15:8] of data doubleword.
7 DATAUM Data Upper Middle. Bits [23:16] of data doubleword.
8 DATAUU Data Upper. Bits [31:24] of data doubleword.
Table 6.16 CSR Register Read or Write Operation Byte Sequence (Part 2 of 2)
The format of the CMD field is shown in Figure 6.8 and described in Table 6.17.
Figure 6.8 CSR Register Read or Write CMD Field Format
Bit
Field Name Type Description
0 BELL Read/Write Byte Enable Lower. When set, the byte enable for bits [7:0] of the
data word is enabled.
1 BELM Read/Write Byte Enable Lower Middle. When set, the byte enable for bits [15:8]
of the data word is enabled.
2 BEUM Read/Write Byte Enable Upper Middle. When set, the byte enable for bits
[23:16] of the data word is enabled.
3 BEUU Read/Write Byte Enable Upper. When set, the byte enable for bits [31:24] of the
data word is enabled.
4 OP Read/Write CSR Operation. This field encodes the CSR operation to be per-
formed.
0 - CSR write
1 - CSR read
5 0 0 Reserved. Must be zero
6 RERR Read-Only
and Clear
Read Error. This bit is set if the last CSR read SMBus transaction was
not claimed by a device. Success indicates that the transaction was
claimed and not that the operation completed without error.
7 WERR Read-Only
and Clear
Write Error. This bit is set if the last CSR write SMBus transaction was
not claimed by a device. Success indicates that the transaction was
claimed and not that the operation completed without error.
Table 6.17 CSR Register Read or Write CMD Field Description
Serial EEPROM Read or Write Operation
Table 6.17 indicates the sequence of data as it is presented on the slave SMBus following the byte
address of the Slave SMBus interface.
PES34H16 User Manual 6 - 20 October 30, 2008
Page 79
IDT SMBus Interfaces
Notes
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
OPUSA0 NAERRLAERROTHERERR 0
Byte
Positio
n
Field
Name Description
0 CCODE Command Code. Slave Command Code field described in Table
6.15.
1 BYTCNT Byte Count. The byte count field is only transmitted for block type
SMBus transactions. SMBus word and byte accesses to not contain
this field. The byte count field indicates the number of bytes following
the byte count field when performing a write or setting up for a read.
The byte count field is also used when returning data to indicate the
number of following bytes (including status).
2CMDCommand. This field contains information related to the serial
EEPROM transaction
3EEADDRSerial EEPROM Address. This field specifies the address of the
Serial EEPROM on the Master SMBus when the USA bit is set in the
CMD field. Bit zero must be zero and thus the 7-bit address must be
left justified.
4 ADDRL Address Low. Lower 8-bits of the Serial EEPROM byte to access.
5 ADDRU Address Upper. Upper 8-bits of the Serial EEPROM byte to access.
6DATAData. Serial EEPROM value read or to be written.
Table 6.18 Serial EEPROM Read or Write Operation Byte Sequence
The format of the CMD field is shown in Figure 6.9 and described in Table 6.19.
Figure 6.9 Serial EEPROM Read or Write CMD Field Format
Bit
Field
Name Type
0 OP RW Serial EEPROM Operation. This field encodes the serial EEPROM
1USA RWUse Specified Address. When this bit is set the serial EEPROM
2 Reserved
1
Description
operation to be performed.
0 - Serial EEPROM write
1 - Serial EEPROM read
SMBus address specified in the EEADDR is used instead of that
specified in the ADDR field in the EEPROMINTF register.
When this bit is set the serial EEPROM SMBus address specified in
the EEADDR is used instead of that specified in the MSMBADDR
field in the SMBUSSTS register.
Table 6.19 Serial EEPROM Read or Write CMD Field Description (Part 1 of 2)
PES34H16 User Manual 6 - 21 October 30, 2008
Page 80
IDT SMBus Interfaces
Notes
DATAUU
N
DATAUM
A
BYTCNT=7
A
ADDRLCMD (status)
S
PES34H16 Slave
SMBus Address
Wr A
A
BYTCNT=3
A
CMD=read
A
ADDRL
A
ADDRU
A P
CCODE
START,END
S
PES34H16 Slave
SMBus Address
Wr A A
CCODE
START,END
S
PES34H16 Slave
SMBus Address
Rd
DATALMDATALL
A A A
A A P
ADDRU
A
S
PES34H16 Slave
SMBus Address
Wr A
N
CCODE
START,END
P
(PES34H16 not ready with data)
Bit
Field
Name Type
1
Description
3 NAERR RC No Acknowledge Error. This bit is set if an unexpected NACK is
observed during a master SMBus transaction when accessing the
serial EEPROM. This bit has the same function as the NAERR bit in
the SMBUSSTS register.
The setting of this bit may indicate the following: that the addressed
device does not exist on the SMBus (i.e., addressing error), data is
unavailable or the device is busy, an invalid command was detected
by the slave, invalid data was detected by the slave.
4 LAERR RC Lost Arbitration Error. This bit is set if the master SMBus interface
loses 16 consecutive arbitration attempts when accessing the serial
EEPROM. This bit has the same function as the LAERR bit in the
SMBUSSTS register.
5 OTHERERR RC Other Error. This bit is set if a misplaced START or STOP condition is
detected by the master SMBus interface when accessing the serial
EEPROM. This bit has the same function as the OTHERERR bit in
the SMBUSSTS register.
7:6 Reserved 0 Reserved. Must be zero
Table 6.19 Serial EEPROM Read or Write CMD Field Description (Part 2 of 2)
1.
See Table 2 in the About This Manual chapter for a definition of these abbreviations.
Sample Slave SMBus Operation
This section illustrates sample Slave SMBus operations. Shaded items are driven by the PES34H16’s
slave SMBus interface and non-shaded items are driven by an SMBus host.
Figure 6.10 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled
PES34H16 User Manual 6 - 22 October 30, 2008
Page 81
IDT SMBus Interfaces
Notes
S
PES34H16 Slave
SMBus Address
Wr A
A
BYTCNT=4
A
CMD=read
A
EEADDR
A
ADDRL
A
P
CCODE
START,END
S
PES34H16 Slave
SMBus Address
Wr A A
CCODE
START,END
S
PES34H16 Slave
SMBus Address
Rd
ADDRU
A
BYTCNT=5
A
EEADDRCMD (status)
A A A
N
DATAADDRU
A P
ADDRL
A
S
PES34H16 Slave
SMBus Address
Wr A N
CCODE
START,END
P
(PES34H16 not ready with data)
S
PES34H16 Slave
SMBus Address
Wr A A
BYTCNT=7
A
CMD=write
A
ADDRL
A
ADDRU
A
CCODE
START,END
DATALL
A
DATALM
A
DATAUM
A
DATAUU
A P
S
PES34H16 Slave
SMBus Address
Wr A
CCODE
START,END
N P
(PES34H16 busy with previous command, not ready for a new command)
S
PES34H16 Slave
SMBus Address
Wr A
CCODE
START,END
N P
(PES34H16 busy with previous command, not ready for a new command)
S
PES34H16 Slave
SMBus Address
Wr A A
BYTCNT=5
A
CMD=write
A
EEADDR
A
ADDRL
A
CCODE
START,END
ADDRU
A
DATA
A P
S
PES34H16 Slave
SMBus Address
Wr A
A
BYTCNT=5
A
CMD=write
A
EEADDR
A
ADDRL
A
CCODE
START,END
ADDRU
A
DATA
A P
PEC
A
Figure 6.11 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC Disabled
Figure 6.12 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled
Figure 6.13 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled
PES34H16 User Manual 6 - 23 October 30, 2008
Figure 6.14 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled
Page 82
IDT SMBus Interfaces
Notes
ADDRU
N
A
ADDRLCMD (status)
S
PES34H16 Slave
SMBus Address
Wr A
A
CMD=read
A
ADDRL
A
CCODE
START, Word
S
PES34H16 Slave
SMBus Address
Wr A
CCODE
START,Word
S
PES34H16 Slave
SMBus Address
Rd
DATALMDATALL
A N
P
P
S
PES34H16 Slave
SMBus Address
Wr A A
ADDRU
A
CCODE
END, Byte
P
A
S
PES34H16 Slave
SMBus Address
Wr
A
CCODE
Byte
A
P
AS
PES34H16 Slave
SMBus Address
Rd A P
S
PES34H16 Slave
SMBus Address
Wr
A
CCODE
Word
A
S
PES34H16 Slave
SMBus Address
Rd A A
S
PES34H16 Slave
SMBus Address
Wr
A
CCODE
START,Word
N P
(PES34H16 not ready with data)
N
DATAUUDATAUM
P
S
PES34H16 Slave
SMBus Address
Wr
A
CCODE
END, Word
A
S
PES34H16 Slave
SMBus Address
Rd A A
Figure 6.15 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled
PES34H16 User Manual 6 - 24 October 30, 2008
Page 83
Notes
®
Chapter 7
D0
Uninitialized
D0
Active
D3
hot
Power-On Reset
D3
cold
Power Management
Introduction
Located in configuration space of each PCI-PCI bridge in the PES34H16 is a power management capability structure. The power management capability structure associated with a PCI-PCI bridge of a downstream port only affects that port. Entering the D3
the L1 state. The power management capability structure associated with the upstream port (i.e., port 0)
affects the entire device. When the upstream port enters a low power state and the PME_TO_Ack
messages are received, then the entire device is placed into a low power state.
The PES34H16 supports the following device power management states: D0 Uninitialized, D0 Active,
D3
, and D3
Hot
. A power management state transition diagram for the states supported by the
Cold
PES34H16 is provided in Figure 7.1 and described in Figure 7.1.
state allows the link associated with the bridge to enter
Hot
Transitioning a port’s power management state from D3
hot
to D0
uninitialized
does not result in any logic
being reset or re-initialization of register values. However, the default value of the No Soft Reset
(NOSOFTRST) bit in the PCI Power Management Control and Status (PMCSR) register corresponds to the
functional context being maintained in the D3
hot
state.
Figure 7.1 PES34H16 Power Management State Transition Diagram
PES34H16 User Manual 7 - 1 October 30, 2008
Page 84
IDT Power Management
Notes
From State To State Description
any D0 Uninitialized Power-on fundamental reset.
D0 Uninitialized D0 Active PCI-PCI bridge configured by software
D0 Active D3
D3
D3
hot
hot
D0 Uninitialized The Power Management State (PMSTATE) field in the PCI Power
D3
Table 7.1 PES34H16 Power Management State Transition Diagram
hot
cold
The Power Management State (PMSTATE) field in the PCI Power
Management Control and Status (PMCSR) register is written with the
value that corresponds to the D3
Management Control and Status (PMCSR) register is written with the
value that corresponds to D0 state.
Power is removed from the device.
hot
state.
The PES34H16 PCI-to-PCI bridges (i.e., ports) have the following behavior when in the D3
management state:
– A bridge accepts, processes and completes all type 0 configuration read and write requests.
– A bridge accepts and processes all message requests that target the bridge.
– All requests received by the bridge on the primary interface, except as noted above, are treated
as unsupported requests (UR).
– Any error message resulting from the receipt of a TLP is reported in the same manner as when
the bridge is not in D3
(e.g, generation of an ERR_NONFTAL message to the root).
hot
– Error messages resulting from any event other than the receipt of a TLP are discarded (i.e., no
error message is generated).
– All completions that target the bridge are treated as unexpected completions (UC).
– Completions flowing in either direction through the bridge are routed as normal. This behavior of
the bridge does not differ from that of the bridge when it is in the D0 power management state.
– All request TLPs received on the secondary interface are treated as unsupported requests (UR).
hot
power
PME Messages
The PES34H16 does not support generation of PME messages from the D3
ports (i.e., PCI-PCI bridges associated with downstream ports) support the generation of hot-plug PME
events (i.e., a PM_PME power management message) from the D3
when the downstream port is in the D3
state or the entire switch is in the D3
hot
state. This includes both the case
hot
hot
The generation of a PME message by downstream ports necessitates the implementation of a PME
service time-out mechanism to ensure that PME messages are not lost. If the PME Status (PMES) bit in the
a downstream port’s PCI Power Management Control and Status (PMCSR) register is not cleared within the
time-out period specified in the PM_PME Time-Out (PMPMETO) field in the ports PM_PME Timer
(PMPMETIMER) register after a PM_PME message is transmitted, then the PM_PME message is retransmitted and the timer is restarted.
state. Downstream
cold
state.
Power Express Power Management Fence Protocol
Root complex takes the following steps to turn off power to a system:
– The root places all devices in the D3 state
– Upon entry to D3, all devices transition their links to the L1 state
– The root broadcasts a PME_Turn_Off message.
– Devices acknowledge the PME_Turn_Off message by returning a PME_TO_ACK message
PES34H16 User Manual 7 - 2 October 30, 2008
Page 85
IDT Power Management
Notes
When the PES34H16 receives a PME_Turn_Off message it broadcasts the PME_Turn_Off message on
all active downstream ports. The PES34H16 transmits a PME_TO_Ack message on its upstream port and
transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its downstream ports.
In order to avoid deadlock, a downstream port that does not receive a PME_TO_Ack message in the
time-out period specified in the PME_TO_Ack Time-Out (PMETOATO) field in its corresponding
PME_TO_Ack Timer (PMETOATIMER) register, declares a time-out, transitions its link to L2/L3 Ready and
signals to the upstream port that a PME_TO_Ack message has been received. If instead of being transitioned to the D3
state, the PES34H16 is transitioned to the D0
cold
uninitialized
state, then the PES34H16
resumes generation of PM_PME messages.
Power Budgeting Capability
The PES34H16 contains the mechanisms necessary to implement the PCI express power budgeting
enhanced capability. However, by default, these mechanisms are not enabled. To enable the power
budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in
the PCI Express VC Enhanced Capability Header (PCIEVCECAP) register should be initialized to point to
the power budgeting capability.
The power budgeting capability consists of the four power budgeting capability registers defined in the
PCIe 1.1 base specification and eight general purpose read-write registers. See section Power Budgeting
Enhanced Capability on page 9-57 for a description of these registers. The Power Budgeting Capabilities
(PWRBCAP) register contains the PCI express enhanced capability header for the power budgeting capability. By default, this register has an initial read-only value of zero. To enable the power budgeting capability, this register should be initialized via the serial EEPROM.
The Power Budgeting Data Value [0..7] (PWRBDV[0..7) registers are used to hold the power budgeting
information for that port in a particular operating condition. The PWRBDV registers may be read and written
when the Power Budgeting Data Value Unlock (PWRBDVUL) bit is set in the System Control (SYSCTL)
register. When the PWRBDVUL bit is cleared, these register are read-only and writes to these registers are
ignored. To enable the power budgeting capability, the PWRBDV registers should be initialized with power
budgeting information via the serial EEPROM.
PES34H16 User Manual 7 - 3 October 30, 2008
Page 86
IDT Power Management
Notes
PES34H16 User Manual 7 - 4 October 30, 2008
Page 87
Notes
®
Chapter 8
PES34H16
Port 0
Port x
Slot
Port x Port y
Master
SMBus
SMBus I/O
Expander
Port y
Slot
Upstream
Link
Hot-Plug Signals
...
... ...
Hot-Plug and Hot-Swap
Introduction
As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configurations. Figure 8.1 illustrates the use of the PES34H16 in an application in which two downstream ports are
connected to slots into which add-in cards may be hot-plugged. Figure 8.2 illustrates the use of the
PES34H16 in an add-in card application. Here the downstream ports are hardwired to devic es on the addin card and the upstream port serves as the add-in card’s PCIe interface. In this application the upstream
port may be hot-plugged into a slot on the main system. Finally, Figure 8.3 illustrates the use of the
PES34H16 in a carrier card application. In this application, the downstream ports are connected to slots
which may be hot-plugged and the entire assembly may be hot-plugged into a slot on the main system.
Since this application requires nothing more than the functionality illustrated in both Figures 8.1 through 8.2,
it will not be discussed further.
Figure 8.1 Hot-Plug on Switch Downstream Slots Application
PES34H16 User Manual 8 - 1 October 30, 2008
Page 88
IDT Hot-Plug and Hot-Swap
Notes
PES34H16
Port 0
Port x Port y
Upstream
Link
PCI Express
Device
PCI Express
Device
Add-In Card
...
... ...
PES34H16
Port 0
Port x
Slot
Port x Port y
Master
SMBus
SMBus I/O
Expander
Port y
Slot
Upstream
Link
Hot-Plug Signals
Carrier
Card
...
... ...
Figure 8.2 Hot-Plug with Switch on Add-In Card Application
Figure 8.3 Hot-Plug with Carrier Card Application
The PCI Express Base Specification revision 1.0a allowed a hot-plug attention indicator, power indicator
and attention button to be located on the board on which the slot is implemented or on the add-in board.
When located on the add-in board, state changes are communicated between the hot-plug controller associated with the slot and the add-in card via hot-plug messages. This capability was removed in revision 1.1
of the PCI Express Base Specification and is not supported in the PES34H16.
PES34H16 User Manual 8 - 2 October 30, 2008
Page 89
IDT Hot-Plug and Hot-Swap
Notes
The remainder of this section discusses the use of the PES34H16 in an application in which one or more
of the downstream ports are used in an application in which an add-in card may be hot-plugged into a
downstream slot. Associated with each downstream port in the PES34H16 is a hot-plug controller. The hotplug controller may be enabled by setting the HPC bit in the PCI Express Slot Capabilities (PCIESCAP)
register associated with that port during configuration (e.g., via serial EEPROM).
The PES34H16 allows sensor inputs and indicator outputs to be located next to the slot or on the plug in
module. Regardless of the physical location, the indicators are controlled by the PES34H16’s downstream
port. Table 8.1 lists the hot-plug inputs and outputs that may be associated with a slot. When enabled during
configuration in the PCIESCAP register, these inputs and outputs ar e made available to external logic using
an external I/O expander located on the master SMBus interface. The PES34H16 only supports presence
detect signalling via a pin assertion. It does not support in-band presence detect.
Signal Type Name/Description
1
PxAPN I Port x
PxPDN I Port x Presence Detect Input.
PxPFN I Port x Power Fault Input.
PxMRLN I Port x Manually-operated Retention Latch (MRL) Input.
PxAIN O Port x Attention Indicator Output.
PxPIN O Port x Power Indicator Output.
Attention Push button Input.
PxPEP O Port x Power Enable Output.
PxILOCKP O Port x Electromechanical Interlock.
PxPWRGDN I Port x Power Good Input (asserted when slot power is good).
2
PxRSTN
1.
x corresponds to downstream port number (i.e., 1 through 15).
2.
This signal is a GPIO pin alternate function and is not available as an I/O expander output.
O Port x Reset Output.
Table 8.1 Downstream Port Hot-Plug Signals
Since the polarity of hot-plug signals has been defined differently in various specifications, each hot-plug
signal has a corresponding control bit in the Hot-Plug Configuration Control (HPCFGCTL) that allows the
polarity of that signal to be inverted. Inversion affects the corresponding signal in all ports.
When a one is written to the EIC bit in the PCIESCTL register, then the PxILOCKP signal is pulsed for
with a pulse length greater than 100 ms and less than 150 ms (i.e., it transactions from negated to asserted,
maintains an asserted state for 100 to 150 ms, and then transitions back to negated). When the Toggle
Electromechanical Interlock Control. (TEMICTL) bit in the HPCFGCTL register is set, writing a one to the
EIC bit inverts the state of the PxILOCKP signal.
When the Replace MRL Status with EMIL Status (RMRLWEMIL) bit is set in the HPCFGCTL register,
then the port’s PxMRLN input is used as the electromechanical state input. The state of this input is used as
the state of the electromechanical interlock state obtained by reading the Electromechanical Interlock
Status (EIS) bit in the PCI Express Slot Status (PCIESSTS) register. In this mode the state of the Manuallyoperated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the
EMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns a value of zero when read.
When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the
Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register,
then power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This
occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control
(PCIESCTL) register.
PES34H16 User Manual 8 - 3 October 30, 2008
Page 90
IDT Hot-Plug and Hot-Swap
Notes
The state of a port’s Power Fault (PxPFN) input is not latched by the PES34H16. For proper operation
the system designer should ensure that once the PxPFN signal is asserted, it remains asserted until the
power enable (PxPEP) signal is toggled. This is required adapter behavior for the PCI Express ExpressModule form factor. Downstream port reset outputs are described in section Downstream Port Reset
Outputs on page 3-8.
The default value of hot-plug registers following a hot or fundamental reset may be configured via serial
EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization,
the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result
of serial EEPROM initialization.
Hot-Plug I/O Expander
the PES34H16 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus interface for hot-plug related signals associated with downstream ports. See section I/O Expanders on page 6-6
for details on the operation of the I/O expanders and for the mapping of downstream hot-plug signals to I/O
expander inputs and outputs.
Hot-Plug Interrupts and Wake-up
The hot-plug controller associated with a downstream slot may generate an interrupt or wake-up event.
Hot-plug interrupts are only generated when the Hot-Plug Interrupt Enable (HPIE) bit is set in the corresponding port’s PCI Express Slot Control (PCIESCTL) register. The following bits, when set in the PCI
Express Slot Status (PCIESSTS) register, generate an interrupt if not masked by the corresponding bit in
the PCI Express Slot Control (PCIESCTL) register or by the HPIE bit: the Attention Button Pressed (ABP),
Power Fault Detected (PFD), MRL Sensor Changed (MRLSC), Presence Detected Changed (PDC), and
Command Completed (CC).
When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable
(EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command
(PCICMD) register. When the downstream port or the entire switch is in a D3
state, then the hot-plug
hot
controller generates a wake-up event using a PM_PME message instead of an interrupt if the event interrupt is not masked in the slot control (PCIESCTL) register and hot-plug interrupts are disabled by the HPIE
bit. If the event interrupt is not masked and hot-plug interrupts are enabled, then both a PM_PME and an
interrupt are generated. If the event interrupt is masked, then neither a PM_PME or interrupt are generated.
Note that a command completed (CC bit) interrupt will not generate a wake-up event.
Legacy System Hot-Plug Support
Some systems require support for operating systems that lack PCIe hot-plug support. The PES34H16
supports these systems by providing a General Purpose Event (GPEN) output as an alternate function of
GPIO[5] that can be used instead of the INTx, MSI, and PME mechanisms defined by PCI Express hotplug.
Associated with each downstream port’s hot-plug controller is a bit in the General Purpose Event
Control (P0_GPECTL) register. When this bit is set, then the corresponding PCIe base 1.1 hot-plug event
notification mechanisms are disabled for that port and INTx, MSI and PME events will not be generated by
that port due to hot-plug events. Instead, hot-plug events are signaled through assertion of the GPEN
signal.
GPEN is an alternate function of GPIO[5] and GPIO[5] will not be asserted when GPEN is asserted
unless it is configured to operate as an alternate function. Whenever a port signals a hot-plug event through
assertion of the GPEN signal, the corresponding port’s status bit in the General Purpose Event Status
(P0_GPESTS) register is set. A bit in the P0_GPESTS register can only be set if the corresponding port’s
hot-plug controller is configured to signal hot-plug events using the general purpose event (GPEN) signal
assertion mechanism.
PES34H16 User Manual 8 - 4 October 30, 2008
Page 91
IDT Hot-Plug and Hot-Swap
Command
Completed
RW1C
Attention Button
Pressed
Power Fault
Detected
MRL Sensor State
Changed
Presence Detected
Changed
Data Link Layer
State Changed
Command
Completed Enable
RW
Attention Button
Pressed Enable
Power Fault
Detected Enable
MRL Sensor State
Changed Enable
Presence Detected
Changed Enable
Data Link Layer
State Changed Enable
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW
RW
RW
RW
RW
PME Enable
Bit
RW
Activate Wake-up
Mechanism
Hot-Plug Interrupt
Enable
RW
RW
MSI Enable
Activate MSI
Mechanism
Activate INTx
Mechanism
RW
Interrupt
Disable
General Purpose Event
Enable
RW
General Purpose
Event Mechanism
Slot Control
Register
Slot Status
Register
Bit
The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events ins tead of the
PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe
slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged. INTx,
MSI and PME events from other sources are also unaffected.
The enhanced hot-plug signalling mechanism supported by the PES34H16 is graphically illustrated in Figure 8.4. This figure provides a conceptual
summary of the enhanced hot-plug signalling mechanism in the form of a pseudo logic diagram. Logic gates in this diagram are intended for
conveying general concepts, and not for direct implementation.
PES34H16 User Manual 8 - 5 October 30, 2008
Figure 8.4 PES34H16 Hot-Plug Event Signalling
Page 92
IDT Hot-Plug and Hot-Swap
Notes
Hot-Swap
The PES34H16 is hot-swap capable and meets the following requirements
In summary, PES34H16 meets all of the I/O requirements necessary to build a PICMG compliant hotswap board or system. The hot-swap I/O buffers of PES34H16 may also be used to construct proprietary
hot-swap systems. See the PES34H16 Data Sheet for a detailed specification of I/O buffer characteristics.
– All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.)
– All I/O cells function predictably from early power. This means that the device is able to tolerate a
non-monotonic ramp-up as well as a rapid ramp-up of the DC power.
– All I/O cells are able to tolerate a precharge voltage
– Since no clock is present during physical connection, the device will maintain all outputs in a high-
impedance state even when no clock is present.
– The I/O cells meet VI requirements for hot-swap.
– The I/O cells respect the required leakage current limits over the entire input voltage range.
PES34H16 User Manual 8 - 6 October 30, 2008
Page 93
Notes
®
Chapter 9
Configuration Registers
Configuration Space Organization
Each software visible registers in the PES34H16 is contained in the PCI configuration space of one of
the ports. Thus, there are no registers in the PES34H16 that cannot be accessed by the root. Each software
visible register in the PES34H16 has a system address. The system address is formed by adding the PCI
configuration space offset value of the register to the base address of the port in which it is located. The
system address is used for serial EEPROM register initialization and slave SMBus register accesses.
The base address for each PES34H16 port is listed in Table 9.1. The PCI configuration space offset
addresses for registers in the upstream port are listed in Table 9.2 while the PCI configuration space offset
addresses for registers in downstream ports are listed Table 9.3.
Base
Address
0x0000 Port 0 configuration space (upstream port)
0x1000 Port 1 configuration space (downstream port)
0x2000 Port 2 configuration space (downstream port)
0x3000 Port 3 configuration space (downstream port)
0x4000 Port 4 configuration space (downstream port)
0x5000 Port 5 configuration space (downstream port)
0x6000 Port 6 configuration space (downstream port)
0x7000 Port 7 configuration space (downstream port)
0x8000 Port 8 configuration space (downstream port)
0x9000 Port 9 configuration space (downstream port)
0xA000 Port 10 configuration space (downstream port)
0xB000 Port 11 configuration space (downstream port)
0xC000 Port 12 configuration space (downstream port)
0xD000 Port 12 configuration space (downstream port)
0xE000 Port 14 configuration space (downstream port)
0xF000 Port 15 configuration space (downstream port)
PCI Configuration Space
Table 9.1 Base Addresses for Port Configuration Space Registers
As shown in Figure 9.1, upstream and downstream ports share a similar PCI configuration space
register layout. The upstream port contains global switch control and status registers as well as test mode
registers which are not present in the configuration space of downstream ports. Due to the ability to
generate MSIs as a result of hot-plug events, the downstream ports contain an MSI capability structure
which is not present in the upstream port.
PCIe configuration reads to an upstream port offset not defined in Table 9.2 or a downstream port offset
not defined in Table 9.3 return a value of zer o. Slave SMBus reads to these of fsets retur n an undefined data
value. PCIe configuration writes or Slave SMBus writes to an offset not defined in Table 9.2 or Table 9.3
complete successfully but modify no data and have no other effect.
PES34H16 User Manual 9 - 1 October 30, 2008
Page 94
IDT Configuration Registers
Notes
PCI
Configuration Space
(64 DWord s)
Internal S w it ch Er ro r
Control & Status Registers
Switch Control
& Status Registers
Upstream Port Only
Power Budgeting
Enhanced Capability
PCIe Virtual Channel
Enhanced Capability
Device Serial Number
Enhanced Capability
Advanced Error Reporting
Enhanced Capability
0x000
0x040
0x0D0
0x0F0
Type 1
Configuration Header
PCI Express
Capability Structure
Extended Config Access
MSI
Capability Structure
Downstream Ports Only
0x0FF
0x100
0x000
0x180
0x200
0x280
0x400
0x4E0
0x740
0x780
0xFFF
0x0C0
PCI Power Management
Capability Structure
Reserved
SSID/SSVID
Reserved
Figure 9.1 Port Configuration Space Organization
PES34H16 User Manual 9 - 2 October 30, 2008
Page 95
IDT Configuration Registers
Notes
Upstream Port (Port 0)
Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.
Cfg.
Offset
0x000 Word P0_VID VID - Vendor Identification Register (0x000) on page 9-11
0x002 Word P0_DID DID - Device Identification Register (0x002) on page 9-12
0x004 Word P0_PCICMD PCICMD - PCI Command Register (0x004) on page 9-12
0x006 Word P0_PCISTS PCISTS - PCI Status Register (0x006) on page 9-13
0x008 Byte P0_RID RID - Revision Identification Register (0x008) on page 9-14
0x009 3 Bytes P0_CCODE CCODE - Class Code Register (0x009) on page 9-14
0x00C Byte P0_CLS CLS - Cache Line Size Register (0x00C) on page 9-14
0x00D Byte P0_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-15
0x00E Byte P0_HDR HDR - Header Type Register (0x00E) on page 9-15
0x00F Byte P0_BIST BIST - Built-in Self Test Register (0x00F) on page 9-15
0x010 DWord P0_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-15
0x014 DWord P0_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-15
0x018 Byte P0_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 9-15
0x019 Byte P0_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 9-16
0x01A Byte P0_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 9-16
0x01B Byte P0_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page 9-16
Size
Register
Mnemonic
Register Definition
0x01C Byte P0_IOBASE IOBASE - I/O Base Register (0x01C) on page 9-16
0x01D Byte P0_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 9-17
0x01E Word P0_SECSTS SECSTS - Secondary Status Register (0x01E) on page 9-17
0x020 Word P0_MBASE MBASE - Memory Base Register (0x020) on page 9-18
0x022 Word P0_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 9-18
0x024 Word P0_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page 9-
18
0x026 Word P0_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 9-19
0x028 DWord P0_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028) on
page 9-19
0x02C DWord P0_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on
page 9-19
0x030 Word P0_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 9-19
0x032 Word P0_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 9-20
0x034 Byte P0_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 9-20
0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on
page 9-20
Table 9.2 Upstream Port 0 Configuration Space Registers (Part 1 of 5)
PES34H16 User Manual 9 - 3 October 30, 2008
Page 96
IDT Configuration Registers
Notes
Cfg.
Offset
0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-20
0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-21
0x03E Word P0_BCTL BCTL - Bridge Control Register (0x03E) on page 9-21
0x040 DWord P0_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 9-22
0x044 DWord P0_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 9-23
0x048 Word P0_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 9-24
0x04A Word P0_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 9-25
0x04C DWord P0_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 9-26
0x050 Word P0_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 9-27
0x052 Word P0_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 9-28
0x064 DWord P0_PCIEDCAP2 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) on page 9-
0x068 Word P0_PCIEDCTL2 PCIEDCTL2 - PCI Express Device Control 2 (0x068) on page 9-33
0x06A Word P0_PCIEDSTS2 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) on page 9-34
0x06C DWord P0_PCIELCAP2 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) on page 9-34
0x070 Word P0_PCIELCTL2 PCIELCTL2 - PCI Express Link Control 2 (0x070) on page 9-34
Size
Register
Mnemonic
Register Definition
33
0x072 Word P0_PCIELSTS2 PCIELSTS2 - PCI Express Link Status 2 (0x072) on page 9-34
0x0C0 DWord P0_PMCAP PMCAP - PCI Power Management Capabilities (0x0C0) on page 9-35
0x0C4 DWord P0_PMCSR PMCSR - PCI Power Management Control and Status (0x0C4) on
page 9-36
0x0F0 Dword P0_SSIDSSVIDCAPSSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capabil-
ity (0x0F0) on page 9-38
0x0F4 Dword P0_SSIDSSVID SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) on
page 9-38
0x0F8 Word P0_ECFGADDR ECFGADDR - Extended Configuration Space Access Address
(0x0F8) on page 9-38
0x0FC Word P0_ECFGDATA ECFGDATA - Extended Configuration Space Access Data (0x0FC)
on page 9-39
0x100 Dword P0_AERCAP AERCAP - AER Capabilities (0x100) on page 9-39
0x104 Dword P0_AERUES AERUES - AER Uncorrectable Error Status (0x104) on page 9-40
0x108 Dword P0_AERUEM AERUEM - AER Uncorrectable Error Mask (0x108) on page 9-41
0x10C Dword P0_AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page 9-42
0x110 Dword P0_AERCES AERCES - AER Correctable Error Status (0x110) on page 9-43
0x114 Dword P0_AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 9-44
0x118 Dword P0_AERCTL AERCTL - AER Control (0x118) on page 9-45
0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 9-
45
0x120 Dword P0_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 9-
45
Table 9.2 Upstream Port 0 Configuration Space Registers (Part 2 of 5)
PES34H16 User Manual 9 - 4 October 30, 2008
Page 97
IDT Configuration Registers
Notes
Cfg.
Offset
0x124 Dword P0_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page 9-
0x128 Dword P0_AERHL4DW AERHL4DW - AER Header Log 4th Doubleword (0x128) on page 9-
0x180 Dword P0_SNUMCAP SNUMCAP - Serial Number Capabilities (0x180) on page 9-46
0x184 Dword P0_SNUMLDW SNUMLDW - Serial Number Lower Doubleword (0x184) on page 9-46
0x188 Dword P0_SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page 9-
0x200 DWord P0_PCIEVCECAP PCIEVCECAP - PCI Express VC Enhanced Capability Header
0x204 DWord P0_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x204) on page 9-47
0x208 DWord P0_PVCCAP2 PVCCAP2- Port VC Capability 2 (0x208) on page 9-47
0x20C Word P0_PVCCTL PVCCTL - Port VC Control (0x20C) on page 9-48
0x20E Word P0_PVCSTS PVCSTS - Port VC Status (0x20E) on page 9-48
0x210 DWord P0_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x210) on page 9-49
0x214 DWord P0_VCR0CTL VCR0CTL- VC Resource 0 Control (0x214) on page 9-49
0x218 DWord P0_VCR0STS VCR0STS - VC Resource 0 Status (0x218) on page 9-50
0x21c DWord P0_VCR1CAP VCR1CAP- VC Resource 1 Capability (0x21C) on page 9-50
Size
Register
Mnemonic
Register Definition
45
46
46
(0x200) on page 9-47
0x220 DWord P0_VCR1CTL VCR1CTL- VC Resource 1 Control (0x220) on page 9-51
0x224 DWord P0_VCR1STS VCR1STS - VC Resource 1 Status (0x224) on page 9-52
0x230 DWord P0_VCR0TBL0 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x230) on
page 9-52
0x234 DWord P0_VCR0TBL1 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x234) on
page 9-53
0x238 DWord P0_VCR0TBL2 VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x238) on
page 9-53
0x23C DWord P0_VCR0TBL3 VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x23C) on
page 9-54
0x240 DWord P0_VCR1TBL0 VCR1TBL0 - VC Resource 1 Arbitration Table Entry 0 (0x240) on
page 9-55
0x244 DWord P0_VCR1TBL1 VCR1TBL1 - VC Resource 1 Arbitration Table Entry 1 (0x244) on
page 9-55
0x248 DWord P0_VCR1TBL2 VCR1TBL2 - VC Resource 1 Arbitration Table Entry 2 (0x248) on
page 9-56
0x24C DWord P0_VCR1TBL3 VCR1TBL3 - VC Resource 1 Arbitration Table Entry 3 (0x24C) on
page 9-56
0x280 Dword P0_PWRBCAP PWRBCAP - Power Budgeting Capabilities (0x280) on page 9-57
0x284 Dword P0_PWRBDSEL PWRBDSEL - Power Budgeting Data Select (0x284) on page 9-57
0x288 Dword P0_PWRBD PWRBD - Power Budgeting Data (0x288) on page 9-58
0x28C Dword P0_PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C) on
page 9-58
Table 9.2 Upstream Port 0 Configuration Space Registers (Part 3 of 5)
PES34H16 User Manual 9 - 5 October 30, 2008
Page 98
IDT Configuration Registers
Notes
Cfg.
Offset
0x300 Dword P0_PWRBDV0 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page
0x304 Dword P0_PWRBDV1 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page
0x308 Dword P0_PWRBDV2 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page
0x30C Dword P0_PWRBDV3 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page
0x310 Dword P0_PWRBDV4 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page
0x314 Dword P0_PWRBDV5 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page
0x318 Dword P0_PWRBDV6 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page
0x31C Dword P0_PWRBDV7 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page
0x400 DWord SWSTS SWSTS - Switch Status (0x400) on page 9-59
0x404 DWord SWCTL SWCTL - Switch Control (0x404) on page 9-61
0x408 DWord HPCFGCTL HPCFGCTL - Hot-Plug Configuration Control (0x408) on page 9-62
Size
Register
Mnemonic
Register Definition
9-58
9-58
9-58
9-58
9-58
9-58
9-58
9-58
0x40C DWord GPR GPR - General Purpose Register (0x40C) on page 9-63
0x418 DWord GPIOFUNC GPIOFUNC - General Purpose I/O Control Function (0x418) on page
9-63
0x41C DWord GPIOCFG GPIOCFG - General Purpose I/O Configuration (0x41C) on page 9-63
0x420 DWord GPIOD GPIOD - General Purpose I/O Data (0x420) on page 9-64
0x424 DWord SMBUSSTS SMBUSSTS - SMBus Status (0x424) on page 9-64
0x428 DWord SMBUSCTL SMBUSCTL - SMBus Control (0x428) on page 9-65
0x42C DWord EEPROMINTF EEPROMINTF - Serial EEPROM Interface (0x42C) on page 9-66
0x430 DWord IOEXPINTF IOEXPINTF - I/O Expander Interface (0x430) on page 9-67
0x434 DWord IOEXPADDR0 IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434) on page 9-
68
0x438 DWord IOEXPADDR1 IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438) on page 9-
69
0x43C DWord IOEXPADDR2 IOEXPADDR2 - SMBus I/O Expander Address 2 (0x43C) on page 9-
69
0x450 DWord GPECTL GPECTL - General Purpose Event Control (0x450) on page 9-70
0x454 DWord GPESTS GPESTS - General Purpose Event Status (0x454) on page 9-72
0x470 DWord USPFSTS USPFSTS - Upstream Port Failover Status (0x470) on page 9-74
0x474 DWord USPFCTL USPFCTL - Upstream Port Failover Control (0x474) on page 9-75
0x478 DWord USPFTIMER USPFTIMER - Upstream Port Failover Watchdog Timer (0x478) on
page 9-75
0x740 Dword P0_SWPECTL SWPECTL - Switch Parity Error Control (0x740) on page 9-76
Table 9.2 Upstream Port 0 Configuration Space Registers (Part 4 of 5)
PES34H16 User Manual 9 - 6 October 30, 2008
Page 99
IDT Configuration Registers
Notes
Cfg.
Offset
0x744 Dword P0_SWPESTS SWPESTS - Switch Parity Error Status (0x744) on page 9-76
0x748 Dword P0_SWPERCTL SWPERCTL - Switch Parity Error Reporting Control (0x748) on page
0x74C Dword P0_SWPECNT SWPECNT - Switch Parity Error Count (0x74C) on page 9-77
0x754 Dword P0_SWTOSTS SWTOSTS - Switch Time-Out Status (0x754) on page 9-77
0x758 Dword P0_SWTORCTL SWTORCTL - Switch Time-Out Reporting Control (0x758) on page 9-
0x75C Dword P0_SWTOCNT SWTOCNT - Switch Time-Out Count (0x75C) on page 9-79
Size
Register
Mnemonic
9-77
78
Table 9.2 Upstream Port 0 Configuration Space Registers (Part 5 of 5)
Register Definition
PES34H16 User Manual 9 - 7 October 30, 2008
Page 100
IDT Configuration Registers
Notes
Downstream Ports (Ports 1 through 15)
Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.
Cfg.
Offset
0x000 Word Px_VID VID - Vendor Identification Register (0x000) on page 9-11
0x002 Word Px_DID DID - Device Identification Register (0x002) on page 9-12
0x004 Word Px_PCICMD PCICMD - PCI Command Register (0x004) on page 9-12
0x006 Word Px_PCISTS PCISTS - PCI Status Register (0x006) on page 9-13
0x008 Byte Px_RID RID - Revision Identification Register (0x008) on page 9-14
0x009 3 Bytes Px_CCODE CCODE - Class Code Register (0x009) on page 9-14
0x00C Byte Px_CLS CLS - Cache Line Size Register (0x00C) on page 9-14
0x00D Byte Px_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-15
0x00E Byte Px_HDR HDR - Header Type Register (0x00E) on page 9-15
0x00F Byte Px_BIST BIST - Built-in Self Test Register (0x00F) on page 9-15
0x010 DWord Px_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-15
0x014 DWord Px_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-15
0x018 Byte Px_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 9-15
0x019 Byte Px_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 9-16
0x01A Byte Px_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 9-16
0x01B Byte Px_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page 9-16
Size
Register
Mnemonic
Register Definition
0x01C Byte Px_IOBASE IOBASE - I/O Base Register (0x01C) on page 9-16
0x01D Byte Px_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 9-17
0x01E Word Px_SECSTS SECSTS - Secondary Status Register (0x01E) on page 9-17
0x020 Word Px_MBASE MBASE - Memory Base Register (0x020) on page 9-18
0x022 Word Px_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 9-18
0x024 Word Px_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page 9-
18
0x026 Word Px_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 9-19
0x028 DWord Px_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028) on
page 9-19
0x02C DWord Px_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on
page 9-19
0x030 Word Px_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 9-19
0x032 Word Px_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 9-20
0x034 Byte Px_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 9-20
0x038 DWord Px_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on
page 9-20
Table 9.3 Downstream Ports 1 through 15 Configuration Space Registers (Part 1 of 4)
PES34H16 User Manual 9 - 8 October 30, 2008
Loading...