IDT 89HPES24T6G2, 89HPES16T4AG2 User Manual

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IDT™ 89HPES24T6G2

PCI Express® Switch

User Manual

April 2013

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

GENERAL DISCLAIMER

Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely at your own risk. IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY OR COMPLETENESS OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with any applicable laws or regulations.

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

CODE DISCLAIMER

LIFE SUPPORT POLICY

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Notes

About This Manual

Introduction

This user manual includes hardware and software information on the 89HPES24T6G2, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard.

Finding Additional Information

Information not included in this manual such as mechanicals, package pin-outs, and electrical characteristics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.

Content Summary

Chapter 1, “PES24T6G2 Device Overview,” provides a complete introduction to the performance capabilities of the 89HPES24T6G2. Included in this chapter is a summary of features for the device as well as a system block diagram and pin description.

Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes.

Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion, link width negotiation, and lane reversal.

Chapter 4, “General Purpose I/O,” describes how the 11 General Purpose I/O (GPIO) pins may be individually configured as general purpose inputs, general purpose outputs, or alternate functions.

Chapter 5, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES24T6G2.

Chapter 6, “Power Management,” describes the power management capability structure located in the configuration space of each PCI-PCI bridge in the PES24T6G2.

Chapter 7, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in the PES24T6G2.

Chapter 8, “Configuration Registers,” discusses the base addresses, PCI configuration space, and registers associated with the PES24T6G2.

Chapter 9, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.

Signal Nomenclature

To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term negate or negation is used to indicate that a signal is inactive or false.

To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be interpreted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the right. No leading zeros will be included.

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Notes

1 2 3 4

high-to-low

transition

low-to-high

transition

single clock cycle

Throughout this manual, when describing signal transitions, the following terminology is used. Rising edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These terms are illustrated in Figure 1.

Figure 1 Signal Transitions

Numeric Representations

To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows: 0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.

Data Units

The following data unit terminology is used in this document.

Ter m Words By tes Bi ts

Byte 1/2 1 8

Word 1 2 16

Doubleword (Dword) 2 4 32

Quadword (Qword) 4 8 64

Table 1 Data Unit Terminology

In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In doublewords, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit and bit 0 is the least significant bit.

The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte of a word. See Figure 2.

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0 1 2 3

bit 0bit 31

Address of Bytes within Words: Big Endian

3 2 1 0

bit 0bit 31

Address of Bytes within Words: Little Endian

Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

Register Terminology

Software in the context of this register terminology refers to modifications made by PCIe root configuration writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initialization. See Table 2.

Type Abbreviation Description

Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms

such as pin strapping or serial EEPROM. (System firmware hardware initialization is only allowed for system integrated devices.) Bits are read-only after initialization and can only be reset (for write-once by firmware) with reset.

Read Only and Clear RC Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bit to be reset to zero. Writing to a RC location has no effect.

Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bits to be reset to zero. Writes cause the register/bits to be modified.

Reserved Reserved The value read from a reserved register/bit is undefined. Thus,

software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back.

Read Only RO Software can only read registers/bits with this attribute. Contents

are hardwired to a constant value or are status bits that may be set and cleared by hardware. Writing to a RO location has no effect.

Read and Write RW Software can both read and write bits with this attribute.

Table 2 Register Terminology (Sheet 1 of 2)

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Type Abbreviation Description

Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.

However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event. To clear a RW1C bit (i.e., change its value to zero) a value of one must be written to the location. An RW1C bit is never cleared by hardware.

Read and Write when Unlocked

Write Transient WT The zero is always read from a bit/field of this type. Writing of a

Zero Zero A zero register or bit must be written with a value of zero and

RWL Software can read the register/bits with this attribute. Writing to

register/bits with this attribute will only cause the value to be modified if the REGUNLOCK bit in the SWCTL register is set. When the REGUNLOCK bit is cleared, writes are ignored and the register/bits are effectively read-only. RWL bits are implicitly “Sitcky.”

one is used to quality the writing of other bits/fields in the same register.

returns a value of zero when read.

Table 2 Register Terminology (Sheet 2 of 2)

Use of Hypertext

In Chapter 8, Tables 8.2 and 8.3 contain register names and page numbers highlighted in blue under the Register Definition column. In pdf files, users can jump from this source table directly to the registers by clicking on the register name in the source table. Each register name in the table is linked directly to the appropriate register in the register section of the chapter. To return to the source table after having jumped to the register section, click on the same register name (in blue) in the register section.

Reference Documents

PCI Express Base Specification, Revision 2.0, PCI Special Interest Group.

PCI Power Management Interface Specification, Revision 1.2, PCI Special Interest Group.

PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group.

SMBus Specification, Revision 2.0.

Revision History

August 8, 2007: Initial publication of preliminary user manual.

September 26, 2007: Updated manual from spec dated September 25, 2007.

November 28, 2007: Updated Chapter 1 to reflect some pins are not available in the 19x19 pinout

package.

December 4, 2007: Added hardwired address locations for MSMBADDR and SSMBADDR to Chapters 1 and 5.

January 7, 2008: In Chapter 1, Table 1.9, MSMBADDR[4:1] pins changed to pull-down. In Chapter 5, I/O Expanders section, added text explaining legacy compatibility with Gen1 PCIe switches. In Chapter 8, modified the following fields: L0SEL in PCIELCAP has default value of 0x6, ARIS in PCIEDCAP2 is RO, and ARIFEN in PCIEDCTL2 is RO.

July 15, 2008: In Chapter 8. added Autonomous Link Reliability Management section and 4 registers. Removed General Purpose Register (0x40C).

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August 25, 2008: In Chapter 2, deleted reference to FRSTS pins.

October 24, 2008: In Chapter 1, updated Table 1.2 with additional silicon revisions.

November 3, 2008: Updated the description for the following fields in Chapter 8: LDIS and LRET in the

PCIELCTL register, ULD in the ALRSTS register, and TLW in the PHYLCFG0 register, and changed the last Reserved field in the PCIEDCTL2 register from 31:6 to 15:6.

May 7, 2009: In Chapter 3, revised the Lane Reversal section.

July 21, 2009: In Chapter 3, revised section Dynamic Link Width Reconfiguration Support in the

PES24T6G2. Also, deleted entire section Software Management of Link Width Upconfiguration and Downconfiguration.

September 15, 2010: In Table 1.9, changed Buffer type for PCI Express from CML to PCIe differential and changed reference clocks to HCSL.

October 26, 2010: In Chapter 2, revised Clocking section on page 1 to remove reference to REFCLKM.

September 23, 2011: Added DDDNC (Disable Downstream Device Number Checking) bit to Switch

Control register in Chapter 8, Configuration Registers.

February 22, 2012: Added paragraph after Table 5.13 to explain use of DWord addresses.

January 29, 2013: In Figure 5.8, changed No-ack to Ack between DATALM and DATAUM.

April 30, 2013: In Table 1.6, changed description for PxxMERGEN pins to pull-up via 92K ohm resistor.

In Table 1.9, changed PxxMERGEN pins from pull-down to pull-up.

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Table of Contents

About This Manual

Introduction ....................................................................................................................................1

Content Summary ..........................................................................................................................1

Signal Nomenclature .....................................................................................................................1

Numeric Representations ..............................................................................................................2

Data Units ...................................................................................................................................... 2

Register Terminology ..................................................................................................................... 3

Use of Hypertext ............................................................................................................................ 4

Reference Documents ................................................................................................................... 4

Revision History .............................................................................................................................4

PES24T6G2 Device Overview

Introduction .....................................................................................................................................1-1

Features.......................................................................................................................................... 1-1

Logic Diagram — PES24T6G2.......................................................................................................1-4

Vendor ID........................................................................................................................................ 1-5

Device ID ........................................................................................................................................1-5

Revision ID......................................................................................................................................1-5

JTAG ID ..........................................................................................................................................1-5

SSID/SSVID.................................................................................................................................... 1-5

Pin Description................................................................................................................................ 1-6

Pin Characteristics........................................................................................................................1-11

Port Configuration.........................................................................................................................1-12

Clocking, Reset and Initialization

Clocking ..........................................................................................................................................2-1

Initialization .....................................................................................................................................2-1

Reset...............................................................................................................................................2-2

Fundamental Reset ................................................................................................................2-2

Hot Reset................................................................................................................................ 2-5

Upstream Secondary Bus Reset ............................................................................................2-6

Downstream Secondary Bus Reset........................................................................................ 2-6

Downstream Port Reset Outputs ....................................................................................................2-7

Power Enable Controlled Reset Output.................................................................................. 2-7

Power Good Controlled Reset Output ....................................................................................2-8

Link Operation

Introduction .....................................................................................................................................3-1

Polarity Inversion ............................................................................................................................3-1

Lane Reversal................................................................................................................................. 3-1

Link Width Negotiation....................................................................................................................3-2

Dynamic Link Width Reconfiguration..............................................................................................3-3

Dynamic Link Width Reconfiguration Support in the PES24T6G2 .........................................3-3

Link Speed Negotiation................................................................................................................... 3-4

Link Speed Negotiation in the PES24T6G2............................................................................3-4

Software Management of Link Speed.....................................................................................3-5

Link Reliability................................................................................................................................. 3-5

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Autonomous Link Reliability Management .............................................................................3-6

Link Retraining................................................................................................................................ 3-7

Link Down ....................................................................................................................................... 3-8

Slot Power Limit Support ................................................................................................................3-8

Upstream Port ........................................................................................................................3-8

Downstream Port....................................................................................................................3-8

Link States ...................................................................................................................................... 3-8

Active State Power Management ...................................................................................................3-9

Link Status .................................................................................................................................... 3-10

De-emphasis Negotiation .............................................................................................................3-10

Low-Swing Transmitter Voltage Mode..........................................................................................3-10

Crosslink ....................................................................................................................................... 3-10

General Purpose I/O

Introduction ..................................................................................................................................... 4-1

GPIO Configuration ........................................................................................................................4-1

GPIO Pin Configured as an Input ........................................................................................... 4-2

GPIO Pin Configured as an Output ........................................................................................4-2

GPIO Pin Configured as an Alternate Function...................................................................... 4-2

SMBus Interfaces

Introduction ..................................................................................................................................... 5-1

Master SMBus Interface ................................................................................................................. 5-2

Initialization.............................................................................................................................5-2

Serial EEPROM...................................................................................................................... 5-2

I/O Expanders......................................................................................................................... 5-7

Slave SMBus Interface .................................................................................................................5-14

Initialization...........................................................................................................................5-15

SMBus Transactions ............................................................................................................5-15

Power Management

Introduction ..................................................................................................................................... 6-1

PME Messages............................................................................................................................... 6-2

PCI-Express Power Management Fence Protocol .........................................................................6-2

Power Budgeting Capability............................................................................................................ 6-3

Hot-Plug and Hot-Swap

Hot-Plug.......................................................................................................................................... 7-1

Hot-Plug I/O Expander ...........................................................................................................7-4

Hot-Plug Interrupts and Wake-up ........................................................................................... 7-4

Legacy System Hot-Plug Support ..........................................................................................7-5

Hot-Swap ........................................................................................................................................ 7-6

Configuration Registers

Configuration Space Organization..................................................................................................8-1

Upstream Port (Port 0) ...........................................................................................................8-2

Downstream Ports .................................................................................................................. 8-6

Register Definitions....................................................................................................................... 8-10

Type 1 Configuration Header Registers ............................................................................... 8-10

PCI Express Capability Structure .........................................................................................8-20

Power Management Capability Structure ............................................................................. 8-36

Message Signaled Interrupt Capability Structure ................................................................. 8-37

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Subsystem ID and Subsystem Vendor ID ............................................................................ 8-39

Extended Configuration Space Access Registers ................................................................ 8-39

Advanced Error Reporting (AER) Enhanced Capability .......................................................8-40

Device Serial Number Enhanced Capability......................................................................... 8-48

PCI Express Virtual Channel Capability ...............................................................................8-49

Power Budgeting Enhanced Capability ................................................................................ 8-55

Switch Control and Status Registers .................................................................................... 8-56

Autonomous Link Reliability Management ...........................................................................8-72

JTAG Boundary Scan

Introduction ..................................................................................................................................... 9-1

Test Access Point ........................................................................................................................... 9-1

Signal Definitions ............................................................................................................................ 9-1

Boundary Scan Chain.....................................................................................................................9-3

Test Data Register (DR) .................................................................................................................9-4

Boundary Scan Registers.......................................................................................................9-4

Instruction Register (IR)..................................................................................................................9-6

EXTEST.................................................................................................................................. 9-7

SAMPLE/PRELOAD............................................................................................................... 9-7

BYPASS ................................................................................................................................. 9-7

CLAMP ................................................................................................................................... 9-8

IDCODE.................................................................................................................................. 9-8

VALIDATE .............................................................................................................................. 9-8

RESERVED............................................................................................................................ 9-8

Usage Considerations ............................................................................................................9-8

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List of Tables

Table 1.1 PES24T6G2 Device ID........................................................................................................ 1-5

Table 1.2 PES24T6G2 Revision ID .....................................................................................................1-5

Table 1.3 PCI Express Interface Pins.................................................................................................. 1-6

Table 1.4 SMBus Interface Pins .......................................................................................................... 1-7

Table 1.5 General Purpose I/O Pins.................................................................................................... 1-7

Table 1.6 System Pins......................................................................................................................... 1-8

Table 1.7 Test Pins.............................................................................................................................. 1-9

Table 1.8 Power, Ground, and SerDes Resistor Pins .......................................................................1-10

Table 1.9 Pin Characteristics............................................................................................................. 1-11

Table 2.1 Boot Configuration Vector Signals.......................................................................................2-1

Table 4.1 General Purpose I/O Pin Alternate Function .......................................................................4-1

Table 4.2 GPIO Pin Configuration .......................................................................................................4-1

Table 5.1 Serial EEPROM SMBus Address ........................................................................................5-2

Table 5.2 PES24T6G2 Compatible Serial EEPROMs......................................................................... 5-3

Table 5.3 Serial EEPROM Initialization Errors ....................................................................................5-6

Table 5.4 I/O Expander Function Allocation ........................................................................................5-7

Table 5.5 I/O Expander Default Output Signal Value ..........................................................................5-8

Table 5.6 I/O Expander 0 Signals...................................................................................................... 5-11

Table 5.7 I/O Expander 1 Signals...................................................................................................... 5-11

Table 5.8 I/O Expander 2 Signals...................................................................................................... 5-13

Table 5.9 I/O Expander 3 Signals...................................................................................................... 5-13

Table 5.10 I/O Expander 4 Signals......................................................................................................5-14

Table 5.11 Slave SMBus Address When a Static Address is Selected............................................... 5-15

Table 5.12 Slave SMBus Command Code Fields ...............................................................................5-15

Table 5.13 CSR Register Read or Write Operation Byte Sequence ...................................................5-16

Table 5.14 CSR Register Read or Write CMD Field Description.........................................................5-17

Table 5.15 Serial EEPROM Read or Write Operation Byte Sequence................................................5-17

Table 5.16 Serial EEPROM Read or Write CMD Field Description.....................................................5-18

Table 6.1 PES24T6G2 Power Management State Transition Diagram...............................................6-2

Table 8.1 Base Addresses for Port Configuration Space Register...................................................... 8-1

Table 8.2 Upstream Port 0 Configuration Space Registers................................................................. 8-2

Table 8.3 Downstream Ports 1 through 5 Configuration Space Registers ..........................................8-6

Table 9.1 JTAG Pin Descriptions.........................................................................................................9-2

Table 9.2 Boundary Scan Chain.......................................................................................................... 9-3

Table 9.3 Instructions Supported by PES24T6G2’s JTAG Boundary Scan ........................................9-7

Table 9.4 System Controller Device Identification Register.................................................................9-8

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List of Figures

Figure 1.1 PES24T6G2 Architectural Block Diagram ..........................................................................1-3

Figure 1.2 PES24T6G2 Logic Diagram ...............................................................................................1-4

Figure 1.3 All Ports Unmerged Configuration ...................................................................................1-13

Figure 1.4 Some Ports Merged Configuration ...................................................................................1-14

Figure 1.5 All Ports Merged Configuration ........................................................................................1-14

Figure 2.1 Fundamental Reset with Serial EEPROM initialization ......................................................2-4

Figure 2.2 Fundamental Reset using RSTHALT to keep device in Quasi-Reset state .......................2-5

Figure 2.3 Power Enable Controlled Reset Output Mode Operation ..................................................2-7

Figure 2.4 Power Good Controlled Reset Output Mode Operation .....................................................2-8

Figure 3.1 Unmerged Port Lane Reversal ..........................................................................................3-1

Figure 3.2 Merged Port Lane Reversal ...............................................................................................3-2

Figure 3.3 PES24T6G2 ASPM Link Sate Transitions .........................................................................3-9

Figure 5.1 SMBus Interface Configuration Examples .........................................................................5-1

Figure 5.2 Single Double Word Initialization Sequence Format ..........................................................5-3

Figure 5.3 Sequential Double Word Initialization Sequence Format ...................................................5-4

Figure 5.4 Configuration Done Sequence Format ..............................................................................5-4

Figure 5.5 Slave SMBus Command Code Format ............................................................................5-15

Figure 5.6 CSR Register Read or Write CMD Field Format ..............................................................5-17

Figure 5.7 Serial EEPROM Read or Write CMD Field Format ..........................................................5-18

Figure 5.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled ..5-19 Figure 5.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC

Disabled ...........................................................................................................................5-19

Figure 5.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........5-20

Figure 5.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........5-20

Figure 5.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........5-20

Figure 5.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....5-21

Figure 6.1 PES24T6G2 Power Management State Transition Diagram .............................................6-1

Figure 7.1 Hot-Plug on Switch Downstream Slots Application ............................................................7-1

Figure 7.2 Hot-Plug with Switch on Add-In Card Application ..............................................................7-2

Figure 7.3 Hot-Plug with Carrier Card Application ..............................................................................7-2

Figure 7.4 PES24T6G2 Hot-Plug Event Signalling .............................................................................7-6

Figure 8.1 Port Configuration Space Organization .............................................................................8-2

Figure 9.1 Diagram of the JTAG Logic ................................................................................................9-1

Figure 9.2 State Diagram of PES24T6G2’s TAP Controller ................................................................9-2

Figure 9.3 Diagram of Observe-only Input Cell ...................................................................................9-5

Figure 9.4 Diagram of Output Cell ......................................................................................................9-5

Figure 9.5 Diagram of Bidirectional Cell ..............................................................................................9-6

Figure 9.6 Device ID Register Format .................................................................................................9-8

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AERCAP - AER Capabilities (0x100) ..................................................................................................... 8-40

AERCEM - AER Correctable Error Mask (0x114) .................................................................................. 8-46

AERCES - AER Correctable Error Status (0x110) ................................................................................. 8-45

AERCTL - AER Control (0x118)............................................................................................................. 8-47

AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..................................................................... 8-47

AERHL2DW - AER Header Log 2nd Doubleword (0x120)..................................................................... 8-47

AERHL3DW - AER Header Log 3rd Doubleword (0x124)...................................................................... 8-48

AERHL4DW - AER Header Log 4th Doubleword (0x128)...................................................................... 8-48

AERUEM - AER Uncorrectable Error Mask (0x108) .............................................................................. 8-41

AERUES - AER Uncorrectable Error Status (0x104) ............................................................................. 8-40

AERUESV - AER Uncorrectable Error Severity (0x10C)........................................................................ 8-44

ALRCNT - Autonomous Link Reliability Counter (0x56C) ...................................................................... 8-74

ALRCTL - Autonomous Link Reliability Control (0x560)......................................................................... 8-72

ALRERT - Autonomous Link Reliability Error Rate Threshold (0x5680) ................................................ 8-73

ALRSTS - Autonomous Link Reliability Status (0x564).......................................................................... 8-73

BAR0 - Base Address Register 0 (0x010).............................................................................................. 8-13

BAR1 - Base Address Register 1 (0x014).............................................................................................. 8-14

BCTL - Bridge Control Register (0x03E) ................................................................................................ 8-19

BIST - Built-in Self Test Register (0x00F) .............................................................................................. 8-13

CAPPTR - Capabilities Pointer Register (0x034) ................................................................................... 8-18

CCODE - Class Code Register (0x009) ................................................................................................. 8-12

CLS - Cache Line Size Register (0x00C)............................................................................................... 8-13

DID - Device Identification Register (0x002) .......................................................................................... 8-10

ECFGADDR - Extended Configuration Space Access Address (0x0F8) ............................................... 8-39

ECFGDATA - Extended Configuration Space Access Data (0x0FC)..................................................... 8-40

EEPROMINTF - Serial EEPROM Interface (0x42C) .............................................................................. 8-64

EROMBASE - Expansion ROM Base Address Register (0x038)........................................................... 8-18

GPECTL - General Purpose Event Control (0x450)............................................................................... 8-66

GPESTS - General Purpose Event Status (0x454)................................................................................ 8-67

GPIOCFG - General Purpose I/O Configuration (0x41C)....................................................................... 8-62

GPIOD - General Purpose I/O Data (0x420).......................................................................................... 8-62

GPIOFUNC - General Purpose I/O Control Function (0x418)................................................................ 8-61

HDR - Header Type Register (0x00E).................................................................................................... 8-13

HPCFGCTL - Hot-Plug Configuration Control (0x408)........................................................................... 8-60

INTRLINE - Interrupt Line Register (0x03C)........................................................................................... 8-18

INTRPIN - Interrupt PIN Register (0x03D) ............................................................................................. 8-19

IOBASE - I/O Base Register (0x01C)..................................................................................................... 8-15

IOBASEU - I/O Base Upper Register (0x030)........................................................................................ 8-17

IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434)..................................................................... 8-66

IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438)..................................................................... 8-66

IOEXPINTF - I/O Expander Interface (0x430)........................................................................................ 8-65

IOLIMIT - I/O Limit Register (0x01D)...................................................................................................... 8-15

IOLIMITU - I/O Limit Upper Register (0x032)......................................................................................... 8-18

MBASE - Memory Base Register (0x020).............................................................................................. 8-16

MLIMIT - Memory Limit Register (0x022)............................................................................................... 8-16

MSIADDR - Message Signaled Interrupt Address (0x0D4).................................................................... 8-38

MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) ................................................ 8-37

MSIMDATA - Message Signaled Interrupt Message Data (0x0DC)....................................................... 8-39

MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) ...................................................... 8-38

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IDT Register List

Notes

PBUSN - Primary Bus Number Register (0x018)....................................................................................8-14

PCICMD - PCI Command Register (0x004)............................................................................................8-10

PCIECAP - PCI Express Capability (0x040) ...........................................................................................8-20

PCIEDCAP - PCI Express Device Capabilities (0x044) ..........................................................................8-21

PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) .....................................................................8-32

PCIEDCTL - PCI Express Device Control (0x048)..................................................................................8-22

PCIEDCTL2 - PCI Express Device Control 2 (0x068).............................................................................8-33

PCIEDSTS - PCI Express Device Status (0x04A) ..................................................................................8-23

PCIEDSTS2 - PCI Express Device Status 2 (0x06A) .............................................................................8-33

PCIELCAP - PCI Express Link Capabilities (0x04C) ..............................................................................8-24

PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) .........................................................................8-33

PCIELCTL - PCI Express Link Control (0x050).......................................................................................8-25

PCIELCTL2 - PCI Express Link Control 2 (0x070)..................................................................................8-33

PCIELSTS - PCI Express Link Status (0x052)........................................................................................8-27

PCIELSTS2 - PCI Express Link Status 2 (0x072)...................................................................................8-35

PCIESCAP - PCI Express Slot Capabilities (0x054) ...............................................................................8-28

PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) ..........................................................................8-35

PCIESCTL - PCI Express Slot Control (0x058).......................................................................................8-30

PCIESCTL2 - PCI Express Slot Control 2 (0x078)..................................................................................8-35

PCIESSTS - PCI Express Slot Status (0x05A) .......................................................................................8-31

PCIESSTS2 - PCI Express Slot Status 2 (0x07A) ..................................................................................8-36

PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) ................................................8-49

PCISTS - PCI Status Register (0x006) ...................................................................................................8-11

PHYLCFG0 - Phy Link Configuration 0 (0x530)......................................................................................8-68

PHYLSTATE0 - Phy Link State 0 (0x540)...............................................................................................8-71

PHYLSTS0 - Phy Link Status 0 (0x538)..................................................................................................8-69

PHYPRBS - Phy PRBS Seed (0x55C)....................................................................................................8-72

PLTIMER - Primary Latency Timer (0x00D)............................................................................................8-13

PMBASE - Prefetchable Memory Base Register (0x024) .......................................................................8-16

PMBASEU - Prefetchable Memory Base Upper Register (0x028)..........................................................8-17

PMCAP - PCI Power Management Capabilities (0x0C0)........................................................................8-36

PMCSR - PCI Power Management Control and Status (0x0C4) ............................................................8-37

PMLIMIT - Prefetchable Memory Limit Register (0x026) ........................................................................8-17

PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) ..........................................................8-17

PVCCAP1- Port VC Capability 1 (0x204)................................................................................................8-49

PVCCAP2- Port VC Capability 2 (0x208)................................................................................................8-50

PVCCTL - Port VC Control (0x20C) ........................................................................................................8-50

PVCSTS - Port VC Status (0x20E) .........................................................................................................8-50

PWRBCAP - Power Budgeting Capabilities (0x280)...............................................................................8-55

PWRBD - Power Budgeting Data (0x288)...............................................................................................8-56

PWRBDSEL - Power Budgeting Data Select (0x284).............................................................................8-55

PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) .....................................................8-56

PWRBPBC - Power Budgeting Power Budget Capability (0x28C) .........................................................8-56

RID - Revision Identification Register (0x008) ........................................................................................8-12

SBUSN - Secondary Bus Number Register (0x019) ...............................................................................8-14

SECSTS - Secondary Status Register (0x01E) ......................................................................................8-15

SERDESCTL- SerDes Control (0x500)...................................................................................................8-68

SLTIMER - Secondary Latency Timer Register (0x01B).........................................................................8-14

SMBUSCTL - SMBus Control (0x428) ....................................................................................................8-63

SMBUSSTS - SMBus Status (0x424) .....................................................................................................8-62

SNUMCAP - Serial Number Capabilities (0x180) ...................................................................................8-48

SNUMLDW - Serial Number Lower Doubleword (0x184) .......................................................................8-48

SNUMUDW - Serial Number Upper Doubleword (0x188).......................................................................8-48

SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) ...........................................................8-39

SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) ...................................8-39

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IDT Register List

Notes

SUBUSN - Subordinate Bus Number Register (0x01A)..........................................................................8-14

SWCTL - Switch Control (0x404) ............................................................................................................8-57

SWSTS - Switch Status (0x400) .............................................................................................................8-56

VCR0CAP- VC Resource 0 Capability (0x210).......................................................................................8-51

VCR0CTL- VC Resource 0 Control (0x214)............................................................................................8-51

VCR0STS - VC Resource 0 Status (0x218)............................................................................................8-52

VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)..............................................................8-53

VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)..............................................................8-53

VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228)..............................................................8-54

VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C).............................................................8-54

VID - Vendor Identification Register (0x000)...........................................................................................8-10

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IDT Register List

Notes

PES24T6G2 User Manual xii April 30, 2013

Page 21

Notes

Chapter 1

PES24T6G2 Device Overview

Introduction

The 89HPES24T6G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES24T6G2 is a 24-lane, 6-port Gen2 peripheral chip that performs PCI Express base switching with a feature set optimized for high performance applications such as servers, storage, and communications systems. It provides connectivity and switching functions between a PCI Express upstream port and up to five downstream ports and supports switching between downstream ports.

Features



High Performance PCI Express Switch

– Twenty-four 5 Gbps Gen2 PCI Express lanes supporting

5 Gbps and 2.5 Gbps operation – Up to six switch ports – Support for Max Payload Size up to 2048 bytes – Supports one virtual channel and eight traffic classes – Fully compliant with PCI Express base specification Revision 2.0



Flexible Architecture with Numerous Configuration Options

– Automatic per port link width negotiation to x8, x4, x2, or x1 – Automatic lane reversal on all ports – Automatic polarity inversion – Supports in-band hot-plug presence detect capability – Supports external signal for hot plug event notification allowing SCI/SMI generation for legacy

operating systems – Dynamic link width reconfiguration for power/performance optimization – Configurable downstream port PCI-to-PCI bridge device numbering – Crosslink support – Supports ARI forwarding defined in the Alternative Routing-ID Interpretation (ARI) ECN for virtu-

alized and non-virtualized environments – Ability to load device configuration from serial EEPROM



Legacy Support

– PCI compatible INTx emulation – Supports bus locked transactions, allowing use of PCI Express with legacy software



Highly Integrated Solution

– Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes, 8B/10B encoder/decoder (no sepa-

rate transceivers needed)



Reliability, Availability, and Serviceability (RAS) Features

– Ability to disable peer-to-peer communications – Supports ECRC and Advanced Error Reporting – All internal data and control RAMs are SECDED ECC protected – Supports PCI Express hot-plug on all downstream ports – Supports upstream port hot-plug – Hot-swap capable I/O – External Serial EEPROM contents are checksum protected – Supports PCI Express Device Serial Number Capability – Capability to monitor link reliability and autonomously change link speed to prevent link instability

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IDT PES24T6G2 Device Overview

Notes



Power Management

– Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Power Management Interface specification (PCI-PM 1.1)

• Supports device power management states: D0, D3

– Support for PCI Express Active State Power Management (ASPM) link state

• Supports link power management states: L0, L0s, L1, L2/L3 Ready and L3 – Supports PCI Express Power Budgeting Capability – Configurable SerDes power consumption

• Supports optional PCI-Express SerDes Transmit Low-Swing Voltage Mode

• Supports numerous SerDes Transmit Voltage Margin settings – Unused SerDes are disabled



Testability and Debug Features

– Per port link up and activity status outputs available on I/O expander outputs – Built in SerDes 8-bit and 10-bit pseudo-random bit stream (PRBS) generators – Numerous SerDes test modes, including a PRBS Master Loopback mode for in-system link

testing

– Ability to read and write any internal register via SMBus and JTAG interfaces, including SerDes

internal controls

– Per port statistics and performance counters, as well as proprietary link status registers



Eleven General Purpose Input/Output Pins

– Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions



Option A Package: 19mm x 19mm 324-ball Flip Chip BGA with 1mm ball spacing



Option B Package: 27mm x 27mm 676-ball Flip Chip BGA with 1mm ball spacing

and D3

hot

cold

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IDT PES24T6G2 Device Overview

TDM Demux

D-Bus

U-Bus

ESP & Arb

Route Map

Table

Ingress

Processor

TLP

Checker

Egress

Processor

Completion

Processor

Message

Processor

TLP

Generator

Hot-Plug Controller

Application Layer

Data Link Layer

Physical Layer & SerDes Mux/Demux

SerDesSerDes

Port 0 Port 1 Port 2 Port 3 Port 4 Port 5

Switch Core

GPIO

Controller

Master SMBus

Interface

Reset

Controller

Slave

SMBus

Interface

Output &

Replay Buffer

TDM Demux

Route Map

Table

Ingress

Processor

TLP

Checker

Egress

Processor

Completion

Processor

Message

Processor

TLP

Generator

Hot-Plug Controller

Application Layer

Data Link Layer

Physical Layer & SerDes Mux/Demux

SerDesSerDes

Output &

Replay Buffer

TDM Demux

Route Map

Table

Ingress

Processor

TLP

Checker

Egress

Processor

Completion

Processor

Message

Processor

TLP

Generator

Hot-Plug Controller

Application Layer

Data Link Layer

Physical Layer & SerDes Mux/Demux

SerDesSerDes

Output &

Replay Buffer

Input Frame Buffer

D-Bus Arbiter

U-Bus Arbiter

Bus Decoupler

Queue

Figure 1.1 PES24T6G2 Architectural Block Diagram

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IDT PES24T6G2 Device Overview

PE0TP[0]

Reference

Clocks

PEREFCLKP PEREFCLKN

JTAG_TCK

GPIO[10:0]

General Purpose

I/O

VDDCORE

I/O

PEA

Power/Ground

MSMBADDR[4:1]

MSMBCLK MSMBDAT

SSMBADDR[5,3:1]

SSMBCLK SSMBDAT

Master

SMBus Interface

Slave

SMBus Interface

CCLKUS

RSTHALT

System

Pins

JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N

JTAG Pins

SWMODE[2:0]

CCLKDS

PERSTN

REFCLKM

MSMBSMODE

PE0RP[0] PE0RN[0]

PE0RP[3] PE0RN[3]

PCI Express

Switch

SerDes Input

PE0TN[0]

PE0TP[3] PE0TN[3]

PCI Express

Switch

SerDes Output

...

Port 0

...

PE3RP[0] PE3RN[0]

PE3RP[3] PE3RN[3]

PCI Express

Switch

SerDes Input

PE3TP[0] PE3TN[0]

PE3TP[3] PE3TN[3]

PCI Express

Switch

SerDes Output

...

Port 3

...

PE4RP[0] PE4RN[0]

PE4RP[3] PE4RN[3]

PCI Express

Switch

SerDes Input

PE4TP[0] PE4TN[0]

PE4TP[3] PE4TN[3]

PCI Express

Switch

SerDes Output

...

Port 4

...

PE5RP[0] PE5RN[0]

PE5RP[3] PE5RN[3]

PCI Express

Switch

SerDes Input

PE5TP[0] PE5TN[0]

PE5TP[3] PE5TN[3]

PCI Express

Switch

SerDes Output

...

Port 5

...

PES24T6G2

REFRES0

SerDes

Reference

Resistors

REFRES2

REFRES4 REFRES5

VDDPEHA

Reference Clock

Frequency Selection

PE2RP[0]

PE2RN[0]

PE2RP[3]

PE2RN[3]

PCI Express

Switch

SerDes Input

...

Port 2

PE1RP[0]

PE1RN[0]

PE1RP[3]

PE1RN[3]

PCI Express

Switch

SerDes Input

...

Port 1

PE2TP[0] PE2TN[0]

PE2TP[3] PE2TN[3]

PCI Express

Switch

SerDes Output

Port 2

...

PE1TP[0] PE1TN[0]

PE1TP[3] PE1TN[3]

PCI Express

Switch

SerDes Output

Port 1

...

REFRES1

REFRES3

VDDPETA

P23MERGEN

P01MERGEN

P45MERGEN

Logic Diagram — PES24T6G2

Note: The following pins are not available in the 19mm package: REFCLKM, MSMBADDR, SSMBADDR, MSMBSMODE, RSTHALT, GPIO[6:3].

PES24T6G2 User Manual 1 - 4 April 30, 2013

Figure 1.2 PES24T6G2 Logic Diagram

Page 25

IDT PES24T6G2 Device Overview

Notes

Vendor ID

All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech-

nology, Inc.

Device ID

The PES24T6G2 device ID is shown in Table 1.1.

Revision ID

The PES24T6G2 revision ID is shown in Table 1.2.

PCIe Device Device ID

0x6 0x806E

Table 1.1 PES24T6G2 Device ID

Revision ID Description

0x00 Corresponds to ZA silicon.

0x01 Corresponds to ZB silicon.

0x02 Corresponds to ZC silicon.

Table 1.2 PES24T6G2 Revision ID

JTAG ID

The JTAG ID is:

– Version: Same value as Revision ID. See Table 1.2. – Part number: Same value as base Device ID. See Table 1.1. – Manufacture ID: 0x33 – LSB: 0x1

SSID/SSVID

The PES24T6G2 contains the mechanisms necessary to implement the PCI-to-PCI bridge Subsystem ID and Subsystem Vendor ID capability structure. However, in the default configuration the Subsystem ID and Subsystem Vendor ID capability structure is not enabled. To enable the capability, the SSID and SSVID fields in the Subsystem ID and Subsystem Vendor ID (SSIDSSVID) register must be initialized with the appropriate ID values. the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to this capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted to point to the next capability if necessary.

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IDT PES24T6G2 Device Overview

Notes

Pin Description

The following tables list the functions of the pins provided on the PES24T6G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal Type Name/Description

PE0RP[3:0] PE0RN[3:0]

PE0TP[3:0] PE0TN[3:0]

I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pairs for port 0. Port 0 is the upstream port.

O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit

pairs for port 0. Port 0 is the upstream port.

PE1RP[3:0] PE1RN[3:0]

PE1TP[3:0] PE1TN[3:0]

PE2RP[3:0] PE2RN[3:0]

PE2TP[3:0] PE2TN[3:0]

PE3RP[3:0] PE3RN[3:0]

PE3TP[3:0] PE3TN[3:0]

PE4RP[3:0] PE4RN[3:0]

PE4TP[3:0] PE4TN[3:0]

PE5RP[3:0] PE5RN[3:0]

PE5TP[3:0] PE5TN[3:0]

PEREFCLKP PEREFCLKN

REFCLKM

REFCLKM is not available in the 19mm package and frequency is set at 100MHz.

I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive

pairs for port 1.

O PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit

pairs for port 1.

I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pairs for port 2.

O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit

pairs for port 2.

I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive

pairs for port 3.

O PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit

pairs for port 3.

I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pairs for port 4.

O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit

pairs for port 4.

I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive

pairs for port 5.

O PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit

pairs for port 5.

I PCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal.

I PCI Express Reference Clock Mode Select. This signal selects the fre-

quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz This pin should be static and not change following the negation of PERSTN.

Table 1.3 PCI Express Interface Pins

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IDT PES24T6G2 Device Overview

Notes

Signal Type Name/Description

MSMBADDR[4:1]

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

I Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

transfers on the master SMBus.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master

SMBus.

SSMBADDR[5,3:1]

I Slave SMBus Address. These pins determine the SMBus address to which

the slave SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

Table 1.4 SMBus Interface Pins

MSMBADDR pins are not available in the 19mm package. Address hardwired to 0x50.

SSMBADDR pins are not available in the 19mm package. Address hardwired to 0x77.

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2

GPIO[1] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4

GPIO[2] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input

GPIO[3]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: I/O Expander interrupt 1 input

GPIO[4]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input

GPIO[5]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: I/O Expander interrupt 3 input

GPIO[6]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Table 1.5 General Purpose I/O Pins (Part 1 of 2)

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Page 28

IDT PES24T6G2 Device Overview

Notes

Signal Type Name/Description

GPIO[7] I/O General Purpose I/O.

GPIO[8] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output

This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1

GPIO[9] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3

GPIO[10] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5

Table 1.5 General Purpose I/O Pins (Part 2 of 2)

GPIO pins 3, 4, 5, 6 are not available in the 19mm package.

Signal Type Name/Description

CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each downstream port’s PCIELSTS register.

CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register.

MSMBSMODE

I Master SMBus Slow Mode. The assertion of this pin indicates that the mas-

ter SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden.

P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled high

internally via a 92K ohm resistor. When this pin is low, port 0 is merged with port 1 to form a single x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7 of port 0. When this pin is high, port 0 and port 1 are not merged, and each operates as a single x4 port.

P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled high

internally via a 92K ohm resistor. When this pin is low, port 2 is merged with port 3 to form a single x8 port. The Serdes lanes associated with port 3 become lanes 4 through 7 of port 2. When this pin is high, port 2 and port 3 are not merged, and each operates as a single x4 port.

Table 1.6 System Pins (Part 1 of 2)

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IDT PES24T6G2 Device Overview

Notes

Signal Type Name/Description

P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled high

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside

RSTHALT

SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T6G2 switch

MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz.

RSTHALT is not available in the 19mm package.

internally via a 92K ohm resistor. When this pin is low, port 4 is merged with port 5 to form a single x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7 of port 4. When this pin is high, port 4 and port 5 are not merged, and each operates as a single x4 port.

PES24T6G2 and initiates a PCI Express fundamental reset.

I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, PES24T6G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master.

operating mode. 0x0 -Normal switch mode 0x1 -Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN.

Table 1.6 System Pins (Part 2 of 2)

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into

or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 1.7 Test Pins

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IDT PES24T6G2 Device Overview

Notes

Signal Type Name/Description

REFRES0 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0

REFRES1 I/O Port 1 External Reference Resistor. Provides a reference for the Port 1

REFRES2 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.

REFRES3 I/O Port 3 External Reference Resistor. Provides a reference for the Port 3

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.

REFRES4 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.

REFRES5 I/O Port 5 External Reference Resistor. Provides a reference for the Port 5

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.

CORE I Core V

I/O I I/O V

PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).

PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).

PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog

power supply (1.0V).

I Ground.

Power supply for core logic.

DD.

LVTTL I/O buffer power supply.

DD.

Table 1.8 Power, Ground, and SerDes Resistor Pins

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IDT PES24T6G2 Device Overview

Notes

Pin Characteristics

Note: Some input pads of the PES24T6G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.

Function Pin Name Type Buffer

PCI Express Interface

SMBus MSMBADDR[4:1]

PE0RN[3:0] I PCIe

PE0RP[3:0] I

PE0TN[3:0] O

PE0TP[3:0] O

PE1RN[3:0] I

PE1RP[3:0] I

PE1TN[3:0] O

PE1TP[3:0] O

PE2RN[3:0] I

PE2RP[3:0] I

PE2TN[3:0] O

PE2TP[3:0] O

PE3RN[3:0] I

PE3RP[3:0] I

PE3TN[3:0] O

PE3TP[3:0] O

PE4RN[3:0] I

PE4RP[3:0] I

PE4TN[3:0] O

PE4TP[3:0] O

PE5RN[3:0] I

PE5RP[3:0] I

PE5TN[3:0] O

PE5TP[3:0] O

PEREFCLKN I HCSL Diff. Clock

PEREFCLKP I

REFCLKM

MSMBCLK I/O STI

MSMBDAT I/O STI pull-up on board

SSMBADDR[5,3:1]

SSMBCLK I/O STI pull-up on board

SSMBDAT I/O STI pull-up on board

Table 1.9 Pin Characteristics (Part 1 of 2)

differential

I LVTTL Input pull-down

I Input pull-up

I/O

Type

Serial Link

Input

Internal

Resistor

Notes

Refer to Table 9

PES24T6G2

Data Sheet

pull-up on board

in the

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IDT PES24T6G2 Device Overview

Notes

Function Pin Name Type Buffer

General Pur-

GPIO[10:0]

I/O LVTTL STI,

pose I/O

I/O

Type

High Drive

Internal

Resistor

pull-up

System Pins CCLKDS I LVTTL Input pull-up

CCLKUS I Input pull-up

MSMBSMODE

I Input pull-down

P01MERGEN I pull-up

P23MERGEN I pull-up

P45MERGEN I pull-up

PERSTN I STI

RSTHALT

I Input pull-down

SWMODE[2:0] I Input pull-down

EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up

JTAG_TDI I STI pull-up

JTAG_TDO O

JTAG_TMS I STI pull-up

JTAG_TRST_N I STI pull-up

SerDes Reference Resistors

REFRES0 I/O Analog

REFRES1 I/O

REFRES2 I/O

REFRES3 I/O

REFRES4 I/O

REFRES5 I/O

Notes

Internal resistor values under typical operating conditions are 92K  for pull-up and 90K for pull-down.

All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.

REFCLKM is not available in the 19mm package.

SMBus address pins are not available in the 19mm package.

Schmitt Trigger Input (STI).

GPIO pins 3, 4, 5, 6 are not available in the 19mm package.

MSMBSMODE and RSTHALT are not available in the 19mm package.

Port Configuration

The PES24T6G2 contains a total of six ports labeled zero through 5. Port zero is always the upstream port. Ports one through five are always downstream ports. All ports support both 2.5 Gbps (Gen1) and 5.0 Gbps (Gen2) operation. The adjacent x4 ports can be merged into x8 ports.

An even port n and its odd counterpart, port n+1, may be merged into a single x8 port. When this occurs, port n is said to be a merged port. When an even port n and its odd counterpart, port n+1, operate independently, then ports n and n+1 are said to be unmerged. The PES24T6G2 supports port merging in a static manner during a fundamental reset. If the Port x and y Merge (PxyMERGEN) signal is asserted, then the two x4 ports x and y are merged into a single x8 merged port called port x.

Table 1.9 Pin Characteristics (Part 2 of 2)

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IDT PES24T6G2 Device Overview

Notes

PES24T6G2

PCI to PCI

Bridge

PCI to PCI

Bridge

PCI to PCI

Bridge

Dev. 1

Dev. 2

PCI to PCI

Bridge

PCI to PCI

Bridge

Dev. 3

Dev. 4

PCI to PCI

Bridge

Dev. 5

Dev. 0

Port 0

Virtual PCI Bus

Port 1

Port 2

Port 3

Port 4

Port 5

When ports x and y are merged, the switch port, the PCI-to-PCI bridge, and all associated resources associated with port y are disabled and the following modifications are made to the default PES24T6G2 configuration.

– All of the output signals associated with port y remain in a negated state (e.g., hot plug outputs,

link status signals, port reset output, etc.)

– All input signals associated with port y are ignored by the PES24T6G2 and have no effect on its

operation.

– Configuration read or write transactions to device y on the PES24T6G2’s virtual PCI bus are

treated by the upstream port (port 0) as an unsupported request (i.e., the device no longer exists).

This renders the registers in port y’s configuration space inaccessible to the root.

– All registers associated with port y become inaccessible via the SMBus. Reading or writing an

inaccessible register has an undefined effect.

Reading a port y register returns an undefined value and writing a port y register has an undefined effect.

– All of the SerDes lanes associated with port y become part of port x and are managed by port x

as native SerDes lanes (i.e., port x operates as though it were a x8 port).

– The initial value of the MAXLNKWDTH field in port x’s PCIELCAP register defaults to x8 mode.

Figures 1.3 through 1.5 illustrate three of many possible PES24T6G2 configurations. In Figure 1.3, all of the ports are unmerged. In this configuration, the PES24T6G2 operates as a 6-port switch with all ports having a x4 width. In Figure 1.4, port zero and one are merged as are ports three and four. In this configuration, the PES24T6G2 operates as a 4-port switch with some having a x4 width and others having a x8 width. Finally, Figure 1.5 illustrates a PES24T6G2 configuration in which all ports are merged. In this configuration, the PES24T6G2 operates as a 3-port switch with all ports having a x8 width.

Figure 1.3 All Ports Unmerged Configuration

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IDT PES24T6G2 Device Overview

Notes

PES24T6G2

PCI to PCI

Bridge

PCI to PCI

Bridge

Dev. 2

PCI to PCI

Bridge

PCI to PCI

Bridge

Dev. 3

Dev. 5

Dev. 0

Port 0

Virtual PCI Bus

Port 2

Port 3

Port 5

PES24T6G2

PCI to PCI

Bridge

PCI to PCI

Bridge

Dev. 2

PCI to PCI

Bridge

Dev. 4

Dev. 0

Port 0

Virtual PCI Bus

Port 2

Port 4

Figure 1.4 Some Ports Merged Configuration

Figure 1.5 All Ports Merged Configuration

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Notes

Chapter 2

Clocking, Reset and

Initialization

Clocking

The PES24T6G2 has a single differential reference clock input (PEREFCLKP/PEREFCLKN) that is used internally to generate all of the clocks required by the internal switch logic and the SerDes. The frequency of the reference clock input is set to 100MHz.

Note: There are no skew requirement between the reference clock inputs.

Initialization

A boot configuration vector consisting of the signals listed in Table 2.1 is sampled by the PES24T6G2 d

uring a Fundamental Reset when PERSTN is negated. The boot configuration vector defines essential parameters for switch operation. Since the boot configuration vector is sampled only during a Fundamental Reset sequence, the value of signals which make up the boot configuration vector is ignored during other times and their state outside of a Fundamental Reset has no effect on the operation of the PES24T6G2.

While basic switch operation may be configured using signals in the boot configuration vector, advanced switch features require configuration via an external serial EEPROM. The external serial EEPROM allows modification of any bit in any software visible register. See Chapter 5, SMBus Interfaces, for more information on the serial EEPROM.

The external serial EEPROM and slave SMBus interface may be used to override the function of some of the signals in the boot configuration vector during a Fundamental Reset. The signals that may be overridden are noted in Table 2.1. The state of all of the boot configuration signals in Table 2.1 sampled during the most recent Fundamental Reset may be determined by reading the SWSTS register.

Signal

CCLKDS I Common Clock Downstream. The assertion of this pin indicates

CCLKUS I Common Clock Upstream. The assertion of this pin indicates that

MSMBSMODE

P01MERGEN I Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with

P23MERGEN I Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with

Overridden

May Be

that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each downstream port’s PCIELSTS register.

the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register.

I Master SMBus Slow Mode. The assertion of this pin indicates that

the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden.

port 0 to form a single x8 port. The SerDes lanes associated with port 1 become lanes 4 through 7 of port 0.

port 2 to form a single x8 port. The SerDes lanes associated with port 3 become lanes 4 through 7 of port 2.

Description

Table 2.1 Boot Configuration Vector Signals

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Notes

Signal

P45MERGEN I Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside

RSTHALT

SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T6G2

MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz.

RSTHALT is not available in the 19mm package.

May Be

Overridden

port 4 to form a single x8 port. The SerDes lanes associated with port 5 become lanes 4 through 7 of port 4.

PES24T6G2 and initiates a PCI Express fundamental reset.

I Reset Halt. When this signal is asserted during a PCI Express fun-

damental reset, PES24T6G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master.

switch operating mode. 0x0 -Normal switch mode 0x1 -Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN.

Table 2.1 Boot Configuration Vector Signals

Description

Reset

The PES24T6G2 defines four Conventional Reset categories: Fundamental reset, Hot Reset, Upstream Secondary Bus Hot-Reset, and Downstream Secondary Bus Hot-Reset.

– A Fundamental Reset causes all logic in the PES24T6G2 to be returned to an initial state. – A Hot Reset causes all logic in the PES24T6G2 to be returned to an initial state, but does not

cause the state of register fields denoted as “sticky” to be modified.

– An Upstream Secondary Bus Reset causes all devices on the virtual PCI bus to be hot reset

except the upstream port (i.e., upstream PCI to PCI bridge).

– A Downstream Secondary Bus Reset causes a hot reset to be propagated on the corresponding

external secondary bus link.

There are two sub-categories of Fundamental Reset: Cold reset and Warm reset. A Cold Reset occurs following the PES24T6G2 being powered on and assertion of PERSTN. A Warm Reset is a Fundamental Reset that occurs without removal of power.

Fundamental Reset

A Fundamental Reset may be initiated by any of the following conditions:

– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input

pin.

– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power

is on.

– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch

Control (SWCTL) register.

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Notes

When configured to operate in normal mode, the following reset sequence is executed.

1. Wait for the Fundamental Reset condition to clear (e.g., negation of PERSTN). Note that PERSTN must be asserted for at least 100ms (Tpvperl) after the PES24T6G2 power supplies are stable, and 100µs (Tperst-clk) after the reference clock input is stable.

2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.1. If PERSTN was not asserted, use the previously sampled boot configuration signal values (e.g., when a Fundamental Reset is the result of setting the Fundamental Reset (FRST) bit in the Switch Control (SWCTL) register).

3. Examine the state of the sampled SWMODE[2:0] signals to determine the switch operating mode.

4. The PLL and SerDes are initialized (i.e., PLL/CDR reset and lock).

5. Link training begins. While link training is in progress, proceed to step 6.

6. If the Reset Halt (RSTHALT) pin is asserted, the RSTHALT bit in the SWSTS register is set.

7. If the switch operating mode is not a test mode, then the reset signal to the PCI Express stacks and associated logic is negated but they are held in a quasi-reset state in which the following actions occur.

• All links enter an active link training state within 20ms of the clearing of the Fundamental Reset condition.

• Within 100ms of the clearing of the Fundamental Reset condition, all of the stacks are able to process configuration transactions and respond to these transactions with a configuration request retry status completion. All other transactions are ignored.

8. The master SMBus operating frequency is determined.

The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is initialized to operate at 100 KHz rather than 400 KHz.

9. The slave SMBus is taken out of reset and initialized. The slave SMBus address specified by the SSMBADDR[5,3:1] pins is used.

10. The master SMBus is taken out of reset and initialized.

11. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then the contents of the serial EEPROM are read and the appropriate PES24T6G2 registers are updated.

• If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using the current link parameters.

• If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the SMBUSSTS register.

When serial EEPROM initialization completes or when an error is detected, the EEPROM Done (EEPROMDONE) bit in the SMBUSSTS register is set. If the RSTHALT bit is set in the SWCTL register, return to step 11. Otherwise, proceed to step 12.

12. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state except the master and slave SMBuses, the control/status registers, and the stacks which continue to be held in a quasi-reset state and respond to configuration transactions with a retry. The device remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an external agent may read and write any internal control and status registers and may access the external serial EEPROM via the EEPROMINTF register.

13. Normal device operation begins.

The PCIe specification indicates that a device must respond to Configuration Request transactions within 100 ms from the end of Conventional Reset (cold, warm, or hot). Additionally, the PCIe specification indicates that a device must respond to Configuration Requests with a Successful Completion within 1.0 second after Conventional Reset of a device. The reset sequence above guarantees that the PES24T6G2 will be ready to respond successfully to configuration request within the 1.0 second period as long as the serial EEPROM initialization process completes within 200 ms. During EEPROM initialization, the

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IDT Clocking, Reset and Initialization

Notes

REFCLK*

Vdd

PERSTN

SerDes

Master SMBus

Slave SMBus

Tpvperl (100ms)

CDR Reset & Lock

Ready for Normal Operation

ReadyIdle

Serial EEPROM Initialization

~70s

20 ms max.

Stacks held in Quasi-Reset Mode

Link Training

50 µs max

PLL Lock

Tperst-clk

(100µs)

Notes:

1) Reference Clock (REFCLK) not shown to scale.

2) The PES24T6G2 requires a minimum time for Tperst-clk of 1µs. The PES24T6G2 requires a minimum time for Tpvperl of 1ms.

3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PES24T6G2 is used. For example, the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.

PES24T6G2 responds to a Configuration Request with Configuration-Request-Retry-Status Completion. Under normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a Master SMBus operating frequency of 100 KHz.

Serial EEPROM initialization may cause writes to register fields that initiate side effects, such as link retraining. These side effects are initiated at the point where the write occurs. Therefore, serial EEPROM initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these side effects.

A warm reset initiated by a configuration request writing a one to the Fundamental Reset (FRST) bit in the Switch Control (SWCTL) register always results in to the requester before the warm reset process begins. The PES24T6G2 provides a reset output signal for each downstream port implemented as a GPIO alternate function. When a Fundamental Reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they are used as reset outputs.

The operation of a Fundamental Reset with serial EEPROM initialization (i.e., SWMODE[2:0] = 0x1) is illustrated in Figure 2.1.

the PES24T6G2 returning a Successful Completion

Figure 2.1 Fundamental Reset with Serial EEPROM initialization

PES24T6G2 User Manual 2 - 4 April 30, 2013

The operation of a Fundamental Reset using RSTHALT is illustrated in Figure 2.2.

Page 39

IDT Clocking, Reset and Initialization

Notes

SerDes

Slave SMBus

CDR Reset & Lock

Ready for Normal Operation

~70



20 ms max.

Stacks held in Quasi-Reset Mode

Link Training

PLL Lock

RSTHALT

RSTHALT bit in SWCTL register is set

RSTHALT bit in SWCTL cleared (i.e., by slave SMBus)

REFCLK*

Vdd

PERSTN

Tpvperl (100ms)

Tperst-clk (100us)

Notes:

1) Reference Clock (REFCLK) not shown to scale.

2) The PES24T6G2 requires a minimum time for Tperst-clk of 1µs. The PES24T6G2 requires a minimum time for Tpvperl of 1ms.

Figure 2.2 Fundamental Reset using RSTHALT to keep device in Quasi-Reset state

Hot Reset

A hot reset may be initiated by any of the following conditions:

– Reception of TS1 ordered-sets on the upstream port indicating a hot reset. – Data link layer of the upstream port transitions to the DL_Down state. – Writing a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL) register.

The initiation of a hot reset due to the data link layer of the upstream port transitioning to the DL_Down state may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the Switch Control (SWCTL) register. Other hot reset conditions are unaffected by this bit.

When a hot reset occurs, the following sequence is executed.

1. Each downstream port whose link is up propagates the hot reset by transmitting TS1 ordered sets with the hot reset bit set.

2. All of the logic associated with the PES24T6G2 except the PLLs, SerDes, master SMBus interface, and slave SMBus interface is reset.

3. All registers fields in all registers, except those denoted as “sticky” or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields denoted as “sticky” or RWL is preserved across a hot reset.

4. Link training begins. While link training is in progress, proceed to step 6.

5. The PCI Express stacks and associated logic are held in a quasi-reset state in which the following actions occur.

6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control (SWCTL) register, the contents of the serial EEPROM are read and the appropriate PES24T6G2 registers are updated.

• All links enter an active link training state within 20ms of the clearing of the hot reset condition.

• Within 100ms of the clearing of the Hot Reset condition, all of the stacks are able to process

configuration transactions and respond to these transactions with a configuration request retry status completion. All other transactions are ignored.

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IDT Clocking, Reset and Initialization

Notes

• If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State 0 (PHYLSTATE0) register, link retraining is initiated on the corresponding port using the current link parameters.

• When serial EEPROM initialization completes or when an error is detected, the DONE bit in the SMBUSSTS register is set.

7. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state except the master and slave SMBuses. The RSTHALT bit is only set if serial EEPROM initialization is enabled in step 6.

8. Normal device operation begins.

The operation of the slave SMBus interface is unaffected by a hot reset. Using the slave SMBus to access a register that is reset by a hot reset causes zero to be returned on a read and written data to be ignored on writes. A hot reset initiated by the writing of a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL) register always results in the hot reset process begins. Additionally, the upstream link is fully retrained (i.e., the upstream LTSSM transitions to the Detect state).

Upstream Secondary Bus Reset

An Upstream Secondary Bus Reset may be initiated by the following condition:

– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (i.e., port 0)

Bridge Control Register (BCTL).

When an Upstream Secondary Bus Reset occurs, the following sequence is executed.

the PES24T6G2 returning a completion to the requester before

1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with the hot reset bit set.

2. All registers fields in all registers associated with downstream ports, except those denoted as “sticky” or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields denoted as “sticky” or RWL is unaffected by an Upstream Secondary Bus Reset.

3. All TLPs received from downstream ports and queued in the PES24T6G2 are discarded.

4. Logic in the stack, application layer, and switch core associated with the downstream ports are gracefully reset.

5. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge Control Register (BCTL).

6. Normal downstream port operation begins.

The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and Type 0 configuration read and write transactions that target the upstream port complete normally. During an Upstream Secondary Bus Reset, all TLPs destined to the secondary side of the upstream port’s PCI-to-PCI bridge are treated in an undefined manner. The user should ensure no TLPs are sent to the secondary side of the upstream port’s PCI-to-PCI bridge until the SRESET bit in the BCTL register is cleared.

The operation of the slave SMBus interface is unaffected by an Upstream Secondary Bus Reset. Using the slave SMBus to access a register that is reset by an Upstream Secondary Bus Reset causes the register’s default value to be returned on a read and written data to be ignored on writes.

Downstream Secondary Bus Reset

A Downstream Secondary Bus Reset may be initiated by the following condition:

– A one is written to the Secondary Bus Reset (SRESET) bit in a downstream port’s (i.e., port 0)

Bridge Control Register (BCTL).

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IDT Clocking, Reset and Initialization

Notes

PxPEP

PxRSTN

PWR2RST

RST2PWR

When a Downstream Secondary Bus Reset occurs, the following sequence is executed.

1. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted.

2. All TLPs received from corresponding downstream port and queued in the PES24T6G2 are discarded.

3. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge Control Register (BCTL).

4. Normal downstream port operation begins.

The operation of the upstream port is unaffected by a Downstream Secondary Bus Reset. The operation of other downstream ports is unaffected by a Downstream Secondary Bus Reset. During a Downstream Secondary Bus Reset, Type 0 configuration read and write transactions that target the downstream port complete normally. During a Downstream Secondary Bus Reset, all TLPs destined to the secondary side of the downstream port’s PCI-to-PCI bridge are treated as unsupported requests. The operation of the slave SMBus interface is unaffected by a Downstream Secondary Bus Reset.

Downstream Port Reset Outputs

Individual downstream port reset outputs (P1RSTN, P2RSTN, P3RSTN, P4RSTN, P5RSTN, P6RSTN, and P7RSTN) are provided as GPIO pin alternate functions. Following a Fundamental Reset, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they are used as reset outputs.

The PES24T6G2 ensures through hardware that the minimum PxRSTN assertion pulse width is no less than 200 µs.

Downstream port reset outputs can be configured to operate in one of two modes. These modes are power enable controlled reset output and power good controlled reset output. The downstream port reset output mode is determined by the Reset Mode (RSTMODE) field in the Hot-Plug Configuration Control (HPCFGCTL) register.

Power Enable Controlled Reset Output

In this mode, a downstream port reset output state is controlled as a side effect of slot power being turned on or off. The operation of this mode is illustrated in Figure 2.3. A downstream port’s slot power is controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register

Figure 2.3 Power Enable Controlled Reset Output Mode Operation

While slot power is disabled, the corresponding downstream port reset output is asserted. When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and then power to the slot is enabled and the corresponding downstream port reset output is negated. The time between the assertion of the PxPEP signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.

While slot power is enabled, the corresponding downstream port reset output is negated. When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power (RST2PWR) field in the HPCFGCTL register.

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Notes

PxPEP

PxPWRGDN

PWR2RST

PxRSTN

RST2PWR

Power Good Controlled Reset Output

As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on the power good state of the slot’s power supply. The operation of this mode is illustrated in Figure 2.4.

The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that when power is enabled, the negation of the corresponding port reset output occurs as a result of and after assertion of the slot’s Power Good (PxPWRGDN) signal is observed. The time between the assertion of the PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.

When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power (RST2PWR) field in the HPCFGCTL register.

If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is detected (i.e., PxPWRGDN is negated), then the corresponding port reset output is immediately asserted. Since the PxPWRGDN signal is an I/O expander input, it may not be possible to meet a profile’s power level invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a shorter time interval may implement this functionality external to the PES24T6G2.

Figure 2.4 Power Good Controlled Reset Output Mode Operation

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Notes

Chapter 3

PExRP[0] PExRP[1] PExRP[2] PExRP[3]

PES24T6G2

lane 0 lane 1 lane 2 lane 3

(a) x4 Port without lane reversal

PExRP[0] PExRP[1] PExRP[2] PExRP[3]

PES24T6G2

lane 3 lane 2 lane 1 lane 0

(b) x4 Port with lane reversal

PExRP[0] PExRP[1] PExRP[2] PExRP[3]

PES24T6G2

lane 0 lane 1

(a) x2 Port without lane reversal

PExRP[0] PExRP[1] PExRP[2] PExRP[3]

PES24T6G2

lane 1 lane 0

(b) x2 Port with lane reversal

PExRP[0] PExRP[1] PExRP[2] PExRP[3]

PES24T6G2

lane 0

(a) x1 Port without lane reversal

PExRP[0] PExRP[1] PExRP[2] PExRP[3]

PES24T6G2

lane 0

(b) x1 Port with lane reversal

Link Operation

Introduction

Link operation in the PES24T6G2 adheres to the PCI Express 2.0 Base Specification, supporting speeds of 2.5 Gbps and 5.0 Gbps. The PES24T6G2 contains six x4 ports which may be merged in pairs to form x8 ports. The default link width of each port is x4 and the SerDes lanes are statically assigned to a port. A full link retrain is defined as retraining of a link that transitions through the Detect LTSSM state.

Polarity Inversion

Each port of the PES24T6G2 supports automatic polarity inversion as required by the PCIe specification. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its data. During link training, the receiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receiving lane automatically inverts received data. Polarity inversion is a lane and not a link function. Therefore, it is possible for some lanes of link to be inverted and for others to not be inverted.

Lane Reversal

The PCIe specification describes an optional lane reversal feature. The PES24T6G2 offers limited support for the automatic lane reversal feature outlined in the PCIe specification. Lane reversal mapping for the various configurations supported by the PES24T6G2 are illustrated in Figures 3.1 and 3.2.

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Figure 3.1 Unmerged Port Lane Reversal

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