IDT 89HPES24N3A User Manual

Download

Page 1

IDT™ 89HPES24N3A

PCI Express® Switch

User Manual

April 2008

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284- 2775

Printed in U.S.A.

Page 2

Integrated Device Technology, Inc. reserves t h e right to make changes to its produc ts or specifications at any time, without notice, in order to improve design or perfor mance and to supply the best possible product. IDT does not assume any responsibility for use of any circui try described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

GENERAL DISCLAIMER

Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely at your own risk. IDT MAKES NO REPRESENTA T IONS OR WARRANTIES OF ANY KIND CONCERNI NG THE NONINFR INGEMEN T, QUALIT Y, SAF ETY OR SU ITABILITY OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WIT HOUT LIMITATION ANY IMPLIED W A RR ANTIES OF MERCHANTABIL ITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENT ATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY O R COMPL ETENES S OF ANY STATEMENTS, INFORMATION OR MAT ERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code examples also ma y b e s ubj ec t t o U ni ted S ta tes e xpo rt con tro l l aws and m ay be subject to the export or imp ort laws of ot he r co un tries and it i s your re sponsi bilit y to comply with any applicable l aws or regulations .

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agr eement pertaining to such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for su rgical implant into the body or (b) support or sustain life and whose failure to perform, when properly us ed in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a significant injury to the user.

2. A critical co mpo nent is an y com pon en t s of a lif e sup po rt dev ice or sy s te m who se f ai lu re t o perform can be reasonably expect ed to cause the failure of the life support device or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trade m arks or registered trademarks of Integrated Device Technology , Inc.

CODE DISCLAIMER

LIFE SUPPORT POLICY

Page 3

About This Manual

Notes

Introduction

This user manual includes hardware and software information on the 89HPES24N3A, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard.

Finding Additional Information

Information not included in this manual such as mechanicals, package pin-outs, and electrical characteristics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.

Content Summary

Chapter 1, “PES24N3A Device Overview,” provides a complete introduction to the performance capabilities of the 89HPES24N3A. Included in this chapter is a summary of features for the device as well as a system block diagram and pin description.

Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes.

Chapter 3, “Theory of Operation,” provides basic information on the architecture and operation of the 89HPES24N3A chip.

Chapter 4, “Link Operation,” describes the operation of the link feature including polarity inversion, link width negotiation, and lane reversal.

Chapter 4, “Switch Operation,” discusses the procedure for forwarding PCIe® TLPs between switch ports.

Chapter 5, “General Purpose I/O,” describes how the 8 General Purpose I/O (GPIO) pins may be individually configured as general purpose inputs, general purpose outputs, or alternate functions.

Chapter 6, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES24N3A.

Chapter 7, “Power Management,” describes the power management capability structure located in the

configuration space of each PCI-PCI bridge in the PES24N3A.

Chapter 8, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in the PES24N3A.

Chapter 9, “Configuration Registers,” discusses the base addresses, PCI configuration space, and registers associated with the PES24N3A.

Chapter 10, “JT AG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.

Signal Nomenclature

To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. T he term negate or negation is used to indicate that a signal is inactive or false.

PES24N3A User Manual 1 April 10, 2008

Page 4

IDT

Notes

To define the ac tive polarity of a si gnal, a s uffix will be used. Signal s ending with an ‘N’ s hould be i nterpreted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the right. No leading zeros will be included.

Throughout this manual, when describing signal transitions, the following terminology is used. Rising edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These terms are illustrated in Figure 1.

single clock cycle

1 2 3 4

high-to-low

transition

low-to-high

transition

Figure 1 Signal Transitions

Numeric Representations

To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows: 0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[x:y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD if x < y or to ABCxD, ABC(x-1)D, ABC(x-2)D,... ABCyD if x > y.

Data Units

The following data unit terminology is used in this document.

Term Words Bytes Bits

Byte 1/2 1 8 Word 1 2 16 Doubleword (Dword) 2 4 32 Quadword (Qword) 4 8 64

Table 1 Data Unit Terminology

In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In doublewords, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always the most significant bit and bit 0 is the leas t significant bit. In bytes, bit 7 is always the most significant bit and bit 0 is the least significant bit.

PES24N3A User Manual 2 April 10, 2008

Page 5

IDT

Notes

The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte of a word. See Figure 2.

bit 0bit 31

0 1 2 3

Address of Bytes within Words: Big Endian

bit 0bit 31

3 2 1 0

Address of Bytes within Words: Little Endian

Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

Software in the context of this register terminology refers to modifications made by PCIe root configuration writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initialization. See Table 2.

Type Abbreviation Description

Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms

such as pin strapping or serial EEPROM. (System firmware hardware initialization is only allowed for system integrated devices.) Bits are read-only after initialization and can only be reset (for write-once by firmware) with reset.

Read Only and Clear RC Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bit to be reset to zero. Writing to a RC location has no effect.

Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bits to be reset to zero. Writes cause the register/bits to be modified.

Reserved Reserved The value read from a reserved register/bit is undefined. Thus,

software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back.

Read Only RO Software can only read registers/bits with this attribute. Contents

are hardwired to a constant value or are status bits that may be set and cleared by hardware. Writing to a RO location has no effect.

Read and Write RW Software can both read and write bits with this attribute.

Table 2 Register Terminology (Sheet 1 of 2)

PES24N3A User Manual 3 April 10, 2008

Page 6

IDT

Notes

Type Abbreviation Description

Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.

However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event. To clear a RW1C bit (i.e., change its value to zero) a value of one must be written to the location. An RW1C bit is never cleared by hardware.

Read and Write when Unlocked

Write Transient WT The zero is always read from a bit/field of this type. Writing of a

Zero Zero A zero register or bit must be written with a value of zero and

RWL Software can read the register/bits with this attribute. Writing to

register/bits with this attribute will only cause the value to be modified if the REGUNLOCK bit in the SWCTL register is set. When the REGUNLOCK bit is cleared, writes are ignored and the register/bits are effectively read-only

one is used to quality the writing of other bits/fields in the same register.

returns a value of zero when read.

Table 2 Register Terminology (Sheet 2 of 2)

Use of Hypertext

In Chapter 9, Tables 9.2 and 9.3 contain register names and page numbers highlighted in blue under the Register Definition column. In pdf files, users can jump from this source table directly to the registers by clicking on the register name in the source table. Each register name in the table is linked directly to the appropriate register in the register section of the chapter. To return to the source table after havi ng jumped to the register section, click on the same register name (in blue) in the register section.

Reference Documents

PCI Express Base Specification, Revision 2.0, PCI Special Interest Group. PCI Power Management Interface Specification, Revision 1.1, PCI Special Interest Group. PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group. SMBus Specification, Revision 2.0.

Revision History

February 8, 2007: Initial Publication.

May 30, 2007: In Table 1.2, added revision information for ZG silicon. Added Notes to Figure 2.5.

July 18, 2007: In Chapter 9, changed bits [10:9] in HPCFGCTL from RO to RW. In Chapter 2, changed

references to correctly state SRESET field is in BCTL register, not the SWCTL register.

April 10, 2008: In the About section, Table 2, changed SYSCNTL to SWCTL. In Chapter 9, changed default value for VER field in PCIECAP register from 0x2 to 0x1 and changed 0x0 definition for bit EEPE in SWPERCTL register from “time-out” to “end-to-end parity error”.

PES24N3A User Manual 4 April 10, 2008

Page 7

Table of Contents

Notes

About This Manual

Introduction ....................................................................................................................................1

Content Summary ..........................................................................................................................1

Signal Nomenclature .....................................................................................................................1

Numeric Representations ..............................................................................................................2

Data Units ......................................................................................................................................2

Register Terminology .....................................................................................................................3

Use of Hypertext ............................................................................................................................4

Reference Documents ...................................................................................................................4

Revision History .............................................................................................................................4

PES24N3A Device Overview

Introduction.....................................................................................................................................1-1

List of Features...............................................................................................................................1-1

System Diagrams............................................................................................................................1-3

Logic Diagram.................................................................................................................................1-4

System Identification.......................................................................................................................1-5

Vendor ID................................................................................................................................1-5

Device ID................................................................................................................................1-5

Revision ID.............................................................................................................................1-5

JTAG ID..................................................................................................................................1-5

SSID/SSVID............................................................................................................................1-5

Device Serial Number Enhanced Capability...........................................................................1-5

Pin Description................................................................................................................................1-6

Pin Characteristics..........................................................................................................................1-9

Clocking, Reset, and Initialization

Introduction.....................................................................................................................................2-1

Initialization.....................................................................................................................................2-3

Reset...............................................................................................................................................2-4

Fundamental Reset................................................................................................................2-4

Hot Reset................................................................................................................................2-6

Upstream Secondary Bus Reset............................................................................................2-7

Downstream Secondary Bus Reset........................................................................................2-7

Downstream Port Reset Outputs....................................................................................................2-8

Power Enable Controlled Reset Output..................................................................................2-8

Power Good Controlled Reset Output....................................................................................2-9

Hot Reset Controlled Reset Output........................................................................................2-9

Theory of Operation

Introduction.....................................................................................................................................3-1

Data Paths......................................................................................................................................3-2

Store-and-Forward vs. Cut-Through Switching and Latency..........................................................3-2

Switch Core.....................................................................................................................................3-3

Transaction Routing................................................................................................................3-4

Transaction Reordering..........................................................................................................3-4

Scheduling and Port Arbitration..............................................................................................3-5

PES24N3A User Manual i April 10, 2008

Page 8

IDT Table of Contents

Notes

Peer-to-Peer Transactions..............................................................................................................3-8

Bus Locking....................................................................................................................................3-8

Port Interrupts...............................................................................................................................3-10

Legacy Interrupt Emulation...........................................................................................................3-10

Standard PCIe Error Detection and Handling...............................................................................3-11

Physical Layer Errors ...........................................................................................................3-11

Data Link Layer Errors..........................................................................................................3-11

Transaction Layer Errors......................................................................................................3-12

Routing Errors ......................................................................................................................3-14

Switch Specific Error Detection and Handling..............................................................................3-15

Switch Time-Outs.................................................................................................................3-16

End-to-End Parity Checking.................................................................................................3-16

TLP Processing ............................................................................................................................3-17

Link Operation

Introduction.....................................................................................................................................4-1

Polarity Inversion............................................................................................................................4-1

Link Width Negotiation....................................................................................................................4-1

Lane Reversal.................................................................................................................................4-1

Link Retraining................................................................................................................................4-4

Link Down.......................................................................................................................................4-5

Slot Power Limit Support................................................................................................................4-5

Upstream Port ........................................................................................................................4-5

Downstream Port....................................................................................................................4-5

Link States......................................................................................................................................4-5

Active State Power Management ...................................................................................................4-6

Link Status......................................................................................................................................4-7

General Purpose I/O

Introduction.....................................................................................................................................5-1

GPIO Configuration ........................................................................................................................5-1

GPIO Pin Configured as an Input...........................................................................................5-2

GPIO Pin Configured as an Output........................................................................................5-2

GPIO Pin Configured as an Alternate Function......................................................................5-2

SMBus Interf aces

Introduction.....................................................................................................................................6-1

Master SMBus Interface.................................................................................................................6-2

Initialization.............................................................................................................................6-2

Serial EEPROM......................................................................................................................6-2

I/O Expanders.........................................................................................................................6-6

Slave SMBus Interface.................................................................................................................6-11

Initialization...........................................................................................................................6-11

SMBus Transactions ............................................................................................................6-11

Power Management

Introduction.....................................................................................................................................7-1

PME Messages...............................................................................................................................7-2

Power Express Power Management Fence Protocol.....................................................................7-3

Power Budgeting Capability............................................................................................................7-3

PES24N3A User Manual ii April 10, 2008

Page 9

IDT Table of Contents

Notes

Hot-Plug and Hot-Swap

Introduction.....................................................................................................................................8-1

Hot-Plug I/O Expander ...........................................................................................................8-4

Hot-Plug Interrupts and Wake-up...........................................................................................8-4

Legacy System Hot-Plug Support ..........................................................................................8-4

Hot-Swap........................................................................................................................................8-6

Configuration Registers

Introduction.....................................................................................................................................9-1

Upstream Port (Port 0) ...........................................................................................................9-3

Downstream Ports (Ports 2 and 4).........................................................................................9-8

Register Definitions.......................................................................................................................9-11

Type 1 Configuration Header Registers...............................................................................9-11

PCI Express Capability Structure.........................................................................................9-21

Power Management Capability Structure.............................................................................9-33

Message Signaled Interrupt Capability Structure.................................................................9-34

Subsystem ID and Subsystem Vendor ID............................................................................9-36

Extended Configuration Space Access Registers................................................................9-36

Advanced Error Reporting (AER) Enhanced Capability.......................................................9-37

Device Serial Number Enhanced Capability.........................................................................9-43

PCI Express Virtual Channel Capability...............................................................................9-43

Power Budgeting Enhanced Capability................................................................................9-49

Switch Control and Status Registers....................................................................................9-50

Internal Switch Error Control and Status Registers..............................................................9-61

JTAG Boundary Scan

Introduction...................................................................................................................................10-1

Test Access Point.........................................................................................................................10-1

Signal Definitions..........................................................................................................................10-1

Boundary Scan Chain...................................................................................................................10-3

Test Data Register (DR)...............................................................................................................10-4

Boundary Scan Registers.....................................................................................................10-4

Instruction Register (IR)................................................................................................................10-6

EXTEST................................................................................................................................10-6

SAMPLE/PRELOAD.............................................................................................................10-7

BYPASS...............................................................................................................................10-7

CLAMP.................................................................................................................................10-7

IDCODE................................................................................................................................10-7

VALIDATE............................................................................................................................10-8

RESERVED..........................................................................................................................10-8

Usage Considerations..........................................................................................................10-8

PES24N3A User Manual iii April 10, 2008

Page 10

IDT Table of Contents

Notes

PES24N3A User Manual iv April 10, 2008

Page 11

List of Tables

Notes

Table 1.1 PES24N3A Device ID..........................................................................................................1-5

Table 1.2 PES24N3A Revision ID.......................................................................................................1-5

Table 1.3 PCI Express Interface Pins..................................................................................................1-6

Table 1.4 SMBus Interface Pins..........................................................................................................1-6

Table 1.5 General Purpose I/O Pins....................................................................................................1-7

Table 1.6 System Pins.........................................................................................................................1-7

Table 1.7 Test Pins..............................................................................................................................1-8

Table 1.8 Power and Ground Pins.......................................................................................................1-8

Table 1.9 Pin Characteristics...............................................................................................................1-9

Table 2.1 Reference Clock Mode Encoding........................................................................................2-1

Table 2.2 Boot Configuration Vector Signals.......................................................................................2-3

Table 3.1 IFB Buffer Sizes...................................................................................................................3-1

Table 3.2 PES24N3A Buffer Sizes......................................................................................................3-2

Table 3.3 Bus Decoupler Queue and Insertion Buffer Size.................................................................3-2

Table 3.4 Latency................................................................................................................................3-3

Table 3.5 Switch Routing Methods......................................................................................................3-4

Table 3.6 IFB Transaction Ordering....................................................................................................3-5

Table 3.7 Downstream Port Interrupts...............................................................................................3-10

Table 3.8 PES24N3A Downstream to Upstream Port Interrupt Routing...........................................3-11

Table 3.9 Physical Layer Errors.........................................................................................................3-11

Table 3.10 Data Link Layer Errors.......................................................................................................3-12

Table 3.11 Transaction Layer Errors...................................................................................................3-12

Table 3.12 Ingress Malformed TLP Error Checks...............................................................................3-13

Table 3.13 Egress Malformed TLP Error Checks................................................................................3-14

Table 5.1 General Purpose I/O Pin Alternate Function.......................................................................5-1

Table 5.2 GPIO Pin Configuration.......................................................................................................5-1

Table 6.1 Serial EEPROM SMBus Address........................................................................................6-2

Table 6.2 PES24N3A Compatible Serial EEPROMs ...........................................................................6-3

Table 6.3 Serial EEPROM Initialization Errors....................................................................................6-5

Table 6.4 I/O Expander Function Allocation........................................................................................6-6

Table 6.5 I/O Expander 0 Signals........................................................................................................6-9

Table 6.6 I/O Expander 2 Signals......................................................................................................6-10

Table 6.7 I/O Expander 4 Signals......................................................................................................6-10

Table 6.8 Slave SMBus Address When a Static Address is Selected...............................................6-11

Table 6.9 Slave SMBus Command Code Fields...............................................................................6-12

Table 6.10 CSR Register Read or Write Operation Byte Sequence...................................................6-13

Table 6.11 CSR Register Read or Write CMD Field Description.........................................................6-13

Table 6.12 Serial EEPROM Read or Write Operation Byte Sequence................................................6-14

Table 6.13 Serial EEPROM Read or Write CMD Field Description.....................................................6-15

Table 7.1 PES24N3A Power Management State Transition Diagram.................................................7-2

Table 8.1 Downstream Port Hot-Plug Signals.....................................................................................8-3

Table 9.1 Base Addresses for Port Configuration Space Registers....................................................9-1

Table 9.2 Upstream Port 0 Configuration Space Registers.................................................................9-3

Table 9.3 Downstream Ports 2 and 4 Configuration Space Registers................................................9-8

Table 10.1 JTAG Pin Descriptions.......................................................................................................10-2

Table 10.2 Boundary Scan Chain........................................................................................................10-3

Table 10.3 Instructions Supported by PES24N3A’s JTAG Boundary Scan........................................10-6

Table 10.4 System Controller Device Identification Register...............................................................10-7

PES24N3A User Manual v April 10, 2008

Page 12

IDT List of Tables

Notes

PES24N3A User Manual vi April 10, 2008

Page 13

List of Figures

Notes

Figure 1.1 PES24N3A Architectural Block Diagram ............................................................................1-3

Figure 1.2 I/O Expansion Application ..................................................................................................1-3

Figure 1.3 PES24N3A Logic Diagram .................................................................................................1-4

Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread

Spectrum Clock) ................................................................................................................2-1

Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable

Spread Spectrum Clock) ....................................................................................................2-2

Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable

Spread Spectrum Clock) ....................................................................................................2-2

Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum

Clock) .................................................................................................................................2-3

Figure 2.5 Fundamental Reset in Transparent Mode with Serial EEPROM initialization ....................2-6

Figure 2.6 Power Enable Controlled Reset Output Mode Operation ..................................................2-8

Figure 2.7 Power Good Controlled Reset Output Mode Operation .....................................................2-9

Figure 3.1 Simplified Switch Core U-Bus and D-Bus Datapath ...........................................................3-3

Figure 3.2 U-Bus Arbitration ................................................................................................................3-7

Figure 4.1 Port Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[5:0]=0x2) ................4-2

Figure 4.2 Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[5:0]=0x4) ................4-3

Figure 4.3 Port Lane Reversal for Maximum Link Width of x8 (MAXLNKWDTH[5:0]=0x8) ................4-4

Figure 4.4 PES24N3A ASPM Link Sate Transitions ...........................................................................4-6

Figure 6.1 SMBus Interface Configuration Examples .........................................................................6-1

Figure 6.2 Single Double Word Initialization Sequence Format ..........................................................6-3

Figure 6.3 Sequential Double Word Initialization Sequence Format ...................................................6-4

Figure 6.4 Configuration Done Sequence Format ..............................................................................6-4

Figure 6.5 Slave SMBus Command Code Format ............................................................................6-12

Figure 6.6 CSR Register Read or Write CMD Field Format ..............................................................6-13

Figure 6.7 Serial EEPROM Read or Write CMD Field Format ..........................................................6-15

Figure 6.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC

Disabled ...........................................................................................................................6-16

Figure 6.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC

Disabled ...........................................................................................................................6-16

Figure 6.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........6-16

Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........6-17

Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........6-17

Figure 6.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....6-18

Figure 7.1 PES24N3A Power Management State Transition Diagram ...............................................7-1

Figure 8.1 Hot-Plug on Switch Downstream Slots Application ............................................................8-1

Figure 8.2 Hot-Plug with Switch on Add-In Card Application ..............................................................8-2

Figure 8.3 Hot-Plug with Carrier Card Application ..............................................................................8-2

Figure 8.4 PES24N3A Hot-Plug Event Signalling ...............................................................................8-5

Figure 9.1 Port Configuration Space Organization .............................................................................9-2

Figure 10.1 Diagram of the JTAG Logic ..............................................................................................10-1

Figure 10.2 State Diagram of PES24N3A’s TAP Controller ................................................................10-2

Figure 10.3 Diagram of Observe-only Input Cell .................................................................................10-4

Figure 10.4 Diagram of Output Cell ....................................................................................................10-5

Figure 10.5 Diagram of Bidirectional Cell ............................................................................................10-5

Figure 10.6 Device ID Register Format ...............................................................................................10-7

PES24N3A User Manual vii April 10, 2008

Page 14

IDT List of Figures

Notes

PES24N3A User Manual viii April 10, 2008

Page 15

Notes

AERCAP - AER Capabilities (0x100)..................................................................................................... 9-37

AERCEM - AER Correctable Error Mask (0x114).................................................................................. 9-41

AERCES - AER Correctable Error Status (0x110)................................................................................. 9-41

AERCTL - AER Control (0x118)............................................................................................................. 9-42

AERHL1DW - AER Header Log 1st Doubleword (0x11C)..................................................................... 9-42

AERHL2DW - AER Header Log 2nd Doubleword (0x120)..................................................................... 9-42

AERHL3DW - AER Header Log 3rd Doubleword (0x124)...................................................................... 9-42

AERHL4DW - AER Header Log 4th Doubleword (0x128)...................................................................... 9-43

AERUEM - AER Uncorrectable Error Mask (0x108).............................................................................. 9-38

AERUES - AER Uncorrectable Error Status (0x104)............................................................................. 9-37

AERUESV - AER Uncorrectable Error Severity (0x10C)........................................................................ 9-39

BAR0 - Base Address Register 0 (0x010).............................................................................................. 9-15

BAR1 - Base Address Register 1 (0x014).............................................................................................. 9-15

BCTRL - Bridge Control Register (0x03E).............................................................................................. 9-20

BIST - Built-in Self Test Register (0x00F).............................................................................................. 9-14

CAPPTR - Capabilities Pointer Register (0x034)................................................................................... 9-19

CCODE - Class Code Register (0x009)................................................................................................. 9-14

CLS - Cache Line Size Register (0x00C)............................................................................................... 9-14

DARBCTC - D-Bus Arbiter Current Transfer Count (0x464).................................................................. 9-60

DARBTC - D-Bus Arbiter Transfer Count (0x460).................................................................................. 9-60

DID - Device Identification Register (0x002).......................................................................................... 9-12

ECFGADDR - Extended Configuration Space Access Address (0x0F8)............................................... 9-36

ECFGDATA - Extended Configuration Space Access Data (0x0FC)..................................................... 9-37

EEPROMINTF - Serial EEPROM Interface (0x42C).............................................................................. 9-56

EROMBASE - Expansion ROM Base Address Register (0x038)........................................................... 9-19

GPECTL - General Purpose Event Control (0x450)............................................................................... 9-58

GPESTS - General Purpose Event Status (0x454)................................................................................ 9-59

GPIOCFG - General Purpose I/O Configuration (0x41C)....................................................................... 9-54

GPIOD - General Purpose I/O Data (0x420).......................................................................................... 9-54

GPIOFUNC - General Purpose I/O Control Function (0x418)................................................................ 9-54

GPR - General Purpose Register (0x40C).............................................................................................9-53

HDR - Header Type Register (0x00E).................................................................................................... 9-14

HPCFGCTL - Hot-Plug Configuration Control (0x408)........................................................................... 9-52

INTRLINE - Interrupt Line Register (0x03C)........................................................................................... 9-19

INTRPIN - Interrupt PIN Register (0x03D)............................................................................................. 9-19

IOBASE - I/O Base Register (0x01C)..................................................................................................... 9-16

IOBASEU - I/O Base Upper Register (0x030)........................................................................................ 9-18

IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434)..................................................................... 9-58

IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438)..................................................................... 9-58

IOEXPINTF - I/O Expander Interface (0x430)........................................................................................ 9-57

IOLIMIT - I/O Limit Register (0x01D)...................................................................................................... 9-16

IOLIMITU - I/O Limit Upper Register (0x032)......................................................................................... 9-19

MBASE - Memory Base Register (0x020).............................................................................................. 9-17

MLIMIT - Memory Limit Register (0x022)............................................................................................... 9-17

MSIADDR - Message Signaled Interrupt Address (0x0D4).................................................................... 9-35

MSICAP - Message Signaled Interrupt Capability and Control (0x0D0)................................................ 9-34

MSIMDATA - Message Signaled Interrupt Message Data (0x0DC)....................................................... 9-36

MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8)...................................................... 9-35

PBUSN - Primary Bus Number Register (0x018)................................................................................... 9-15

PES24N3A User Manual ix April 10, 2008

Page 16

IDT Register List

Notes

PCICMD - PCI Command Register (0x004)............................................................................................9-12

PCIECAP - PCI Express Capability (0x040) ...........................................................................................9-21

PCIEDCAP - PCI Express Device Capabilities (0x044)..........................................................................9-21

PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064).....................................................................9-31

PCIEDCTL - PCI Express Device Control (0x048)..................................................................................9-22

PCIEDCTL2 - PCI Express Device Control 2 (0x068).............................................................................9-31

PCIEDSTS - PCI Express Device Status (0x04A) ..................................................................................9-23

PCIEDSTS2 - PCI Express Device Status 2 (0x06A) .............................................................................9-31

PCIELCAP - PCI Express Link Capabilities (0x04C) ..............................................................................9-24

PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) .........................................................................9-31

PCIELCTL - PCI Express Link Control (0x050).......................................................................................9-25

PCIELCTL2 - PCI Express Link Control 2 (0x070)..................................................................................9-32

PCIELSTS - PCI Express Link Status (0x052)........................................................................................9-26

PCIELSTS2 - PCI Express Link Status 2 (0x072)...................................................................................9-32

PCIESCAP - PCI Express Slot Capabilities (0x054)...............................................................................9-27

PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074)..........................................................................9-32

PCIESCTL - PCI Express Slot Control (0x058).......................................................................................9-29

PCIESCTL2 - PCI Express Slot Control 2 (0x078)..................................................................................9-32

PCIESSTS - PCI Express Slot Status (0x05A) .......................................................................................9-30

PCIESSTS2 - PCI Express Slot Status 2 (0x07A) ..................................................................................9-33

PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200)................................................9-43

PCISTS - PCI Status Register (0x006) ...................................................................................................9-13

PLTIMER - Primary Latency Timer (0x00D)............................................................................................9-14

PMBASE - Prefetchable Memory Base Register (0x024).......................................................................9-17

PMBASEU - Prefetchable Memory Base Upper Register (0x028)..........................................................9-18

PMCAP - PCI Power Management Capabilities (0x0C0)........................................................................9-33

PMCSR - PCI Power Management Control and Status (0x0C4) ............................................................9-34

PMLIMIT - Prefetchable Memory Limit Register (0x026)........................................................................9-18

PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)..........................................................9-18

PVCCAP1- Port VC Capability 1 (0x204)................................................................................................9-44

PVCCAP2 - Port VC Capability 2 (0x208)...............................................................................................9-44

PVCCTL - Port VC Control (0x20C)........................................................................................................9-45

PVCSTS - Port VC Status (0x20E) .........................................................................................................9-45

PWRBCAP - Power Budgeting Capabilities (0x280)...............................................................................9-49

PWRBD - Power Budgeting Data (0x288)...............................................................................................9-49

PWRBDSEL - Power Budgeting Data Select (0x284).............................................................................9-49

PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300).................................................................9-50

PWRBPBC - Power Budgeting Power Budget Capability (0x28C) .........................................................9-50

RID - Revision Identification Register (0x008) ........................................................................................9-14

SBUSN - Secondary Bus Number Register (0x019)...............................................................................9-15

SECSTS - Secondary Status Register (0x01E) ......................................................................................9-16

SLTIMER - Secondary Latency Timer Register (0x01B).........................................................................9-15

SMBUSCTL - SMBus Control (0x428)....................................................................................................9-55

SMBUSSTS - SMBus Status (0x424) .....................................................................................................9-54

SNUMCAP - Serial Number Capabilities (0x180) ...................................................................................9-43

SNUMLDW - Serial Number Lower Doubleword (0x184) .......................................................................9-43

SNUMUDW - Serial Number Upper Doubleword (0x188).......................................................................9-43

SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4)...........................................................9-36

SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0)...................................9-36

SUBUSN - Subordinate Bus Number Register (0x01A)..........................................................................9-15

SWCTL - Switch Control (0x404)............................................................................................................9-51

SWPECNT - Switch Parity Error Count (0x74C).....................................................................................9-62

SWPECTL - Switch Parity Error Control (0x740)....................................................................................9-61

SWPERCTL - Switch Parity Error Reporting Control (0x748).................................................................9-62

SWPESTS - Switch Parity Error Status (0x744) .....................................................................................9-61

PES24N3A User Manual x April 10, 2008

Page 17

IDT Register List

Notes

SWSTS - Switch Status (0x400) .............................................................................................................9-50

SWTOCNT - Switch Time-Out Count (0x75C)........................................................................................9-64

SWTOCTL - Switch Time-Out Control (0x750).......................................................................................9-62

SWTORCTL - Switch Time-Out Reporting Control (0x758)....................................................................9-63

SWTOSTS - Switch Time-Out Status (0x754) ........................................................................................9-62

SWTOTSCTL - Switch Time-Out Time-Stamp Control (0x760)..............................................................9-64

SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8).............................................................9-61

UARBCTC - U-Bus Arbiter Current Transfer Count (0x45C) ..................................................................9-60

UARBTC - U-Bus Arbiter Transfer Count (0x458)...................................................................................9-59

VCR0CAP- VC Resource 0 Capability (0x210).......................................................................................9-45

VCR0CTL- VC Resource 0 Control (0x214)............................................................................................9-46

VCR0STS - VC Resource 0 Status (0x218)............................................................................................9-46

VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)..............................................................9-47

VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)..............................................................9-47

VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228)..............................................................9-48

VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C).............................................................9-48

VID - Vendor Identification Register (0x000)...........................................................................................9-11

PES24N3A User Manual xi April 10, 2008

Page 18

IDT Register List

Notes

PES24N3A User Manual xii April 10, 2008

Page 19

Chapter 1

PES24N3A Device Overview

Notes

Introduction

The 89HPES24N3A is a member of the IDT PRECISE™ family of PCI Express® switching s olutions. The PES24N3A is a 24-lane, 3-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high performance applications such as servers, storage, and communications/ networking. It provides connectivity and switching functions between a PCI Express upstream port and two downstream ports and supports switching between downstream ports

Utilizing standard PCI Express interconnect, the PES24N3A provides the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides connectivity for up to 3 ports across 24 integrated serial lanes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1.

The PES24N3A is based on a flexible and efficient layered architecture. The PCI Express layers consist of SerDes, Physical, Data Link and Transaction layers. The PES24N3A can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity.

List of Features



High Performance PCI Express Switch

– Twenty-four 2.5 Gbps PCI Express lanes – Three switch ports – Upstream port configurable up to x8 – Downstream ports configurable up to x8 – Low-latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant



Flexible Architecture with Numerous Configuration Options

– Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device configuration from serial EEPROM



Legacy Support

– PCI compatible INTx emulation – Bus locking



Highly Integrated Solution

– Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate

transceivers needed)

PES24N3A User Manual 1 - 1 April 10, 2008

Page 20

IDT PES24N3A Device Overview



Notes

Reliability, Availability, and Serviceability (RAS) Features

– Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do

not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC and server motherboards



Power Management

– Utilizes advanced low-power design techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCI-PM 1.1)

• Supports device power management states: D0, D3

– Unused SerDes are disabled



Testability and Debug Features

– Built in Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters



Eight General Purpose Input/Output Pins

– Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions



Packaged in 27x27mm 420 ball BGA with 1mm ball spacing

and D3

hot

cold

PES24N3A User Manual 1 - 2 April 10, 2008

Page 21

IDT PES24N3A Device Overview

System Diagrams

Frame Buffer Route Ta ble

3-Port Switch Core

Arbitration

Port

Scheduler

Transaction Layer

Data Link Layer

Multiplexer / Demultiplexer

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

...

Transaction Layer

Data Link Layer

Multiplexer / Demultiplexer

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

Multiplexer / Demultiplexer

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

...

Phy

Logical

Layer

SerDes

24 PCI Express Lanes

x8 Upstream Port and Two x8 Downstream Ports

Figure 1.1 PES24N3A Architectural Block Diagram

Processor

North

Bridge

Memory

Data Link Layer

Phy

Logical

Layer

...

SerDes

Phy

Logical

Layer

SerDes

PES24N3APES24N3A PES24N3A

PCI Express

Slots

I/O

10GbE

I/O

10GbE

I/O

SATA

I/O

SATA

Figure 1.2 I/O Expansion Application

PES24N3A User Manual 1 - 3 April 10, 2008

Page 22

IDT PES24N3A Device Overview

Logic Diagram

Reference

Clocks

PCI Express

Switch

SerDes Input

Port 0

PCI Express

Switch

SerDes Input

Port 2

PCI Express

Switch

SerDes Input

Port 4

Master

SMBus Interface

Slave

SMBus Interface

System

Functions

PEREFCLKP PEREFCLKN

REFCLKM

PE0RP[0]

PE0RN[0]

PE0RP[7]

PE0RN[7]

PE2RP[0]

PE2RN[0]

PE2RP[7]

PE2RN[7]

PE4RP[0]

PE4RN[0]

PE4RP[7]

PE4RN[7]

MSMBADDR[4:1]

MSMBCLK MSMBDAT

SSMBADDR[5,3:1]

SSMBCLK

SSMBCLK SSMBDA T

SSMBDA T

MSMBSMODE

CCLKDS CCLKUS

RSTHALT

PERSTN

SWMODE[3:0]

...

PES24N3A

...

PE0TP[0] PE0TN[0]

PE0TP[7] PE0TN[7]

PE2TP[0] PE2TN[0]

PE2TP[7] PE2TN[7]

PE4TP[0] PE4TN[0]

PE4TP[7] PE4TN[7]

GPIO[7:0 ]

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N

VDDCORE

APE

VTTPE

PCI Express

Switch

SerDes Output

Port 0

PCI Express

Switch

SerDes Output

Port 2

PCI Express

Switch

SerDes Output

Port 4

General Purpose

I/O

JTAG

Power/Ground

Figure 1.3 PES24N3A Logic Diagram

Note: In the PES24N3A, the two downstream ports are labeled port 2 and port 4.

PES24N3A User Manual 1 - 4 April 10, 2008

Page 23

IDT PES24N3A Device Overview

Notes

System Identification

Vendor ID

All vendor ID fields in the device are hardwired to 0x111D which corresponds to Integrated Device Tech-

nology, Inc.

Device ID

The PES24N3A device ID is shown in Table 1.1.

PCIe Device Device ID

0x2 0x801C

Table 1.1 PES24N3A Device ID

Revisio n ID

The PES24N3A revision ID is shown in Table 1.2.

Revision ID Description

0x0F Corresponds to ZA silicon 0x0E Corresponds to ZC silicon 0x0D Corresponds to ZG silicon

Table 1.2 PES24N3A Revision ID

JTAG ID

The JTAG ID is:

– Version: Same value as Revision ID. See Table 1.2 – Part number: Same value as base Device ID. See Table 1.1. – Manufacturer ID: 0x33 – LSB: 0x1

SSID/SSVID

The PES24N3A contains the mechanisms necessary to implement the PCI-to-PCI bridge Subsystem ID and Subsystem Vendor ID capability structure. However, in the default configuration the Subsystem ID and Subsystem Vendor ID capability structure is not enabled. To enable this capability, the SSID and SSVID fields in the Subsystem ID and Subsystem Vendor ID (SSIDSSVID) register must be initialized with the appropriate ID values. the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to this capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted to point to the next capability if necessary.

Device Serial Nu m ber E nha nced Capability

The PES24N3A contains the mechanisms necessary to implement the PCI express device serial number enhanced capability. However, in the default configuration this capability structure is not enabled. To enable the device serial number enhanced capability, the Serial Number Lower Doubleword (SNUMLDW) and the Serial Number Upper Doubleword (SNUMUDW) registers should be initialized. The Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to this capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted to point to the next capability if necessary.

PES24N3A User Manual 1 - 5 April 10, 2008

Page 24

IDT PES24N3A Device Overview

Notes

Pin Description

The following tables list the functions of the pins provided on the PES24N3A. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal Type Name/Description

PE0RP[7:0]

PE0RN[7:0] PE0TP[7:0]

PE0TN[7:0] PE2RP[7:0]

PE2RN[7:0] PE2TP[7:0]

PE2TN[7:0] PE4RP[7:0]

PE4RN[7:0] PE4TP[7:0]

PE4TN[7:0]

PEREFCLKP[2:1] PEREFCLKN[2:1]

REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre-

I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pairs for port 0. Port 0 is the upstream port.

O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 0. Port 0 is the upstream port.

I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pairs for port 2.

O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 2.

I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pairs for port 4.

O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 4.

I PCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal.

quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz

Table 1.3 PCI Express Interface Pins

Signal Type Name/Description

MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

Table 1.4 SMBus Interface Pins

PES24N3A User Manual 1 - 6 April 10, 2008

Page 25

IDT PES24N3A Device Overview

Notes

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

GPIO[1] I/O General Purpose I/O.

GPIO[2] I/O General Purpose I/O.

GPIO[3] I/O General Purpose I/O.

GPIO[4] I/O General Purpose I/O.

GPIO[5] I/O General Purpose I/O.

GPIO[6] I/O General Purpose I/O.

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2

This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4

This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output

Table 1.5 General Purpose I/O Pins

Signal Type Name/Description

CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi-

cates that a common clock is being used between the downstream device and the downstream port.

CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi-

cates that a common clock is being used between the upstream device and the upstream port.

MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the

master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden.

Table 1.6 System Pins (Part 1 of 2)

PES24N3A User Manual 1 - 7 April 10, 2008

Page 26

IDT PES24N3A Device Overview

Notes

Signal Type Name/Description

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside

PES24N3A and initiates a PCI Express fundamental reset.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, PES24N3A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master.

SWMODE[3:0] I Switch Mode. These configuration pins determine the PES24N3A switch

operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved

Table 1.6 System Pins (Part 2 of 2)

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 1.7 Test Pins

Signal Type Name/Description

CORE I Core VDD. Power supply for core logic.

IO I I/O VDD. LVTTL I/O buffer power supply.

VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital

power of the SerDes.

Table 1.8 Power and Ground Pins

PES24N3A User Manual 1 - 8 April 10, 2008

Page 27

IDT PES24N3A Device Overview

Notes

Signal Type Name/Description

VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL

and bias generator.

VTTPE I PCI Express Termination Power.

I Ground.

Table 1.8 Power and Ground Pins

Pin Characteristics

Note: Some input pads of the PES24N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.

Function Pin Name Type Buffer

PCI Express Interface

SMBus MSMBADDR[4:1] I LVTTL Input pull-up

General Purpose I/O

PE0RN[7:0] I CML Serial link PE0RP[7:0] I PE0TN[7:0] O PE0TP[7:0] O PE2RN[7:0] I PE2RP[7:0] I PE2TN[7:0] O PE2TP[7:0] O PE4RN[7:0] I PE4RP[7:0] I PE4TN[7:0] O PE4TP[7:0] O PEREFCLKN[2:1] I LVPECL/ PEREFCLKP[2:1] I

REFCLKM I LVTTL Input pull-down

MSMBCLK I/O STI MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board GPIO[7:0] I/O LVTTL High Drive pull-up

CML

I/O

Type

Diff. Clock

Input

Internal

Resistor

Notes

Refer to Table 9

PES24N3A Data

pull-up on board

in the

Sheet

Table 1.9 Pin Characteristics (Part 1 of 2)

PES24N3A User Manual 1 - 9 April 10, 2008

Page 28

IDT PES24N3A Device Overview

Notes

Function Pin Name Type Buffer

I/O

Type

Internal

Resistor

System Pins CCLKDS I LVTTL Input pull-up

CCLKUS I pull-up MSMBSMODE I pull-down PERSTN I RSTHALT I pull-down SWMODE[3:0] I pull-down

EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up

JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up External pull-

Table 1.9 Pin Characteristics (Part 2 of 2)

Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down.

Schmitt Trigger Input (STI).

Notes

down

PES24N3A User Manual 1 - 10 April 10, 2008

Page 29

Chapter 2

Clocking, Reset, and

Initialization

Notes

Introduction

The PES24N3A has two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both reference clock input pairs be driven from a common clock source. The frequency of the reference clock inputs may be selected by the Reference Clock Mode Select (REFCLKM) input.

REFCLKM Description

0 100 MHz reference clock input. 1 125 MHz reference clock input.

Table 2.1 Reference Clock Mode Encoding

Each of the reference clock differential inputs feeds several on-chip PLLs. Each PLL generates a 2.5 GHz clock which is used by several SerDes lanes and produces a 250 MHz core clock.

Clock Operation

When the CCLKUS and CCLKDS pins are asserted, they indicate that a common clock is being used between the upstream device and the upstream port, as well as between the downstream devices and the downstream ports. The Spread Spectrum Clock (SSC) must be disabled when the non-common clock is used on either the upstream port or downstream port. Figures 2.1 through 2.4 illustrate the operation of the CCLKUS and CCLKDS clocks using a common clock and a non-common clock.

PES24N3A

Root Complex

Port A

Port B Port C

Clock Generator

Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock)

PES24N3A User Manual 2 - 1 April 10, 2008

CCLKUS

REFCLK0

CCLKDS

REFCLK1

Page 30

IDT Clocking, Reset, and Initialization Clock Operation

Notes

PES24N3A

Root Complex

Port A

Port B Port C

Low

Clock Generator

Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum

CCLKUS

REFCLK0

CCLKDS

REFCLK1

Clock)

EP EP

Clock Generator

PES24N3A

Root Complex

Port A

Port B Port C

EP EP

Clock Generator

Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable Spread Spectrum

CCLKUS

REFCLK0

Clock)

CCLKDS

REFCLK1

Low

Clock Generator

PES24N3A User Manual 2 - 2 April 10, 2008

Page 31

IDT Clocking, Reset, and Initialization Clock Operation

Notes

PES24N3A

Root Complex

Port A

Port B Port C

Low

Clock Generator

Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock)

CCLKUS

REFCLK0

CCLKDS

REFCLK1

Clock Generator

EP EP

Low

Clock Generator

Initialization

A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES24N3A during a fundamental reset when PERSTN is negated. The boot configuration vector defines essential parameters for switch operation. Since the boot configuration vector is sampled only during a fundamental reset sequence, the value of signals which make up the boot configuration vector is ignored during other times and their state outside of a fundamental reset has no effect on the operation of the PES24N3A.

While basic switch operation may be configured using signals in the boot configuration vector, advanced switch features may require configuration via an external serial EEPROM. The external serial EEPROM allows modification of any bit in any software visible register. See Chapter 6, SMBus Interfaces, for more information on the serial EEPROM.

The external serial EEPROM and slave SMBus interface may be used to override the function of some of the signals in the boot configuration vector during a fundamental reset. The signals that may be overridden are noted in Table 2.2. The state of all of the boot configuration signals in Table 2.2 sampled during the most recent cold reset may be determined by reading the SWSTS register.

Signal Type Name/Description

CCLKDS I Common Clock Downstream. When the CCLKDS pin is

asserted, it indicates that a common clock is being used between the downstream device and the downstream port.

CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted,

it indicates that a common clock is being used between the upstream device and the upstream port.

MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates

that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden.

Table 2.2 Boot Configuration Vector Signals (Part 1 of 2)

PES24N3A User Manual 2 - 3 April 10, 2008

Page 32

IDT Clocking, Reset, and Initialization Clock Operation

Notes

Signal Type Name/Description

PERSTN I Fundamental Reset. Assertion of this signal resets all logic

inside PES24N3A and initiates a PCI Express fundamental reset.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express

fundamental reset, PES24N3A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master.

SWMODE[3:0] I Switch Mode. These configuration pins determine the

PES24N3A switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 through 0xF - Reserved

Table 2.2 Boot Configuration Vector Signals (Part 2 of 2)

Reset

The PES24N3A defines four reset categories:

– fundamental reset – hot reset – upstream secondary bus reset – downstream secondary bus reset.

A fundamental reset causes all logic in the PES24N3A to be returned to its initial state. A hot reset causes all logic in the PES24N3A to be returned to its initial state, but does not cause the state of register fields denoted as “sticky” to be modified. An upstream secondary bus reset causes all devices on the virtual PCI bus to be hot reset except the upstream port (i.e., upstream PCI to PCI bridge). A downstream secondary bus reset causes a hot reset to be propagated on the corresponding external secondary bus link.

There are two sub-categories of fundamental reset: cold reset and warm reset. A cold reset occurs following a device being powered on and assertion of PERSTN. A warm reset is a fundamental reset that occurs without removal of power.

Fundamental R eset

A fundamental reset may be initiated by any of the following conditions:

– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input

pin.

– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power

is on.

– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch

Control (SWCTL) register.

PES24N3A User Manual 2 - 4 April 10, 2008

Page 33

IDT Clocking, Reset, and Initialization Clock Operation

Notes

The following reset sequence is executed.

1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN).

2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.2. If PERSTN was not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental reset is the result of a one being written to the FRST bit in the SWCTL register). Examine the state of the sampled SWMODE[3:0] signals to determine the switch operating mode.

3. Initialize the PLL and SerDes.

4. Begin link training. While link training is in progress, proceed to step 5.

5. If the Reset Halt (RSTHALT) pin is asserted, set the RSTHALT bit in the SWSTS register.

6. If the switch operating mode is not a test mode, then the reset signal to the PCI Express phy, data link, and transaction layers (stacks) and associated logic is negated, but these stacks are held in a quasi-reset state in which the following actions occur:

– All links enter an active link training state within 20ms of the clearing of the fundamental reset

condition.

– Within 100ms of the clearing of the fundamental reset condition, all of the stacks are able to

process configuration transactions and respond to these transactions with a configuration request retry status completion. All other transactions are ignored.

7. The master SMBus operating frequency is determined.

The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is initialized to operate at 100 KHz rather than 400 KHz.

8. The slave SMBus is taken out of reset and initialized. The slave SMBus address specified by the SSMBADDR[5,3:1] pins is used.

9. The master SMBus is taken out of reset and initialized.

10. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then the contents of the serial EEPROM are read and the appropriate PES24N3A registers are updated.

– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM

is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the SMBUSSTS register.

– When serial EEPROM initialization completes or when an error is detected, the DONE bit in the

SMBUSSTS register is set.

11. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state except the master and slave SMBuses, the control/status registers, and the stacks which continue to be held in a quasi-reset state and respond to configuration transactions with a retry. The device remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an external agent may read and write any internal control and status registers and may access the external serial EEPROM via the EEPROMINTF register.

12. Normal device operation begins.

The PCIe base specification indicates that normal operation should begin within 1.0 second after a fundamental reset of a device. The reset sequence above guarantees that normal operation will begin within this period as long as the serial EEPROM initialization process completes within 200 ms. Under normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a Master SMBus operating frequency of 100 KHz.

Serial EEPROM initialization may cause writes to register fiel ds that initiate side effects such as link retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these side effects.

A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch Control (SWCTL) register always results in the PES24N3A returning a completion to the requester before the warm reset process begins.

PES24N3A User Manual 2 - 5 April 10, 2008

Page 34

IDT Clocking, Reset, and Initialization Clock Operation

Notes

The PES24N3A provides a reset output signal for each downstream port implemented as a GPIO alternate function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they are used as reset outputs. The operation of a fundamental reset with serial EEPROM initialization (i.e., SWMODE[3:0] = 0x1) is illustrated in Figure 2.5.

RSTHALT bit cleared

in SWCTL

REFCLK*

Vdd

PERSTN

SerDes

Master SMBus

Slave SMBus

Notes:

1) Reference Clock (REFCLK) not shown to scale.

2) The PES24N3A requires a minimum time for Tperst-clk of 1µs. The PES24N3A requires a minimum time for Tpvperl of 1ms.

3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PES24N3A is used. For example, the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.

Tpvperl

20ms max.

11μs

PLL Reset and Lock CDR Reset & Lock Ready for Normal Operation

s max.

Stacks in Quasi Reset State

Link Training

ReadyIdle Serial EEPROM Initialization

Ready for Normal Operation

Figure 2.5 Fundamental Reset in Transparent Mode with Serial EEPROM initialization

Hot Reset

A hot reset may be initiated by any of the following conditions:

– Reception of TS1 ordered-sets on the upstream port indicating a hot reset. – Data link layer of the upstream port transitions to the DL_Down state. – Writing a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL) register.

The initiation of a hot reset due to the data l ink la yer of the upstream port transitioning to the DL_D own state may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the Switch Control (SWCTL) register. Other hot reset conditions are unaffected by this bit.

When a hot reset occurs, the following sequence is executed.

1. Each downstream port whose link is up propagates the hot reset by transmitting TS1 ordered sets with the hot reset bit set.

2. All of the logic associated with the PES24N3A except the PLLs, SerDes, master SMBus interface, and slave SMBus interface is reset.

3. All registers fields in all registers, except those denoted as “sticky” or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields denoted as “sticky” or RWL is preserved across a hot reset.

4. Link training begins. While link training is in progress, proceed to step 5.

5. The PCI Express stacks and associated logic are held in a quasi-reset state in which the following actions occur.

– All links enter an active link training state within 20ms of the clearing of the hot reset condition. – Within 100ms of the clearing of the fundamental reset condition, all of the stacks are able to

process configuration transactions and respond to these transactions with a configuration request retry status completion. All other transactions are ignored.

PES24N3A User Manual 2 - 6 April 10, 2008

Page 35

IDT Clocking, Reset, and Initialization Clock Operation

Notes

6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control (SWCTL) register, then the contents of the serial EEPROM are read and the appropriate PES24N3A registers are updated.

– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM

is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the SMBUSSTS register.

– When serial EEPROM initialization completes or when an error is detected, the DONE bit in the

SMBUSSTS register is set.

7. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state except the master and slave SMBuses. The RSTHALT bit is set only under the following two conditions:

– serial EEPROM initialization is enabled in step 6 and an error is detected during loading of the

serial EEPROM or

– the user intentionally sets this bit through the EEPROM code.

8. Normal device operation begins.

The operation of the slave SMBus interface is unaffected by a hot reset. Using the slave SMBus to access a register that is reset by a hot reset causes zero to be returned on a read and written data to be ignored on writes. A hot reset initiated by the writing of a one to the H ot Reset (HRST) bit in the Switch Control (SWCTL) register always results in the PES24N3A returning a completion to the requester before the hot reset process begins.

Upstream Secondary Bus Reset

An upstream secondary bus reset may be initiated by the following condition:

– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (i.e., port 0)

Bridge Control Register (BRCTL).

When an upstream secondary bus reset occurs, the following sequence is executed.

1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with the hot reset bit set.

2. All registers fields in all registers associated with downstream ports, except those denoted as “sticky” or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields denoted as “sticky” or RWL is unaffected by an upstream secondary bus reset.

3. All TLPs received from downstream ports and queued in the PES24N3A are discarded.

4. Logic in the stack, application layer and switch core associated with the downstream ports are gracefully reset.

5. Wait for the Secondary Bus Reset (SRESET) bit in the Bridge Control Register (BCTL) to clear.

6. Normal downstream port operation begins.

The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and Type 0 configuration read and write transactions that target the upstream port complete normally. During an upstream secondary bus reset, all TLPs destined to the secondary side of the upstream port’s PCI-to-PCI bridge are treated as unsupported requests.

The operation of the slave SMBus interface is unaffected by an upstream secondary bus reset. Using the slave SMBus to access a register that is reset by an upstream secondary bus reset causes zero to be returned on a read and written data to be ignored on writes.

Downstream Secondary Bus Reset

A downstream secondary bus reset may be initiated by the following condition:

– A one is written to the Secondary Bus Reset (SRESET) bit in a downstream port’s (i.e., port 0)

Bridge Control Register (BCTRL).

PES24N3A User Manual 2 - 7 April 10, 2008

Page 36

IDT Clocking, Reset, and Initialization Clock Operation

Notes

When a downstream secondary bus reset occurs, the following sequence is executed.

1. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted

2. All TLPs received from corresponding downstream port and queued in the PES24N3A are discarded.

3. Wait for the Secondary Bus Reset (SRESET) bit in the Bridge Control Register (BCTL) to clear.

4. Normal downstream port operation begins.

The operation of the upstream port is unaffected by a downstream secondary bus reset. The operation of other downstream ports is unaffected by a downstream secondary bus reset. During a downstream secondary bus reset, Type 0 configuration read and write transactions that target the downstream port complete normally. During a downstream secondary bus reset, all TLPs destined to the secondary side of the downstream port’s PCI-to-PCI bridge are treated as unsupported requests.

The operation of the slave SMBus interface is unaffected by a downstream secondary bus reset.

Downstream Port Reset Outputs

Individual downstream port reset outputs (PxRSTN) are provided as GPIO pin alternate functions. Following a fundamental reset, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they are used as reset outputs.

The PES24N3A ensures through hardware that the minimum PxRSTN assertion pulse width is no less than 200 µS.

Downstream port reset outputs can be configured to operate in one of three modes. These modes are: power enable controlled reset output, power good controlled reset output, and hot reset controlled output. The downstream port reset output mode is determined by the Reset Mode (RSTMODE) field in the Hot-Plug Configuration Control (HPCFGCTL) register.

Power Enable Controlled Reset Output

In this mode, a downstream port reset output state is controlled as a side effect of slot power being turned on or off. The operation of this mode is illustrated in Figure 2.6. A downstream port’s slot power is controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register.

PxPEP

PxRSTN

PWR2RST

Figure 2.6 Power Enable Controlled Reset Output Mode Operation

RST2PWR

While slot power is disabled, the corresponding downstream port reset output is asserted. When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and then power to the slot is enabled and the corresponding downstream port reset output is negated. The time between the assertion of the PxPEP signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.

PES24N3A User Manual 2 - 8 April 10, 2008

Page 37

IDT Clocking, Reset, and Initialization Clock Operation

Notes

While slot power is enabled, the corresponding downstream port reset output is negated. When slot power is disabled by writing a one to the PCC bi t, the corresponding downstream port reset output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power (RST2PWR) field in the HPCFGCTL register.

Power Good Controlled Reset Output

As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on the power good state of the slot’s power supply. The operation of this mode is illustrated in Figure 2.7.

PxPEP

PxPWRGDN

PxRSTN

PWR2RST

Figure 2.7 Power Good Controlled Reset Output Mode Operation

RST2PWR

The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that when power is enabled, the negation of the corresponding port reset output occurs as a result of and after assertion of the slot’s Power Good (PxPWRGDN) signal is observed. The time between the assertion of the PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.

When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power (RST2PWR) field in the HPCFGCTL register.

If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is detected (i.e., PxPWRGDN is negated), the corresponding port reset output is immediately asserted. Since the PxPWRGDN signal is an I/O expander input, it may not be possible to meet a profile’s power level invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a shorter time interval may implement this functionality external to the PES24N3A.

Hot Reset Controlled Reset Output

In this mode the following conditions cause a downstream port’s reset output to be asserted:

– Hot reset – Upstream secondary bus reset – Downstream secondary bus reset

When a downstream port reset output is asserted, it remains asserted while one of the above conditions persists or for 200 µS, whichever is longer.

PES24N3A User Manual 2 - 9 April 10, 2008

Page 38

IDT Clocking, Reset, and Initialization Clock Operation

Notes

PES24N3A User Manual 2 - 10 April 10, 2008

Page 39

Chapter 3

Theory of Operation

Notes

Introduction

An architectural block diagram of the PES24N3A is shown in Figure 1.1 in Chapter 1. The PES24N3A contains three ports labeled port 0, port 2, and port 4. Port 0 is always the upstream port and port 2 and port 4 are always downstream ports.

At a high level, the PES24N3A consists of three PCIe stacks and a switch core. Each stack is configured to operate as a single x8 stack. A stack consists of logic that performs functions associated with the physical, data link, and transactions layers described in the PCIe base 1.1 specification. In addition, a stack performs switch application layer functions such as TLP routing using route map tables, processing configuration read and write requests, etc.

The switch core is responsible for transferring TLPs between stacks. Its main functions are: input buffering, maintaining per-port ingress and egress flow control information, port arbitration, scheduling, and forwarding TLPs between stacks. In typical fan-out applications, all data from downstream ports are destined to memory in the root complex and all TLPs from the root complex are destined to endpoints. Thus, in general there is no peer-to-peer (i.e., endpoint to endpoint) traffic. Since the PES24N3A is optimized for fan-out applications, its switch core is based on a dual bus architecture.

The downstream bus (D-Bus) is used to transfer TLPs from the upstream port to a downstream port while the upstream bus (U-Bus) is used to transfer TLPs from a downstream port to an upstream port. DBus and U-Bus transfers may occur in parallel. While not optimized for peer-to-peer traffic, the PES24N3A supports these transfers. A peer-to-peer transfer occurs by first transferring a TLP from a downstream port into a bus decoupler queue over the U-Bus. Once in the bus decoupler queue, the TLP is transferred to the peer downstream port over the D-Bus. Thus, unlike upstream and downstream traffic which utilize either the U-Bus or D-Bus, peer-to-peer transfers utilize both buses.

The size and constraints of the bus decoupler queue are shown in Table 3.3.

The PES24N3A switch core implements a per-port input buffer called the Input Frame Buffer (IFB). Each input buffer consists of four queues. These queues are the posted transaction queue (posted queue), the non-posted transaction queue (non-posted queue), the completion transaction queue (completion queue), and an insertion buffer to hold TLPs generated by the stack.

The size of each of these queues is shown in Table 3.1. Each queue is implemented as a data queue and a descriptor queue. Thus, there is a limitation on both the amount of data as well as on the number of TLPs that can be stored in a queue.

Advertised

IFB Queue Total Queue Size and Limitations

Posted 8 KB or up to 64 TLPs 64 416 (6656 bytes)

Non-posted 1.5 KB or up to 64 TLPs 64 64 (1024 bytes)

Completion 8 KB or up to 64 TLPs 64 416 (6656 bytes)

Table 3.1 IFB Buffer Sizes

Associated with each port in the data link layer is a shared output and replay buffer. That is, the buffer is partitioned into two sections with a section dedicated to each x8 port. This buffer contains TLPs that have been transmitted but have not been acknowledged by the link partner. Space unused to hold replay TLPs is

PES24N3A User Manual 3 - 1 April 10, 2008

Header Credits

Advertised

Data

Credits

Page 40

IDT Theory of Operation

Notes

used to provide a per-port output buffer. This output buffer enables switch core transfers to occur at x8 rates even when the corresponding output port has negotiated to a lower link width. The size is shown in Table

3.2.

Buffer Size and Limitations

Output and Replay Buffer 8 KB of data or up to 32 TLPs

Table 3.2 PES24N3A Buffer Sizes

The size of the bus decoupler queue and insertion buffer is shown in Table 3.3.

Buffer Size and Limitations

Bus Decoupler Queue 2 KB of data (i.e., 1 maximum size TLP) or up to 1 TLP

(2112 byte total size)

Insertion Buffer 12 Dwords of data (3 or 4 DW of header, 0 or 1 DW of

payload data, 0 or 1 DW for ECRC) or up to 2 TLPs (one posted and one completion)

Table 3.3 Bus Decoupler Queue and Insertion Buffer Size

Data Paths

All data paths through the stacks and switch core are 66-bits wide and consists of 64 data bits and two even DWord parity bits.

A stack allocates all clock cycles to port data received from the SerDes. However, depending on the negotiated link width, not all clock cycles may be used to transfer data. The switch port presents data to the switch core every clock cycle.

After being queued in an input frame buffer, all data transferred through the switch core is transferred in a continuous TLP manner. Thus, TLPs are transferred at a x8 rate from an input frame buffer, across the appropriate bus or buses, and to an egress stack. Egress data is always presented by the switch core, processed by a stack, and queued in an output and replay buffer in continuous TLP manner. Data is read from the output and replay buffer by the data link layer in a TDM manner. The physical layer demultiplexes this data and presents it to the appropriate SerDes.

Store-and-Forward vs. Cut-Through Switching and Latency

The PES24N3A utilizes an input buffered cut-through switching architecture to forward PCIe TLPs between switch ports. All TLPs that are received on an ingress link whose width is greater than or equal to the width of the egress link are cut-through the switch. Switch latency is defined as the time from the first TLP symbol being received on the ingress link to the first TLP symbol being transmitted on the egress link.

The best case latency for transactions that can be cut-through is shown in Table 3.4.

PES24N3A User Manual 3 - 2 April 10, 2008

Page 41

IDT Theory of Operation

Notes

can be transmitted on the switch egress port. This is necessary since once a TLP transmission begins, it must complete uninterrupted at the rate of the egress port. Thus, when the negotiated ingress link width is less than the egress link width, the PES8T5 operates in a store and forward manner. Ingress TLPs are queued in the IFB until the entire TLP has been received.

Switch Core

primary purpose of the Upstream Bus (U-Bus) is to route TLPs received on a downstream port to the upstream port while the primary purpose of the Downstream Bus (D-Bus) is route TLPs received on the upstream port to a downstream port.

addition to providing a data path between the U-Bus and the D-Bus, the bus decoupler provides adequate buffering to accommodate one maximum-sized TLP to allow the U-Bus and D-Bus to operate independently. Thus, the transfer from a downstream port to bus decoupler is independent of the transfer from the bus decoupler to a downstream port. While it may appear that the bus decoupler introduces a store-andforward architecture for peer-to-peer transfers, this is not the case. Transactions flowing through the bus decoupler may be cut-through and typically add no more than five clock cycles of latency.

Ingress to Egress Latency (ns)

x8 to x8 184 x8 to x4 184 x8 to x1 184 x4 to x4 204 x4 to x1 204 x1 to x1 272

Table 3.4 Latency

If the ingress link width is less than the egress link width, then an entire TLP must be received before it

A simplified view of the switch core is shown in Figure 3.1. The switch core consists of two buses. The

To facilitate peer-to-peer transactions, a bus decoupler is provided to link the U-Bus to the D-Bus. In

Bus Decoupler

Queue

U-Bus

D-Bus

Upstream

Port

Downstream

Port

Downstream

Port

Figure 3.1 Simplified Switch Core U-Bus and D-Bus Datapath

In addition to transactions between the upstream port and downstream port and peer-to-peer transactions, the switch core is responsible for routing of transactions which are destined to the same stack on which the TLP was received. These transactions are referred to as route-to-self.

PES24N3A User Manual 3 - 3 April 10, 2008

Page 42

IDT Theory of Operation

Notes

Transaction Routing

The PES24N3A supports routing of all transaction types defined in the PCIe base 1.1 specification. This includes routing of specification-defined transactions as well as those that may be used in vendor defined messages and in future revisions of the PCIe specification.

Note: The PES24N3A supports routing of trusted configuration transactions.

Specifically, the PES24N3A supports the following type of routing:

– Address routing with 32-bit or 64-bit format – ID based routing using bus, device and function numbers. – Implicit routing utilizing

• Route to root

• Broadcast from root

• Local - terminate at receiver

• Gathered and routed to root

A summary of TLP types that use the above routing methods is provided in Table 3.5.

Routing Method TLP Type Using Routing Method

Route by Address MRd, MrdLk, MWr, IORd, IOWr, Msg, MsgD ID Based Routing CfgRd0, CfgWr0, CfgRd1, CfgWr1, TCfgRd, TCfgWr, Cpl,

CpdD, CplLk, CplDLk, Msg, MsgD Imlicit Routing - Route to Root Msg, MsgD Implicit Routing - Broadcast

from Root Implicit Routing - Local Msg, MsgD Implicit Routing - Gathered

and Routed to Root

The only Gathered and Routed to Root message supported is a PME_TO_Ack message received on a

downstream port.

Msg, MsgD

Only supported for PME_TO_Ack messages in response to a

root initiated PME_Turn_Off message.

Table 3.5 Switch Routing Methods

Transaction Reordering

Each IFB has a 25-bit free-running timer which is clocked at the 250 MHz core clock frequency. When a TLP is enters the IFB, a 25-bit time-stamp of when the TLP arrived is stored in a descriptor associated with the TLP. This time-stamp is used to implement a switch time-out and to provide a relative order of TLPs in the IFB.

The IFB contains four input queues per port. These queues are the posted transaction queue (posted queue), the non-posted transaction queue (non-posted queue), the completion transaction queue (completion queue) and an insertion buffer to hold TLPs generated by the stack.

While there are four physical queues in the IFB, TLPs in the insertion buffer are either posted or completion TLPs. Using the time-stamp with each TLP, the IFB logically merges the head of the completion queue with the appropriate TLP type queue. Thus, the IFB has three logical queue heads corresponding to posted, non-posted and completion TLPs.

The IFB examines information associated with the heads of the three l ogical queues, and presents a signal called “valid” to the switch core for each TLP that may be dispatched. Along with the “valid” signal, the IFB indicates the destination port, payload size, and relative age of the TLPs. This information is used by the switch core scheduling and port arbitration logic to select a TLP to transfer through the switch core.

PES24N3A User Manual 3 - 4 April 10, 2008

Page 43

IDT Theory of Operation

Notes

The generation of “valid” signals is based on PCIe ordering rules and is summarized Table 3.6. The notation x > y indicates that the TLP of type x is older (i.e., has an older time-stamp) than the TLP of type y. It is impossible for two TLPs to have the same timestamp. The notation x.ro

indicates that the relaxed ordering attribute is set in the header of the TLP at the head of logical queue type x. Table 3.6 only lists the relaxed ordering attributes in cases where it affects the state of a valid signal.

Logical Queue Head

Ordering

P > NP > CP.ro

P > NP > CP 100 P > CP > NP 100

P > CP.ro

NP > P > CP.ro

> NP 110

NP > P > CP 1 1 0

NP > CP > P 111 CP > P > NP 1 0 0 CP > NP > P 111

Table 3.6 IFB Transaction Ordering

Posted Valid

101

111

Non-Posted

Valid

Completion

Valid

When two logical TLP types are destined to the same egress port from the same ingress port, the relative TLP type age is used to order the TLPs (i.e., the older one is allowed to progress first). Other than the ordering rules shown in Table 3.6, relative age plays no role in ordering of TLPs destined to different egress ports from the same ingress ports. Thus, TLPs destined to different egress ports may be aggressively reordered even when there is no congestion in the system.

Since ordering is performed by examining the heads of the three logical IFB queues, TLPs of a particular type are never reordered (i.e., a posted will never bypass another posted with an earlier timestamp).

When the Disable Relaxed Ordering (DRO) bit is set in the Switch Control (SWCTL) register, all of the IFBs in the PES24N3A strongly order transactions regardless of the state of the relaxed ordering attribute.

Scheduling and Port Arbitration

Associated with each port is an Egress Selection Picker (ESP) and associated with each bus (i.e., UBus or D-Bus) is a bus arbiter. The function of the ESP is to provide a candidate vector with one bit per port indicating which ports have a TLP in their input frame buffer or insertion buffer that can be transferred to that output port.

In producing the candidate vector, each port’s ESP takes the following factors into consideration.

– The availability and ordering, as reported by each port’s Input Frame Buffer (IFB), of TLPs of each

type (i.e., posted, non-posted, completion, and insertion) that can be transferred from the head of the port’s IFB queues.

– The size of each TLP type that can be transferred from each port’s IFB queues. – The amount of space available in the corresponding (i.e., the port with which the ESP is associ-

ated) port’s output and replay buffer.

– The ability of the application layer in the corresponding port to accept a TLP not destined to that

port’s egress (e.g., one that is processed by the completion processor).

– The number of PCIe header and data credits available of each TLP type indicated by the corre-

sponding port’s link partner.

– The occupancy of the bus decoupler queue.

PES24N3A User Manual 3 - 5 April 10, 2008

Page 44

IDT Theory of Operation

Notes

The candidate vector produced by each port’s ESP is presented to the U-Bus and D-Bus arbiters.

– For downstream ports:

• The upstream portion of the candidate vector is provided to the D-Bus arbiter.

• The downstream portion of the candidate vector is provided to the U-Bus arbiter. An assertion

in this portion of the candidate vector indicates a peer-to-peer or downstream route-to-self transfer.

– For the upstream port:

• The entire candidate vector is provided to the U-Bus arbiter.

The U-Bus and D-Bus arbiters select the transaction that will occur on the corresponding bus and initiate the transfer. U-Bus and D-Bus transactions are independent of each other and proceed in parallel.

U-Bus Arbiter

The function of the U-Bus arbiter is to select the transaction that will take place on the U-Bus. Arbitration of the U-Bus proceeds in parallel with transfers on the bus. U-Bus arbitration takes at most 2 clock cycles and in most cases is completely overlapped with U-Bus transfers. In the worst case of back-to-back 3 Dword TLPs, the maximum overhead introduced by the U-Bus arbiter is one clock cycle per TLP. U-Bus arbitration logically occurs in two stages. In the first stage, a transfer class is selected, and in the second stage, the actual transfer within that transfer class is selected.

There are four U-Bus transfer classes. The transfer classes are: downstream-to-upstream, peer-to-peer, upstream route-to-self, and downstream route-to-self.

– Downstream-to-upstream transfers occur from a downstream port, through the U-Bus multiplexor

to the upstream port. The requests for this transfer class come from the candidate vector produced by the upstream port’s ESP.

– Peer-to-peer transfers occur from a downstream port, through the U-Bus multiplexor, and to the

bus decoupler queue. The requests for this transfer class come from the downstream portion of the candidate vector produced by each downstream ports’ ESP.

– Upstream route-to-self transfers occur from the upstream port insertion buffer output, thr ough the

U-Bus multiplexor, and to the upstream port. The request for this transfer class comes from the candidate vector produced by the upstream port’s ESP.

– Downstream route-to-self transfers occur from a downstream port, through the U-Bus multiplexor,

and to the bus decoupler queue. The requests for this transfer class come from the candidate vector produced by the downstream port’s ESP.

A weighted round robin arbitration scheme is used to select a U-Bus transfer class. The percentage of transfers on the U-Bus allocated to a transfer class is controlled by fields in the U-Bus Arbiter Transaction Count (UARBTC) register and U-Bus Arbiter Current Transaction Count (UARBCTC) register.

There are two 8-bit fields in these registers associated with each transfer class. The first field is a transfer count field that indicates how many transfers of that class can occur in an arbitration period. The second field is a current transfer count field that indicates how many transfers from that class are remaining in the current arbitration period.

At the start of each arbitration period, all of the current transfer count fields are initialized to their corresponding transfer count field values. During each arbitration period, the U-Bus arbiter selects, in a fair manner, a transfer class which (a) is requesting service and (b) has the corresponding current transfer count field equal to non-zero. If no such transfer cl ass exists, then the arbitration period is said to have ended, and each current transfer count field is re-initialized with the corresponding transfer count field value.

An arbitration period may end due to all current transaction count registers being zero or because there are no transfer classes with a non-zero current transaction count requesting service. In either case, there is no overhead introduced by the end of an arbitration period (i.e., no clock cycles are added to the arbitration). Once a transfer class has been selected, the U-Bus arbiter selects a transaction within that transfer to initiate on the U-Bus. The arbitration algorithm used to select this transaction is dependent on the selected transaction class.

PES24N3A User Manual 3 - 6 April 10, 2008

Page 45

IDT Theory of Operation

Notes

For downstream-to-upstream transfers, the upstream port’s port arbiter selects the transaction that is initiated. The upstream port arbiter implements both a hardwired fixed round robin algorithm as well as a weighted round robin with 32 phases algorithm as defined by the PCIe base 1.1 specification. The arbitration algorithm, as well as weighted round robin arbitration parameters, are software selectable.

– Weighted round robin arbitration with 32-phases is implemented by converting the PCIe port arbi-

tration table into weighted round robin weights. Therefore, over short intervals grants may not match the phase table configuration.

For peer-to-peer transfers, the U-Bus employs a hardwired fair arbitration algorithm that selects the transaction that is initiated. This algorithm ensures fair arbitration among each downstream candidate vector bit that selects a peer-to-peer transfer.

No arbitration is necessary for upstream-to-self transfers since there is only one choice. For downstream-to-self transfers, the U-Bus employs a hardwired fair arbitration algorithm that selects among the downstream ports requesting service.

Figure 3.2 summarizes the two stage U-Bus arbitration process.

Transaction Class Arbitration

Weighted Round Robin

Downstream

Upstream

Upstream port arbiter selects transfer using hardwired fixed round

Peer

Peer-to-peer transfer selected using fair arbitration.

Upstream

Self

Upstream route-to-self selected (only choice)

Downstream

Self

Downstream route-toself selected using fair arbitration.

Figure 3.2 U-Bus Arbitration

D-Bus Arbiter

D-Bus arbitration is similar to U-Bus arbitration but logically occurs in only a single stage. Arbitration of the D-Bus proceeds in parallel with transfers on the bus. D-Bus arbitration takes at most 2 clock cycles and in most cases is completely overlapped with D-Bus transfers. In the worst case of back-to-back 3 Dword TLPs, the maximum overhead introduced by the D-Bus arbiter is one clock cycle per TLP.

There are two D-Bus transfer classes. They are upstream-to-downstream and bus decoupler queue transfers. Upstream-to-downstream transfers proceed from the upstream port, through the D-Bus multiplexor, and to a downstream port. The requests for this transfer comes from the upstream portion of the candidate vector produced by the downstream ports.

Bus decoupler queue transfers proceed from the bus decoupler queue, through the D-Bus multiplexor, and to a downstream port. The queue contains a peer-to-peer or downstream route-to-self transaction performed on the U-Bus. The request for this transfer comes from the bus decoupler queue (i.e., when the bus decoupler queue indicates that there is a transaction in the queue).

A weighted round robin arbitration scheme, identical to the one used by the U-Bus arbiter, is used to select the D-Bus transfer class.

The percentage of transfers on the D-Bus allocated to a transfer class are controlled by fields in the DBus Arbiter Transaction Count (DARBTC) and D-Bus Arbiter Current Transaction Count (DARBCTC) register. Once a transaction class is selected, the D-Bus arbiter selects a transaction within that transfer class to initiate on the D-Bus. Unlike U-Bus arbitration, once the transaction cl ass has been selected, there is typically no choice regarding which transfer to perform (i.e., the upstream to downstream or bus decou-

PES24N3A User Manual 3 - 7 April 10, 2008

Page 46

IDT Theory of Operation

Notes

pler queue transfer is initiated). However, since the upstream input frame buffer has a queue per transaction type, it is possible for multiple upstream to downstream transactions to simultaneously request service. In such a situation, the oldest transaction (i.e., the one with the oldest time-stamp) is selected.

Peer-to-Peer Transactions

The broadest definition of a peer-to-peer transaction is a transaction that originates at one endpoint and targets another endpoint (i.e., the endpoints are peers). In the context of the PES24N3A, transactions between downstream ports are referred to as peer-to-peer transactions. However, depending on system topology and configuration, transactions between the upstream port and a downstream port may also be peer-to-peer (i.e., between endpoints). While it is understood that such transactions may be peer-to-peer, in the context of the PES24N3A these are not considered peer-to-peer transactions.

Thus, a peer-to-peer transaction in this specification refers to a transaction which originates at a PES24N3A downstream port and targets another PES24N3A downstream port. While the architecture of the PES24N3A supports peer-to-peer transactions, the performance of these transactions has not been optimized since in fan-out applications peer-to-peer transactions are rare.

Some systems view peer-to-peer transactions as a potential security vulnerability since this capability allows one endpoint to modify the state of another without protection checks. When the Disable Peer-toPeer (DP2P) bit is set in the Switch Control (SWCTL) register, all PES24N3A peer-to-peer transactions are disabled. In this mode, any transaction received at a PES24N3A downstream port that targets another downstream port is treated as an unsupported request (UR). Enabling this mode may cause TLPs with legal PCI system architecture routing to be terminated with an error. Thus, it is the responsibility of the system designer and system software to ensure proper system operation in this mode.

The PES24N3A also supports selective disabling of peer-to-peer transactions in a matrix fashion. Associated with each port is TLP Routing Control (Px_TROUTECTL) register. Each bit in the Port Routing Disable (PRDIS) field in this register corresponds to a PES24N3A port (e.g., bit one corresponds to port one). When a bit in this field is set, forwarding of TLPs is disabled to the corresponding port from port in which the TROUTECTL register is located. TLPs with a disabled route are treated as an unsupported request (UR).

– Route-to-self can never be disabled. – Routing to the upstream port from a downstream port cannot be disabled. – -Routing to a downstream port from the upstream port cannot be disabled.

Bus Locking

The PES24N3A supports locked transactions, allowing legacy software to run without modification on PCIe. Only one locked transaction sequence may be in progress at a time.

– A locked transaction sequence is requested by the root by issuing a Memory Read Request -

Locked (MRdLk) transaction. A lock is established when a lock request is successfully completed with a Completion with Data - Locked (CplDLk). A lock is released with an Unlock message (Msg).

When the PES24N3A receives a MRdLk transaction on its upstream port destined for a downstream port, it forwards the MRdLK transaction to the downstream port and locks the downstream port so that all subsequent TLPs destined to that downstream port from ports other than the root are blocked until the lock is released.

– The MRdLK transaction obeys PCI ordering rules, meaning that all queued posted requests for

the downstream port are completed prior to the MRdLK being transmitted. The MRdLK is allowed by bypass queued non-posted requests and completions.

– When only the downstream port is locked, no transactions destined to any other port are blocked

(e.g., transactions from the other downstream ports to the upstream port and peer-to-peer transactions are not blocked)

When a CplDLk is returned by the locked downstream port, the upstream port becomes locked causing all transactions destined to the upstream port from sources other than the locked downstream port (i.e., other downstream ports) to be blocked. If the lock is unsuccessful, then a CPlLk is returned by the down-

PES24N3A User Manual 3 - 8 April 10, 2008

Page 47

IDT Theory of Operation

Notes

stream port. Regardless of the success of a lock, the root complex is required to terminate all lock sequences with an Unlock message. The upstream port lock associated with an unsuccessful completion is released when this Unlock message is received.

The CplDLk transaction obeys PCI ordering rules, meaning that all queued posted requests at the locked downstream port destined to the upstream port are completed prior to the CplDLk being transmitted. The CplDLk is allowed to bypass queued non-posted requests and completions. When a CplDLk is returned by the locked downstream port and the upstream port becomes locked, the entire switch becomes locked. This means that all transactions from the other downstream ports destined to the upstream port or the locked downstream port are blocked until the switch is unlocked.

While the switch is locked:

– any register in the switch may be read or written via the SMBus – it is illegal to read or write any of the PCIe configuration space headers in the switch since the

switch can not generate a completion until the switch is unlocked.

The behavior of the switch is undefined when:

– a PCIe configuration space register is read while the switch is locked – any transaction other than a MWr, MRdLk, and Unlock message is received on the upstream port

when the switch is locked

– any transaction other than a CplLk and a CplDLk is received on the locked downstream port when

the switch is locked.

While the switch is locked:

– it is possible for the root to perform subsequent reads from the locked device by issuing a MRdLk

requests to the locked device and receiving a CplDLk or CplLk response from the locked device. These transactions do not change the state of the switch when the switch is locked. Therefore, a CplLk completion once the switch is locked in no way “unlocks” the switch.

– it is possible for the root to perform subsequent writes to the locked device by issuing MWr

requests to the locked device. These transactions in no way change the state of the switch when the switch is locked.

– the upstream port and the locked downstream port may generate messages (i.e., “insert

messages”). These messages include interrupt emulation messages and error messages. A locked switch port may also generate MSIs.

When an Unlock message is received on the upstream port, the switch is unlocked. This causes the Unlock message to be forwarded to the locked downstream port and the unblocking of transactions destined to the upstream and previously locked downstream port. The unlock message obeys PCI ordering rules, meaning that all queued posted requests from the upstream port are completed prior to the switch becoming unlocked.

When a TLP from a downstream port is blocked from being forwarded due to a locked switch, then the TLP is delayed until the switch is unlocked. If the switch is locked for an extended period, this may cause TLPs to be discarded due to switch time-outs (see section Switch Time-Outs on page 3-16).

The behavior of the switch is undefined when:

– a MRdLk TLP is received on the upstream port destined to an unlocked downstream port while

the switch is locked

– the upstream port is locked with a downstream port and a TLP is received by the upstream port

destined to an unlocked downstream port.

The locked status of the switch may be determined by examining the Lock Mode (LOCKMODE) bit in the SWSTS register. This register is meant to be read via the slave SMBus interface.

PES24N3A User Manual 3 - 9 April 10, 2008

Page 48

IDT Theory of Operation

Notes

Port Interrupts

The upstream port, port 0, does not generate legacy interrupts or MSIs. Downstream ports support generation of legacy interrupts and MSIs. The following are sources of downstream port interrupts and MSIs.

– Downstream port’s hot-plug controller – Link bandwidth notification capability (i.e., assertion of the LBWSTS or LABWSTS bits in the

PCIELSTS register when interrupt notification is enabled for these bits)

When a downstream port is configured to generate INTx messages, only INTA is used. When an unmasked interrupt condition occurs, then an MSI or interrupt message is generated by the corresponding port as described in Table 7.6. The removal of the interrupt condition occurs when unmasked status bit(s) causing the interrupt are masked or cleared.

The PES24N3A assumes that all downstream port generated MSIs are targeted to the root and routes these transactions to the upstream port. Configuring the address contained in a downstream port’s MSIADDR and MSIADDRU registers to an address that does not route to the upstream port and generating an MSI produces undefined results.

Unmasked

Interrupt

Asserted 1 X MSI message generated

EN bit in

MSICAP

0 0 Assert_INTA message request generated to switch

0 1 None

INTXD bit

in PCICMD

Actions

core

Negated 1 X None

0 0 Deassert_INTA message request generated to

switch core

0 1 None

Table 3.7 Downstream Port Interrupts

Legacy Interrupt Emulation

The PES24N3A supports legacy PCI INTx emulation. Rather than use sideband INTx signals, PCIe defines two messages that indicate the assertion and negation of an interrupt signal. An Assert_INTx message is used to signal the assertion of an interrupt signal and an Deassert_INTx message is used to signal its negation.

The PES24N3A maintains an aggregated INTx state for each of the four interrupt signals (i.e., A through D) at each port.

– The value of the INT A, INTB, INTC and INTD aggregated state for the entire switch may be de ter-

mined by examining the corresponding field in the upstream port’s Interrupt Status (P0_INTSTS) register.

– The aggregated INTx state for a downstream port may be determined by reading the corre-

sponding field in the port’s Interrupt Status (Px_INTSTS) register. This register contains the aggregated state of interrupts generated by that port (i.e., hot-plug) plus interrupt messages received from the downstream link partner. The interrupt state reflects the state of interrupts as seen by that port (i.e., before downstream port interrupts are mapped to upstream port interrupts).

PES24N3A User Manual 3 - 10 April 10, 2008

Page 49

IDT Theory of Operation

Notes

An Assert_INTx message is sent to the root by the upstream port (i.e., port 0), when the aggregated state of the corresponding interrupt in the upstream port transitions from a negated to an asserted state. A Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the corresponding interrupt in the upstream port transitions from an asserted to a negated state.

PCI to PCI bridges must map interrupts on the secondary side of the bridge according to the device number of the device on the secondary side of the bridge. No mapping is performed for the PCI to PCI bridges corresponding to downstream ports as these ports only connect to device zero. A mapping is performed for the upstream port (i.e., port 0). This mapping for the PES24N3A is summarized in Table 3.8.

Upstream Port Interrupt (Port 0)

INTA INTB INTC INTD

Downstream Port1 Interrupt

Table 3.8 PES24N3A Downstream to Upstream Port Interrupt Routing

Port X INTy corresponds to external downstream generated INTy interrupts and INTy interrupts generated by the port

Port 2 INTC Port 2 INTD Port 2 INTA Port 2 INTB

Port 4 INTA Port 4 INTB Port 4 INTC Port 4 INTD

If a Downstream Port goes to DL_Down status, the INTx virtual wires associated with that port are negated, and the upstream port’s aggregate sate is updated accordingly. This may result in the upstream port generating a Deassert_Intx message.

Standard PCIe Error Detection and Handling

This section describes standard PCIe error detection and handling as prescribed by the PCIe base 1.1 specification.

Physical Layer Error s

Table 3.9 lists error checks performed by the physical layer and action taken when an error is detected.

PCIe Base 1.1

Error Condition

Invalid symbol or running disparity error detected.

Any TLP or DLLP framing rule violation. 4.2.2.1 Correctable error processing 8b/10b decode error 4.2.4.4 Correctable error processing Any violation of the link initialization or training

protocol

Table 3.9 Physical Layer Errors

Specification

Section

4.2.1.3 Correctable error processing

4.2.4 Uncorrectable error processing

Action Taken

Data Link Layer E rrors

Table 3.10 lists error checks performed by the data link layer and action taken when an error is detected.

PES24N3A User Manual 3 - 11 April 10, 2008

Page 50

IDT Theory of Operation

Notes

Error Condition

PCIe Base 1.1

Specification

Section

Action Taken

TLP ending in ENDB with LCRC that does not match inverted calculated LCRC

TLP received with incorrect LCRC 3.5.3.1 Correctable error processing TLP received with sequence number not equal

to NEXT_RCV_SEQ and this is not a duplicate TLP

Bad DLLP Replay time-out 3.5.2.1 Correctable error processing REPLAY NUM rollover 3.5.2.1 Correctable error processing Violation of flow control initialization protocol 3.3.1 Uncorrectable error processing Sequence number specified by AckNak_Seq

does not correspond to an unacknowledged TLP or to the value in ACKD_SEQ

Non-blocked surprise down as defined in 3.2.1 3.5.2.1 & 3.2.1 If checking is enabled, fatal error

Table 3.10 Data Link Layer Errors

A bad DLLP is a DLP with a bad LCRC.

3.5.3.1 TLP discarded

3.5.3.1 Correctable error processing

3.5.2.1 Correctable error processing

3.5.2.1 Uncorrectable error processing

processing

Transaction Layer Errors

The PES24N3A transaction layer functions are performed by the application layer. Table 3.11 lists error checks performed by the transaction link layer and action taken when an error is detected.

PCIe Base 1.1

Error Condition

Poisoned TLP received 2.7.2.2 For the non-advisory cases: non-

ECRC check failure 2.7.1 For the non-advisory cases: non-

Unsupported request Numerous For the non-advisory cases: non-

Table 3.11 Transaction Layer Errors (Part 1 of 2)

Specification

Section

Action Taken

fatal error processing. Advisory cases: correctable error processing. TLP header logged in AER.

fatal error processing. Advisory cases when ECRC checking is enabled: non-fatal error processing. TLP header logged in AER.

fatal error processing. Advisory cases: correctable error processing. TLP header logged in AER.

PES24N3A User Manual 3 - 12 April 10, 2008

Page 51

IDT Theory of Operation

Notes

PCIe Base 1.1

Error Condition

Completer abort Completion time-out

Unexpected completion 2.3.2 For the non-advisory cases: non-

Receiver overflow 2.6.1.2 RO bit set in TLSTSE debug reg-

Flow control protocol error 2.6.1 Not applicable. The PES24N3A

Malformed TLP See Table 3.12 and

Table 3.11 Transaction Layer Errors (Part 2 of 2)

Specification

Section

2.3.1

2.8

Table 3.13

Action Taken

Not applicable. The PES24N3A never generates non-posted transactions as a requester.

fatal error processing. Advisory cases: correctable error processing. TLP header logged in AER.

ister. Fatal error processing. TLP header is not AER.

does not check for any flow control errors.

Fatal error processing. TLP header logged in AER.

logged in

The PES24N3A supports the following advisory non-fatal error cases as defined by the PCIe base 1.1 specification.

– Non-posted request that is treated as an Unsupported Request (UR). – Poisoned TLP in which the PES24N3A is not the ultimate destination. – TLP with an ECRC error in which the PES24N3A is not the ultimate destination. – Unexpected completion.

When ECRC checking is enabled, the PES24N3A checks the ECRC of all TLPs in which the TLP Digest (TD) bit is set in the TLP header. When an ECRC error is detected for a TLP destined to the PES24N3A as the ultimate destination, then non-fatal error processing is initiated. When an E CRC error is detected for a TLP in which the PES24N3A is not the ultimate destination, then advisory correctable error processing is initiated.

Table 3.12 l ists the error checks performed by the i ngress transaction layer for malformed TLP s. These TLP error checks are performed when a TLP is received by the switch (i.e., by the stack associated with the port on which the switch receives the TLP).

TLP Type Error Check

All TLP must have a valid FMT/TYPE combination.

Data payload length ≤ Max_Payload_Size (i.e., MPS field in PCIEDCTL register).

All TLPs with data (i.e., FMT[1]=1)

LENGTH field must match actual payload data.

All TLPs with ECRC (i.e., TD=1)

Table 3.12 Ingress Malformed TLP Error Checks (Part 1 of 2)

PES24N3A User Manual 3 - 13 April 10, 2008

Actual TLP length must match calculated length (HEADER + PAYLOAD + ECRC).

Page 52

IDT Theory of Operation

Notes

TLP Type Error Check

I/O read or write request LENGTH = 1 (doubleword)

TC = 0 ATTR = 0 Last DWord BE[3:0] = 0b0000

Configuration read or write request LENGTH = 1 (doubleword)

TC = 0 ATTR = 0 Last DWord BE[3:0] = 0b0000

Message Requests interrupt message Power management message Error signalling message Unlock message Set power limit message

TLPs with Route to Root Complex routing.

TLPs with Broadcast from Root Complex routing.

TLPs with Gathered and Routed to Root Complex routing

Interrupt messages (INTx) May only be received by the downstream ports

TC = 0

May only be received on downstream ports.

May only be received on upstream ports.

May only be received by the downstream ports. Must be a PME_TO_ACK message (all other TLP types with this routing are illegal).

Trusted Cfg Request May only be received on upstream port (refer to PCIe

specification 2.0, section 6.12.1).

All TLP traffic class (TC) must be mapped to VC0. TC to

VC mapping is controlled by the TC/VC Map (TCVCMAP) field in the ingress port’s VC Resource 0 Control (VCR0CTL) register.

Table 3.12 Ingress Malformed TLP Error Checks (Part 2 of 2)

Table 3.13 lists the error checks performed by the egress transaction layer for malformed TLPs . These error checks are performed when a TLP leaves the switch (i.e., by the stack associated with the port on which the TLP leaves the switch).

TLP Type Error Check

All TLP traffic class (TC) must be mapped to VC0. TC to

VC mapping is controlled by the TC/VC Map (TCVCMAP) field in the egress port’s VC Resource 0 Control (VCR0CTL) register

Table 3.13 Egress Malformed TLP Error Checks

Routing Errors

This section lists TLP routing errors that are detected by the PES24N3A. All of these errors are treated as unsupported requests.

PES24N3A User Manual 3 - 14 April 10, 2008

Page 53

IDT Theory of Operation

Notes

Address R o ut e d TL Ps

– TLPs whose address decoding indicates they are to route back to the port on which they were

received.

– TLPs received on the upstream port that match the upstream port’s address range but which do

not match a downstream port’s address range (i.e., TLPs that do not route through the PES24N3A).

– TLPs that target a downstream port that is not enabled for such transactions.

• For prefetchable memory and non-prefetchable memory transactions, the Memory Access

Enable (MAE) bit must be set in the PCI Command (PCICMD) register.

• For I/O transactions, the I/O Access Enable (IOAE) bit must be set in the PCI Command (PCICMD) register.

– Memory and IO requests from downstream ports that target the upstream port and the Bus Master

Enable (BME) bit is cleared in the upstream port’s PCICMD register.

– Memory and IO requests received on downstream ports and the Bus Master Enable (BME) bit is

cleared in the downstream port’s PCICMD register.

– A VGA route from a VGA enabled downstream port.

Configuration Requests (Routed by ID)

– Type 0 requests that arrive on a downstream port. – Type 1 requests that arrive on a downstream port. – Type 1 requests that do not route through the upstream port’s PCI-to-PCI bridge. – Type 1 requests that are converted to T ype 0 requests at the upstream port but which do not target

an enabled downstream port device number (i.e., target a PCI-to-PCI bridge device number that doesn’t exist).

– Type 1 requests that route through the PES24N3A target a downstream port’s link partner (i.e.,

are converted to a Type 0 request at the downstream port), and which do not target device zero. Note that this check may be disabled by the DDDNC bit in the SWCTL register. See section SWCTL - Switch Control (0x404) on page 9-51 for more information.

Completions (Routed by ID)

– Completions that attempt to route back onto the link on which they were received. – Completions that do not have a valid route through the PES24N3A. – All completions that terminate within the PES24N3A (i.e., ones that target the upstream port bus

number or any device/function on the virtual PCI bus within the switch) are treated as unexpected completions.

ID Routed Messages

– Messages that attempt to route back onto the link on which they were received. – Messages that do not have a valid route through the PES24N3A. – Messages that target a downstream port device number that does not exist. – A non Vendor Defined Type 1 message which targets an enabled PES24N3A port (i.e., PCI-to-

PCI bridge). Vendor Defined Type 1 messages received by a PES24N3A port are silently discarded.

– A non Vendor Defined Type 1 message which is received by the upstream port.

Switch Specific Error Detection and Handling

This section describes PES24N3A-specific error detection and handling. Since these mechanisms are outside of the PCIe base 1.1 specification, the PES24N3A-specific initialization and error handling code may be required to take full advantage of these features.

PES24N3A User Manual 3 - 15 April 10, 2008

Page 54

IDT Theory of Operation

Notes

Switch Time-Outs

The switch core discards any TLP that reaches the head of an IFB queue and is more than 64 seconds old. This includes posted, non-posted, completion and inserted TLPs. Although this feature is enabled by default, it may be disabled by setting the Enable Switch Time-outs (ETO) bit in a port’s Switch Time-Out Control (SWTOCTL) register.

Whenever a TLP is discarded by a port due to a switch time-out, a bit corresponding to the type of TLP that was discarded is set in port’s Switch Time-Out Status (SWTOSTS) register. In addition, a saturating count field corresponding to the type of TLP that was discarded is incremented in the port’s Switch TimeOut Count (SWTOCNT) register. These saturating count fields are atomically cleared when read.

Corresponding to each TLP type that may be discarded in the SWTOSTS register is an associated field in the Switch Time-Out Reporting Control (SWTORCTL) register that controls the manner in which a dropped TLP of that type is reported. Error message reporting due to dropped TLPs is considered an internally generated error message and thus may be masked in the same manner as other internally generated error messages with the SERR Enable (SERRE) bit in the PCI Command (PCICMD) register and the error reporting enables (i.e., CERN, NFEREN, FEREN, and UREREN bits) in the PCI Express Device Control (PCIEDCTL) register.

If error reporting is enabled, an error message is generated when a status bit transitions from a zero to a one (i.e., is set) in the SWTOSTS register. A subsequent error of the same type is not reported until software clears the corresponding status bit and it is again set.

Following a fundamental reset, discarded posted and inserted TLPs are reported with an ERR_NONFATAL message. Discarded non-posted and completion TLPs are not reported by default since the requester’s completion timer will detect the loss of a TLP of this type. The default error reporting policy my be modified by the root, serial EEPROM, or slave SMBus master.

If during processing of a TLP with broadcast routing a switch core time-out occurs, then the switch core will abort processing of the TLP. This may result in the broadcast TLP being transmitted on some but not all downstream pots.

End-to-End Parity Checking

PCI Express provides reliable hop-by-hop communication between interconnected devices, such as roots, switches, and endpoints, by utilizing a 32-bit Link CRC (LCRC), sequence numbers, and a link level retransmission protocol. While this mechanism provides reliable communication between interconnected devices, it does not protect against corruption that may occur inside of a device. PCI Express defines an optional end-to-end data integrity mechanism that consists of appending a 32-bit end-to-end CRC (ECRC) computed at the source over the invariant fields of a Transaction Layer Packet (TLP) that is checked at the ultimate destination of the TLP. While this mechanism provides end-to-end error detection, unfortunately it is an optional PCI Express feature and has not been implemented in many North bridges and endpoints. In addition, the ECRC mechanism does not cover variant fields within a TLP.

Since deep sub-micron devices are known to be susceptible to single-event-upsets, a mechanism is desired that detects errors that occur within a PCI express switch. The PES24N3A parity protects all TLPs in the switch, thus enabling corruption that may occur inside of the device to be detected and reported even in systems that do not implement ECRC.

Data flowing into the PES24N3A is protected by the LCRC. Within the Data Link (DL) layer of the switch ingress port, the LCRC is checked and 32-bit DWord even parity is computed on the received TLP data. If an LCRC error is detected at this point, the link level retransmission protocol is used to recover from the error by forcing a retransmission by the link partner. As the TLP flows through the switch, its alignment or contents may be modified. In all such cases, parity is updated and not recomputed. Hence, any error that occurs is propagated and not masked by a parity regeneration. When the TLP reaches the DL layer of the switch egress port, parity is checked and in parallel a LCRC is computed. If the TLP is parity error free, then the LCRC and TLP contents are known to be correct and the LCRC is used to protect the packet through the lower portion of the DL layer, PHY layer, and link transmission.

PES24N3A User Manual 3 - 16 April 10, 2008

Page 55

IDT Theory of Operation

Notes

If a parity error is detected by the DL layer of an egress port, then the TLP is null ified by inverting the computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by the link-partner are discarded. In addition to nullifying the TLP, the End-to-End Parity Error (EEPE) bit is set in the Switch parity Error Status (SWPESTS) register, and the saturating End-to-End Parity Error Count (EEPEC) field is incremented in the Switch Parity Error Count (SWPECNT) register. The EEPEC field is atomically cleared when read.

All internal memories used to store TLP data within the PES24N3A are Dword even parity protected. Parity errors in these memories are propagated and reported using the end-to-end parity protection mechanism.

The End-to-End Parity Error Reporting (EEPE) field in the Switch Parity Error Reporting Control (SWPERCTL) register controls the manner in which end-to-end parity errors are reported. If error reporting is enabled, an error message is generated when the EEPE bit in the SWPESTS register transitions from a zero to a one. A subsequent error of the same type is not reported until software clears the corresponding status bit and it is again set. End-to-end parity checking at a port may be disabled by setting the Disable End-to-End Parity Checking (DEEPC) bit in the Switch Parity Error Control (SWPECTL) register.

Parity generation can never be disabled at a port. However, to facilitate parity generation and checking testing a mechanism exists to generate bad parity. When the Generate Bad End-to-End Parity (GBEEP) bit is set in the SWPECTL register, bad (i.e., inverted) parity is generated for all Dwords of a TLP when the length field in the TLP header matches the value of the Length (LENGTH) field in the SWPECTL register. TLPs whose header length field does not match the LENGTH field are passed to the switch core with correct parity.

Following a fundamental reset, end-to-end parity checking is enabled and errors are reported with an ERR_NONFATAL message to the root. The default error reporting policy may be modified by the root, serial EEPROM, or slave SMBus master.

In addition to TLPs that flow through the switch, cases exist in which TLPs are produced and consumed by the switch (e.g., a configuration requests and responses). Whenever a TLP is produced by the switch, parity is computed as the TLP is generated. Thus, error protection is provided on produced TLPs as they flow through the switch. In addition, parity is checked on all consumed TLPs. If an error is detected, the TLP is discarded and an error is reported using the mechanism described above.

This means that a parity error reported at a switch port cannot be definitively used to identify the location at which the error occurred as the error may have occurred when parity as generated at another port, in the switch core, or may have been generated locally (i.e., for ingress TLPs to the switch core which are consumed by the port such as Type 0 configuration read requests on the upstream port).

TLP Processing

The PES24N3A supports two forms of very basic processing on TLPs that flow through the switch. Since TLP processing modifies the contents of a TLP, it may not be used in systems that employ ECRC since ECRC is not recomputed after TLP modifications. When the Force Relaxed Ordering (FRO) bit is set in the TLP Processing Control (TLPPCTL) register, the value of the relaxed ordering attribute is set to the value dictated by the Relaxed Ordering Modification (ROM) field in the TLPPCTL register. This transformation is only performed on TLPs in which the relaxed ordering attribute is applicable.

The relaxed ordering attribute is applicable to all TLPs except: configuration requests, I/O requests, memory requests that are Message Signaled Interrupts (MSIs), and Message requests (except where specifically permitted). Since MSIs cannot be distinguished from memory write transactions by the sw itch, the relaxed ordering attribute of MSIs will be modified.

When the Force No-Snoop (FNS) bit is set in the TLP Processing Control (TLPPCTL) register, the value of the no-snoop attribute is set to the value dictated by the No-Snoop Modification (NSM) field in the TLPPCTL register. This transformation is only performed on TLPs in which the no-snoop attribute is applicable. The no-snoop attribute is applicable to all TLPs except: configuration requests, I/O requests, memory

PES24N3A User Manual 3 - 17 April 10, 2008

Page 56

IDT Theory of Operation

Notes

requests that are Message Signaled Interrupts (MSIs), and Message requests (except where specifically permitted). Since MSIs cannot be distinguished from memory write transactions by the switch, the no-snoop attribute of MSIs will be modified.

PES24N3A User Manual 3 - 18 April 10, 2008

Page 57

Chapter 4

Link Operation

Notes

Introduction

The PES24N3A contains three x8 ports. The default link width of each port is x8 and the SerDes lanes are statically assigned to a port.

Polarity Inversion

Each port of the PES24N3A supports automatic polarity inversion as required by the PCIe specification. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its data. During link training, the receiver examines symbols 6 through 16 of the TS1 and TS2 ordered sets for inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receivi ng lane automatically inverts received data.

Polarity inversion is a lane and not a link function. Therefore, it is possible for some lanes of link to be inverted and for others not

to be inverted.

Link Width Negotiation

The PES24N3A supports the optional link variable width negotiation feature outlined in the PCIe specification. During link training, each x8 port is capable of negotiating to a x8, x4, x2 or x1 link width. The negotiated width of each link may be determined from the Link Width (LW) field in the corresponding port’s PCI Express Link Status (PCIELSTS) register.

The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCAP) register contains the maximum link width of the port. This field is of RWL type and may be modified when the REGUNLOCK bit is set in the SWCTL register. Modification of this field allows the maximum link width of the port to be configured. The new link width takes effect the next time link training occurs. To force a link width to a smaller width than the default value, the MAXLNKWDTH field could be configured through Serial EEPROM initialization and full link retraining forced.

When port link negotiates to a width less than x8, the unused group of four lanes are powered down to save power. In addition, unused SerDes in a four lane group are put in a low power state (i.e. L1 state). When a port is disabled, all SerDes lanes associated with that port are powered down.

Lane Reversal

The PCIe specification describes an optional lane reversal feature. The PES24N3A supports the automatic lane reversal feature outlined in the PCIe specification. The operation of lane reversal is dependant on the maximum link width selected by the MAXLNKWDTH field. Lane reversal mapping for the various non-trivial x8 port maximum link width configurations supported by the PES24N3A are illustrated in Figures

4.1 through 4.2.

PES24N3A User Manual 4 - 1 April 10, 2008

Page 58

IDT Link Operation

Notes

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(a) x2 Port without lane reversal

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

lane 0 lane 1

PES24N3A

(b) x2 Port with lane reversal

lane 0

PES24N3A

(d) x1 Port with lane reversal

PExRP[0] PExRP[1] PExRP[2] PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

Figure 4.1 Port Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[5:0]=0x2)

lane 1 lane 0

lane 0

PES24N3A User Manual 4 - 2 April 10, 2008

Page 59

IDT Link Operation

Notes

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(a) x4 Port without lane reversal

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(e) x1 Port without lane reversal

lane 0 lane 1 lane 2 lane 3

lane 0 lane 1

lane 0

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(b) x4 Port with lane reversal

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(d) x2 Port with lane reversal

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(f) x1 Port with lane reversal

lane 3 lane 2 lane 1 lane 0

lane 1 lane 0

lane 0

Figure 4.2 Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[5:0]=0x4)

PES24N3A User Manual 4 - 3 April 10, 2008

Page 60

IDT Link Operation

Notes

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(a) x8 Port without lane reversal

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(e) x2 Port without lane reversal

lane 0 lane 1 lane 2 lane 3 lane 4 lane 5 lane 6 lane 7

lane 0 lane 1 lane 2 lane 3

lane 0 lane 1

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(b) x8 Port with lane reversal

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(d) x4 Port with lane reversal

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(f) x2 Port with lane reversal

lane 7 lane 6 lane 5 lane 4 lane 3 lane 2 lane 1 lane 0

lane 3 lane 2 lane 1 lane 0

lane 1 lane 0

PExRP[0] PExRP[1] PExRP[2]

PES24N3A

PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

(g) x1 Port without lane reversal

lane 0

PES24N3A

(h) x1 Port with lane reversal

PExRP[0] PExRP[1] PExRP[2] PExRP[3] PExRP[4] PExRP[5] PExRP[6] PExRP[7]

lane 0

Figure 4.3 Port Lane Reversal for Maximum Link Width of x8 (MAXLNKWDTH[5:0]=0x8)

Link Retraining

Link retraining should not cause either a downstream component or an upstream component to reset or revert to default values. Writing a one to the Link Retrain (LRET) bit in the upstream port’s PCI Express Link Control (PCIELCTL) register when the REGUNLOCK bit is set in the SYSCTL register forces the upstream PCIe link to retrain. When this occurs, the LTSSM transitions directly to the Recovery state.

Writing a one to the Link Retrain (LRET) bit in a downstream port’s PCI Express Link Control (PCIELCTL) register regardless of the REGUNLOCK bit state in the SYSCTL register forces the downstream PCIe link to retrain. When this occurs, the LTSSM transitions directly to the Recovery state.

PES24N3A User Manual 4 - 4 April 10, 2008

Page 61

IDT Link Operation

Notes

Link Down

When a link goes down, all TLPs received by that port and queued in the switch are discarded and all TLPs received by other ports and destined to the port whose link is down are treated as Unsupported Requests (UR). While a downstream link is down, it is possible to perform configuration read and write operations to the PCI-PCI bridge associated with that link. When a link comes up, flow control credits for the configured size of the IFB queues are advertised.

Slot Power Limit Support

The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream switch port or root port to the upstream port of a connected device or switch.

Upstream Port

When a Set_Slot_Power_Limit message is received by the upstream switch port, the fields in the message are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.

– Byte 0 bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale

(CSPLS) field.

– Byte 1 bits 1:0 of the message payload are written to the Captured Slot Power Limit Value

(CSPLV) field.

Downstream Port

A Set_Slot_Power_Limit message is sent by downstream switch ports when either of the following occurs:

– A configuration write is performed to the corresponding PCIESCAP register when the link associ-

ated with the downstream port is up.

– A link associated with the downstream port transitions from a non-operational state to an opera-

tional (i.e., up) state.

Link States

The PES24N3A supports the following link states:

– L0

Fully operational link state.

– L0s

Automatically entered low power state with shortest exit latency.

– L1

Lower power state than L0s. May be automatically entered or directed by software by placing the device in the D3hot state.

– L2/L3 Ready

The L2/L3 state is entered after the acknowledgement of a PM_Turn_Off Message. There is no TLP or DLLP communications over a link in this state.

– L3

Link is completely unpowered and off.

– Link Down

A transitional link down pseudo-state prior to L0. This pseudo-state is associated with the LTSSM Detect, Polling, Configuration, Disabled, Loopback, and Hot-Reset states.

PES24N3A User Manual 4 - 5 April 10, 2008

Page 62

IDT Link Operation

Notes

L0s L1

L2/L3 Ready

Figure 4.4 PES24N3A ASPM Link Sate Transitions

Fundamental Reset

Hot Reset

Etc.

Link Down

Active State Power Management

The operation of Active State Power Management (ASPM) is independent of power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transitions are initiated by hardware without software involvement. The PES24N3A ASPM supports the required L0s state as well as the optional L1 state.

The L0s Entry Timer (L0ET) field in the PCI Power Management Proprietary Control (PMPC) register controls the amount of time L0s entry conditions must be met before the hardware transitions the link to the L0s state.

The upstream switch port has the following L0s entry conditions:

– The receive lanes of all of the switch downstream ports whic h are not in a low power state (i.e.,

D3) and whose link is not down are in the L0s state.

– The switch has no TLPs to transmit on the upstream port or there are no available flow control

credits to transmit a TLP.

– There are no DLLPs pending for transmission on the upstream port.

The downstream switch ports have the following L0s entry conditions:

– The receive lanes of the switch upstream port are in the L0s state. – The switch has no TLPs to transmit on the downstream port or there are no available flow control

credits to transmit a TLP.

– There are no DLLPs pending for transmission on the downstream port.

The L1 Entry Timer (L1ET) field in the PCI Power Management Proprietary Control (PMPC) register controls the amount of time L1 entry conditions must be met before the hardware transitions the link to the L1 state. If these conditions are met and the link is in the L0 or L0s states, then the hardware will request a transition to the L1 state from its link partner. Note that L1 entry requests are only made by the PES24N3A’s upstream port. If the link partner acknowledges the transition, the L1 state is entered. Otherwise, the L0s state is entered.

The upstream switch port will only request entry into the L1 state when all of the downstream ports which are not in a low power state (i.e., D3) and whose links are not down are in the L1 state.

PES24N3A User Manual 4 - 6 April 10, 2008

Page 63

IDT Link Operation

Notes

Link Status

Associated with each port is a Port Link Up (PxLINKUP) status output and a Port Activity (PxACTIVE) status output. These outputs are provided on I/O Expander 4. See section I/O Expanders on page 6-6 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.

The PxLINKUP and PxACTIVE status outputs may be used to provide a visual indication of system state and activity or for debug. The PxLINKUP output is asserted when the PCI Express data link layer is up (i.e., when the LTSSM is in the L0, L0s, L1, or recovery states). When the data link layer is down, this output is negated.

The PxACTIVE output is asserted whenever any TLP, other than a vendor defined message, is transmitted or received on the corresponding port’s link. Whenever a PxACTIVE output is asserted, it remains asserted for at least 200 ms. Since an I/O expander output may change no more frequently than once every 40 ms, this translates into five I/O expander update periods.

PES24N3A User Manual 4 - 7 April 10, 2008

Page 64

IDT Link Operation

Notes

PES24N3A User Manual 4 - 8 April 10, 2008

Page 65

Chapter 5

General Purpose I/O

Notes

Introduction

The PES24N3A has 8 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space. As shown in Table 5.1, some GPIO pins are shared with other on-chip functions. The GPIO Function (GPIOFUNC) register determines whether a GPIO bit operates as a general purpose I/O or as the specified alternate function.

GPIO

0 P2RSTN Reset output for downstream port 2 Output 1 P4RSTN Reset output for downstream port 4 Output 2 IOEXPINTN0 SMBus I/O expander interrupt 0 Input 4 IOEXPINTN2 SMBus I/O expander interrupt 2 Input 7 GPEN General purpose event output Output

Alternate

Function

Pin Name

Alternate Function Description

Table 5.1 General Purpose I/O Pin Alternate Function

After reset, all GPIO pins default to the GPIO input function. GPIO pins configured as GPIO inputs are sampled no more frequently than once every 128ns and may be treated as asynchronous inputs.

Alternate

Function Pin Type

When a GPIO pin is configured to use the GPIO function, the unneeded alternate function associated with the pin is held in an inactive state by internal logic.

Note: Care should be exercised when configuring the GPIO pins as outputs since an incorrect configuration could cause damage to external components as well as the PES24N3A.

GPIO Configuration

Associated with each GPIO pin is a bit in the GPIOFUNC, GPIOCFG and GPIOD registers. Table 5.2 summarizes the configuration of GPIO pins.

GPIOFUNC GPIOCFG Pin Function

0 0 GPIO input 0 1 GPIO output 1 don’t care Alternate function

Table 5.2 GPIO P in Configuration

PES24N3A User Manual 5 - 1 April 10, 2008

Page 66

IDT General Purpose I/O

Notes

GPIO Pin Config ured as an Input

When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the GPIO pin is sampled and registered in the GPIOD register. The value of the input pin can be determined at any time by reading the GPIOD register. Note that the value in this register corresponds to the value of the pin whether the pin is configured as a GPIO input, GPIO output, or alternate function.

GPIO Pin Configured as an Output

When configured as an output in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the value in the corresponding bit position of the GPIOD register is driven on the pin. System designers should treat the GPIO outputs as asynchronous outputs. The actual value of the output pin can be determined by reading the GPIOD register

GPIO Pin Configured as an Al t ernate Function

When configured as an alternate function in the GPIOFUNC register, the pin behaves as described by the section associated with that function. The value of the alternate function pin can be determined at any time by reading the GPIOD register.

PES24N3A User Manual 5 - 2 April 10, 2008

Page 67

Chapter 6

SMBus Interfaces

Notes

Introduction

The PES24N3A contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES24N3A, allowing every register in the device to be read or written by an external SMBus master. The slave SMBus may also be used to initialize the serial EEPROM used for initialization. The Master SMBus interface provides connection for an optional external serial EEPROM used for initialization and optional external I/O expanders.

Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. As shown in Figure 6.1, the master and slave SMBuses may be used in a unified or split configuration.

PES24N3A

SSMBCLK SSMBDAT

MSMBCLK MSMBDAT

Processor

SMBus Master

Serial

EEPROM

(a) Unified Configuration

Hot-Plug

I/O

Expander

...

Other

SMBus

Devices

PES24N3A

SSMBCLK SSMBDAT

MSMBCLK MSMBDAT

Processor

SMBus Master

Serial

EEPROM

...

Hot-Plug

Expander

Other

SMBus

Devices

I/O

(b) Split Configuration

Figure 6.1 SMBus Interface Configuration Examples

In the unified configuration, shown in Figure 6.1(a), the master and slave SMBuses are tied together and the PES24N3A acts both as an SMBus master as well as an SMBus slave on this bus. This requires that the external SMBus master or processor that has access to the PES24N3A registers support SMBus arbitration. In some systems, this external SMBus master interface may be implemented using general purpose I/O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these systems, the PES24N3A may be configured to operate in a split configuration as shown in Figure 6.1(b).

PES24N3A User Manual 6 - 1 April 10, 2008

Page 68

IDT SMBus Interfaces

Notes

In the split configuration, the master and slave SMBuses operate as two independent buses. Thus, multi-master arbitration is not required.

Master SMBus Interface

The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM. It is also used to support optional I/O expanders used for hot-plug and other status signals.

Initialization

Master SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page 2-4). During a fundamental reset initialization sequence, the state of the Master SMBus Slow Mode (MSMBSMODE) signal is examined. If this signal is asserted, then the Master SMBus Clock Prescalar (MSMBCP) field in the SMBus Control (SMBUSCTL) register is initialized to support 100 KHz SMBus operation. If the signal is negated, then the MSMBCP field is initialized for 400 KHz SMBus operation.

Serial EEPROM

During a fundamental or hot reset, an optional serial EEPROM may be used to initialize any software visible register in the device. Serial EEPROM loading occurs if the Switch Mode (SWMODE[3:0]) field selects an operating mode that performs serial EEPROM initialization. The address used by the SMBus interface to access the serial EEPROM is specified by the MSMBADDR[4:1] signals as shown in Table 6.1.

Address Bit Address Bit Value

1 MSMBADDR[1] 2 MSMBADDR[2] 3 MSMBADDR[3] 4 MSMBADDR[4] 51 60 71

Table 6.1 Serial EEPROM SMBus Address

Device Initialization from a Serial EEPROM

During initialization from the optional serial EEPROM, the master SMBus interface reads configuration blocks from the serial EEPROM and updates corresponding registers in the PES24N3A. Any PES24N3A software visible register in any port may be initialized with values stored in the serial EEPROM.

Each software visible register in the PES24N3A has a CSR system address which is formed by adding the PCI configuration space offset value of the register to the base address of the configuration space in which the register is located. Configuration blocks stored in the serial EEPROM use this CSR system address shifted right two bits (i.e., configuration blocks in the serial EEPROM use doubleword CSR system addresses and not byte CSR system addresses).

Base addresses for the PCI configuration spaces in the PES24N3A are listed in Table 9.1 of Chapter 9. Since configuration blocks are used to store only the value of those registers that are initialized, a serial EEPROM much smaller than the total size of all of the configuration spaces may be used to initialize the device.

Any serial EEPROM compatible with those listed in Table 6.2 may be used to store the PES24N3A initialization values. Some of these devices are larger than the total size of all of the PCI configuration spaces in the PES24N3A that may be initialized and thus may not be fully utilized.

PES24N3A User Manual 6 - 2 April 10, 2008

Page 69

IDT SMBus Interfaces

Notes

Serial EEPROM Size

24C32 4 KB

24C64 8 KB 24C128 16 KB 24C256 32 KB 24C512 64 KB

Table 6.2 PES24N3A Compatible Serial EEPROMs

During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial EEPROM address zero. These bytes are interpreted as configuration blocks and sequential reading of the serial EEPROM continues until the end of a configuration done block is reached or the serial EEPROM address rolls over from 0xFFFF to 0x0. All register initialization performed by the serial EEPROM is performed in double word quantities.

There are three configuration block types that may be stored in the serial EEPROM. The first type is a single double word initialization sequence. A double word initialization sequence oc cupies six bytes in the serial EEPROM and is used to initialize a single double word quantity in the PES24N3A. A double word initialization sequence occupies six byes in the serial EEPROM and is used to initialize a single double word quantity in the PES24N3A.

A single double word initialization sequence consists of three fields and its format is shown in Figure 6.2. The CSR_SYSADDR field contains the double word C SR system address of the double word to be initialized. The actual CSR system address, which is a by te address, equals this value w ith two lower zero bits appended. The next field is the TYPE field that indicates the type of the configuration block. For single double word initialization sequence, this value is always 0x0. The final DATA field contains the double word initialization value.

Bit

Byte 0 CSR_SYSADDR[7:0]

Byte 1

Byte 2 DATA[7:0]

Byte 3 DATA[15:8]

Byte 4 DATA[23:16]

Byte 5 DATA[31:24]

TYPE

0x0

CSR_SYSADDR[13:8]

Bit

Figure 6.2 Single Double Word Initialization Sequence Format

The second type of configuration block is the sequential double word initialization sequence. It is similar to a single double word initialization sequence except that it contains a double word count that allows multiple sequential double words to be initialized in one configuration block.

A sequential double word initialization sequence consists of four required fields and one to 65535 double word initialization data fields. The format of a sequential double word initialization sequence is shown in Figure 6.3. The CSR_SYSADDR field contains the starting double word CSR system address to be initialized. The next field is the TYPE field that indicates the type of the configuration block. For sequential double word initialization sequences, this value is always 0x1. The NUMDW field specifies the number of double words initialized by the configuration block. This is followed by the number of DATA fields specified in the NUMDW field.

PES24N3A User Manual 6 - 3 April 10, 2008

Page 70

IDT SMBus Interfaces

Notes

Bit

Byte 0 CSR_SYSADDR[7:0]

Byte 1

Byte 2 NUMDW[7:0]

Byte 3 NUMDW[15:8]

Byte 4 DATA0[7:0]

Byte 5 DATA0[15:8]

Byte 6 DATA0[23:16]

Byte 7 DATA0[31:24]

TYPE

0x1

CSR_SYSADDR[13:8]

Bit

...

Byte 4n+4 DATAn[7:0]

Byte 4n+ 5 DATAn[15:8]

Byte 4n+6 DA TAn[23:16]

Byte 4n+7 DA TAn[31:24]

...

Figure 6.3 Sequential Double Word Initialization Sequence Format

The final type of configuration block is the configuration done sequence w hich is used to signify the end of a serial EEPROM initialization sequence. If during serial EEPROM initialization an attempt is made to initialize a register that is not defined in a configuration space (i.e., not defined in Chapter 9, Configuration Registers), then the Unmapped Register Initialization Attempt (URIA) bit is set in the S MBUSSTS register and the write is ignored.

The configuration done sequence consists of two fields and its format is shown in Figure 6.4. The CHECKSUM field contains the checksum of all of the bytes in all of the fields read from the serial EEPROM from the first configuration block to the end of this done sequence. The second field is the TYPE field which is always 0x3 for configuration done sequences.

Bit

Byte 0 CHECKSUM[7:0]

Byte 1

0x3

ReservedTYPE

(must be zero)

Figure 6.4 Configuration Done Sequence Format

The checksum in the configuration done sequence enables the integrity of the serial EEPROM initialization to be verified. Since uninitialized EEPROMs typically have a value of all ones, initialization from an uninitialized serial EEPROM will result in a checksum mismatch. The checksum is computed in the following manner:

An 8-bit counter is initialized to zero and the 8-bit sum is computed over the configuration bytes stored in the serial EEPROM, including the entire contents of the configuration done sequence, with the checksum field initialized to zero

. The 1’s complement of this sum is placed in the check-

sum field.

The checksum is verified in the following manner:

This includes the byte containing the TYPE field.

PES24N3A User Manual 6 - 4 April 10, 2008

Page 71

IDT SMBus Interfaces

Notes

An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence

. The correct result

should always be 0xFF (i.e., all ones).

Checksum checking may be disabled by setting the Ignore Checksum Errors (ICHEC KSUM) bit in the SMBus Control (SMBUSCTL) register.

If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM is aborted and the RSTHALT bit is set in the SWCTL register. This allows debugging of the error condition via the slave SMBus interface but prevents normal system operation with a potentially incorrectly initialized device. Error information is recorded in the SMBUSSTS register. Once serial EEPROM initialization completes, or when an error is detected, the EEPROM Done (EEPROMDONE) bit is set in the SMBus Status (SMBSTS) register. A summary of possible errors during serial EEPROM initialization and specific action taken when detected is summarized in Table 6.3.

Error Action Taken

Configuration Done Sequence checksum mismatch with that computed by the PES24N3A

Serial EERPOM address roll-over from 0xFFFF to 0x0000

Invalid configuration block type (only invalid type is 0x2)

Set RSTHALT bit in SWCTL register ICSERR bit is set in the SMBUSSTS register Abort initialization, set DONE bit in the SMBUSSTS register

An unexpected NACK is observed during a master SMBus transaction

Master SMBus interface loses 16 consecutive arbitration attempts

A misplaced START or STOP condition is detected by the master SMBus interface

Table 6.3 Serial EEPROM Initialization Errors

Set RSTHALT bit in SWCTL register NAERR bit is set in the SMBUSSTS register Abort initialization, set DONE bit in the SMBUSSTS register

Set RSTHALT bit in SWCTL register LAERR bit is set in the SMBUSSTS register Abort initialization, set DONE bit in the SMBUSSTS register

Set RSTHALT bit in SWCTL register OTHERERR bit is set in the SMBUSSTS register Abort initialization, set DONE bit in the SMBUSSTS register

Programming the Serial EEPROM

The serial EEPROM may be programmed prior to board assembly or in-system via the slave SMBus interface or a PCIe root. Programming the serial EEPROM via the slave SMBus is described in section Serial EEPROM Read or Write Operation on page 6-14. A PCIe root may read and write the serial EEPROM by performing configuration read and write transactions to the Serial EEPROM Interface (EEPROMINTF) register.

To read a byte from the serial EEPROM, the root should configure the Address (ADDR) field in the EEPROMINTF register with the byte address of the serial EEPROM location to be read and the Operation (OP) field to “read.” The Busy (BUSY) bit should then be checked. If the EEPROM is not busy, the read operation may be initiated by performing a write to the Data (DATA) field. When the serial EEPROM read operation completes, the Done (DONE) bit in the EEPROMINTF register is set and the busy bit is cleared. When this occurs, the DATA field contains the byte data of the value read from the serial EEPROM.

This includes the checksum byte as well as the byte that contains the type and reserved field.

PES24N3A User Manual 6 - 5 April 10, 2008

Page 72

IDT SMBus Interfaces

Notes

To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy (i.e., the BUSY bit is cleared), the write operation may be initiated by writing the v alue to be written to the DATA field. When the write operation completes, the DONE bit is set and the busy bit is cleared.

Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results. SMBus errors may occur when accessing the serial EEPROM. If an error occurs, it is reported in the SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial EEPROM access.

I/O Expanders

The PES24N3A utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus interface for hot-plug and port status signals. The PES24N3A is designed to work with Phillips PCA9555 compatible I/O expanders (i.e., PCA9555, PCA9535, and PCA9539). See the Phillips PCA9555 data sheet for details on the operation of this device.

An external SMBus I/O expander provides 16 bit I/O pins that may be configured as inputs or outputs. The PES24N3A supports up to five external I/O expanders. Table 6.4 summarizes the allocation of functions to I/O expanders. I/O expanders zero through three are used to provide hot-plug I/O signals while I/O expander four is used to provide link status and activity LED control.

I/O expander signals associated with LED control (i.e., link status and activity) are active low (i.e., driven low when an LED should be turned on). I/O expander signals associated with hot-plug signals are not inverted.

SMBus I/O

Expander

0 Lower Port 2 hot-plug

2 Lower Reserved

4 Lower Link status

Section Function

Upper Port 4 hot-plug

Upper Pow er good inputs

Upper Link activity

Table 6.4 I/O Expander Function Allocation

During the PES24N3A initialization, the SMBus/I2C-bus address allocated each I/O expander used in that system configuration should be written to the corresponding IO Expander Address (IOE[0,2,4]ADDR) field. The IOE[0,2]ADDR fields are contained in the I/O Expander Address 0 (IOEXPADDR0) register while the IOE[4]ADDR field is contained in the SMBus I/O Expander Address 1 (IOEXPADDR1) register.

Hot-plug outputs and I/O expanders may be initialized via serial EEPROM. Since the I/O expanders and serial EEPROM both utilize the master SMBus, no I/O expander transactions are initiated until serial EEPROM initialization completes.

– Since no I/O expander transactions are initiated until serial EEPROM initialization completes, it is

not possible to toggle a hot-plug output through serial EEPROM initialization (i.e., it is not possible to cause a 0 → 1 → 0 transition or a 1 → 0 → 1 transition).

Whenever the value of a IOExADDR field is modified, SMBus write transactions are issued to the corresponding I/O expander by the PES24N3A to configure the device. This configuration initializes the direction of each I/O expander signal and sets outputs to their default value. Outputs for ports that are disabled or are not implemented in that configuration, are set to their negated value (e.g., the power indicator is turned off, the link is down, there is no activity, etc.).

PES24N3A User Manual 6 - 6 April 10, 2008

Page 73

IDT SMBus Interfaces

Notes

The following I/O expander configuration sequence is issued by the PES24N3A to I/O expander zero:

– Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through

I/O-0.7) to I/O expander register 2.

– Write the default value of the outputs bits on the upper eight I/O expander pins (i.e.,I/O-1.0 through

I/O-1.7) to I/O expander register 3.

– Write value 0x0 to I/O expander register 4 (no inversion in IO-0) – Write value 0x0 to I/O expander register 5 (no inversion in IO-1). – Write the configuration value to select inputs/outputs in the lower eight I/O expander bits (i.e., I/O-

0.0 through I/O-0.7) to I/O expander register 6.

– Write the configuration value to select inputs/outputs in the upper eight I/O expander bits (i.e., I/

O-1.0 through I/O-1.7) to I/O expander register 7.

– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander

bits (i.e., I/O-0.0 through I/O-0.7).

– Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander

bits (i.e., I/O-1.0 through I/O-1.7).

The following I/O expander configuration sequence is issued by the PES24N3A to I/O expander two (i.e., the one that contains hot-plug signals and power good inputs):

– Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through

I/O-0.7) to I/O expander register 2.

– Write value 0x0 to I/O expander register 4 (no inversion in IO-0). – Write value 0x0 to I/O expander register 5 (no inversion in IO-1). – Write the configuration value to select inputs/outputs in the lower eight I/O expander bits (i.e., I/O-

0.0 through I/O-0.7) to I/O expander register 6.

– Write the configuration value to select all inputs upper eight I/O expander bits (i.e.,I/O-1.0 through

I/O-1.7) to I/O expander register 7.

– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander

bits (i.e., I/O-0.0 through I/O-0.7).

– Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander

bits (i.e., I/O-1.0 through I/O-1.7).

The following I/O expander configuration sequence is issued by the PES24N3A to I/O expander four:

– Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through

I/O-0.7) to I/O expander register 2.

– Write the default value of the outputs bits on the upper eight I/O expander pins (i.e.,I/O-1.0 through

I/O-1.7) to I/O expander register 3.

– Write value 0x0 to I/O expander register 4 (no inversion in IO-0) – Write value 0x0 to I/O expander register 5 (no inversion in IO-1). – Write the configuration value to select outputs in the lower eight I/O expander bits (i.e., I/O-0.0

through I/O-0.7) to I/O expander register 6.

– Write the configuration value to select outputs in the upper eight I/O expander bits (i.e., I/O-1.0

through I/O-1.7) to I/O expander register 7.

– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander

bits (i.e., I/O-0.0 through I/O-0.7).

– Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander

bits (i.e., I/O-1.0 through I/O-1.7).

While the I/O expander is enabled, the PES24N3A maintains the I/O bus expander signals and the PES24N3A internal view of the hot-plug signals in a consistent state. This means that whenever that I/O bus expander state and the PES24N3A internal view of the signal state differs, an SMBus transaction is initiated by the PES24N3A to resolve the state conflict.

PES24N3A User Manual 6 - 7 April 10, 2008

Page 74

IDT SMBus Interfaces

Notes

An example of an event that may lead to a state conflict is a hot reset. When a hot reset occurs, one or more hot-plug register control fields may be re-initialized to its default value. When this occurs, the internal PES24N3A state of the hot-plug signals is in conflict with the state of I/O expander hot-plug output signals. In such a situation, the PES24N3A will initiate an SMBus transaction to modify the state of the I/O expander hot-plug outputs.

Each I/O expander has an open drain interrupt output that is asserted when a pin configured as an input changes state from the value previously read. Each interrupt output from an I/O expander should be connected to the corresponding PES24N3A I/O expander interrupt input. Since the PES24N3A I/O expander interrupt inputs are GPIO alternate functions, the corresponding GPIOs should be initialized during configuration to operate in alternate function mode. See Chapter 5, General Purpose I/O.

Whenever the PES24N3A needs to change the state of an I/O expander signal output, a master SMBus transaction is initiated to update the state of the I/O expander. This write operation causes the corresponding I/O expander to change the state of its output(s). The PES24N3A will not update the state of an I/ O expander output more frequently than once every 40 milliseconds. This 40 millisecond time interval is referred to as the I/O expander update period.

Whenever an input to the I/O expander changes state from the value previously read, the interrupt output of the I/O expander is asserted. This causes the PES24N3A to issue a master SMBus transaction to read the updated state of the I/O expander inputs. Regardless of the state of the interrupt output of the I/O expander, the PES24N3A will not issue a master SMBus transaction to read the updated state of the I/O expander inputs more frequently than once every 40 milliseconds (i.e., the I/O expander update period). This delay in sampling may be used to eliminate external debounce circuitry.

The I/O expander interrupt request output is negated whenever the input values are read or w hen the input pin changes state back to the value previously read. The PES24N3A ensures that I/O expander transactions are initiated on the master SMBus in a fair manner. This guarantees that all I/O expanders have equal service latencies. Any errors detected during I/O expander SMBus read or write transactions is reflected in the status bits of the SMBus Status (SMBUSSTS) register.

The I/O Expander Interface (IOEXPINTF) register allows direct testing and debugging of the I/O expander functionality. The Select (SEL) field in the IOEXPINTF register selects the I/O expander number on which other fields in the register operate.

The I/O Expander Data field in the IOEXPINTF register reflects the current state, as viewed by the PES24N3A, of the I/O expander inputs and outputs selected by the SEL field.

Writing a one to the Reload I/O Expander Signals (RELOADIOEX) bit in the IOEXPINTF register causes the PES24N3A to generate SMBus write and read transactions to the I/O expander number selected in the SEL field. This results in the value of the IOEDATA field being updated to reflect the current state of the corresponding I/O expander signals. This feature may be used to aid in debugging I/O expander operation. For example, a user who neglects to configure a GPIO as an alternate function may use this feature to determine that master SMBus transactions to the I/O expander function properly and that the issue is with the interrupt logic.

The IO Expander Test Mode (IOEXTM) bit in the IOEXPTINF register allows an I/O expander test mode to be entered. When this bit is s et, the PES24N3A c ore logic outputs are ignored and the values written to the I/O expander for output bits are the values in the IOEDATA field. In this mode, the PES24N3A issues a transaction to update the state of the I/O expander whenever a bit corresponding to an I/O expander output changes state due to a write to the IOEDATA field. Bits in the IOEDATA field that correspond to outputs are dependent on the I/O expander number selected in the SEL field in the IOEXPINTF register. The outputs for each I/O expander number are shown in Tables 6.5 through 6.7.

PES24N3A User Manual 6 - 8 April 10, 2008

Page 75

IDT SMBus Interfaces

Notes

System Design Recommendations

1. I/O expander addresses and default output values may be configured during serial EEPROM initialization. If I/O expander addresses are configured via the serial EEPROM, then the PES24N3A will initialize the I/O expanders when normal device operation begins following the completion of the fundamental reset sequence.

2. If the I/O expanders are initialized via serial EEPROM, then the data value for output signals during the SMBus initialization sequence will correspond to those at the time the SMBus transactions are initiated. It is not possible to toggle SMBus I/O expander outputs by modifying data values during serial EEPROM initialization.

3. During a fundamental reset and before the I/O expander outputs are initialized, all I/O expander output signals default to inputs. Therefore, pull-up or pull-down resistors should be placed on outputs to ensure that they are held in the desired state during this period.

4. All hot-plug data value modifications that correspond to hot-plug outputs result in SMBus transactions. This includes modifications due to upstream secondary bus resets and hot-resets.

5. I/O expander outputs are not modified when the device transitions from normal operation to a fundamental reset. In systems where I/O expander output values must be reset during a fundamental reset, a PCA9539 I/O expander should be used.

I/O Expander 0

SMBus I/O

Expander

Bit

0 (I/O-0.0)

1 (I/O-0.1) I P2PDN Port 2 presence detect input

Type Signal Description

I P2APN Port 2 attention push button input

2 (I/O-0.2) I P2PFN Port 2 power fault input 3 (I/O-0.3) I P2MRLN Port 2 manually-operated retention latch

(MRL) input 4 (I/O-0.4) O P2AIN Port 2 attention indicator output 5 (I/O-0.5) O P2PIN Port 2 power indicator output 6 (I/O-0.6) O P2PEP Port 2 power enable output 7 (I/O-0.7) O P2ILOCKP Port 2 electromechanical interlock 8 (I/O-1.0) I P4APN Tie high

9 (I/O-1.1) I P4PDN Tie high

10 (I/O-1.2) I P4PFN Tie high 11 (I/O-1.3) I P4MRLN Tie high 12 (I/O-1.4) O P4AIN Tie high or low 13 (I/O-1.5) O P4PIN Tie high or low 14 (I/O-1.6) O P4PEP Tie high or low

15 (I/O-1.7) O P4ILOCKP Tie high or low

Table 6.5 I/O Expander 0 Signals

I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.

PES24N3A User Manual 6 - 9 April 10, 2008

Page 76

IDT SMBus Interfaces

Notes

I/O Expander 2

SMBus I/O

Expander

Bit

0 (I/O-0.0)

1 (I/O-0.1) I Reserved Tie high 2 (I/O-0.2) I Reserved Tie high 3 (I/O-0.3) I Reserved Tie high 4 (I/O-0.4) O Reserved Tie high or low 5 (I/O-0.5) O Reserved Tie high or low 6 (I/O-0.6) O Reserved Tie high or low 7 (I/O-0.7) O Reserved Tie high or low

8 (I/O-1.0) I Reserved Tie high 9 (I/O-1.1) I Reserved Tie high 10 (I/O-1.2) I P2PWRGDN Port 2 power good input

11 (I/O-1.3) I Reserved Tie high 12 (I/O-1.4) I P4PWRGDN Port 4 power good input

Type Signal Description

I Reserved Tie high

13 (I/O-1.5) I Reserved Tie high or low 14 (I/O-1.6) I Reserved Tie high or low

15 (I/O-1.7) I Reserved Tie high or low

Table 6.6 I/O Expander 2 Signals

I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.

I/O Expander 4

SMBus I/O

Expander

Bit

0 (I/O-0.0)

1 (I/O-0.1) O Reserved Tie high or low 2 (I/O-0.2) O P2LINKUPN Port 2 link up status output 3 (I/O-0.3) O Reserved Tie high or low 4 (I/O-0.4) O P4LINKUPN Port 4 link up status output 5 (I/O-0.5) O Reserved Tie high or low 6 (I/O-0.6) O Reserved Tie high or low

Type Signal Description

O P0LINKUPN Port 0 link up status output

7 (I/O-0.7) O Reserved Tie high or low 8 (I/O-1.0) O P0ACTIVEN Port 0 activity output

9 (I/O-1.1) O Reserved Tie high or low

Table 6.7 I/O Expander 4 Signals

PES24N3A User Manual 6 - 10 April 10, 2008

Page 77

IDT SMBus Interfaces

Notes

SMBus I/O

Expander

Bit

10 (I/O-1.2) O P2ACTIVEN Port 2 activity output 11 (I/O-1.3) O Reserved Tie high or low 12 (I/O-1.4) O P4ACTIVEN Port 4 activity output 13 (I/O-1.5) O Reserved Tie high or low 14 (I/O-1.6) O Reserved Tie high or low

15 (I/O-1.7) O Reserved Tie high or low

I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.

Type Signal Description

Table 6.7 I/O Expander 4 Signals

Slave SMBus Interface

The slave SMBus interface provides the PES24N3A with a configuration, management and debug interface. Using the slave SMBus interface, an external master can read or write any software visible register in the device.

Initialization

Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page 2-4). During the fundamental reset initialization sequence, the slave SMBus address is initialized. The address is specified by the SSMBADDR[5,3:1] signals as shown in Table 6.8.

Address Bit Address Bit Value

1 SSMBADDR[1] 2 SSMBADDR[2] 3 SSMBADDR[3] 40 5 SSMBADDR[5] 61 71

Table 6.8 Slave SMBus Address When a Static Address is Selected

SMBus Transactions

The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. See the SMBus 2.0 specification for a detailed description of these transactions.

– Byte and Word Write/Read – Block Write/Read

Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces undefined results. Associated with each of the above transactions is a command code. The command code format for operations supported by the slave SMBus interface is shown in Figure 6.5 and described in Table

6.9.

PES24N3A User Manual 6 - 11 April 10, 2008

Page 78

IDT SMBus Interfaces

Notes

Bit

ENDSTARTFUNCTIONSIZEPEC

Figure 6.5 Slave SMBus Command Code Format

Bit Name Description

0 END End of transaction indicator. Setting both START and END

signifies a single transaction sequence. 0 - Current transaction is not the last read or write

sequence.

1 - Current transaction is the last read or write sequence.

1 START Start of transaction indicator. Setting both START and END

signifies a single transaction sequence. 0 - Current transaction is not the first of a read or write

sequence.

1 - Current transaction is the first of a read or write

sequence.

4:2 FUNCTION This field encodes the type of SMBus operation.

0 - CSR register read or write operation 1 - Serial EEPROM read or write operation 2 through 7 - Reserved

6:5 SIZE This field encodes the data size of the SMBus transaction.

0 - Byte 1 - Word 2 - Block 3 - Reserved

7 PEC This bit controls whether packet error checking is enabled

for the current SMBus transaction.

0 - Packet error checking disabled for the current SMBus

transaction.

1 - Packet error checking enabled for the current SMBus

transaction.

Table 6.9 Slave SMBus Command Code Fields

The FUNCTION field in the command code indicates if the SMBus operation is a CSR register read/ write or a serial EEPROM read/write operation. Since the format of these transactions is different, each will be described in the following sections. If a command is issued while one is already in progress or if the slave is unable to supply data associated with a command, the command is NACKed. This indicates to the master that the transaction should be retried.

CSR Register Read or Write Operation

Table 6.10 indicates the sequenc e of data as it is presented on the slave SMBus following the byte address of the Slave SMBus interface.

PES24N3A User Manual 6 - 12 April 10, 2008

Page 79

IDT SMBus Interfaces

Notes

Byte

Position

Field Name Description

0CCODECommand Code. Slave Command Code field described in

Table 6.9.

1 BYTCNT Byte Count. The byte count field is only transmitted for

block type SMBus transactions. SMBus word and byte accesses do not contain this field. The byte count field indicates the number of bytes following the byte count field when performing a write or setting up for a read. The byte count field is also used when returning data to indicate the number of following bytes (including status). Note that the

byte count field does not include the PEC byte if PEC is enabled.

2CMDCommand. This field encodes fields related to the CSR

3 ADDRL Address Low. Lower 8-bits of the doubleword CSR system

address of register to access.

4 ADDRU Address Upper. Upper 6-bits of the doubleword CSR sys-

tem address of register to access. Bits 6 and 7 in the byte

must be zero and are ignored by the hardware. 5 DATALL Data Lower. Bits [7:0] of data doubleword. 6 DATALM Data Lower Midd l e. Bits [15:8] of data doubleword. 7 DATAUM Data Upper Middle. Bits [23:16] of data doubleword. 8 DATAUU Data Upper. Bits [31:24] of data doubleword.

Table 6.10 CSR Register Read or Write Operation Byte Sequence

The format of the CMD field is shown in Figure 6.6 and described in Table 6.11.

Bit

Bit Field Name Type Description

0 BELL Read/Write Byte Enable Lower. When set, the byte enable for bits

1 BELM Read/Write Byte Enable Lower Middle. When set, the byte enable

2 BEUM Read/Write Byte Enable Upper Middle. When set, the byte enable

Bit

Figure 6.6 CSR Register Read or Write CMD Field Format

[7:0] of the data word is enabled.

for bits [15:8] of the data word is enabled.

for bits [23:16] of the data word is enabled.

Bit

BELLBELMWERR BEUMBEUUOPRERR 0

3 BEUU Read/Write Byte Enable Upper. When set, the byte enable for bits

[31:24] of the data word is enabled.

Table 6.11 CSR Register Read or Write CMD Field Description (Part 1 of 2)

PES24N3A User Manual 6 - 13 April 10, 2008

Page 80

IDT SMBus Interfaces

Notes

Bit Field Name Type Description

4 OP Read/Write CSR Operation. This field encodes the CSR operation to

be performed. 0 - CSR write

1 - CSR read 5 0 0 Reserved. Must be zero 6 RERR Read-Only

and Clear

7 WERR Read-Only

and Clear

Table 6.11 CSR Register Read or Write CMD Field Description (Part 2 of 2)

Read Error. This bit is set if the last CSR read SMBus

transaction was not claimed by a device. Success indi-

cates that the transaction was claimed and not that the

operation completed without error.

Write Error. This bit is set if the last CSR write SMBus

transaction was not claimed by a device. Success indi-

cates that the transaction was claimed and not that the

operation completed without error.

Serial EEPROM Read or Write Operation

Table 6.12 indicates the sequenc e of data as it is presented on the slave SMBus following the byte

address of the Slave SMBus interface.

Byte

Position

Field Name Description

0CCODECommand Code. Slave Command Code field described in

Table 6.9.

1 BYTCNT Byte Count. The byte count field is only transmitted for

block type SMBus transactions. SMBus word and byte accesses to not contain this field. The byte count field indicates the number of bytes following the byte count field when performing a write or setting up for a read. The byte count field is also used when returning data to indicate the number of following bytes (including status).

2CMDCommand. This field contains information related to the

serial EEPROM transaction

3 EEADDR Serial EEPROM Address. This field specifies the address

of the Serial EEPROM on the Master SMBus when the USA bit is set in the CMD field. Bit zero must be zero and thus the 7-bit address must be left justified.

4 ADDRL Address Low. Lower 8-bits of the Serial EEPROM byte to

access.

5 ADDRU Address Upper. Upper 8-bits of the Serial EEPROM byte

to access.

6DATAData. Serial EEPROM value read or to be written.

Table 6.12 Serial EEPROM Read or Write Operation Byte Sequence

The format of the CMD field is shown in Figure 6.7 and described in Table 6.13.

PES24N3A User Manual 6 - 14 April 10, 2008

Page 81

IDT SMBus Interfaces

Notes

Bit

Figure 6.7 Serial EEPROM Read or Write CMD Field Format

Bit

OPUSA0 NAERRLAERROTHERERR 0

Bit Field Name Type

Description

0OPRWSerial EEPROM Operation. This field encodes the serial

EEPROM operation to be performed.

0 - Serial EEPROM write

1 - Serial EEPROM read 1USARWUse Specified Address. When this bit is set the serial

EEPROM SMBus address specified in the EEADDR is

used instead of that specified in the ADDR field in the

EEPROMINTF register.

When this bit is set the serial EEPROM SMBus address

specified in the EEADDR is used instead of that specified

in the MSMBADDR field in the SMBUSSTS register. 2 Reserved 3 NAERR RC No Acknowledge Error. This bit is set if an unexpected

NACK is observed during a master SMBus transaction

when accessing the serial EEPROM. This bit has the

same function as the NAERR bit in the SMBUSSTS reg-

ister.

The setting of this bit may indicate the following: that the

addressed device does not exist on the SMBus (i.e.,

addressing error), data is unavailable or the device is

busy, an invalid command was detected by the slave,

invalid data was detected by the slave. 4 LAERR RC Lost Arbitration Error. This bit is set if the master

SMBus interface loses 16 consecutive arbitration

attempts when accessing the serial EEPROM. This bit

has the same function as the LAERR bit in the

SMBUSSTS register. 5 OTHERERR RC Other Error. This bit is set if a misplaced START or

STOP condition is detected by the master SMBus inter-

face when accessing the serial EEPROM. This bit has

the same function as the OTHERERR bit in the

SMBUSSTS register.

7:6 Reserved 0 Reserved. Must be zero.

Table 6.13 Serial EEPROM Read or Write CMD Field Description

See Table 2 in the About This Manual chapter for a definition of these abbreviations.

Sample Slave SMBus Operation

Figures 6.8 through 6.13 illustrate sample Slave SMBus operations. Shaded items are driven by the

PES24N3A’s slave SMBus interface and non-shaded items are driven by an SMBus host.

PES24N3A User Manual 6 - 15 April 10, 2008

Page 82

IDT SMBus Interfaces

)

Notes

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

Wr A

Wr A A

ADDRU

CCODE

START,END

CCODE

START,END

CCODE

START,END

BYTCNT=3

(PES24N3A not ready with data)

PES24N3A Slave

SMBus Address

DATALMDATALL

A A P

CMD=read

BYTCNT=7

DATAUM

ADDRL

A A A

DATAUU

ADDRU

Figure 6.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

Wr A A

ADDRU

Wr A N

Wr A A

CCODE

START,END

CCODE

START,END

CCODE

START,END

BYTCNT=4

(PES24N3A not ready with data)

PES24N3A Slave

SMBus Address

CMD=read

BYTCNT=5

EEADDR

ADDRL

A A A

A P

ADDRLCMD (status)

EEADDRCMD (status)

ADDRL

DATAADDRU

A P

Figure 6.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC Disabled

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

Wr A

DATALL

CCODE

START,END

CCODE

START,END

CCODE

START,END

DATALM

(PES24N3A busy with previous command, not ready for a new command

N P

(PES24N3A busy with previous command, not ready for a new command

N P

BYTCNT=7

DATAUM

CMD=write

DATAUU

A P

ADDRL

ADDRU

Figure 6.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled

PES24N3A User Manual 6 - 16 April 10, 2008

Page 83

IDT SMBus Interfaces

Notes

PES24N3A Slave

SMBus Address

Wr A

ADDRU

CCODE

START,END

DATA

A P

BYTCNT=5

CMD=write

EEADDR

ADDRL

Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled

PES24N3A Slave

SMBus Address

Wr A A

ADDRU

CCODE

START,END

DATA

BYTCNT=5

A P

PEC

CMD=write

EEADDR

ADDRL

Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled

PES24N3A User Manual 6 - 17 April 10, 2008

Page 84

IDT SMBus Interfaces

Notes

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave SMBus Address

PES24N3A Slave

SMBus Address

CCODE

STAR T, Word

CCODE

END, Byte

CCODE

START,Word

CCODE

START,Word

CCODE

ADDRU

CCODE

Word

Wr A

Wr A A

Wr A

Rd A P

Byte

N P

A N

CMD=read

ADDRU

ADDRL

(PES24N3A not ready with data)

ADDRLCMD (status)

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

PES24N3A Slave

SMBus Address

Rd A A

CCODE

END, Word

Rd A A

DATALMDATALL

DATAUUDATAUM

Figure 6.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled

PES24N3A User Manual 6 - 18 April 10, 2008

Page 85

Chapter 7

Power Management

Notes

Introduction

Located in configuration space of each PCI-PCI bridge in the PES24N3A is a power management capability structure. The power management capability structure associated with a PCI-PCI bridge of a downstream port only affects that port. Entering the D3

the L1 state.

– The link associated with a port in the D3

spective of the link or power management state of any other switch port.

The power management capability structure associated with the upstream port (i.e., port 0) affects the entire device. When the upstream port enters a low power state and the PME_TO_Ack messages are received, then the entire device is placed into a low power state.

The PES24N3A supports the following device power management states: D0 Uninitialized, D0 Active, D3

, and D3

hot

. A power management state transition diagram for the states supported by the

cold

PES24N3A is provided in Figure 7.1 and described in Table 7.1.

Transitioning a port’s power management state from D3 being reset or re-initialization of register values. However, the default value of the No Soft Reset

(NOSOFTRST) bit in the PCI Power Management Control and Status (PMCSR) register corresponds to the functional context being maintained in the D3

Power-On Reset

state allows the link associated with the bridge to enter

hot

state will attempt to transition into L1 link state irre-

hot

to D0uninitialized does not result in any logic

hot

state.

hot

Uninitialized

Active

hot

cold

Figure 7.1 PES24N3A Power Management State Transition Diagram

PES24N3A User Manual 7 - 1 April 10, 2008

Page 86

IDT Power Management

Notes

From State To State Description

Any D0 Uninitialized Power-on fundamental reset.

D0 Uninitialized D0 Active PCI-PCI bridge configured by software

D0 Active D3

hot

Table 7.1 PES24N3A Power Management State Transition Diagram

D0 Uninitialized The Power Management State (PMSTATE) field in the

hot

cold

The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the

state.

hot

PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to D0 state.

Power is removed from the device.

The PES24N3A PCI-to-PCI bridges (i.e., ports) have the following behavior when in the D3 management state:

– A bridge accepts, processes and completes all type 0 configuration read and write requests. – A bridge accepts and processes all message requests that target the bridge. – All requests received by the bridge on the primary interface, except as noted above, are treated

as unsupported requests (UR).

– Any error message resulting from the receipt of a TLP is reported in the same manner as when

the bridge is not in D3

(e.g, generation of an ERR_NONFTAL message to the root).

hot

– Error messages resulting from any event other than the receipt of a TLP are discarded (i.e., no

error message is generated).

– All completions that target the bridge are treated as unexpected completions (UC). – Completions flowing in either direction through the bridge are routed as normal. This behavior of

the bridge does not differ from that of the bridge when it is in the D0 power management state.

– All request TLPs received on the secondary interface are treated as unsupported requests (UR).

hot

power

PME Messages

The PES24N3A does not support generation of PME messages from the D3 ports (i.e., PCI-PCI bridges associated with downstream ports) support the generation of hot-plug PME

events (i.e., a PM_PME power management message) from the D3 when the downstream port is in the D3

state or the entire switch is in the D3

hot

state. This includes both the case

hot

The generation of a PME message by downstream ports necessitates the implementation of a PME service time-out mechanism to ensure that PME messages are not lost. If the PME Status (PMES) bit in the a downstream port’s PCI Power Management Control and Status (PMCSR) register is not cleared within the time-out period specified in the PM_PME Time-Out (PMPMETO) field in the ports PM_PME Timer (PMPMETIMER) register after a PM_PME message is transmitted, then the PM_PME message is retransmitted and the timer is restarted.

state. Downstream

cold

state.

Power Express Power Management Fence Protocol

Root complex takes the following steps to turn off power to a system.

– The root places all devices in the D3 state – Upon entry to D3, all devices transition their links to the L1 state – The root broadcasts a PME_Turn_Off message. – Devices acknowledge the PME_Turn_Off message by returning a PME_TO_ACK message

PES24N3A User Manual 7 - 2 April 10, 2008

Page 87

IDT Power Management

Notes

The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any power management state. When the PES24N3A receives a PME_Turn_Off message, it broadcasts the PME_Turn_Off message on all active downstream ports. The PES24N3A transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its active downstream ports. This process is called PME_TO_Ack aggregation.

The aggregation of PME_TO_Ack messages on downstream ports is abandoned by the PES24N3A when it receives a TLP on its upstream port after it has received a PME_Turn_Off message on that port, but before it has responded with a PME_TO_Ack message. Once a PME_TO_Ack message has been scheduled for transmission on the upstream port, the PME_TO_Ack aggregation process has completed, and all received TLPs at that point may be discarded.

If the TLP that causes PME_TO_Ack aggregation to be abandoned targets the PES24N3A, then the PES24N3A responds to the TLP normally. If the TLP that causes aggregation to be abandoned targets a downstream port and the port is in L0, then the TLP is transmitted on the downstream port. If the downstream port is not in L0 (i.e., it is in L2/L3 Ready), the switch transitions the link to Detect and then to L0. Once the link reaches L0, the TLP is transmitted on the downstream port.

When PME_TO_Ack aggregation is abandoned, the PES24N3A makes no attempt to abandon the PME_Turn_Off and PME_TO_Ack protocol on downstream ports. Devices downstream of the PES24N3A are allowed to respond with a PME_TO_Ack and to transition to L2/L3 Ready. When a TLP is received that targets the downstream port, the switch transitions the link to Detect and then to L0. Once the link reaches L0, the TLP is transmitted on the downstream port.

In order to avoid a deadlock, a downstream port that does not receive a PME_TO_Ack message in the time-out period specified in the PME_TO_Ack Time-Out (PMETOATO) field in its corresponding PME_TO_Ack Timer (PMETOATIMER) register declares a time-out, transitions its link to L2/L3 Ready, and signals to the upstream port that a PME_TO_Ack message has been received.

If instead of being transitioned to the D3 state, it will resume generating PM_PME messages.

cold state, the PES24N3A is transitioned to the D0uninitialized

Power Budgeting Capability

The PES24N3A contains the mechanisms necessary to implement the PCI express power budgeting enhanced capability. However, by default, these mechanisms are not enabled. To enable the power budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to the power budgeting capability. The Next Pointer (NXTPTR) of the power budgeting capability should be adjusted if necessary.

The power budgeting capability consists of the four power budgeting capability registers defined in the PCIe 1.1 base specification and eight general purpose read-write registers. See section Power Budgeting Enhanced Capability on page 9-49 for a description of these registers.

The Power Budgeting Capabilities (PWRBCAP) register contains the PCI express enhanced capability header for the power budgeting capability. By default, this register has an initial read-only value of zero. To enable the power budgeting capability, this register should be initialized via the serial EEPROM. The Power Budgeting Data Value [0..7] (PWRBDV[0..7) registers are used to hold the power budgeting information for that port in a particular operating condition.

The PWRBDV registers may be read and written when the Power Budgeting Data Value Unlock (PWRBDVUL) bit is set in the Switch Control (SWCTL) register. When the PWRBDVUL bit is cleared, these register are read-only and writes to these registers are ignored. To enable the power budgeting capability, the PWRBDV registers should be initialized with power budgeting information via the serial EEPROM.

PES24N3A User Manual 7 - 3 April 10, 2008

Page 88

IDT Power Management

Notes

PES24N3A User Manual 7 - 4 April 10, 2008

Page 89

Chapter 8

Hot-Plug and Hot-Swap

Notes

Introduction

As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configurations. Figure 8.1 illustrates the use of the PES24N3A in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged. Figure 8.2 illustrates the use of the PES24N3A in an add-in card application. Here the downstream ports are hardwired to devices on the addin card and the upstream port serves as the add-in card’s PCIe interface. In this application the upstream port may be hot-plugged into a slot on the main system. Finally, Figure 8.3 illustrates the use of the PES24N3A in a carrier card application. In this application, the downstream ports are connected to slots which may be hot-plugged and the entire assembly may be hot-plugged into a slot on the main system. Since this application requires nothing more than the functionality illustrated in both Figures 8.1 through 8.3, it will not be discussed further.

Upstream

Link

Port 0

PES24N3A

Master SMBus

Port 1

Port 2

SMBus I/O

Expander

Hot-Plug Signals

Port 1

Slot

Figure 8.1 Hot-Plug on Switch Downstream Slots Application

Port 2

Slot

PES24N3A User Manual 8 - 1 April 10, 2008

Page 90

IDT Hot-Plug and Hot-Swap

Notes

Add-In Card

Upstream

Link

Port 0

PES24N3A

Port 1

PCI Express

Device

Port 2

PCI Express

Device

Figure 8.2 Hot-Plug with Switch on Add-In Card Application

Upstream

Link

Carrier

Card

Port 0

PES24N3A

Master SMBus

Port 1 Port 2

SMBus I/O

Expander

Hot-Plug Signals

Port 1

Slot

Port 2

Slot

Figure 8.3 Hot-Plug with Carrier Card Application

The PCI Express Base Specification revision 1.1 allowed a hot-plug attention indicator, power indicator, and attention button to be located on the board on which the slot is implemented or on the add-in board. When located on the add-in board, state changes are communicated between the hot-plug controller associated with the slot and the add-in card via hot-plug messages. This capability was removed in revision 1.1 of the PCI Express Base Specification and is not supported in the PES24N3A.

PES24N3A User Manual 8 - 2 April 10, 2008

Page 91

IDT Hot-Plug and Hot-Swap

Notes

The remainder of this section discusses the use of the PES24N3A in an application involving an add-in card hot-plugged into a downstream slot. Associated with each downstream port in the PES24N3A is a hotplug controller. The hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capabilities (PCIESCAP) register associated with that port during configuration (e.g., via serial EEPROM).

The PES24N3A allows sensor inputs and indicator outputs to be located next to the slot or on the plug in the module. Regardless of the physical location, the indicators are controlled by the PES24N3A’s downstream port. Table 8.1 lists the hot-plug inputs and outputs that may be associated with a slot. When enabled during configuration in the PCIESCAP register, these inputs and outputs are made available to external logic using an external I/O expander located on the master SMBus interface. The PES24N3A only supports Presence Detect Signalling via a pin assertion. It does not support In-band Presence Detect.

Signal Type Name/Description

PxAPN I Port x PxPDN I Port x Presence Detect Input.

PxPFN I Port x Power Fault Input.

PxMRLN I Port x Manually-operated Retention Latch (MRL) Input.

PxAIN O Port x Attention Indicator Output. PxPIN O Port x Power Indicator Output.

PxPEP O Port x Power Enable Output.

PxILOCKP O Port x Electromechanical Interlock.

PxPWRGDN I Port x Power Good Input (asserted when slot power is good).

PxRSTN

O Port x Reset Output.

Attention Push button Input.

Table 8.1 Downstream Port Hot-Plug Signals

x corresponds to downstream port number (i.e., 2 and 4).

This signal is a GPIO pin alternate function and is not available as an I/O expander output .

Since the polarity of hot-plug signals has been defined differently in various specifications, each hot-plug signal has a corresponding control bit in the Hot-Plug Configuration Control (HPCFGCTL) that allows the polarity of that signal to be inverted. Inversion affects the corresponding signal in all ports.

When a one is written to the EIC bit in the PCIESCTL register, then the PxILOCKP signal is pulsed with a pulse length greater than 100 ms and less than 150 ms (i.e., it transactions from negated to asserted, maintains an asserted state for 100 to 150 ms, and then transitions back to negated). When the Toggle Electromechanical Interlock Control. (TEMICTL) bit in the HPCFGCTL register is set, writing a one to the EIC bit inverts the state of the PxILOCKP signal.

When the Replace MRL Status with EMIL Status (RMRLWEMIL) bit is set in the HPCFGCTL register, then the port’s PxMRLN input is used as the electromechanical state input. The state of this input is used as the state of the electromechanical interlock state obtained by reading the Electromechanical Interlock Status (EIS) bit in the PCI Express Slot Status (PCIESSTS) register. In this mode, the state of the manuallyoperated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of the corresponding PxILOCKP I/O expander signal output.

When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register, then power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register.

Downstream port reset outputs are described in section Downstream Port Reset Outputs on page 2-8.

PES24N3A User Manual 8 - 3 April 10, 2008

Page 92

IDT Hot-Plug and Hot-Swap

Notes

The default value of hot-plug registers following a hot or fundamental reset may be configured via serial EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization, the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result of serial EEPROM initialization.

Hot-Plug I/O Expander

The PES24N3A utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus interface for hot-plug related signals associated with downstream ports. See section I/O Expanders on page 6-6 for details on the operation of the I/O expanders and for the mapping of downstream hot-plug signals to I/O expander inputs and outputs.

Hot-Plug Interrupts and Wake-up

The hot-plug controller associated with a downstream slot may generate an interrupt or wake-up event. Hot-plug interrupts are only generated when the Hot-Plug Interrupt Enable (HPIE) bit is set in the corresponding port’s PCI Express Slot Control (PCIESCTL) register.

The following bits, when set in the PCI Express Slot Status (PCIESSTS) register, generate an interrupt if not masked by the corresponding bit in the PCI Express Slot Control (PCIESCTL) register or by the HPIE bit:

– Attention Button Pressed (ABP) – Power Fault Detected (PFD) – MRL Sensor Changed (MRLSC) – Presence Detected Changed (PDC) – Command Completed (CC).

When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable (EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command (PCICMD) register. When the downstream port or the entire switch is in a D3

state, the hot-plug

Hot

controller generates a wake-up event using a PM_PME message instead of an interrupt if the event interrupt is not masked in the slot control (PCIESCTL) register and hot-plug interrupts are disabled by the HPIE bit. If the event interrupt is not masked and hot-plug interrupts are enabled, both a PM_PME and an interrupt are generated. If the event interrupt is masked, neither a PM_PME nor interrupt are generated.

Note: A command completed (CC bit) interrupt will not generate a wake-up event.

Legacy System Hot-Plug Support

Some systems require support for operating systems that lack PCIe hot-plug support. The PES24N3A supports these systems by providing a General Purpose Event (GPEN) output as an alternate function of GPIO[7] that can be used instead of the INTx, MSI, and PME mechanisms defined by PCI Express hotplug. Associated with each downstream port’s hot-plug controller is a bit in the General Purpose Event Control (P0_GPECTL) register. When this bit is set, then the corresponding PCIe base 1.1 hot-plug event notification mechanisms are disabled for that port and INTx, MSI and PME events will not be generated by that port due to hot-plug events. Instead, hot-plug events are signaled through assertion of the GPEN signal.

GPEN is an alternate function of GPIO[7], and GPIO[7] will not be asserted when GPEN is asserted unless it is configured to operate as an alternate function. Whenever a port signals a hot-plug event through assertion of the GPEN signal, the corresponding port’s status bit in the General Purpose Event Status (P0_GPESTS) register is set. A bit in the P0_GPESTS register can only be set if the corresponding port’s hot-plug controller is configured to signal hot-plug events using the general purpose event (GPEN) signal assertion mechanism.

PES24N3A User Manual 8 - 4 April 10, 2008

Page 93

IDT Hot-Plug and Hot-Swap

Notes

The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged. INTx, MSI and PME events from other sources are also unaffected.

The enhanced hot-plug signalling mechanism supported by the PES24N3A is graphically illustrated in Figure 8.4. This figure provides a conceptual summary of the enhanced hot-plug signalling mechanism in the form of a pseudo logic diagram. Logic gates in this diagram are intended for conveying general concepts, and not for direct implementation

Note: Logic gates in this diagram are intended to convey general concepts, not a direct implementation scheme.

General Purpose Event

Enable

General Purpose

Event Mechanism

Activate INTx

Mechanism

Activate MS I

Mechanism

Activate Wake-up

Mechanism

Slot Status

Command

Completed

RW1C

Attention Button

Pressed

RW1C

Power Fault

Detected

RW1C

MRL Sensor State

Changed

RW1C

Presence Detected

Changed

RW1C

Data Link Layer

State Changed

RW1C

Slot Control

Hot-Plug Inter r u p t

Enable

Command

Completed Enable

Attention Button Pressed Enable

Power Fault

Detected Enable

MRL Sensor State

Changed Enable

Presence Detected

Changed Enable

Data Link Layer

State Changed Enable

MSI Enable

Bit

PME Enable

Bit

Interrupt

Disable

Figure 8.4 PES24N3A Hot-Plug Event Signalling

PES24N3A User Manual 8 - 5 April 10, 2008

Page 94

IDT Hot-Plug and Hot-Swap

Notes

Hot-Swap

The PES24N3A is hot-swap capable and meets the following requirements:

– All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.). – All I/O cells function predictably from early power. This means that the device is able to tolerate a

non-monotonic ramp-up as well as a rapid ramp-up of the DC power.

– All I/O cells are able to tolerate a precharge voltage. – Since no clock is present during physical connection, the device will maintain all outputs in a high-

impedance state even when no clock is present.

– The I/O cells meet VI requirements for hot-swap. – The I/O cells respect the required leakage current limits over the entire input voltage range.

In summary, the PES24N3A meets all of the I/O requirements necessary to build a PICMG compliant hot-swap board or system. The hot-swap I/O buffers of the PES24N3A may also be used to construct proprietary hot-swap systems. See the 89PES24N3A Data Sheet on ID T’s web site (www.IDT.com) for a detailed specification of I/O buffer characteristics.

PES24N3A User Manual 8 - 6 April 10, 2008

Page 95

Chapter 9

Configuration Registers

Notes

Introduction

Each software-visible register in the PES24N3A is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES24N3A that cannot be accessed by the root. Each softwarevisible register in the PES24N3A has a system address. The system address is formed by adding the PCI configuration space offset value of the register to the base address of the port in which it is located. The system address is used for serial EEPROM register initialization and slave SMBus register accesses.

The base address for each PES24N3A port is listed in Table 9.1. The PCI configuration space offset addresses for registers in the upstream port are listed in Table 9.2 while the PCI configuration space offset addresses for registers in downstream ports are listed Table 9.3.

Base

Address

0x0000 Port 0 configuration space (upstream port) 0x2000 Port 2 configuration space (downstream port) 0x4000 Port 4 configuration space (downstream port)

Table 9.1 Base Addresses for Port Configuration Space Registers

As shown in Figure 9.1, upstream and downstream ports share a similar PCI configuration space register layout. The upstream port contains global switch control and status registers as well as test mode registers which are not present in the configuration space of downstream ports. Due to the ability to generate MSIs as a result of hot-plug events, the downstream ports contain an MSI capability structure which is not present in the upstream port.

PCI Configuration Space

PCIe configuration reads to an upstream port offset not defined in Table 9.2 or a downstream port offset not defined in Table 9.3 return a value of zero. Slave SMBus reads to these offsets return an undefined data value. PCIe configuration writes or Slave SMBus writes to an offset not defined in Table 9.2 or Table 9.3 complete successfully but modify no data and have no other effect.

PES24N3A User Manual 9 - 1 April 10, 2008

Page 96

IDT Configuration Registers

Notes

0x000

PCI

Configuration Space

(64 DWords)

0x000

0x040

0x0C0

0x0D0

0x0F8 0x0FF

Type 1

Configuration Header

PCI Express

Capability Structure

PCI Power Management

Capability Structure

MSI

Capability Structure

Downstream Ports Only

Extended Config Access

Advanced Error Reporting

Enhanced Capability

Device Serial Number

Enhanced Capability PCIe Virtual Channel

Enhanced Capability

Power Budgeting

Enhanced Capability

Switch Control

& Status Registers

Upstream Port Only

Reserved

0x100

0x180

0x200

0x280

0x400

0x480

Internal Switch Error

Control & Status Registers

Reserved

0x740

0x800

0xE00

0xF00 0xFFFF

Figure 9.1 Port Configuration Space Organization

PES24N3A User Manual 9 - 2 April 10, 2008

Page 97

IDT Configuration Registers

Notes

Upstream Port (Port 0)

Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.

Cfg.

Offset

0x000 Word P0_VID VID - Vendor Identification Register (0x000) on page 9-11 0x002 Word P0_DID DID - Device Identification Register (0x002) on page 9-12 0x004 Word P0_PCICMD PCICMD - PCI Command Register (0x004) on page 9-12 0x006 Word P0_PCISTS PCISTS - PCI Status Register (0x006) on page 9-13 0x008 Byte P0_RID RID - Revision Identification Register (0x008) on page 9-14

0x009 3 Bytes P0_CCODE CCODE - Class Code Register (0x009) on page 9-14 0x00C Byte P0_CLS CLS - Cache Line Size Register (0x00C) on page 9-14 0x00D Byte P0_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-14 0x00E Byte P0_HDR HDR - Header Type Register (0x00E) on page 9-14

0x00F Byte P0_BIST BIST - Built-in Self Test Register (0x00F) on page 9-14

0x010 DWord P0_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-15

Size

Mnemonic

0x014 DWord P0_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-15

0x018 Byte P0_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 9-15

0x019 Byte P0_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 9-15 0x01A Byte P0_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 9-

0x01B Byte P0_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page

9-15

0x01C Byte P0_IOBASE IOBASE - I/O Base Register (0x01C) on page 9-16 0x01D Byte P0_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 9-16 0x01E Word P0_SECSTS SECSTS - Secondary Status Register (0x01E) on page 9-16

0x020 Word P0_MBASE MBASE - Memory Base Register (0x020) on page 9-17 0x022 Word P0_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 9-17 0x024 Word P0_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page

9-17

0x026 Word P0_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page

9-18

0x028 DWord P0_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028)

on page 9-18

0x02C DWord P0_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)

on page 9-18

0x030 Word P0_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 9-18 0x032 Word P0_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 9-19 0x034 Byte P0_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 9-19

Table 9.2 Upstream Port 0 Configuration Space Registers (Part 1 of 5)

PES24N3A User Manual 9 - 3 April 10, 2008

Page 98

IDT Configuration Registers

Notes

Cfg.

Offset

0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038)

0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-19 0x03E Word P0_BCTRL BCTRL - Bridge Control Register (0x03E) on page 9-20

0x040 DWord P0_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 9-21 0x044 DWord P0_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 9-

0x048 Word P0_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 9-22 0x04A Word P0_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 9-23 0x04C DWord P0_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 9-24

0x050 Word P0_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 9-25

0x052 Word P0_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 9-26

0x064 DWord P0_PCIEDCAP2 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) on

0x068 Word P0_PCIEDCTL2 PCIEDCTL2 - PCI Express Device Control 2 (0x068) on page 9-

0x06A Word P0_PCIEDSTS2 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) on page 9-

Size

Mnemonic

on page 9-19

page 9-31

0x06C DWord P0_PCIELCAP2 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) on page

9-31

0x070 Word P0_PCIELCTL2 PCIELCTL2 - PCI Express Link Control 2 (0x070) on page 9-32 0x072 Word P0_PCIELSTS2 PCIELSTS2 - PCI Express Link Status 2 (0x072) on page 9-32

0x0C0 DWord P0_PMCAP PMCAP - PCI Power Management Capabilities (0x0C0) on page

9-33

0x0C4 DWord P0_PMCSR PMCSR - PCI Power Management Control and Status (0x0C4) on

page 9-34

0x0F8 Word P0_ECFGADDR ECFGADDR - Extended Configuration Space Access Address

(0x0F8) on page 9-36

0x0FC Word P0_ECFGDATA ECFGDATA - Extended Configuration Space Access Data

(0x0FC) on page 9-37

0x100 Dword P0_AERCAP AERCAP - AER Capabilities (0x100) on page 9-37 0x104 Dword P0_AERUES AERUES - AER Uncorrectable Error Status (0x104) on page 9-37 0x108 Dword P0_AERUEM AERUEM - AER Uncorrectable Error Mask (0x108) on page 9-38

0x10C Dword P0_AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page

9-39

0x110 Dword P0_AERCES AERCES - AER Correctable Error Status (0x110) on page 9-41 0x114 Dword P0_AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 9-41 0x118 Dword P0_AERCTL AERCTL - AER Control (0x118) on page 9-42

Table 9.2 Upstream Port 0 Configuration Space Registers (Part 2 of 5)

PES24N3A User Manual 9 - 4 April 10, 2008

Page 99

IDT Configuration Registers

Notes

Cfg.

Offset

0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page

0x120 Dword P0_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page

0x124 Dword P0_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page

0x128 Dword P0_AERHL4DW AERHL4DW - AER Header Log 4th Doubleword (0x128) on page

0x180 Dword P0_SNUMCAP SNUMCAP - Serial Number Capabilities (0x180) on page 9-43 0x184 Dword P0_SNUMLDW SNUMLDW - Serial Number Lower Doubleword (0x184) on page

0x188 Dword P0_SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page

0x200 DWord P0_PCIEVCECAP PCIEVCECAP - PCI Express VC Enhanced Capability Header

0x204 DWord P0_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x204) on page 9-44 0x208 DWord P0_PVCCAP2 PVCCAP2 - Port VC Capability 2 (0x208) on page 9-44

0x20C Word P0_PVCCTL PVCCTL - Port VC Control (0x20C) on page 9-45

Size

Mnemonic

9-42

9-43

(0x200) on page 9-43

0x20E Word P0_PVCSTS PVCSTS - Port VC Status (0x20E) on page 9-45

0x210 DWord P0_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x210) on page 9-45 0x214 DWord P0_VCR0CTL VCR0CTL- VC Resource 0 Control (0x214) on page 9-46 0x218 DWord P0_VCR0STS VCR0STS - VC Resource 0 Status (0x218) on page 9-46 0x220 DWord P0_VCR0TBL0 VCR0TBL0 - VC Resource 0 Arbitration T able Entry 0 (0x220) on

page 9-47

0x224 DWord P0_VCR0TBL1 VCR0TBL1 - VC Resource 0 Arbitration T able Entry 1 (0x224) on

page 9-47

0x228 DWord P0_VCR0TBL2 VCR0TBL2 - VC Resource 0 Arbitration T able Entry 2 (0x228) on

page 9-48

0x22C DWord P0_VCR0TBL3 VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C) on

page 9-48

0x280 Dword P0_PWRBCAP PWRBCAP - Power Budgeting Capabilities (0x280) on page 9-49 0x284 Dword P0_PWRBDSEL PWRBDSEL - Power Budgeting Data Select (0x284) on page 9-

0x288 Dword P0_PWRBD PWRBD - Power Budgeting Data (0x288) on page 9-49

0x28C Dword P0_PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C)

on page 9-50

0x300 Dword P0_PWRBDV0 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on

page 9-50

0x304 Dword P0_PWRBDV1 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on

page 9-50

0x308 Dword P0_PWRBDV2 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on

page 9-50

Table 9.2 Upstream Port 0 Configuration Space Registers (Part 3 of 5)

PES24N3A User Manual 9 - 5 April 10, 2008

Page 100

IDT Configuration Registers

Notes

Cfg.

Offset

0x30C Dword P0_PWRBDV3 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on

0x310 Dword P0_PWRBDV4 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on

0x314 Dword P0_PWRBDV5 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on

0x318 Dword P0_PWRBDV6 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on

0x31C Dword P0_PWRBDV7 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on

0x400 DWord SWSTS SWSTS - Switch Status (0x400) on page 9-50 0x404 DWord SWCTL SWCTL - Switch Control (0x404) on page 9-51 0x408 DWord HPCFGCTL HPCFGCTL - Hot-Plug Configuration Control (0x408) on page 9-

0x40C DWord GPR GPR - General Purpose Register (0x40C) on page 9-53

0x418 DWord GPIOFUNC GPIOFUNC - General Purpose I/O Control Function (0x418) on

0x41C DWord GPIOCFG GPIOCFG - General Purpose I/O Configuration (0x41C) on page

Size

Mnemonic

page 9-50

page 9-54

9-54

0x420 DWord GPIOD GPIOD - General Purpose I/O Data (0x420) on page 9-54 0x424 DWord SMBUSSTS SMBUSSTS - SMBus Status (0x424) on page 9-54 0x428 DWord SMBUSCTL SMBUSCTL - SMBus Control (0x428) on page 9-55

0x42C DWord EEPROMINTF EEPROMINTF - Serial EEPROM Interface (0x42C) on page 9-56

0x430 DWord IOEXPINTF IOEXPINTF - I/O Expander Interface (0x430) on page 9-57 0x434 DWord IOEXPADDR0 IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434) on page

9-58

0x438 DWord IOEXPADDR1 IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438) on page

9-58

0x450 DWord GPECTL GPECTL - General Purpose Event Control (0x450) on page 9-58 0x454 DWord GPESTS GPESTS - General Purpose Event Status (0x454) on page 9-59 0x458 DWord UARBTC UARBTC - U-Bus Arbiter Transfer Count (0x458) on page 9-59

0x45C DWord UARBCTC UARBCTC - U-Bus Arbiter Current Transfer Count (0x45C) on

page 9-60

0x460 DWord DARBTC DARBTC - D-Bus Arbiter Transfer Count (0x460) on page 9-60 0x464 DWord DARBCTC DARBCTC - D-Bus Arbiter Current Transfer Count (0x464) on

page 9-60

0x4A8 DWord SWTSCNTCTL SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8) on

page 9-61

0x740 Dword P0_SWPECTL SWPECTL - Switch Parity Error Control (0x740) on page 9-61 0x744 Dword P0_SWPESTS SWPESTS - Switch Parity Error Status (0x744) on page 9-61

Table 9.2 Upstream Port 0 Configuration Space Registers (Part 4 of 5)

PES24N3A User Manual 9 - 6 April 10, 2008