IDT 89HPES16NT2 User Manual

®

IDT™ 89HPES16NT2

PCI Express® Switch

User Manual

April 2008

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: [phone] • [phone] • FAX: [phone]

©2008 Integrated Device Technology, Inc.

Printed in U.S.A.

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

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CODE DISCLAIMER

LIFE SUPPORT POLICY

About This Manual

®

Notes

Introduction

This user manual includes hardware and software information on the 89HPES16NT2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.

Finding Additional Information

Information not included in this manual such as mechanicals, package pin-outs, and electrical character­istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.

Content Summar y

Chapter 1, “PES16NT2 Device Overview,” provides a complete introduction to the performance capa­bilities of the 89HPES16NT2. Included in this chapter is a summary of features for the device as well as a
system block diagram and pin description.

Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer­ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.

Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.

Chapter 4, “Switch Operation,” discusses the procedure for forwarding PCIe® TLPs between switch
ports.

Chapter 5, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-PCI bridge in the PES16NT2.

Chapter 6, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES16NT2.

Chapter 7, “NTB Upstream Port Failover,” describes the NTB upstream port failover mechanism that

enables the construction of fault tolerant systems.

Chapter 8, “General Purpose I/O,” describes how the eight General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions

Chapter 9, “Transparent Mode Operation,” describes how the PES16NT2 can be configured during a
fundamental reset to operate in transparent mode or transparent mode with serial EEPROM initialization.

Chapter 10, “Non-Transparent Mode Operation,” describes how the PES16NT2 can be configured
during a fundamental reset to operate in non-transparent mode or non-transparent mode with serial
EEPROM initialization.

Chapter 11, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.

Signal Nomenclature

To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.

PES16NT2 User Manual 1 April 15, 2008

IDT

Notes

To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter­preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. To
define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the
right. No leading zeros will be included.

Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.

single clock cycle

1 2 3 4

high-to-low

transition

low-to-high

transition

Figure 1 Signal Transitions

Numeric Representations

To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.

Data Units

The following data unit terminology is used in this document.

Term Words Bytes Bits

Byte 1/2 1 8

Word 1 2 16

Doubleword (Dword) 2 4 32

Quadword (Qword) 4 8 64

Table 1 Data Unit Terminology

In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double­words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.

The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.

PES16NT2 User Manual 2 April 15, 2008

IDT

Notes

bit 0bit 31

0 1 2 3

Address of Bytes within Words: Big Endian

bit 0bit 31

3 2 1 0

Address of Bytes within Words: Little Endian

Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

Register Terminology

Software in the context of this register terminology refers to modifications made by PCIe root configura­tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial­ization. See Table 2.

Type Abbreviation Description

Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms

such as pin strapping or serial EEPROM. (System firmware hard­ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.

Read Only and Clear RC Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.

Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.

Reserved Reserved The value read from a reserved register/bit is undefined. Thus,

software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi­tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi­tions and then written back.

Read Only RO Software can only read registers/bits with this attribute. Contents

are hardwired. Writing to a RO location has no effect.

Read Only and set by
Hardware

Read and Write RW Software can both read and write bits with this attribute.

ROS Software can only read registers/bits with this attribute. Contents

are set by hardware and may change. Writing to a ROS location
has no effect.

Table 2 Register Terminology (Sheet 1 of 2)

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IDT

Notes

Type Abbreviation Description

Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.

However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.

Read and Write when
Unlocked

Zero Zero A zero register or bit must be written with a value of zero and

RWL Software can read the register/bits with this attribute. Writing to

register/bits with this attribute will only cause the value to be modi­fied if the REGUNLOCK bit in the SWCNTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis­ter/bits are effectively read-only

returns a value of zero when read.

Table 2 Register Terminology (Sheet 2 of 2)

Use of Hypertext

In Chapters 9 and 10 there are tables which contain register names and page numbers highlighted in
blue under the Register Definition column. In pdf files, users can jump from the source table directly to the
registers by clicking on the register name in the source table. Each register name in the table is linked
directly to the appropriate register in the register section of the chapter. To return to the source table after
having jumped to the register section, click on the same register name (in blue) in the register section.

Revision History

April 15, 2008: Initial publication of user manual.

PES16NT2 User Manual 4 April 15, 2008

Table of Contents

®

Notes

About This Manual

Introduction ....................................................................................................................................1

Content Summary ..........................................................................................................................1

Signal Nomenclature .....................................................................................................................1

Numeric Representations ..............................................................................................................2

Data Units ......................................................................................................................................2

Register Terminology .....................................................................................................................3

Use of Hypertext ............................................................................................................................4

Revision History .............................................................................................................................4

PES16NT2 Device Overview

Introduction.....................................................................................................................................1-1

List of Features...............................................................................................................................1-3

System Identification.......................................................................................................................1-4

Vendor ID................................................................................................................................1-4

Device ID................................................................................................................................1-4

Revision ID.............................................................................................................................1-5

JTAG ID..................................................................................................................................1-5

Logic Diagram.................................................................................................................................1-6

Pin Description................................................................................................................................1-7

Pin Characteristics........................................................................................................................1-10

Clocking, Reset, and Initialization

Introduction.....................................................................................................................................2-1

Initialization.....................................................................................................................................2-3

Reset...............................................................................................................................................2-5

Fundamental Reset................................................................................................................2-7

Hot Reset................................................................................................................................2-8

Non-Transparent Mode Reset................................................................................................2-9

Link Operation

Introduction.....................................................................................................................................3-1

Polarity Inversion............................................................................................................................3-1

Link Width Negotiation....................................................................................................................3-1

Lane Reversal.................................................................................................................................3-1

Link Retraining................................................................................................................................3-4

Link Down.......................................................................................................................................3-4

Slot Power Limit Support................................................................................................................3-4

Crosslink.........................................................................................................................................3-5

Link Status......................................................................................................................................3-5

PES16NT2 User Manual i April 15, 2008

IDT Table of Contents

Notes

Switch Operation

Introduction.....................................................................................................................................4-1

Routing ...........................................................................................................................................4-3

Data Integrity ..................................................................................................................................4-4

Switch Time-Outs ...........................................................................................................................4-5

Interrupts.........................................................................................................................................4-5

Switch Core Errors..........................................................................................................................4-6

Power Management

Introduction.....................................................................................................................................5-1

PME Messages ......................................................................................................................5-2

Link States......................................................................................................................................5-2

Active State Power Management ...................................................................................................5-3

SMBus Interfaces

Introduction.....................................................................................................................................6-1

SMBus Registers............................................................................................................................6-2

Master SMBus Interface.................................................................................................................6-4

Initialization.............................................................................................................................6-4

Serial EEPROM......................................................................................................................6-4

Slave SMBus Interface...................................................................................................................6-8

Initialization.............................................................................................................................6-9

SMBus Transactions ..............................................................................................................6-9

NTB Upstream Port Failover

Introduction.....................................................................................................................................7-1

Failover...........................................................................................................................................7-2

Static Upstream Port Failover.................................................................................................7-3

Dynamic Upstream Port Failover............................................................................................7-3

General Purpose I/O

Introduction.....................................................................................................................................8-1

GPIO Registers...............................................................................................................................8-1

GPIO Configuration ........................................................................................................................8-2

GPIO Pin Configured as an Input...........................................................................................8-2

GPIO Pin Configured as an Output........................................................................................8-2

GPIO Pin Configured as an Alternate Function......................................................................8-2

Transparent Mode Operation

Introduction.....................................................................................................................................9-1

End-to-End CRC.............................................................................................................................9-2

Interrupts.........................................................................................................................................9-2

Error Detection and Handling .........................................................................................................9-2

Configuration Requests..........................................................................................................9-5

Port Configuration Space Organization..........................................................................................9-5

Upstream Port A Configuration Space Registers ...........................................................................9-7

PCI Express Capability Structure.........................................................................................9-19

Power Management Capability Structure.............................................................................9-26

Switch Control and Status Registers....................................................................................9-30

Extended Configuration Space Access and INTx Status Registers.....................................9-36

PCI Express Virtual Channel Capability...............................................................................9-37

PES16NT2 User Manual ii April 15, 2008

IDT Table of Contents

Notes

Physical Layer Control and Status Registers.......................................................................9-42

Non-Transparent Mode Operation

Introduction...................................................................................................................................10-1

Transaction Routing......................................................................................................................10-3

Address Routing...................................................................................................................10-3

ID Routing.............................................................................................................................10-6

Route to Root Implicit Routing..............................................................................................10-6

Broadcast from Root Implicit Routing...................................................................................10-6

Local Terminate at Receiver Implicit Routing.......................................................................10-6

Gather and Route to Root Implicit Routing...........................................................................10-7

Non-Transparent Bridge Interprocessor Communications............................................................10-7

Message Registers...............................................................................................................10-7

Doorbell Registers................................................................................................................10-8

Scratchpad Registers...........................................................................................................10-8

Interrupts.......................................................................................................................................10-8

MSI and INTx Message Generation.....................................................................................10-8

Non-Transparent Bridge TLP Processing.....................................................................................10-9

Configuration ................................................................................................................................10-9

Configuration Space...........................................................................................................10-10

Memory Mapped Configuration Space...............................................................................10-11

Configuration Requests......................................................................................................10-11

End-to-End CRC.........................................................................................................................10-12

Error Detection and Handling .....................................................................................................10-12

Power Management....................................................................................................................10-15

Initializing the Non-Transparent Bridge ......................................................................................10-16

Non-Transparent Port C Configuration Space Organization.......................................................10-18

Non-Transparent Mode Downstream Port C Configuration Space Organization Registers.......10-19

Port C Registers .........................................................................................................................10-21

PCI Express Capability Structure.......................................................................................10-31

Power Management Capability Structure...........................................................................10-38

Switch Control and Status Registers..................................................................................10-41

Extended Configuration Space Access and INTx Status Registers...................................10-47

PCI Express Virtual Channel Capability.............................................................................10-48

Physical Layer Control and Status Registers.....................................................................10-53

NTB Endpoint Configuration Space Organization ......................................................................10-55

NTB Internal Endpoint Configuration Space Registers...............................................................10-56

Non-Transparent Bridge Internal Endpoint Registers.................................................................10-59

PCI Express Capability Structure.......................................................................................10-68

Message Signaled Interrupt Capability Structure...............................................................10-72

Non-Transparent Bridge Configuration Capability Structure..............................................10-73

Non-Transparent Bridge Communications Capability Structure.........................................10-89

Power Management Capability Structure...........................................................................10-95

Extended Configuration Space Access Registers..............................................................10-97

PCI Express Extended Capability Header..........................................................................10-97

Non-Transparent Bridge Control and Status Registers......................................................10-98

NTB External Endpoint Configuration Space Registers ...........................................................10-104

Non-Transparent Bridge External Endpoint Registers..............................................................10-107

PCI Express Capability Structure.....................................................................................10-116

Message Signaled Interrupt Capability Structure.............................................................10-120

Non-Transparent Bridge Configuration Capability Structure............................................10-121

Non-Transparent Bridge Communications Capability Structure.......................................10-137

Power Management Capability Structure.........................................................................10-143

Extended Configuration Space Access Registers............................................................10-145

PCI Express Extended Capability Header........................................................................10-145

PES16NT2 User Manual iii April 15, 2008

IDT Table of Contents

Notes

Non-Transparent Bridge Control and Status Registers....................................................10-146

JTAG Boundary Scan

Introduction...................................................................................................................................11-1

Test Access Point.........................................................................................................................11-1

Signal Definitions..........................................................................................................................11-1

Boundary Scan Chain...................................................................................................................11-3

Test Data Register (DR)...............................................................................................................11-3

Boundary Scan Registers.....................................................................................................11-4

Instruction Register (IR)................................................................................................................11-5

EXTEST................................................................................................................................11-6

SAMPLE/PRELOAD.............................................................................................................11-6

BYPASS...............................................................................................................................11-6

CLAMP.................................................................................................................................11-7

IDCODE................................................................................................................................11-7

VALIDATE............................................................................................................................11-7

RESERVED..........................................................................................................................11-7

Usage Considerations..........................................................................................................11-7

PES16NT2 User Manual iv April 15, 2008

List of Tables

®

Notes

Table 1.1 PES16NT2 Offset Device IDs..............................................................................................1-4

Table 1.2 PES16NT2 Revision IDs......................................................................................................1-5

Table 1.3 PCI Express Interface Pins..................................................................................................1-7

Table 1.4 SMBus Interface Pins..........................................................................................................1-7

Table 1.5 General Purpose I/O Pins....................................................................................................1-8

Table 1.6 System Pins.........................................................................................................................1-8

Table 1.7 Test Pins..............................................................................................................................1-9

Table 1.8 Power and Ground Pins.......................................................................................................1-9

Table 1.9 Pin Characteristics.............................................................................................................1-10

Table 2.1 Reference Clock Mode Encoding........................................................................................2-1

Table 2.2 Boot Configuration Vector Signals.......................................................................................2-3

Table 2.3 System Pins.........................................................................................................................2-4

Table 2.4 Reset Conditions and Their Effect.......................................................................................2-5

Table 4.1 PES16NT2 Buffer Sizes......................................................................................................4-1

Table 4.2 PES16NT2 Advertised Flow Control Credits.......................................................................4-2

Table 4.3 Switch Routing Methods......................................................................................................4-3

Table 4.4 PCI Compatible INTx Aggregation.......................................................................................4-6

Table 4.5 PES16NT2 Upstream Port Bridge Interrupt Mapping..........................................................4-6

Table 5.1 PES16NT2 Power Management State Transition Diagram.................................................5-2

Table 6.1 SMBUSSTS - SMBus Status...............................................................................................6-2

Table 6.2 SMBUSCTL - SMBus Control..............................................................................................6-3

Table 6.3 Serial EEPROM SMBus Address........................................................................................6-4

Table 6.4 Base Addresses for PCI Configuration Spaces in the PES16NT2......................................6-5

Table 6.5 PES16NT2 Compatible Serial EEPROMs...........................................................................6-5

Table 6.6 Serial EEPROM Initialization Errors....................................................................................6-8

Table 6.7 Slave SMBus Address When a Static Address is Selected.................................................6-9

Table 6.8 Slave SMBus Command Code Fields...............................................................................6-10

Table 6.9 CSR Register Read or Write Operation Byte Sequence...................................................6-11

Table 6.10 CSR Register Read or Write CMD Field Description.........................................................6-11

Table 6.11 Serial EEPROM Read or Write Operation Byte Sequence................................................6-12

Table 6.12 Serial EEPROM Read or Write CMD Field Description.....................................................6-13

Table 8.1 General Purpose IO Registers.............................................................................................8-1

Table 8.2 General Purpose I/O Pin Alternate Function.......................................................................8-2

Table 8.3 GPIO Pin Configuration.......................................................................................................8-2

Table 9.1 Physical Layer Errors...........................................................................................................9-2

Table 9.2 Data Link Layer Errors.........................................................................................................9-2

Table 9.3 Transaction Layer Errors.....................................................................................................9-3

Table 9.4 Malformed TLP Error Checks..............................................................................................9-4

Table 9.5 Upstream Port A Configuration Space Registers................................................................9-7

Table 10.1 Non-Transparent Bridge Mapping Table Fields.................................................................10-4

Table 10.2 Physical Layer Errors.......................................................................................................10-12

Table 10.3 Data Link Layer Errors.....................................................................................................10-13

Table 10.4 Transaction Layer Errors.................................................................................................10-13

Table 10.5 Malformed TLP Error Checks..........................................................................................10-14

Table 10.6 Downstream Port C Configuration Space Registers in Non-Transparent Mode..............10-19

Table 10.7 Non-Transparent Bridge Internal Endpoint Configuration Space Registers....................10-56

Table 10.8 Non-Transparent Bridge External Endpoint Configuration Space Registers.................10-104

Table 11.1 JTAG Pin Descriptions.......................................................................................................11-2

Table 11.2 Boundary Scan Chain........................................................................................................11-3

PES16NT2 User Manual v April 15, 2008

IDT List of Tables

Notes

Table 11.3 Instructions Supported by PES16NT2’s JTAG Boundary Scan........................................11-6

Table 11.4 System Controller Device Identification Register..............................................................11-7

PES16NT2 User Manual vi April 15, 2008

List of Figures

®

Notes

Figure 1.1 PES16NT2 Functional Block Diagram ...............................................................................1-2

Figure 1.2 PES16NT2 Architectural Block Diagram ............................................................................1-3

Figure 1.3 PES16NT2 Logic Diagram .................................................................................................1-6

Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread

Spectrum Clock) ................................................................................................................2-1

Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable

Spread Spectrum Clock) ....................................................................................................2-2

Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable

Spread Spectrum Clock) ....................................................................................................2-2

Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum

Clock) .................................................................................................................................2-3

Figure 2.5 Fundamental Reset in Transparent Mode with Serial EEPROM initialization ....................2-8

Figure 3.1 Lane Reversal for Maximum Link Width of x8 ....................................................................3-2

Figure 3.2 Lane Reversal for Maximum Link Width of x4 ....................................................................3-3

Figure 3.3 Lane Reversal for Maximum Link Width of x2 ....................................................................3-4

Figure 4.1 PES16NT2 Switch Data Flow and Buffering ......................................................................4-1

Figure 5.1 PES16NT2 Power Management State Transition Diagram ...............................................5-1

Figure 5.2 PES16NT2 ASPM Link Sate Transitions ...........................................................................5-3

Figure 6.1 SMBus Interface Configuration Examples .........................................................................6-1

Figure 6.2 Single Double Word Initialization Sequence Format ..........................................................6-6

Figure 6.3 Sequential Double Word Initialization Sequence Format ...................................................6-6

Figure 6.4 Configuration Done Sequence Format ..............................................................................6-7

Figure 6.5 Slave SMBus Command Code Format ..............................................................................6-9

Figure 6.6 CSR Register Read or Write CMD Field Format ..............................................................6-11

Figure 6.7 Serial EEPROM Read or Write CMD Field Format ..........................................................6-12

Figure 6.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC

Disabled ...........................................................................................................................6-13

Figure 6.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC

Disabled ...........................................................................................................................6-14

Figure 6.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........6-14

Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........6-14

Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........6-14

Figure 6.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....6-15

Figure 7.1 NTB Upstream Port Failover Usage Model ........................................................................7-1

Figure 7.2 PES16NT2 NTB Upstream Port Failover Architecture .......................................................7-2

Figure 9.1 PES16NT2 Functional Block Diagram in Transparent Mode .............................................9-1

Figure 10.1 PES16NT2 Functional Block Diagram in Non-Transparent Mode ...................................10-2

Figure 10.2 Internal and External Endpoint Non-Transparent Bridge Mapping Table Format ............10-3

Figure 10.3 NTB Base and Limit Address Translation ........................................................................10-5

Figure 10.4 Non-Transparent Bridge Interprocessor Communications Facilities ................................10-7

Figure 10.5 Non-Transparent Bridge Configuration Window ............................................................10-10

Figure 10.6 Port C Configuration Space Organization in Non-Transparent Mode ............................10-18

Figure 10.7 Non-Transparent Bridge Endpoint Configuration Space Layout ....................................10-55

Figure 11.1 Diagram of the JTAG Logic ..............................................................................................11-1

Figure 11.2 State Diagram of PES16NT2’s TAP Controller ................................................................11-2

Figure 11.3 Diagram of Observe-only Input Cell .................................................................................11-4

Figure 11.4 Diagram of Output Cell ....................................................................................................11-4

Figure 11.5 Diagram of Bidirectional Cell ............................................................................................11-5

Figure 11.6 Device ID Register Format ...............................................................................................11-7

PES16NT2 User Manual vii April 15, 2008

DT List of Figures

Notes

PES16NT2 User Manual viii April 15, 2008

Register List

®

Notes

PA_BAR0 - Base Address Register 0 (0x010).......................................................................................9-13

PA_BAR1 - Base Address Register 1 (0x014).......................................................................................9-13

PA_BCTRL - Bridge Control (0x03E)..................................................................................................... 9-18

PA_BIST - Built-in Self Test (0x00F)...................................................................................................... 9-12

PA_CAPPTR - Capabilities Pointer (0x034)........................................................................................... 9-17

PA_CCODE - Class Code (0x009)......................................................................................................... 9-12

PA_CLS - Cache Line Size (0x00C) ...................................................................................................... 9-12

PA_DID - Device Identification (0x002).................................................................................................... 9-9

PA_ECFGADDR - Extended Configuration Space Access Address (0x0F8)........................................ 9-36

PA_ECFGDATA - Extended Configuration Space Access Data (0x0FC).............................................. 9-37

PA_EEPROMINTF - Serial EEPROM Interface (0x0B4)........................................................................ 9-35

PA_EROMBASE - Expansion ROM Base Address (0x038).................................................................. 9-17

PA_GPIOCS - General Purpose I/O Control and Status (0x0A8).......................................................... 9-32

PA_HDR - Header Type (0x00E)........................................................................................................... 9-12

PA_INTRLINE - Interrupt Line (0x03C).................................................................................................. 9-17

PA_INTRPIN - Interrupt PIN (0x03D)..................................................................................................... 9-18

PA_INTSTS - Interrupt Status (0x0F4)................................................................................................... 9-36

PA_IOBASE - I/O Base (0x01C)............................................................................................................ 9-14

PA_IOBASEU - I/O Base Upper (0x030) ............................................................................................... 9-17

PA_IOLIMIT - I/O Limit (0x01D)............................................................................................................. 9-14

PA_IOLIMITU - I/O Limit Upper (0x032) ................................................................................................ 9-17

PA_MBASE - Memory Base (0x020) ..................................................................................................... 9-15

PA_MLIMIT - Memory Limit (0x022)....................................................................................................... 9-15

PA_PBUSN - Primary Bus Number (0x018)...........................................................................................9-13

PA_PCICMD - PCI Command (0x004).....................................................................................................9-9

PA_PCIECAP - PCI Express Capability (0x040).................................................................................... 9-19

PA_PCIEDCAP - PCI Express Device Capabilities (0x044).................................................................. 9-19

PA_PCIEDCTL - PCI Express Device Control (0x048).......................................................................... 9-20

PA_PCIEDSTS - PCI Express Device Status (0x04A)........................................................................... 9-21

PA_PCIELCAP - PCI Express Link Capabilities (0x04C)....................................................................... 9-22

PA_PCIELCTL - PCI Express Link Control (0x050)............................................................................... 9-23

PA_PCIELSTS - PCI Express Link Status (0x052)................................................................................ 9-23

PA_PCIESCAP - PCI Express Slot Capabilities (0x054)....................................................................... 9-24

PA_PCIESCTL - PCI Express Slot Control (0x058)............................................................................... 9-25

PA_PCIESSTS - PCI Express Slot Status (0x05A)................................................................................ 9-25

PA_PCIEVCECAP - PCI Express Virtual Channel Enhanced Capability Header (0x100) ..................... 9-37

PA_PCISTS - PCI Status (0x006).......................................................................................................... 9-10

PA_PLTIMER - Primary Latency Timer (0x00D).................................................................................... 9 -12

PA_PMBASE - Prefetchable Memory Base (0x024).............................................................................. 9-15

PA_PMBASEU - Prefetchable Memory Base Upper (0x028).................................................................9-16

PA_PMCAP - PCI Power Management Capabilities (0x070)................................................................. 9-26

PA_PMCSR - PCI Power Management Control and Status (0x074)..................................................... 9-27

PA_PMLIMIT - Prefetchable Memory Limit (0x026)...............................................................................9-16

PA_PMLIMITU - Prefetchable Memory Limit Upper (0x02C)................................................................. 9-16

PA_PMPC - PCI Power Management Proprietary Control (0x078)........................................................9-27

PA_PVCCAP1- Port VC Capability 1 (0x104)........................................................................................9-37

PA_RID - Revision Identification (0x008)............................................................................................... 9-11

PA_SBUSN - Secondary Bus Number (0x019)...................................................................................... 9-13

PA_SECSTS - Secondary Status (0x01E)............................................................................................. 9-14

PES16NT2 User Manual ix April 15, 2008

IDT Register List

Notes

PA_SERDESCTL - SerDes Control (0x200)...........................................................................................9-42

PA_SLTIMER - Secondary Latency Timer (0x01B)................................................................................9-13

PA_SMBUSCTL - SMBus Control (0x0B0).............................................................................................9-34

PA_SMBUSSTS - SMBus Status (0x0AC)..............................................................................................9-33

PA_SUBUSN - Subordinate Bus Number (0x01A) .................................................................................9-13

PA_SWCTL - Switch Control (0x0A4).....................................................................................................9-31

PA_SWSTS Switch Status (0x0A0)........................................................................................................9-30

PA_VCR0CAP- VC Resource 0 Capability (0x110)................................................................................9-38

PA_VCR0CTL- VC Resource 0 Control (0x114).....................................................................................9-38

PA_VCR0STS - VC Resource 0 Status (0x118).....................................................................................9-39

PA_VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120).......................................................9-40

PA_VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124).......................................................9-41

PA_VID - Vendor Identification (0x000)....................................................................................................9-9

PC_BAR0 - Base Address Register 0 (0x010)......................................................................................10-25

PC_BAR1 - Base Address Register 1 (0x014)......................................................................................10-25

PC_BCTRL - Bridge Control (0x03E)....................................................................................................10-30

PC_BIST - Built-in Self Test (0x00F).....................................................................................................10-24

PC_CAPPTR - Capabilities Pointer (0x034) .........................................................................................10-29

PC_CCODE - Class Code (0x009) .......................................................................................................10-24

PC_CLS - Cache Line Size (0x00C).....................................................................................................10-24

PC_DID - Device Identification (0x002).................................................................................................10-21

PC_ECFGADDR - Extended Configuration Space Access Address (0x0F8).......................................10-47

PC_ECFGDATA - Extended Configuration Space Access Data (0x0FC).............................................10-48

PC_EEPROMINTF - Serial EEPROM Interface (0x0B4)......................................................................10-46

PC_EROMBASE - Expansion ROM Base Address (0x038).................................................................10-29

PC_GPIOCS - General Purpose I/O Control and Status (0x0A8).........................................................10-43

PC_HDR - Header Type (0x00E)..........................................................................................................10-24

PC_INTRLINE - Interrupt Line (0x03C).................................................................................................10-30

PC_INTRPIN - Interrupt PIN (0x03D)....................................................................................................10-30

PC_INTSTS - Interrupt Status (0x0F4).................................................................................................10-47

PC_IOBASE - I/O Base (0x01C)...........................................................................................................10-26

PC_IOBASEU - I/O Base Upper (0x030)..............................................................................................10-29

PC_IOLIMIT - I/O Limit (0x01D)............................................................................................................10-26

PC_IOLIMITU - I/O Limit Upper (0x032)...............................................................................................10-29

PC_MBASE - Memory Base (0x020)....................................................................................................10-27

PC_MLIMIT - Memory Limit (0x022).....................................................................................................10-27

PC_PBUSN - Primary Bus Number (0x018).........................................................................................10-25

PC_PCICMD - PCI Command (0x004).................................................................................................10-21

PC_PCIECAP - PCI Express Capability (0x040) ..................................................................................10-31

PC_PCIEDCAP - PCI Express Device Capabilities (0x044).................................................................10-31

PC_PCIEDCTL - PCI Express Device Control (0x048).........................................................................10-32

PC_PCIEDSTS - PCI Express Device Status (0x04A) .........................................................................10-33

PC_PCIELCAP - Port C NTB Mode PCI Express Link Capabilities (0x04C)........................................10-34

PC_PCIELCTL - Port C NTB Mode PCI Express Link Control (0x050)................................................10-35

PC_PCIELSTS - Port C NTB Mode PCI Express Link Status (0x052) .................................................10-36

PC_PCIESCAP - Port C NTB Mode PCI Express Slot Capabilities (0x054).........................................10-36

PC_PCIESCTL - Port C NTB Mode PCI Express Slot Control (0x058)................................................10-37

PC_PCIESSTS - Port C NTB Mode PCI Express Slot Status (0x5A)...................................................10-37

PC_PCIEVCECAP - PCI Express Virtual Channel Enhanced Capability Header (0x100) ...................10-48

PC_PCISTS - PCI Status (0x006).........................................................................................................10-22

PC_PLTIMER - Primary Latency Timer (0x00D)...................................................................................10-24

PC_PMBASE - Prefetchable Memory Base (0x024).............................................................................10-28

PC_PMBASEU - Prefetchable Memory Base Upper (0x028)...............................................................10-28

PC_PMCAP - PCI Power Management Capabilities (0x070)...............................................................10-38

PC_PMCSR - PCI Power Management Control and Status (0x074)....................................................10-38

PES16NT2 User Manual x April 15, 2008

IDT Register List

Notes

PC_PMLIMIT - Prefetchable Memory Limit (0x026)..............................................................................10-28

PC_PMLIMITU - Prefetchable Memory Limit Upper (0x02C)................................................................10-29

PC_PMPC - PCI Power Management Proprietary Control (0x078)......................................................10-39

PC_PVCCAP1- Port VC Capability 1 (0x104).......................................................................................10-48

PC_RID - Revision Identification (0x008)..............................................................................................10-23

PC_SBUSN - Secondary Bus Number (0x019)....................................................................................10-25

PC_SECSTS - Secondary Status (0x01E)............................................................................................10-26

PC_SERDESCTL - SerDes Control (0x200).........................................................................................10-53

PC_SLTIMER - Secondary Latency Timer (0x01B)..............................................................................10-25

PC_SMBUSCTL - SMBus Control (0x0B0)...........................................................................................10-45

PC_SMBUSSTS - SMBus Status (0x0AC) ...........................................................................................10-44

PC_SUBUSN - Subordinate Bus Number (0x01A)...............................................................................10-25

PC_SWCTL - Switch Control (0x0A4)...................................................................................................10-42

PC_SWSTS Switch Status (0x0A0)......................................................................................................10-41

PC_VCR0CAP- VC Resource 0 Capability (0x110)..............................................................................10-49

PC_VCR0CTL- VC Resource 0 Control (0x114)...................................................................................10-49

PC_VCR0STS - VC Resource 0 Status (0x118)...................................................................................10-50

PC_VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120).....................................................10-51

PC_VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124).....................................................10-52

PC_VID - Vendor Identification (0x000)................................................................................................10-21

PCEE_BAR0 - Base Address Register 0 (0x010)...............................................................................10-111

PCEE_BAR1 - Base Address Register 1 (0x014)...............................................................................10-112

PCEE_BAR2 - Base Address Register 2 (0x018)...............................................................................10-112

PCEE_BAR3 - Base Address Register 3 (0x01C) ..............................................................................10-113

PCEE_BAR4 - Base Address Register 4 (0x020)...............................................................................10-114

PCEE_BARSETUP0 - BAR 0 Setup (0x07C) .....................................................................................10-125

PCEE_BARSETUP1 - BAR 1 Setup (0x084)......................................................................................10-127

PCEE_BARSETUP2 - BAR 2 Setup (0x08C) .....................................................................................10-129

PCEE_BARSETUP3 - BAR 3 Setup (0x094)......................................................................................10-131

PCEE_BARSETUP4 - BAR 4 Setup (0x09C) .....................................................................................10-133

PCEE_BARTBASE0 - BAR 0 Translated Base Address (0x080).......................................................10-126

PCEE_BARTBASE1 - BAR 1 Translated Base Address (0x088).......................................................10-128

PCEE_BARTBASE2 - BAR 2 Translated Base Address (0x090).......................................................10-130

PCEE_BARTBASE3 - BAR 3 Translated Base Address (0x098).......................................................10-132

PCEE_BARTLIMIT0 - BAR 0 Translated Limit Address (0x218)........................................................10-150

PCEE_BARTLIMIT1 - BAR 1 Translated Limit Address (0x21C)........................................................10-151

PCEE_BARTLIMIT2 - BAR 2 Translated Limit Address (0x220)........................................................10-151

PCEE_BARTLIMIT3 - BAR 3 Translated Limit Address (0x224)........................................................10-151

PCEE_BIST - Built-on Self Test (0x00F).............................................................................................10-111

PCEE_CAPPTR - Capabilities Pointer (0x034)...................................................................................10-115

PCEE_CCODE - Class Code (0x009).................................................................................................10-110

PCEE_CLS - Cache Line Size (0x00C) ..............................................................................................10-110

PCEE_DID - Device Identification (0x002)..........................................................................................10-107

PCEE_ECFGADDR - Extended Configuration Space Access Address (0x0F8)................................10-145

PCEE_ECFGDATA - Extended Configuration Space Access Data (0x0FC)......................................10-145

PCEE_FOVRCTL - Failover Control (0x22C) .....................................................................................10-152

PCEE_FOVRSTS - Failover Status (0x228).......................................................................................10-152

PCEE_FOVRTIMER - Failover Watchdog Timer (0x230)...................................................................10-153

PCEE_HDR - Header Type (0x00E)...................................................................................................10-110

PCEE_INDBELL - Inbound Doorbell (0x0E0) .....................................................................................10-138

PCEE_INMSG[0|1|2|3] - Inbound Message [0|1|2|3] (0x0B8-0C4).....................................................10-137

PCEE_INTCTL0 - Interrupt Control 0 (0x0EC)....................................................................................10-140

PCEE_INTCTL1 - Interrupt Control 1 (0x210).....................................................................................10-146

PCEE_INTRLINE - Interrupt Line (0x03C)..........................................................................................10-115

PCEE_INTRPIN - Interrupt PIN (0x03D).............................................................................................10-115

PES16NT2 User Manual xi April 15, 2008

IDT Register List

Notes

PCEE_INTSTS - Interrupt Status (0x0E8)..........................................................................................10-138

PCEE_MAXLAT - Maximum Latency (0x03F) ....................................................................................10-116

PCEE_MINGNT - Minimum Grant (0x03E).........................................................................................10-115

PCEE_MLTIMER - Master Latency Timer (0x00D).............................................................................10-110

PCEE_MSIADDR - Message Signaled Interrupt Address (0x068).....................................................10-121

PCEE_MSICAP - Message Signaled Interrupt Capability and Control (0x064)..................................10-120

PCEE_MSIMDATA - Message Signaled Interrupt Message Data (0x070).........................................10-121

PCEE_MSIUADDR - Message Signaled Interrupt Upper Address (0x06C) .......................................10-121

PCEE_MTADDR - Mapping Table Address (0x0AC)..........................................................................10-135

PCEE_MTDATA - Mapping Table DATA (0x0B0)...............................................................................10-136

PCEE_NTBCFG - Non-Transparent Bridge Configuration (0x200) ....................................................10-146

PCEE_NTBCFGC - Non-Transparent Bridge Configuration Capability (0x074).................................10-121

PCEE_NTBCOMC - Non-Transparent Bridge Communications Capability (0x0B4) ..........................10-137

PCEE_NTBCTL - Non-Transparent Bridge Control (0x078)...............................................................10-122

PCEE_NTBEPID - Non-Transparent Bridge Endpoint Identification (0x07A).....................................10-124

PCEE_NTBSTS - Non-Transparent Bridge Status (0x079)................................................................10-123

PCEE_OUTDBELL - Outbound Doorbell (0x0E4)...............................................................................10-138

PCEE_OUTMSG[0|1|2|3] - Outbound Message [0|1|2|3] (0x0C8-0D4)..............................................10-137

PCEE_PCICMD - PCI Command (0x004) ..........................................................................................10-108

PCEE_PCIECAP - PCI Express Capability (0x040)............................................................................10-116

PCEE_PCIEDCAP - PCI Express Device Capabilities (0x044)..........................................................10-116

PCEE_PCIEDCTL - PCI Express Device Control (0x048)..................................................................10-117

PCEE_PCIEDSTS PCI Express Device Status (0x04A).....................................................................10-118

PCEE_PCIEECAP - PCI Express Extended Capability (0x100).........................................................10-145

PCEE_PCIELCAP - PCI Express Link Capabilities (0x04C)...............................................................10-119

PCEE_PCIELCTL - PCI Express Link Control (0x050).......................................................................10-119

PCEE_PCIELSTS - PCI Express Link Status (0x052)........................................................................10-120

PCEE_PCISTS - PCI Status (0x006)..................................................................................................10-109

PCEE_PMCAP - PCI Power Management Capabilities (0x0F0) ........................................................10-143

PCEE_PMCSR - PCI Power Management Control and Status (0x0F4).............................................10-144

PCEE_PTCCFG - Punch Through Configuration Control (0x0A0) .....................................................10-133

PCEE_PTCDATA - Punch Through Configuration Data (0x0A4) .......................................................10-134

PCEE_PTCSTS - Punch Through Configuration Status (0x0A8) .......................................................10-135

PCEE_RID - Revision Identification (0x008).......................................................................................10-110

PCEE_SCRATCHPAD[0..1] - Scratchpad [0..1] (0x0D8-ODC) ..........................................................10-138

PCEE_SUBID - Subsystem ID Pointer (0x02E)..................................................................................10-115

PCEE_SUBVID - Subsystem Vendor ID Pointer (0x02C)...................................................................10-115

PCEE_TLPPCTL - TLP Processing Control (0x214) ..........................................................................10-150

PCEE_VID - Vendor Identification (0x000) .........................................................................................10-107

PCIE_BAR0 - Base Address Register 0 (0x010) ..................................................................................10-63

PCIE_BAR1 - Base Address Register 1 (0x014) ..................................................................................10-64

PCIE_BAR2 - Base Address Register 2 (0x018) ..................................................................................10-64

PCIE_BAR3 - Base Address Register 3 (0x01C)..................................................................................10-65

PCIE_BAR4 - Base Address Register 4 (0x020) ..................................................................................10-66

PCIE_BARSETUP0 - BAR 0 Setup (0x07C).........................................................................................10-77

PCIE_BARSETUP1 - BAR 1 Setup (0x084) .........................................................................................10-79

PCIE_BARSETUP2 - BAR 2 Setup (0x08C).........................................................................................10-81

PCIE_BARSETUP3 - BAR 3 Setup (0x094) .........................................................................................10-83

PCIE_BARSETUP4 - BAR 4 Setup (0x09C).........................................................................................10-85

PCIE_BARTBASE0 - BAR 0 Translated Base Address (0x080)...........................................................10-78

PCIE_BARTBASE1 - BAR 1 Translated Base Address (0x088)...........................................................10-80

PCIE_BARTBASE2 - BAR 2 Translated Base Address (0x090)...........................................................10-82

PCIE_BARTBASE3 - BAR 3 Translated Base Address (0x098)...........................................................10-84

PCIE_BARTLIMIT0 - BAR 0 Translated Limit Address (0x218)..........................................................10-102

PCIE_BARTLIMIT1 - BAR 1 Translated Limit Address (0x21C).........................................................10-103

PES16NT2 User Manual xii April 15, 2008

IDT Register List

Notes

PCIE_BARTLIMIT2 - BAR 2 Translated Limit Address (0x220)..........................................................10-103

PCIE_BARTLIMIT3 - BAR 3 Translated Limit Address (0x224)..........................................................10-103

PCIE_BIST - Built-on Self Test (0x00F)................................................................................................10-63

PCIE_CAPPTR - Capabilities Pointer (0x034)......................................................................................10-67

PCIE_CCODE - Class Code (0x009)....................................................................................................10-62

PCIE_CLS - Cache Line Size (0x00C)..................................................................................................10-62

PCIE_DID - Device Identification (0x002).............................................................................................10-59

PCIE_ECFGADDR - Extended Configuration Space Access Address (0x0F8)....................................10-97

PCIE_ECFGDATA - Extended Configuration Space Access Data (0x0FC).........................................10-97

PCIE_HDR - Header Type (0x00E).......................................................................................................10-62

PCIE_INDBELL - Inbound Doorbell (0x0E0).........................................................................................10-90

PCIE_INMSG[0|1|2|3] - Inbound Message [0|1|2|3] (0x0B8-0C4)........................................................10-89

PCIE_INTCTL0 - Interrupt Control 0 (0x0EC).......................................................................................10-92

PCIE_INTCTL1 - Interrupt Control 1 (0x210)........................................................................................10-98

PCIE_INTRLINE - Interrupt Line (0x03C).............................................................................................10-67

PCIE_INTRPIN - Interrupt PIN (0x03D)................................................................................................10-67

PCIE_INTSTS - Interrupt Status (0x0E8)..............................................................................................10-90

PCIE_MAXLAT - Maximum Latency (0x03F)........................................................................................10-68

PCIE_MINGNT - Minimum Grant (0x03E) ............................................................................................10-67

PCIE_MLTIMER - Master Latency Timer (0x00D)................................................................................10-62

PCIE_MSIADDR - Message Signaled Interrupt Address (0x068).........................................................10-73

PCIE_MSICAP - Message Signaled Interrupt Capability and Control (0x064).....................................10-72

PCIE_MSIMDATA - Message Signaled Interrupt Message Data (0x070)............................................10-73

PCIE_MSIUADDR - Message Signaled Interrupt Upper Address (0x06C)...........................................10-73

PCIE_MTADDR - Mapping Table Address (0x0AC).............................................................................10-87

PCIE_MTDATA - Mapping Table DATA (0x0B0)..................................................................................10-88

PCIE_NTBCFG - Non-Transparent Bridge Configuration (0x200)........................................................10-98

PCIE_NTBCFGC - Non-Transparent Bridge Configuration Capability (0x074)....................................10-73

PCIE_NTBCOMC - Non-Transparent Bridge Communications Capability (0x0B4)..............................10-89

PCIE_NTBCTL - Non-Transparent Bridge Control (0x078) ..................................................................10-74

PCIE_NTBEPID - Non-Transparent Bridge Endpoint Identification (0x07A).........................................10-76

PCIE_NTBSTS - Non-Transparent Bridge Status (0x079)....................................................................10-75

PCIE_OUTDBELL - Outbound Doorbell (0x0E4)..................................................................................10-90

PCIE_OUTMSG[0|1|2|3] - Outbound Message [0|1|2|3] (0x0C8-0D4) .................................................10-89

PCIE_PCICMD - PCI Command (0x004)..............................................................................................10-59

PCIE_PCIECAP - PCI Express Capability (0x040)...............................................................................10-68

PCIE_PCIEDCAP - PCI Express Device Capabilities (0x044)..............................................................10-68

PCIE_PCIEDCTL - PCI Express Device Control (0x048).....................................................................10-69

PCIE_PCIEDSTS - PCI Express Device Status (0x04A)......................................................................10-70

PCIE_PCIEECAP - PCI Express Extended Capability (0x100) ............................................................10-97

PCIE_PCIELCAP - PCI Express Link Capabilities (0x04C)..................................................................10-71

PCIE_PCIELCTL - PCI Express Link Control (0x050)..........................................................................10-71

PCIE_PCIELSTS - PCI Express Link Status (0x052) ...........................................................................10-72

PCIE_PCISTS - PCI Status (0x006).....................................................................................................10-61

PCIE_PMCAP - PCI Power Management Capabilities (0x0F0)............................................................10-95

PCIE_PMCSR - PCI Power Management Control and Status (0x0F4)................................................10-96

PCIE_PTCCFG - Punch Through Configuration Control (0x0A0).........................................................10-85

PCIE_PTCDATA - Punch Through Configuration Data (0x0A4)...........................................................10-86

PCIE_PTCSTS - Punch Through Configuration Status (0x0A8)...........................................................10-87

PCIE_RID - Revision Identification (0x008) ..........................................................................................10-62

PCIE_SCRATCHPAD[0..1] - Scratchpad [0..1] (0x0D8-ODC) ..............................................................10-90

PCIE_SUBID - Subsystem ID Pointer (0x02E) .....................................................................................10-67

PCIE_SUBVID - Subsystem Vendor ID Pointer (0x02C)......................................................................10-67

PCIE_TLPPCTL - TLP Processing Control (0x214)............................................................................10-102

PCIE_VID - Vendor Identification (0x000).............................................................................................10-59

PES16NT2 User Manual xiii April 15, 2008

IDT Register List

Notes

PES16NT2 User Manual xiv April 15, 2008

Chapter 1

PES16NT2 Device Overview

®

Notes

Introduction

The 89HPES16NT2 is a member of the IDT PRECISE™ family of PCI Express® switching solutions
offering the next-generation I/O interconnect standard. The PES16NT2 is a 16-lane, 2-port peripheral chip
that provides high-performance switching and non-transparent bridging (NTB) functions between a PCIe®
upstream port and an NTB downstream port. The PES16NT2 is a part of the IDT PCIe System Interconnect
Products and is intended to be used with IDT PCIe System Interconnect Switches. Together, the chipset
targets multi-host and intelligent I/O applications such as communications, storage, and blade servers
where inter-domain communication is required.

Utilizing standard PCI Express interconnect, the PES16NT2 provides the most efficient high-perfor­mance I/O connectivity solution for applications requiring high throughput, low latency, and simple board
layout with a minimum number of board layers. With support for non-transparent bridging, the PES16NT2 is
part of the IDT PCIe System Interconnect Products that target multi-host and intelligent I/O applications
requiring inter-domain communication. The PES16NT2 provides 64 Gbps (8 GBps) of aggregated, full­duplex switching capacity through 16 integrated serial lanes, using proven and robust IDT technology . Each
lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base speci­fication 1.0a.

The PES16NT2 is based on a flexible and efficient layered architecture. The PCI Express layer consists
of SerDes, Physical, Data Link, and Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES16NT2 can operate either as a store and forward or cut-through switch depending
on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic Classes
(TCs) and one Virtual Channel (VC) with sophisticated resource management.

Figure 1.1 provides a functional block diagram while Figure 1.2 illustrates the architecture of the device.

PES16NT2 User Manual 1 - 1 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Port A

(Upstream Port)

Type 1

Configuration Header

PCI-PCI

Transparent

Bridge

Virtual PCI Bus

Type 1

Configuration Header

PCI-PCI

Transparent

Bridge

Internal Type 0

Configuration Header

Non-Transparent

Bridge

External Type 0

Configuration Header

Port C

(Non-Transparent Port)

Figure 1.1 PES16NT2 Functional Block Diagram

As shown in Figure 1.1, port A is configured as the upstream port and port C as the non-transparent
downstream port. Port C resides on the internal PCI Bus at Device 1, Function 0.

PES16NT2 User Manual 1 - 2 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Egress

Scheduler

Input Frame Buffer

PT NP CP

Transaction

Layer

Data Link

Layer

Physical

Layer MAC/PCS

SerDes

Port Arbiter

Route

Map

Table

Retry

Buffer

2-Port Switch Core

Egress

Scheduler

Input Frame Buffer

PT NP CP

Transaction

Layer

Data Link

Layer

Physical

Layer MAC/PCS

SerDes

Port Arbiter

Route

Map

Table

Retry

Buffer

GPIO

Controller

Master
SMBus

Interface

Slave

SMBus

Interface

Port A

Upstream Port

Downstream Port

Figure 1.2 PES16NT2 Architectural Block Diagram

List of Features



High Performance PCI Express Switch

– Sixteen PCI Express lanes (2.5Gbps), two switch ports
– Delivers 64 Gbps (8 GBps) of aggregate switching capacity
– Low latency cut-through switch architecture
– Support for Max Payload size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base specification Revision 1.0a compliant



Flexible Architecture with Numerous Configuration Options

– Supports automatic per port link width negotiation (x8, x4, x2, or x1)
– Static lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy software
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus



Non-Transparent Port

– Crosslink support on NTB port
– Four mapping windows supported

• Each may be configured as a 32-bit memory or I/O window

• May be paired to form a 64-bit memory window

– Interprocessor communication

• Thirty-two inbound and outbound doorbells

• Four inbound and outbound message registers

Port C

PES16NT2 User Manual 1 - 3 April 15, 2008

IDT PES16NT2 Device Overview

Notes

• Two shared scratchpad registers
– Allows up to sixteen masters to communicate through the non-transparent port
– No limit on the number of supported outstanding transactions through the non-transparent bridge
– Completely symmetric non-transparent bridge operation allows similar/same configuration soft-

ware to be run

– Supports direct connection to a transparent or non-transparent port of another switch



Highly Integrated Solution

– Requires no external components
– Incorporates on-chip internal memory for packet buffering and queueing
– Integrates sixteen 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate

transceivers needed)



Reliability, Availability, and Serviceability (RAS) Features

– Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do

not implement end-to-end CRC (ECRC)

– Supports ECRC pass-through
– Supports Hot-Swap



Power Management

– Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM)
– Unused SerDes are disabled



Testability and Debug Features

– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters



Two SMBus Interfaces

– Slave interface provides full access to all software-visible registers by an external SMBus master
– Master interface provides connection for an optional serial EEPROM used for initialization
– Master and slave interfaces may be tied together so the switch can act as both master and slave



Eight General Purpose Input/Output pins



Packaged in a 23mm x 23mm 484-ball BCG with 1mm ball spacing

System Identification

Vendor ID

All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech-

nology, Inc.

Device ID

The device IDs for the PES16NT2 are shown in Table 1.1.

PCI Device

Transparent bridge associated with Port A 0x804C
Transparent bridge associated with Port C 0x804D
Internal NTB Endpoint associated with Port C 0x804E
External NTB Endpoint associated with Port C 0x804F

Table 1.1 PES16NT2 Offset Device IDs

Offset

Device ID

PES16NT2 User Manual 1 - 4 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Revision ID

All revision IDs in the PES16NT2 are set to the same value. The value of the revision ID is determined in
one place and is easily modified during a metal mask change. The revision ID shall be incremented with
each all layer or metal mask change.

Revision ID Description

0x0 Corresponds to ZA silicon

Table 1.2 PES16NT2 Revision IDs

JTAG ID

The JTAG ID is:

– Version: Same value as Revision ID. See the Revision ID section above.
– Part number: Same value as base Device ID. See the Device ID section above.
– Manufacture ID: 0x33
– LSB: 0x1

PES16NT2 User Manual 1 - 5 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Logic Diagram

Reference

Clocks

PCI Express

Switch

SerDes Input

Port A

PCI Express

Switch

SerDes Input

Port C

PEREFCLKP
PEREFCLKN

REFCLKM

PEALREV
PEARP[0]
PEARN[0]

PEARP[1]
PEARN[1]

PEARP[7]
PEARN[7]

PECLREV

PECRP[0]
PECRN[0]

PECRP[1]
PECRN[1]

PECRP[7]
PECRN[7]

...

...

2

2

PEATP[0]
PEATN[0]

PCI Express

Switch

SerDes Output

Port A

PCI Express

Switch

SerDes Output

Port C

PES16NT2

...

...

PEATP[1]
PEATN[1]

PEATP[7]
PEATN[7]

PECTP[0]
PECTN[0]

PECTP[1]
PECTN[1]

PECTP[7]
PECTN[7]

Master

SMBus Interface

Slave

SMBus Interface

System

Functions

MSMBADDR[4:1]

MSMBCLK
MSMBDAT

SSMBADDR[5,3:1]

SSMBCLK
SSMBDAT

MSMBSMODE

CCLKDS
CCLKUS

RSTHALT

PERSTN

PENTBRSTN

SWMODE[3:0]

4

4

4

Figure 1.3 PES16NT2 Logic Diagram

8

GPIO[7:0]

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

VDDCORE

IO

V

DD

PE

V

DD

APE

V

DD

V

SS

VTTPE

General Purpose

I/O

JTAG

Power/Ground

PES16NT2 User Manual 1 - 6 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Pin Description

The following tables list the functions of the pins provided on the PES16NT2. Some of the functions
listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals
ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals
(including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic
one (high) level.

Signal Type Name/Description

PEALREV I PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of

PCI Express Port A are reversed. This value may be overridden by modify­ing the value of the PALREV bit in the PA_SWCTL register.

PEARP[7:0]
PEARN[7:0]

PEATP[7:0]
PEATN[7:0]

PECLREV I PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of

PECRP[7:0]
PECRN[7:0]

PECTP[7:0]
PECTN[7:0]

PEREFCLKP[1:0]
PEREFCLKN[1:0]

REFCLKM I PCI Express Reference Clock Mode Select . These signals select the fre-

I PCI Express Port A Serial Data Receive. Differential PCI Express receive

pairs for port A.

O PCI Express Port A Serial Data Transmit. Differential PCI Express trans-

mit pairs for port A

PCI Express Port C are reversed. This value may be overridden by modify­ing the value of the PCLREV bit in the PA_SWCTL register.

I PCI Express Port C Serial Data Receive. Differential PCI Express receive

pairs for port C.

O PCI Express Port C Serial Data Transmit. Differential PCI Express trans-

mit pairs for port C

I PCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif­ferential reference clock is determined by the REFCLKM signal.

quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz

Table 1.3 PCI Express Interface Pins

Signal Type Name/Description

MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus. It is active and generating the clock only
when the EEPROM is being accessed.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

Table 1.4 SMBus Interface Pins

PES16NT2 User Manual 1 - 7 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

GPIO[1] I/O General Purpose I/O.

GPIO[2] I/O General Purpose I/O.

GPIO[3] I/O General Purpose I/O.

GPIO[4] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PECRSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port C

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PALINKUPN
Alternate function pin type: Output
Alternate function: Port A link up status output

This pin can be configured as a general purpose I/O pin.

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PCLINKUPN
Alternate function pin type: Output
Alternate function: Port C link up status output

GPIO[5] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: FAILOVERP
Alternate function pin type: Input
Alternate function: NTB upstream port failover

GPIO[6] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Table 1.5 General Purpose I/O Pins

Signal Type Name/Description

CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi-

cates that a common clock is being used between the downstream device
and the downstream port.

CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi-

cates that a common clock is being used between the upstream device and
the upstream port.

MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the

master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.

PENTBRSTN I Non-Transparent Bridge Reset. Assertion of this signal indicates a reset

on the external side of the non-transparent bridge. This signal is only used
when the switch mode selects a non-transparent mode and has no effect
otherwise.

Table 1.6 System Pins (Part 1 of 2)

PES16NT2 User Manual 1 - 8 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Signal Type Name/Description

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the

PES16NT2 and initiates a PCI Express fundamental reset.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, the PES16NT2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera­tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.

SWMODE[3:0] I Switch Mode. These configuration pins determine the PES16NT2 switch

operating mode.
0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode with serial EEPROM initialization
0x6 through 0xF - Reserved

Table 1.6 System Pins (Part 2 of 2)

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 1.7 Test Pins

Signal Type Name/Description

CORE I Core VDD. Power supply for core logic.

V

DD

IO I I/O VDD. LVTTL I/O buffer power supply.

V

DD

V

PE I PCI Express Digital Power. PCI Express digital power used by the digital

DD

power of the SerDes.

Table 1.8 Power and Ground Pins

PES16NT2 User Manual 1 - 9 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Signal Type Name/Description

VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL

and bias generator.

PE I PCI Express Termination Power.

V

TT

V

SS

I Ground.

Table 1.8 Power and Ground Pins

Pin Characteristics

Note: Some input pads of the PES16NT2 do not contain internal pull-ups or pull-downs. Unused
inputs should be tied off to appropriate levels. This is especially critical for unused control signal
inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can
cause a slight increase in power consumption.

Function Pin Name Type Buffer I/O Type

PCI Express
Interface

SMBus MSMBADDR[4:1] I LVTTL Input pull-up

General Pur­pose I/O

PEALREV I LVTTL Input pull-down
PEARN[7:0] I CML Serial link
PEARP[7:0] I
PEATN[7:0] O
PEATP[7:0] O
PECLREV I LVTTL Input pull-down
PECRN[7:0] I CML Serial link
PECRP[7:0] I
PECTN[7:0] O
PECTP[7:0] O
PEREFCLKN[1:0] I LVPECL/
PEREFCLKP[1:0] I

REFCLKM I LVTTL Input pull-down

MSMBCLK I/O STI
MSMBDAT I/O
SSMBADDR[5,3:1] I Input pull-up
SSMBCLK I/O STI
SSMBDAT I/O
GPIO[7:0] I/O LVTTL Input,

CML

Diff. Clock

Input

High Drive

Internal

Resistor

Notes

Refer to

Table 8 in the

PES16NT2
Data Sheet

pull-up

Table 1.9 Pin Characteristics (Part 1 of 2)

PES16NT2 User Manual 1 - 10 April 15, 2008

IDT PES16NT2 Device Overview

Notes

Function Pin Name Type Buffer I/O Type

System Pins CCLKDS I LVTTL Input pull-up

CCLKUS I pull-up
MSMBSMODE I pull-down
PENTBRSTN I
PERSTN I
RSTHALT I pull-down
SWMODE[3:0] I pull-up

JTAG JTAG_TCK I LVTTL STI pull-up

JTAG_TDI I pull-up
JTAG_TDO O Low Drive
JTAG_TMS I STI pull-up
JTAG_TRST_N I pull-up External

Table 1.9 Pin Characteristics (Part 2 of 2)

Internal

Resistor

Notes

pull-down

PES16NT2 User Manual 1 - 11 April 15, 2008

IDT PES16NT2 Device Overview

Notes

PES16NT2 User Manual 1 - 12 April 15, 2008

Chapter 2

Clocking, Reset, and

Initialization

®

Notes

Introduction

The PES16NT2 has two differential reference clock inputs that are used internally to generate all of the
clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both
reference clock input pairs be driven from a common clock source. There are no skew requirements
between the reference clock inputs.The frequency of the reference clock inputs may be selected by the
Reference Clock Mode Select (REFCLKM) input.

REFCLKM Description

0 100 MHz reference clock input.
1 125 MHz reference clock input.

Table 2 .1 Reference Clock Mode Encoding

Each of the reference clock differential inputs feeds six on-chip PLLs. Each PLL generates a 2.5 GHz
clock which is used by four SerDes lanes and produces a 250 MHz core clock.The 250 MHz core clock
output from one of the six internal PLLs is used as the system clock for internal switch logic.

Each of the reference clock differential inputs feeds six on-chip PLLs. Each PLL generates a 2.5 GHz
clock which is used by four SerDes lanes and produces a 250 MHz core clock. The 250 MHz core clock
output from one of the six internal PLLs is used as the system clock for internal switch logic.

Clock Operation

When the CCLKUS and CCLKDS pins are asserted, they indicate that a common clock is being used
between the upstream device and the upstream port, as well as between the downstream devices and the
downstream port. The Spread Spectrum Clock (SSC) must be disabled when the non-common clock is
used on either the upstream port or downstream port. Figures 2.1 through 2.4 illustrate the operation of the
CCLKUS and CCLKDS clocks using a common clock and a non-common clock.

PES16NT2

Root Complex

Hi

Clock Generator

Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock)

PES16NT2 User Manual 2 - 1 April 15, 2008

Port A

CCLKUS

REFCLK0

Port C

CCLKDS

REFCLK1

EP

Hi

IDT Clocking, Reset, and Initialization Clock Operation

Notes

PES16NT2

Root Complex

Low

Clock Generator

Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum

Port A

CCLKUS

REFCLK0

Clock)

Port C

CCLKDS

REFCLK1

EP

Hi

Clock Generator

PES16NT2

Root Complex

Port A

Port C

EP

Hi

Clock Generator

Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable Spread Spectrum

CCLKUS

REFCLK0

Clock)

CCLKDS

REFCLK1

Low

Clock Generator

PES16NT2 User Manual 2 - 2 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

Notes

PES16NT2

Root Complex

Low

Clock Generator

Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock)

Port A

CCLKUS

REFCLK0

REFCLK1

Clock Generator

Port C

CCLKDS

EP

Low

Clock Generator

Initialization

A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES16NT2
during a fundamental reset when PERSTN is negated. The boot configuration vector defines essential
parameters for switch operation.

While basic switch operation may be configured using signals in the boot configuration vector , advanced
switch features require configuration via an external serial EEPROM. The external serial EEPROM allows
modification of any bit in any software visible register. See Chapter 6, SMBus Interfaces, for more informa­tion on the serial EEPROM.

The external serial EEPROM and slave SMBus interface may be used to override the function of some
of the signals in the boot configuration vector during a fundamental reset. The signals that may be over­ridden are noted in Table 2.2. The state of all of the boot configuration signals in Table 2.2 sampled during
the most recent cold reset may be determined by reading the PA_SWSTS register.

Signal

CCLKDS Y Common Clock Downstream. When the CCLKDS pin is

CCLKUS Y Common Clock Upstream. When the CCLKUS pin is asserted,

MSMBSMODE N Master SMBus Slow Mode. The assertion of this pin indicates

PES16NT2 User Manual 2 - 3 April 15, 2008

May Be

Overridden

asserted, it indicates that a common clock is being used
between the downstream device and the downstream port. This
pin is used as the initial value of the Slot Clock Configuration bit
in all of the Link Status Registers for downstream ports. The
value may be overridden by modifying the SCLK bit in the
PC_PCIELSTS register.

it indicates that a common clock is being used between the
upstream device and the upstream port. This pin is used as the
initial value of the Slot Clock Configuration bit in the Link Status
Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.

that the master SMBus should operate at 100 KHz instead of
400 kHz.

Table 2.2 Boot Configuration Vector Signals (Part 1 of 2)

Description

IDT Clocking, Reset, and Initialization Clock Operation

Notes

Signal

PEALREV Y PCI Express Port A Lane Reverse. When this pin is asserted,

PECLREV Y PCI Express Port C Lane Reverse. When this pin is asserted,

REFCLKM N PCI Express Reference Clock Mode Select. These signals

RSTHALT Y Reset Halt. When this signal is asserted during a PCI Express

SWMODE[3:0] N Switch Mode. These configuration pins determine the

May Be

Overridden

Description

the lanes of PCI Express Port A are reversed. This value may
be overridden by modifying the value of the PALREV bit in the
PA_SWCTL register.

the lanes of PCI Express Port C are reversed. This value may
be overridden by modifying the value of the PCLREV bit in the
PA_SWCTL register.

select the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz

fundamental reset, the PES16NT2 executes the reset proce­dure and remains in a reset state with the Master and Slave
SMBuses active. This allows software to read and write regis­ters internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT bit
is cleared in the PA_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in
the PA_SWCTL register.

PES16NT2 switch operating mode.
0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode with serial EEPROM initial-

ization

0x6 through 0xF - Reserved

Table 2.2 Boot Configuration Vector Signals (Part 2 of 2)

Signal Type Name/Description

CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi-

cates that a common clock is being used between the downstream device
and the downstream port.

CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi-

cates that a common clock is being used between the upstream device and
the upstream port.

MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the

master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.

PENTBRSTN I Non-Transparent Bridge Reset. Assertion of this signal indicates a reset

on the external side of the non-transparent bridge. This signal is only used
when the switch mode selects a non-transparent mode and has no effect
otherwise.

Table 2.3 System Pins (Part 1 of 2)

PES16NT2 User Manual 2 - 4 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

Notes

Signal Type Name/Description

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the

PES16NT2 and initiates a PCI Express fundamental reset.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, the PES16NT2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera­tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.

SWMODE[3:0] I Switch Mode. These configuration pins determine the PES16NT2 switch

operating mode.
0x0 - Transparent mode
0x1 - Transparent mode with serial EEPROM initialization
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode with serial EEPROM initialization
0x6 through 0xF - Reserved

Table 2.3 System Pins (Part 2 of 2)

Reset

PCI Express® defines two reset categories: fundamental reset and hot reset. A fundamental reset
causes all associated logic to be returned to an initial state. A hot reset causes all associated logic to be
returned to an initial state, but does not cause the state of register fields denoted as “sticky” to be modified.

There are two sub-categories of fundamental reset: cold reset and warm reset. A cold reset occurs
following a device being powered on and assertion of PERSTN. A warm reset is a fundamental reset that
occurs without removal of power.

A summary of reset conditions and their effect is exhibited in Table 2.4.

Global

Hot
Reset to
Downstr

eam

Ports

Local

Hot

Reset

Ext.

NTB

Fund.

Reset

Ext.

NTB

Hot

1

Reset

Fund.

Reset

Global

Hot

Reset to

Entire

Device

Master SMBus YNNNNN
Slave SMBus YNNNNN
Serial EEPROM Initial-

ization

Y

if mode

NNNNN

requires it

Switch Core Y Y N (flush

NNN

buffer

only)

Port A All Registers YNNNNN
Port A All Registers

YYNNNN
Except Those of Type
Sticky or RWL

Table 2.4 Reset Conditions and Their Effect (Part 1 of 2)

PES16NT2 User Manual 2 - 5 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

Notes

Global

Hot
Reset to
Downstr

eam

Ports

Local

Hot

Reset

Ext.

NTB

Fund.

Reset

Ext.

NTB

Hot

1

Reset

Fund.

Reset

Global

Hot

Reset to

Entire

Device

Port A Transaction LayerYYNNNN
Port A Data Link LayerYYNNNN
Port A Phy Layer YYNNNN
Port C All Registers YNNNNN
Port C All Registers

YYYNNN
Except Those of Type
Sticky or RWL

Port C Transaction Layer Y Y Y N N N
Port C Data Link Layer Y Y

(Y in NTB

Mode)

Y

(Y in NTB

Mode)

Y if

selected

(Y in NTB

Y in NTB

mode

Y in NTB

mode

Mode only
if Port C is

reset)

Port C Phy Layer Y Y Y Y if

selected

Y in NTB

mode

Y in NTB

mode

(Y in NTB
Mode only
if Port C is

reset)

Port C Downstream Hot
Reset Req.

NY

(N in NTB

(N in NTB

Mode)

Y

Mode)

Y if

selected

(N in NTB

NN

mode)

NTB Internal Endpoint

YNNNNN

All Registers
NTB Internal Endpoint

All Registers Except
Those of Type Sticky or

YY

2

2

Y

Y2 only if

NN

port C

reset

RWL
NTB External Endpoint

YNNNY

2

N

All Registers
NTB External Endpoint

All Registers Except
Those of Type Sticky or

YY

2

2

Y

Y2 only if

2

Y

2

Y

port C

reset

RWL
PECRSTN asserted N (tri-

state)

Y in trans-

parent

mode or if

selected

by

NTBROS

field in

NTB mode

Y in trans-

parent

mode or if

selected

by

NTBROS

field in

NTB mode

Y in trans-

parent

mode

or if

in NTB

mode and

if port C

reset

PECRSTN

if selected

by

NTBROS

field in

NTB mode

PECRSTN
if selected

by

NTBROS

field in

NTB mode

Table 2.4 Reset Conditions and Their Effect (Part 2 of 2)

PES16NT2 User Manual 2 - 6 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

1.

Notes

An External Fundamental reset in non-transparent mode with the PEFR bit set in either NTBCTL register is the same

as a fundamental reset. See that column for its behavior.

2.

All registers except those in the NTB configuration capability structure.

Fundamental Reset

A fundamental reset of the entire device may be initiated by one of five conditions:

– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input

pin.

– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power

is on.

– A warm reset initiated by the writing of a one to the Reset (RST) bit in the Port A Switch Control

(PA_SWCTL) register.

– A warm reset initiated by the writing of a one to the Reset (RST) bit in the Non-Transparent Bridge

Control (NTBCTL) register of the internal side of the non-transparent bridge when the switch is in
a non-transparent operating mode.

– A warm reset initiated by the writing of a one to the Reset (RST) bit in the Non-Transparent Bridge

Control (NTBCTL) register of the external side of the non-transparent bridge when the switch is in
a non-transparent operating mode.

– A warm reset initiated by the assertion of the non-transparent bridge fundamental reset (PENT-

BRSTN) signal when the device is configured to operate in non-transparent mode and the Prop­agate External Fundamental Reset (PEFR) bit is set in the NTBCTL register of the internal or
external side of the non-transparent bridge.

The PCIe® standard specifies that normal operation should begin within 1.0 second after a fundamental
reset of a device. The reset sequence above guarantees that normal operation will begin within this period
as long as the serial EEPROM initialization process completes within 200 ms. Under normal circumstances,
200 ms is more than adequate to initialize every register in the device even with a Master SMBus operating
frequency of 100 KHz.

Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.

The PES16NT2 provides a reset output signal for each downstream port implemented as a GPIO alter­nate function. The downstream port C reset output (PECRSTN) signal is an alternate function of GPIO[1].
When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream
port resets are tri-stated. A system designer should use a pull-down on these signals if they are used as
reset outputs.

Fundamental and hot resets in non-transparent mode are described in section section Non-Transparent
Mode Reset on page 2-9.

The operation of a fundamental reset in Transparent mode with serial EEPROM initialization (i.e.,
SWMODE[3:0] = 0x1) is illustrated in Figure 2.5.

PES16NT2 User Manual 2 - 7 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

Notes

Boot vector sampled

REFCLK

Vdd

PERSTN

RSTHALT

SerDes
Stacks

Master SMBus

Slave SMBus

Notes:

1) Reference Clock (REFCLK) not shown to scale.

2) The PES16NT2 requires a minimum time for Tperst-clk of 1µs. The PESPES16NT2 requires a minimum time for Tpvperl of 1ms.

3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PESPES16NT2 is use d. F or example ,
the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.

Tpvperl

1.01 ms

PLL Reset and Lock

< 100 ms

up to 12 µs

CDR Reset & Lock Ready for Normal Operation

Quasi Reset Mode

< 1 sec

Link Training

Ready

Figure 2.5 Fundamental Reset in Transparent Mode with Serial EEPROM initialization

Hot Reset

A hot reset may be initiated globally to the entire device, globally to downstream ports or locally to down­stream port(s).

The PES16NT2 provides a reset output signal for each downstream port implemented as a GPIO alter­nate function. The downstream port C reset output (PECRSTN) signal is an alternate function of GPIO[1].

When a hot reset occurs, the corresponding port reset output is asserted

1

for at least 250 ns. When a global
hot reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri­stated. A system designer should use a pull-down on these signals if they are used as reset outputs.

When the switch is configured for non-transparent operation, a hot reset may be initiated on the external
side of the non-transparent bridge. Fundamental and hot resets in non-transparent mode are described in
the Non-Transparent Mode Reset section.

Device ready for
normal operation

Ready for Normal Operation

ReadySerial EEPROM Initialization

Globally Initiated Hot Reset To Entire Device

A hot reset is initiated globally to the entire device when any of the following conditions occur.

– Reception of TS1 ordered-sets on the upstream port indicating a hot reset.
– Data link layer of the upstream port transitions to the DL_Down state.

Hot reset is only propagated downstream. TS1 ordered-sets indicating a hot reset received on a down­stream port do not result in a hot reset of the downstream port or any function inside the switch.

When a globally initiated hot reset occurs, all of the logic associated with the transparent bridges, stacks
and the switch core are reset except for the PLLs, SerDes, master SMBus interface, slave SMBus interface,
and some registers. Regardless of the switch operating mode, a hot-reset does not result in reloading of the
serial EEPROM. The value of register fields denoted as “sticky” or as Read and Write when Unlocked (i.e.,
RWL) are preserved in all ports across a hot-reset. All other register fields in all ports are reset to their initial
values.

When a hot reset is initiated globally, each downstream port sends a hot-reset message to its link
partner prior to being reset.

1.

Since the PExRSTN signals are active low, the signal should be driven low for 250ns.

PES16NT2 User Manual 2 - 8 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

Notes

Globally Initiated Hot Reset To Downstream Ports

A hot reset is initiated globally to downstream ports when the following condition occurs:

– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (port A) Bridge

Control Register (BCTRL).

When a globally initiated hot reset is initiated to downstream ports, all of the logic associated with the
transparent bridges, stacks and FIFOs in the switch core associated with the downstream ports are reset
except for the PLLs, SerDes, master SMBus interface, slave SMBus interface, and some registers. Regard­less of the switch operating mode, it does not result in reloading of the serial EEPROM.

The value of register fields denoted as “sticky” or as Read and Write when Unlocked (i.e., RWL) in
downstream ports are preserved. All other register fields are reset to their initial values.

When a hot reset is initiated globally to downstream ports, each downstream port sends a hot-reset
message to its link partner prior to being reset. Unlike a globally initiated hot reset to the entire device, a
globally initiated hot reset to downstream ports does not affect the state of the upstream port’s configuration
register except those required to update port status.

Locally Initiated Hot Reset to a Downstream Port

A hot reset is initiated locally to a downstream port by writing to the SRESET bit of a downstream port’s
BCTRL registers. When this occurs, a hot-reset message is sent on that port to its link partner. After the
message is sent, the phy layer is effectively reset.

A locally initiated hot reset does not affect the state of any port (i.e., transparent bridge) configuration
register except those required to update port status.

Non-Transparent Mode Reset

Fundamental and hot resets may be initiated on both the internal side and external sides of the non­transparent bridge. Associated with each side of the non-transparent bridge are control and status registers
(NTBCTL and NTBSTS) that aid in the handling of hot and fundamental resets in non-transparent modes.

The Reset Action Enable (RAEN) bit in the PCIE_NTBCTL register together with the Reset Action (RA)
field in that register allow a side (internal or external) of the non-transparent bridge to become “not ready”
when a reset is detected on the opposite side of the non-transparent bridge. This allows a root on one side
of the non-transparent bridge to configure the system before transactions are accepted on the opposite side
of the non-transparent bridge.

Internal Side Fundamental Reset

In non-transparent mode, a fundamental reset from the internal side operates as described in section
Fundamental Reset on page 2-7. An internal side fundamental reset resets all logic in the device including
both sides of the non-transparent bridge.

In addition to performing the actions outlined in that section, an internal side fundamental reset causes
the Opposite Side Mode (OSMODE) field in the PCIE_NTBCTL register to be set to opposite side not
ready. This disables accesses from the external side until the internal side root complex has configured the
non-transparent bridge.

If a system designer wishes to have the external side root complex initialize the non-transparent bridge,
then this can be achieved by initializing the state of the PCIE_NTBCTL and PCEE_NTBCTL registers via
the serial EEPROM.

External Side Fundamental Reset

An external side fundamental reset is initiated when the switch is configured to operate in non-trans­parent mode and the PCI Express Non-Transparent Bridge Reset (PENTBRSTN) signal is asserted.

Assertion of the non-transparent bridge fundamental reset (PENTBRSTN) signal when the device is
configured to operate in non-transparent mode and the Propagate External Fundamental Reset (PEFR) bit
is set in the NTBCTL register of the internal or external side of the non-transparent bridge results in a funda-

PES16NT2 User Manual 2 - 9 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

Notes

mental reset of the entire device and behaves in the same manner as an internal side fundamental reset
(see section Fundamental Reset on page 2-7). Otherwise, an external side fundament reset results in the
following.

– The resetting of the transaction, data link and phy layers associated with the external side of the

non-transparent bridge.

– The initialization of all registers associated with the external side of the non-transparent bridge are

set to their initial values except those with a read and write when unlocked (RWL) attribute and
those associated with the non-transparent bridge configuration capability structure.

– If the Reset Action Enable (RAEN) bit is set in the PCIE_NTBCTL register, then the action speci-

fied by the Reset Action (RA) field in that register is performed. This can result in the internal or
external side of the non-transparent bridge becoming not ready and may be used by the system
designer to block accesses until configuration of the non-transparent bridge has been performed
by the internal or external root.

– The Opposite Side Reset Detected (OSRD) bit is set in the PCIE_INTSTS register and an interrupt

or MSI is generated if enabled and selected by the PCIE_INTCTL0 register.

– The Opposite Side Fundamental Reset Detected (OSFRD) bit is set in the PCIE_NTBSTS

register.

– The PES16NT2 provides a reset output signal for each downstream port implemented as a GPIO

alternate function. The downstream port C reset output (PECRSTN) signal is an alternate function
of GPIO[1]. When an external side fundamental reset occurs, the corresponding port reset output
is asserted for at least 250 ns if the Non-Transparent Bridge Reset Output Select (NTBROS) field
in the PA_SWCTL register is set to external reset. When an internal global hot reset occurs, all of
the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A
system designer should use a pull-down on these signals if they are used as reset outputs.

Internal Side Hot Reset

An internal side hot reset is initiated when any of the following conditions occur:

– Reception of TS1 ordered-sets on the upstream port indicating a hot reset.
– Data link layer of the upstream port transitions to the DL_Down state.
– A one is written to the Reset (RST) bit in the Port C Bridge Control Register (NTBCTL).
– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (port A) Bridge

Control Register (BCTRL).

An internal side hot-reset results in the following:

– All of the logic associated with the internal and external sides of the non-transparent bridge is

reset.

– The initialization of all registers associated with the internal and external sides of the non-trans-

parent bridge to their initial values except those denoted as sticky, those with a read and write
when unlocked (RWL) attribute, and those associated with the non-transparent bridge configura­tion capability structure.

– The Reset Action Enable (RAEN) bit and the Reset Action field in the PCEE_NTBCTL register are

hardwired to zero since the external side of the NTB is also reset.

– The Opposite Side Reset Detected (OSRD) bit is set in the PCEE_INTSTS register. The OSRD

bit is preserved across a hot reset since registers in the non-transparent bridge configuration
capability structure are not reset.

– The Opposite Side Hot Reset Detected (OSHRD) bit is set in the PCEE_NTBSTS register. The

OSHRD bit is sticky and thus preserved across a hot reset.

– The PES16NT2 provides a reset output signal for each downstream port implemented as a GPIO

alternate function. The downstream port C reset output (PECRSTN) signal is an alternate function
of GPIO[1]. When an internal side hot reset occurs, the corresponding port reset output is
asserted1 for 250ns.

External Side Hot Reset

An external side hot reset is initiated when the following condition occurs:

1.

Since the PExRSTN signals are active low, the signal should be driven low for 250ns.

PES16NT2 User Manual 2 - 10 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

Notes

Reception of TS1 ordered-sets on the external side on the non-transparent bridge port indicating a hot
reset.

The handling of an external side hot reset mirrors that of an external side fundament reset.

An external side hot-reset results in the following:

– All of the logic associated with the external side of the non-transparent bridge is reset except for

the PLL and SerDes

– The initialization of all registers associated with the external side of the non-transparent bridge to

their initial values except those denoted as sticky, those with a read and write when unlocked
(RWL) attribute, sticky attribute, and those associated with the non-transparent bridge configura­tion capability structure.

– If the Reset Action Enable (RAEN) bit is set in the PCIE_NTBCTL register, then the action speci-

fied by the Reset Action (RA) field in that register is performed. This can result in the internal or
external side of the non-transparent bridge becoming not ready and may be used by the system
designer to block accesses until configuration of the non-transparent bridge has been performed
by the internal or external root.

– The Opposite Side Reset Detected (OSRD) bit is set in the PCIE_INTSTS register and an interrupt

or MSI is generated if enabled and selected by the PCIE_INTCTL0 register.

– The Opposite Side Hot Reset Detected (OSHRD) bit is set in the PCIE_NTBSTS register.
– The PES16NT2 provides a reset output signal for each downstream port implemented as a GPIO

alternate function. The downstream port C reset output (PECRSTN) signal is an alternate function
of GPIO[1]. When an external side hot reset occurs, the corresponding port reset output is
asserted

1

for 250ns if the Non-Transparent Bridge Reset Output Select (NTBROS) field in the

PA_SWCTL register is set to external reset.

1.

Since the PECRSTN signals are active low, the signal should be driven low for 250ns.

PES16NT2 User Manual 2 - 11 April 15, 2008

IDT Clocking, Reset, and Initialization Clock Operation

Notes

PES16NT2 User Manual 2 - 12 April 15, 2008

Chapter 3

Link Operation

®

Notes

Introduction

The PES16NT2 contains two ports. The default link width of each port is x8 and the SerDes lanes are
statically assigned to a port.

Polarity Inversion

Each port of the PES16NT2 supports automatic polarity inversion as required by the PCIe® specifica­tion. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its
data. During link training, the receiver examines symbols six through 16 of the TS1 and TS2 ordered sets
for inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receiving
lane automatically inverts received data.

Polarity inversion is a lane and not a link function. Therefore, it is possible for some lanes of link to be
inverted and for others to not be inverted.

Link Width Negotiation

The PES16NT2 supports the option link variable width negotiation feature outlined in the PCIe specifica­tion. During link training, each of the x8 ports is capable of negotiating to a x8, x4, x2 or x1 link width. The
negotiated width of each link may be determined from the Link Width (LW) field in the corresponding port’s
PCI Express® Link Status (PCIELSTS) register.

The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCAP)
register contains the maximum link width of the port. This field is of RWL type and may be modified when
the REGUNLOCK bit is set in the PA_SWCTL register. Modification of this field allows the maximum link
width of the port to be configured. The new link width takes effect the next time link training occurs.

To force a link width to x4 despite a link partner’s ability to negotiate to x8, the MAXLNKWDTH field
could be configured through Serial EEPROM initialization and link retraining forced. Assuming the link
partner has a link width greater than or equal to x4 and the capability to negotiate to a width of x4, the link
width will negotiate to x4.

Lanes associated with a x8 link are partitioned into two groups of four lanes.When a link negotiates to a
width less than x8, then the unused group of four lanes are powered down to save power. In addition,
unused SerDes in a four lane group are put in a low power state (i.e. L1 state).

Lane Reversal

The PCIe specification describes an optional lane reversal feature. The PES16NT2 does not support the
automatic lane reversal feature outlined in the PCIe specification. However, it does support static lane
reversal on a per port basis.

Associated with each PES16NT2 switch port is a lane reversal signal. The lane reversal signal for port A
is PEALREV and for port C is PECLREV. The status of the lane reversal signals sampled during a funda­mental reset may be determined from the PALREV and PCLREV fields in the PA_SWSTS register.

The port lane reversal signals are sampled during a fundamental reset and used as the initial value of
the PALREV and PCLREV fields in the PA_SWCTL register. When these bits are set, then the lanes of the
corresponding port(s) are reversed during link training. Lane reversal mapping for the various non-trivial
maximum link width configurations is illustrated in Figures 3.1 through 3.3.

PES16NT2 User Manual 3 - 1 April 15, 2008

IDT Link Operation

Notes

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(a) x8 Port with PExLREV negated

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(c) x4 Port with PExLREV negated

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(e) x2 Port with PExLREV negated

lane 0
lane 1
lane 2
lane 3
lane 4
lane 5
lane 6
lane 7

lane 0
lane 1
lane 2
lane 3

lane 0
lane 1

PES16NT2

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

lane 7
lane 6
lane 5
lane 4
lane 3
lane 2
lane 1
lane 0

(b) x8 Port with PExLREV asserted

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

lane 3
lane 2
lane 1
lane 0

(d) x4 Port with PExLREV asserted

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

lane 1
lane 0

(f) x2 Port with PExLREV asserted

lane 0

PES16NT2

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(g) x1 Port with PExLREV negated

PES16NT2

(h) x1 Port with PExLREV asserted

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

lane 0

Figure 3.1 Lane Reversal for Maximum Link Width of x8

PES16NT2 User Manual 3 - 2 April 15, 2008

IDT Link Operation

Notes

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(a) x4 Port with PExLREV negated

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(c) x2 Port with PExLREV negated

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(e) x1 Port with PExLREV negated

lane 0
lane 1
lane 2
lane 3

lane 0
lane 1

lane 0

PES16NT2

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

lane 3
lane 2
lane 1
lane 0

(b) x4 Port with PExLREV asserted

PExRP[0]
PExRP[1]

PES16NT2

PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

lane 1
lane 0

(d) x2 Port with PExLREV asserted

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

lane 0

(f) x1 Port with PExLREV asserted

Figure 3.2 Lane Reversal for Maximum Link Width of x4

PES16NT2 User Manual 3 - 3 April 15, 2008

IDT Link Operation

Notes

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(a) x2 Port with PExLREV negated

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(c) x1 Port with PExLREV negated

lane 0
lane 1

lane 0

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(b) x2 Port with PExLREV asserted

PExRP[0]
PExRP[1]
PExRP[2]

PES16NT2

PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]

(d) x1 Port with PExLREV asserted

lane 1
lane 0

lane 0

Figure 3.3 Lane Reversal for Maximum Link Width of x2

When link training occurs, the corresponding lane reversal bits in the P A_SWCTL register are examined.
If a bit is set, then the lanes associated with that link are reversed. This mechanism may be used to
configure lane reversal via the serial EEPROM, slave SMBus, or root.

Link Retraining

Link retraining should not cause either a downstream component or an upstream component to reset or
revert to default values.

Link Down

When a link goes down, all TLPs received by the port and queued in the switch are discarded and all
TLPs received by other ports and destined to the port whose link is down are treated as Unsupported
Requests (UR). While a link is down, it is possible to perform configuration read and write operations to the
PCI-PCI bridge associated with the link. However, it is possible to lose configuration read or write comple-

tions when TLPs queued in the switch are discarded.

1

If this occurs, the root’s completion timer associated
with the transaction(s) will time-out and the transaction will be retired. When a link comes up, flow control
credits for the configured size of the IFB FIFOs are advertised.

Slot Power Limit Support

The Set_Slot_Power_Limit message is used to convey a slot power limit value from the downstream
switch port (port C) to the upstream port of a connected device or switch. A Set_Slot_Power_Limit message
is set by downstream switch ports when either of the following events occurs:

– A configuration write is performed to the corresponding PCIESCAP register when the link associ-

ated with the downstream port is up.

– A link associated with the downstream port transitions from a non-operational state to an opera-

tional (i.e., up) state.

1.

In the case of a configuration write that causes link retraining or a secondary bus reset, a completion corre-

sponding to the configuration write is always returned and never lost.

PES16NT2 User Manual 3 - 4 April 15, 2008

IDT Link Operation

Notes

Crosslink

Port A is an upstream port and only supports link training with a downstream port. Port C is an upstream
port that supports crosslink operation. This allows port C to link train and operate with any standard PCIe
upstream or downstream port. This feature enables the NTB port (i.e., port C) of two interconnected
PES16NT2 switches to link train and operate.

Link Status

Associated with each port is a Port Link Up (PxLINKUPN) status output. These outputs are provided on
GPIO alternate functions. The PxLINKUPN status outputs may be used to provide a visual indication of
system state, for error recovery or for debug. The PxLINKUPN output is asserted when the PCI Express
data link layer is up (i.e., when the LTSSM is in the L0, L0s, L1 or recovery states). When the data link layer
is down, this output is negated.

An interrupt may be generated by the external or internal NTB endpoints when a change occurs in link
status of any of the switch ports. Change in switch port link status may be selectively reported as an inter­rupt (INTx or MSI) in the internal NTB domain, external NTB domain, or both.

Associated with each switch port are two status bits in the internal and external NTB endpoint INTSTS
registers. When the data link layer associated with a switch port transitions from a DL_Down state to a
DL_Up state, the corresponding PxLINKUP bit is set. When the data link layer associated with a switch port
transitions from a DL_Up state to a DL_Down state, the corresponding PxLINKDN bit is set. The interrupt
action (i.e., no action, INTx or MSI) taken when one of these bits is set is determined by the corresponding
field in the associated NTB endpoint’s INTCTL1 register.

PES16NT2 User Manual 3 - 5 April 15, 2008

IDT Link Operation

Notes

PES16NT2 User Manual 3 - 6 April 15, 2008

Chapter 4

Switch Operation

®

Notes

Introduction

The PES16NT2 utilizes an input buffered cut-through switch to forward PCIe® TLPs between switch
ports. At a high level the switch may be viewed as consisting of three PCIe stacks and a switch core. The
PCIe stacks are each responsible for performing the per port Phy, data link and transaction layer functions
defined in the PCIe specification. The switch core is responsible for maintaining routing information in route
map tables, maintaining per port ingress and egress flow control information, buffering TLPs, and
forwarding TLPs between stacks.

The buffering and data flow of the switch is graphically depicted in Figure 4.1 below. Note that an ingress
stack can transfer a TLP to its own egress stack through the switch core. This path is necessary since all
transactions in the PES16NT2 are routed through the switch core, even those that could be satisfied locally,
due to the fact that the switch core is responsible for maintaining flow control information.

Port A

Link

Input

Port C

Link

Input

Port A Stack

Ingress Functions

Port C Stack

Ingress Functions

Posted FIFO

Non-Posted FIFO

Completion FIFO

Posted FIFO

Non-Posted FIFO

Completion FIFO

Port A Stack

Egress Functions

Replay Buffer

Port C Stack

Egress Functions

Replay Buffer

Port A

Link

Output

Port C

Link

Output

Figure 4.1 PES16NT2 Switch Data Flow and Buffering

TLPs are received by a port stack and passed to the switch core. Associated with each port in the switch
core are three input buffers: One for posted transactions, one for non-posted transactions and one for
completions. The size of each of these buffers is shown in T able 4.1. Associated with each TLP in a buf fer is
a descriptor. Thus, a buffer has a limitation on the total number of TLPs that can be stored a s well as on the
number of bytes.

Buffer Size and Limitations

Posted FIFO 4 KB and up to 32 TLPs

Non-posted FIFO 1 KB and up to 32 TLPs

Completions FIFO 4 KB and up to 32 TLPs

Egress Stack Replay Buffer

1.

Stored with each TLP is a 32-bit LCRC as well as other information.

PES16NT2 User Manual 4 - 1 April 15, 2008

1

5120 bytes and up to 15 TLPs

Table 4.1 PES16NT2 Buffer Sizes

IDT Switch Operation

Notes

A flow control mechanism exists between the switch buffers and the transaction layer in the ingress
stack to prevent overflows. This flow control mechanism forms the basis of the PCIe flow control credits
advertised by the stack to the ingress port’s link partner. When a TLP is sent to the switch core from an
ingress stack, its header is looked-up in a routing map table and the TLP is queued in a buffer that corre­sponds to the TLP type (i.e., posted, non-posted or completion).

Scheduling of a TLP to be forwarded from an input buffer to an egress stack is performed by an egress
scheduler and port arbiter associated with each egress stack. Thus, the PES16NT2 has three egress
schedulers and three port arbiters. A flow control mechanism exists between the egress scheduler and the
transaction layer in the egress stack. This flow control mechanism ensures that only TLPs which may be
accepted by the egress stack’s link partner are forwarded through the switch.

TLPs are routed in a cut-through manner through the PES16NT2 if the ingress link width is greater than
or equal to the egress link width. If the ingress link width is less than the egress link width, then the entire
TLP must be received before it is forwarded. The egress scheduler selects the TLP from each ingress port
that may be forwarded to the associated egress port. If multiple ingress ports have TLPs which may be
forwarded to the same egress port, the port scheduler selects the ingress port from which a TLP is
forwarded.

Associated with each TLP in an input buffer is a timestamp. An egress scheduler always selects the TLP
in the input buffer that contains the oldest timestamp. If that TLP is destined for a different egress port, then
the egress scheduler makes no selection for that input port (i.e., TLPs are always forwarded from an
ingress port in chronological order). TLP timestamps are also used to discard any TLP from the head of an
input buffer that is more than 50 ms old. See section Switch Time-Outs on page 4-5 for additional details.

In making its selection, the egress scheduler considers the PCIe ordering rules. The PES16NT2
supports relaxed ordering for requests as well as completions. When the Disable Relaxed Ordering (DRO)
bit is set in the port A Switch Control (SWCTL) register, the switch strongly orders all transactions regard­less of the state of the relaxed ordering bit in TLPs.

The port scheduler associated with each egress port in the PES16NT2 supports hardwired round robin
and weighted round robin with 32 phases. Both of these algorithms only arbitrate TLP requests and do not
consider bandwidth consumption.

In addition to the input buffers in the switch core, each egress stack contains a replay FIFO. When the
replay buffer fills, backpressure is provided to the switch core and no TLPs are forwarded to that egress
port. Table 4.2 enumerates the default flow control credits advertised by each port of the switch core.

Flow Control

Category

Posted Header 30 credits Each credit represents 20 bytes (i.e., 5 doublewords) for a max-

Posted Data 204 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-

Non-Posted Header 30 credits Each credit represents 20 bytes (i.e., 5 doublewords) for a max-

Default

Advertised

Credits

imum of 600 bytes

imum of 3264 bytes

imum of 600 bytes

Table 4.2 PES16NT2 Advertised Flow Control Credits

Notes

PES16NT2 User Manual 4 - 2 April 15, 2008

IDT Switch Operation

Notes

Flow Control

Category

Non-Posted Data 30 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-

Completion Header 30 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-

Completion Data 204 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-

Default

Advertised

Credits

imum of 480 bytes (note that non-posted data is assumed to
consists of only one doubleword per header)

imum of 480 bytes

imum of 3264 bytes

Table 4.2 PES16NT2 Advertised Flow Control Credits

Notes

Each header credit is allocated 20 bytes (3 double doublewords) in a FIFO regardless of whether or not
a credit represents 16 or 20 bytes. Each posted and completion data credit is allocated 16 bytes (2 double
doublewords) in a FIFO. Non-posted data credits are allocated 8 bytes (one double doubleword). Two
header and data credits are reserved in each FIFO for TLPs generated by the switch (e.g., configuration
read completions).

The header and data flow control credits advertised may be configured on a per port basis via the Flow
Control Credit Posted Configuration (FCPTCFG), Flow Control Credit Non-Posted Configuration
(FCNPCFG) and Flow Control Credit Completion Configuration (FCCPCFG) registers. These registers may
only be modified using the serial EEPROM or during initialization via the SMBus when the RSTHALT bit is
set in the PA_SWCTL register. Modifying these registers in a running system produces undefined results.

Routing

The PES16NT2 supports routing of all transaction types defined in the PCIe specification. This includes
routing using in specification defined transactions as well as those that may be used in vendor defined
messages and in future revisions of the PCIe specifications.

Specifically, the PES16NT2 supports the following type of routing:

– Address routing with 32-bit or 64-bit format
– ID based routing using bus, device and function numbers.
– Implicit routing utilizing

Route to root
Broadcast from root
Local - terminate at receiver
Gathered and routed to root

– A summary of TLP types that use the above routing methods is provided in Table 4.3.

Routing Method TLP Type Using Routing Method

Route by Address MRd, MrdLk, MWr, IORd, IOWr, Msg, MsgD
ID Based Routing CfgRd0, CfgWr0, CfgRd1, CfgWr1, Cpl, CpdD, CplLk, CplDLk,

Msg, MsgD

Imlicit Routing - Route to Root Msg, MsgD

Table 4.3 Switch Routing Methods

PES16NT2 User Manual 4 - 3 April 15, 2008

IDT Switch Operation

Notes

Routing Method TLP Type Using Routing Method

Implicit Routing - Broadcast from Root1Msg, MsgD
Implicit Routing - Local Msg, MsgD
Implicit Routing - Gathered and Routed to

Root

1.

Broadcast from root messages are only accepted from the root port (i.e., port A). An unsup ported reques t is gene rated

if a TLP with this routing method is received from any other port.

Only supported for PME_TO_Ack messages in response to a
root initiated PME_Turn_Off message.

Table 4.3 Switch Routing Methods

Data Integrity

PCI Express® provides reliable hop-by-hop communication between interconnected devices, such as
roots, switches, and endpoints, by utilizing a 32-bit Link CRC (LCRC), sequence numbers, and a link level
retransmission protocol. While this mechanism provides reliable communication between interconnected
devices, it does not protect against corruption that may occur inside of a device. PCI Express defines an
optional end-to-end data integrity mechanism that consists of appending a 32-bit end-to-end CRC (ECRC)
computed at the source over the invariant fields of a Transaction Layer Packet (TLP) that is checked at the
ultimate destination of the TLP. While this mechanism provides end-to-end error detection, unfortunately it
is an optional PCI Express feature and has not been implemented in some North bridges and endpoints. In
addition, the ECRC mechanism does not cover variant fields within a TLP.

Since deep sub-micron devices are known to be susceptible to single-event-upsets, a mechanism is
desired that detects errors that occur within a PCI express switch. The PES16NT2 parity protects all TLPs
in the switch, thus enabling corruption that may occur inside of the device to be detected and reported even

in systems that do not implement ECRC.

Associated with each port of the PES16NT2 is a PCI-PCI bridge. Located in the switch integrity region in
extended configuration space of each PCI-PCI bridge are the Switch System Integrity Control (SWSICTL)
and Switch System Integrity Parity Error Count (SWSIPECNT) registers. These registers provide control
and status over switch errors associated with that switch port and may be read by a root or via the slave
SMBus interface.

Data flowing into the PES16NT2 is protected by the LCRC. Within the Data Link (DL) layer of the switch
ingress port, the LCRC is checked and 32-bit Doubleword (DWord) even parity is computed on the received
TLP data. If an LCRC error is detected at this point, the link level retransmission protocol is used to recover
from the error by forcing a retransmission by the link partner. As the TLP flows through the switch, its align­ment or contents may be modified. In all such cases, parity is updated and not recomputed. Hence, any
error that occurs is propagated and not masked by a parity regeneration. When the TLP reaches the DL
layer of the switch egress port, parity is checked and in parallel a LCRC is computed. If the TLP is parity
error free, then the LCRC and TLP contents are known to be correct and the LCRC is used to protect the
packet through the lower portion of the DL layer, PHY layer, and link transmission.

1

If a parity error is detected by the DL layer of an egress port, then the TLP is nullified by inverting the
computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by the link-partner are
discarded. In addition to nullifying the TLP, the PES16NT2 performs the following when a parity error is
detected: sends an error non-fatal (ERR_NONF AT AL) message (if this message reporting is enabled) to the
root; increments the End-to-End Parity Error Count (EEPERRC) field in the SWSIPECNT register associ­ated with the port on which the error was detected; and sets the Detected Parity Error (DPE) bit in the
PCISTS register if the error was detected by a downstream port or sets DPE bit in the PCI Secondary
Status (SECSTS) register if the error was detected by an upstream port.

1.

Nullified TLPs are not parity protected and no parity errors are reported for nullified TLPs since these TLPs are

discarded.

PES16NT2 User Manual 4 - 4 April 15, 2008

IDT Switch Operation

Notes

To prevent error flooding, error messages are not sent to the root once the EEPERRC field saturates.
Since PCI Express switches do not normally generate ERR_NONFATAL messages, the Silent End-to-End
Parity Checking bit (SEEPC) bit in the SWSICTL register is provided to disable generation of error
messages and setting of the Detected Parity Error bit when internal corruption is detected.

The default state of the switch following a fundamental reset is to enable this error reporting. (Note that
the Device Control register in the PCI Express capability structure also has a bit that enables generation of
ERR_NONFATAL messages and that the default value of this bit is to disable these messages.)

In addition to TLPs that flow through the switch, cases exist in which TLPs are produced and consumed
by the switch (e.g., a configuration requests and responses). Whenever a TLP is produced by the switch,
parity is computed as the TLP is generated. Thus, error protection is provided on produced TLPs as they
flow through the switch. In addition, parity is checked on all consumed TLPs. If an error is detected, the TLP
is discarded and an error is reported using the mechanism described above.

This means that a parity error reported at a switch port cannot be definitively used to identify the location
at which the error occurred as the error may have occurred when parity as generated at another port, in the
switch core, or may have been generated locally (i.e., for ingress TLPs to the switch core which are
consumed by the port such as Type 0 configuration read requests on the root port).

Switch Time-Outs

The switch discards any TLP that reaches the head of an input buffer and is more than 50ms old. For
non-posted and completion TLPs, the requester’s completion time-out mechanism will detect discarded
TLPs. No similar mechanism exists in PCIe for posted TLPs. Therefore, whenever a posted TLP is
discarded by the switch due to a time-out, an error non-fatal (ERR_NONFATAL) message (if this message
reporting is enabled) is sent to the root.

Whenever a TLP is discarded from a posted input buffer, the Posted TLP Time-out Count (PTLPTOC)
field is incremented in the Switch System Integrity Time-Out Drop Count (SWSITDCNT) register in the port
on which the TLP was received. This is a saturating counter that is automatically cleared when read. When­ever a TLP is discarded from a non-posted input buffer, the Non-Posted TLP Time-out Count (NPTLPTOC)
field is incremented in this register and whenever a TLP is discarded from a completion input buffer, the
Completion TLP Time-out Count (NPTLPTOC) field is incremented.

To prevent error flooding, error messages are not sent to the root once the PTLPT OC counter saturates.
Since PCI Express switches do not normally generate ERR_NONFATAL messages, the Silent Posted TLP
Time-out (SPTLPTO) bit in the SWSICTL register is provided to disable generation of error non-fatal
messages. When this bit is set, ERR_NONFATAL messages are not generated when posted transactions
received on the corresponding port are discarded. The PTLPTOC field however is always updated.

Interrupts

The PES16NT2 supports legacy PCI INTx emulation where x is A, B, C or D. Rather than use sideband
INTx signals, PCIe defines two messages that indicate the assertion and negation of an interrupt signal. An
Assert_INTx message is used to signal the assertion of an interrupt signal and an Deassert_INTx message
is used to signal its negation.

The PES16NT2 maintains an aggregated INTx state for each of the four interrupt signals (i.e., A through
D). The value of the INTA, INTB, INTC, and INTD aggregated state may be determined by examining the
corresponding fields in the PA_SWSTS register. The aggregated INTx state of each port for each of the four
interrupt signals (i.e., A through D) on the primary side of its PCI to PCI bridge may be determined by exam­ining the state of the INTA, INTB, INTC, and INTD fields in the corresponding port’s Interrupt Status
(PA_INTSTS and PC_INTSTS) register.

An Assert_INTx message is sent to the root by the upstream port (i.e., port A), when the aggregated
state of the corresponding interrupt in the switch transitions from a negated to an asserted state. A
Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the corre­sponding interrupt transitions from an asserted to a negated state.

PES16NT2 User Manual 4 - 5 April 15, 2008

IDT Switch Operation

Notes

Table 4.4 exhibits the interrupt sources that are aggregated by the switch.

PCI Compatible

INTx

INTA - External downstream port C (in transparent mode)

- Non-transparent bridge internal endpoint

INTB - External downstream port C (in transparent mode)

- Non-transparent bridge internal endpoint

INTC - External downstream port C (in transparent mode)

- Non-transparent bridge internal endpoint

INTD - External downstream port C (in transparent mode)

- Non-transparent bridge internal endpoint

Table 4.4 PCI Compatible INTx Aggregation

Interrupt Sources

PCI to PCI bridges must map interrupts on the secondary side of the bridge according to the device
number of the device on the secondary side of the bridge. No mapping is performed for the PCI to PCI
bridges corresponding to downstream ports as these ports only connect to device zero. A mapping is
performed for the upstream port (i.e., port A).This mapping is summarized in Table 4.6 for the PES16NT2.

Port A Interrupt Interrupt Sources

1

INTA Port C INTD
INTB Port C INTA
INTC Port C INTB
INTD Port C INTC

Table 4.5 PES16NT2 Upstream Port Bridge Interrupt Mapping

1.

Port X INTy corresponds to external downstream genera te d INTy interrup ts or I NTy in-

terrupts generated by the internal side of the non-transparent bridge (o nly for port C).

Assert_INTx and Deassert_INTx messages may also be generated by the non-transparent bridge
external endpoint when the switch is configured to operate in non-transparent mode. These interrupt
messages are transmitted out on port C, as that is the direction of the root for the non-transparent bridge
external endpoint.

If a Downstream Port goes to DL_Down status, the INTx virtual wires associated with that port are deas­serted, and the port A aggregates are updated accordingly. This may result in the upstream port generating
a Deassert_Intx message.

Switch Core Errors

This section lists error conditions that are checked by the switch core. Due to limited buffering of Unsup­ported Request (UR) completions, it is possible for the PES16NT2 to discard UR completions if errors are
generated faster than UR completions can be transmitted. Even when UR completions are discarded, error
status bits are always correctly updated and an error message is generated.

Due to limited buffering, error messages may be collapsed if errors are generated faster than error
messages can be transmitted. This means that multiple error conditions may result in only a single error
message being generated. However, under no circumstances are error messages discarded.

PES16NT2 User Manual 4 - 6 April 15, 2008

IDT Switch Operation

Notes

Port arbitration should never be configured to starve a port. If a port arbitration table configuration
results in port starvation, then TLPs generated by the port may be dropped (e.g., error messages, inter­rupts, configuration completions, etc.).

The following events received by the switch core from the upstream port are treated as Unsupported
Requests (UR), and for non-posted transactions, result in a Unsupported Request (UR) completion being
returned to the upstream port.

– Reception of a CfgRd0 or CfgWr0 TLP. All CfgRd0 and CfgWr0 TLPs should have been received

and processed by the upstream stack. Therefore, the upstream stack should never pass a CfgRd0
or CfgWr0 to the switch core.

– Reception of a CfgRd1 or CfgWr1 TLP that is transformed into a CfgRd0 or CfgW r0 TLP destined

to the link partner of a downstream port and in which the device number is non-zero (covers condi­tion outlined in PCIe base 1.0a Section 7.3.1). The device number must be zero in CfgRd0 and
CfgWr0 transactions to a downstream link partner.

– Reception of Msg or MsgD TLPs with route by address routing prior to initialization of the PCI-PCI

bridge. Prior to initialization of the PCI-PCI bridge, no transactions should be routed to the switch
core.

– Reception of route by address TLPs whose address matches an upstream port’s memory or I/O

base/limit pair and does not match a downstream ports’ memory or I/O base/limit pair. TLPs that
have no route (i.e., not destined for any upstream or downstream port) should be treated as
unsupported requests.

– Reception of route by address TLPs destined to the upstream port. There are no route by address

TLPs that should have been destined to the upstream port since the upstream port does not
process these types of TLPs.

– Reception of TLPs that have no route (i.e., do not match an address or ID route through the

switch). TLPs that have no route should be treated as unsupported requests.

– Reception of a TLP destined to a disabled downstream port (link down or MAE/IOAE bit cleared

in PA_PCICMD register). TLPs destined to a disabled downstream port should be treated as
unsupported requests.

– Reception of a TLP that matches a VGA region and the VGA Enable (VGAEN) bit is set in the

upstream port but the TLP does not map to either downstream port (i.e., VGAEN is cleared in both
downstream ports and the transaction does not map to any of the base/limit pairs associated with
the downstream ports).

The following events received by the switch core from the downstream ports are treated as Unsupported
Requests (UR) and for non-posted transactions, result in a Unsupported Request (UR) completion to be
returned to the port on which the TLP was received.

– Reception of Msg or MsgD TLPs with route by address routing prior to initialization of the PCI-PCI

bridge. Prior to initialization of the PCI-PCI bridge, no transactions should be routed to the switch
core.

– Reception of Msg or MsgD TLPs with route by ID to the PCI-PCI bridge primary bus number after

bus enumeration has completed. There are no entities that generate accept messages on the
virtual PCI bus within the switch (i.e., the primary bus number).

– Reception of route by address TLPs whose address matches an upstream port’s memory or I/O

base/limit pair and does not match a downstream ports’ memory or I/O base/limit pair. TLPs that
have no route (i.e., not destined for any upstream or downstream port) should be treated as
unsupported requests.

– Reception of TLPs that have no route (i.e., do not match an address or ID route through the

switch). TLPs that have no route should be treated as unsupported requests.

– Reception of any configuration TLP. Configuration requests can only be generated by the root and

received on the upstream port in either mode or external endpoint of the non-transparent bridge
in non-transparent mode.

– Reception of a route by ID TLP to a port that has its primary bus number set to its secondary bus

number. Such a port is uninitialized.

– Reception of a TLP that utilizes implicit routing - broadcast from root. Such a TLP can only be

received by the upstream port.

PES16NT2 User Manual 4 - 7 April 15, 2008

IDT Switch Operation

Notes

– Reception of a TLP that matches a VGA region in a downstream port when the downstream port’s

VGA Enable (VGAEN) bit is set in its Bridge Control (BCTRL) register.

– Reception of a TLP destined to a disabled downstream port (link down or MAE/IOAE bit cleared

in PCICMD register) or the upstream port when the Bus Master Enable (BME) bit is not set in the
PCICMD register. TLPs destined to a disabled downstream port should be treated as unsupported
requests.

PES16NT2 User Manual 4 - 8 April 15, 2008

Chapter 5

Power Management

®

Notes

Introduction

A power management capability structure is located in the configuration space of each PCI-PCI bridge
in the PES16NT2. The structure associated with a PCI-PCI bridge of a downstream port only affects that
port. Entering the D3

The power management capability structure associated with the root port (i.e., port A) affects the entire
device. When the root port enters a low power state and the PME_TO_Ack messages are received, then
the entire device is placed into a low power state. The PES16NT2 supports the following device power
management states: D0 Uninitialized, D0 Active, D3

ment state from D3
values.

A power management state transition diagram for the states supported by the PES16NT2 is provided in
Figure 5.1 and described in Table 5.1.

state allows the link associated with the bridge to enter the L1 state.

hot

hot

to D0

uninitialized

Power-On Reset

, and D3

hot

does not result in any logic being reset or re-initialization of register

D0

Uninitialized

D0

Active

. Transitioning a port’s power manage-

cold

D3

hot

D3

cold

Figure 5.1 PES16NT2 Power Management State Transition Diagram

PES16NT2 User Manual 5 - 1 April 15, 2008

IDT Power Management

Notes

From State To State Description

Any D0 Uninitialized Power-on fundamental reset.

D0 Uninitialized D0 Active PCI-PCI bridge configured by software

D0 Active D3

D3

D3

hot

hot

D0 Uninitialized The Power Management State (PMSTATE) field in the PCI Power

D3

Table 5.1 PES16NT2 Power Management State Transition Diagram

hot

cold

The Power Management State (PMSTATE) field in the PCI Power
Management Control and Status (PMCSR) register is written with
the value that corresponds to the D3

Management Control and Status (PMCSR) register is written with
the value that corresponds to D0 state.

Power is removed from the device.

hot

state.

PME Messages

The PES16NT2 does not support generation of PME messages from the D3

state or D3

hot

Link States

The PES16NT2 supports the following link states:

– L0 — Fully operational link state.
– L0s — Automatically entered low power state with shortest exit latency.
– L1 — (Port C does not support L1 ASPM).

• Lower power state than L0s.

• May be automatically entered or directed by software by placing the device in the D3

– L2/L3 Ready — The L2/L3 state is entered after the acknowledgement of a PM_Turn_Off

Message. There is no TLP or DLLP communications over a link in this state.

– L3 — Link is completely unpowered and off.

Link states are shown in Figure 5.2.

cold

state.

state.

hot

PES16NT2 User Manual 5 - 2 April 15, 2008

IDT Power Management

Notes

L0s L1

L0

L2/L3 Ready

L3

Figure 5.2 PES16NT2 ASPM Link Sate Transitions

Active State Power Management

The operation of Active State Power Management (ASPM) is orthogonal to power management. Once
enabled by the ASPM field in the PCI Express® Link Control (PCIELCTL) register, ASPM link state transi­tions are initiated by hardware without software involvement. The PES16NT2 ASPM supports the required
L0s state on both ports. The optional ASPM L1 is only supported on port A.

Note: Port C, the non-transparent port, does not support L1 ASPM.

The L0s Entry Timer (L0SET) field in the PCI Power Management Proprietary Control (PMPC) register
controls the amount of time L0s entry conditions must be met before the hardware transitions the link to the
L0s state. The L1 Entry Timer (L1SET) field in the PCI Power Management Proprietary Control (PMPC)
register controls the amount of time L1 entry conditions must be met before the hardware transitions the link
to the L1 state. If these conditions are met and the link is in the L0 or L0s states, then the hardware will
request a transition to the L1 state from its link partner. Note that L1 entry requests are only made by the
PES16NT2 upstream port. If the link partner acknowledges the transition, then the L1 state is entered.
Otherwise the L0s state is entered.

PES16NT2 User Manual 5 - 3 April 15, 2008

IDT Power Management

Notes

PES16NT2 User Manual 5 - 4 April 15, 2008

Chapter 6

SMBus Interfaces

®

Notes

Introduction

The PES16NT2 contains two SMBus interfaces. The slave SMBus interface provides full access to all
software visible registers in the PES16NT2, allowing every register in the device to be read or written by an
external SMBus master. The slave SMBus may a lso be used to initialize the serial EEPROM used for initial­ization.

Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an
SMBus data pin, and 4 SMBus address pins. As shown in Figure 6.1, the master and slave SMBuses may
be used in a unified or split configuration.

PES16NT2

SSMBCLK
SSMBDAT

MSMBCLK
MSMBDAT

Processor

SMBus
Master

Serial

EEPROM

(a) Unified Configuration

...

Other

SMBus

Devices

PES16NT2

SSMBCLK
SSMBDAT

MSMBCLK
MSMBDAT

Processor

SMBus

Master

EEPROM

...

Serial

Other

SMBus

Devices

(b) Split Configuration

Figure 6.1 SMBus Interface Configuration Examples

In the unified configuration, shown in Figure 6.1(a), the master and slave SMBuses are tied together and
the PES16NT2 acts both as an SMBus master as well as an SMBus slave on this bus. This requires that
the external SMBus master or processor that has access to PES16NT2 registers support SMBus arbitra­tion. In some systems, this external SMBus master interface may be implemented using general purpose I/
O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these
systems, the PES16NT2 may be configured to operate in a split configuration as shown in Figure 6.1(b).

PES16NT2 User Manual 6 - 1 April 15, 2008

IDT SMBus Interfaces

Notes

In the split configuration, the master and slave SMBuses operate as two independent buses and thus
multi-master arbitration is not required.

SMBus Registers

Bit

Field

0 Reserved RO 0x0 Reserved field.

7:1 SSMBADDR RO HWINIT Slave SMBus Address. This field contains the SMBus

8 Reserved RO 0x0 Reserved field.

15:9 MSMBADDR RO HWINIT Master SMBus Address. This field contains the SMBus

23:16 Reserved RO 0x0 Reserved field.

24 EEPROM-

25 NAERR RW1C 0x0 No Acknowledge Error. This bit is set if an unexpected

26 LAERR RW1C 0x0 Lost Arbitration Error. When the master SMBus inter-

Field

Name

DONE

Type

RO 0x0 Serial EEPROM Initialization Done. When the switch is

Default

Value

Description

address assigned to the slave SMBus interface.

address assigned to the master SMBus interface.

configured to operate in a mode in which serial EEPROM
initialization occurs during a fundamental reset, this bit is
set when serial EEPROM initialization completes or when
an error is detected.

NACK is observed during a master SMBus transaction.
The setting of this bit may indicate the following: that the
addressed device does not exist on the SMBus (i.e.,
addressing error); data is unavailable or the device is
busy; an invalid command was detected by the slave; or
invalid data was detected by the slave.

face loses arbitration for the SMBus, it automatically re­arbitrates for the SMBus. If the master SMBus interface
loses 16 consecutive arbitration attempts, then the trans­action is aborted and this bit is set.

27 OTHERERR RW1C 0x0 Other Error. This bit is set if a misplaced START or STOP

condition is detected by the master SMBus interface.

28 ICSERR RW1C 0x0 Initialization Checksum Error. This bit is set if an invalid

checksum is computed during Serial EEPROM initializa­tion or when a configuration done command is not found in
the serial EEPROM.

29 URIA RW1C 0x0 Unmapped Register Initialization Attempt. This bit is set

if an attempt is made to initialize via serial EEPROM a reg­ister that is not defined in the corresponding PCI configu­ration space.

31:30 Reserved RO 0x0 Reserved field.

Table 6.1 SMBUSSTS - SMBus Status

PES16NT2 User Manual 6 - 2 April 15, 2008

IDT SMBus Interfaces

Notes

Bit

Field

Field

Name

Type

Default

Value

Description

15:0 MSMBCP RW HWINIT Master SMBus Clock Prescalar. This field contains a

clock prescalar value used during master SMBus transac­tions. The prescalar clock period is equal to 32 ns multi­plied by the value in this field. When the field is cleared to
zero or one, the clock is stopped.
The initial value of this field is 0x0139 when the master
SMBus is configured to operate in slow mode (i.e., 100
KHz) in the boot configuration and to 0x0053

1

when it is

configured to operate in fast mode (i.e., 400 KHz).

16 MSMBIOM RW 0x0 Master SMBus Ignore Other Masters. When this bit is

set, the master SMBus proceeds with transactions regard­less of whether it won or lost arbitration.

17 ICHECKSUM RW 0x0 Ignore Checksu m Errors. When this bit is set, serial

EEPROM initialization checksum errors are ignored (i.e.,
the checksum always passes).

19:18 SSMBMODE RW 0x0 Slave SMBus Mode. The slave SMBus contains internal

glitch counters on the SSMBCLK and SSMBDAT signals
that wait approximately 1 µS before sampling or driving
these signals. This field allows the glitch counter time to be
reduced or entirely removed. In some systems, this may
permit high speed slave SMBus operation.
0x0 - (normal) Slave SMBus normal mode. Glitch counters

operate with 1 µS delay.

0x1 - (fast) Slave SMBus interface fast mode. Glitch

counters operate with 100 nS delay.

0x2 - (disabled) Slave SMBus interface with glitch

counters disabled. Glitch counters operate with zero
delay which effectively removes them.

0x3 - reserved.

21:20 MSMBMODE RW 0x0 Master SMBus Mode. The master SMBus contains inter-

nal glitch counters on the MSMBCLK and MSMBDAT sig­nals that wait approximately 1 µS before sampling or
driving these signals. This field allows the glitch counter
time to be reduced or entirely removed. In some systems,
this may permit high speed master SMBus operation.
0x0 - (normal) Master SMBus normal mode. Glitch

counters operate with 1 µS delay.

0x1 - (fast) Master SMBus interface fast mode. Glitch

counters operate with 100 nS delay.

0x2 - (disabled) Master SMBus interface with glitch

counters disabled. Glitch counters operate with zero
delay which effectively removes them.

0x3 - reserved.

31:22 Reserved RO 0x0 Reserved field.

1.

The MSMBCLK low minimum pulse width is equal to half the period programmed in this field. The value of 0x53, which corre­sponds to ~373 KHz, allows the min low pulse width to be satisfied. In systems where this timing parameter is not critical, the
operating frequency may be increased.

PES16NT2 User Manual 6 - 3 April 15, 2008

Table 6.2 SMBUSCTL - SMBus Control

IDT SMBus Interfaces

Notes

Master SMBus Interface

The master SMBus interface is used during a fundamental reset to load configuration values from an

optional serial EEPROM.

Initialization

Master SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
2-7). During a fundamental reset initialization sequence, the state of the Master SMBus Slow Mode
(MSMBSMODE) signal is examined. If this signal is asserted, the Master SMBus Clock Prescalar
(MSMBCP) field in the port A SMBus Control (PA_SMBUSCTL) register is initialized to support 100 KHz
SMBus operation. If the signal is negated, then the MSMBCP field is initialized for 400 KHz SMBus opera­tion.

Serial EEPROM

During a fundamental reset, an optional serial EEPROM may be used to initialize any software visible
register in the device. Serial EEPROM loading occurs if the Switch Mode (SWMODE[3:0]) field selects an
operating mode that performs serial EEPROM initialization (e.g., transparent mode with serial EEPROM
initialization and non-transparent mode with serial EEPROM initialization).

The address used by the SMBus interface to access the serial EEPROM is specified by the
MSMBADDR[4:1] signals as shown in Table 6.3.

Address

Bit

Address Bit Value

1 MSMBADDR[1]
2 MSMBADDR[2]
3 MSMBADDR[3]
4 MSMBADDR[4]
51
60
71

Table 6.3 Serial EEPROM SMBus Address

Device Initialization from a Serial EEPROM

During initialization from the optional serial EEPROM, the master SMBus interface reads configuration
blocks from the serial EEPROM and updates corresponding registers in the PES16NT2. Any PES16NT2
software visible register in the upstream port, downstream port(s), and internal side of the non-transparent
bridge may be initialized with values stored in the serial EEPROM.

Each software visible register in the PES16NT2 has a CSR system address which is formed by adding
the PCI configuration space offset value of the register to the base address of the configuration space in
which the register is located. Configuration blocks stored in the serial EEPROM use this CSR system
address shifted right two bits (i.e., configuration blocks in the serial EEPROM use doubleword CSR system
addresses and not byte CSR system addresses). Base addresses for the PCI configuration spaces in the
PES16NT2 are listed in Table 6.4. While there is no direct accesses to non-transparent bridge external
endpoint registers, these register may be initialized by using the external non-transparent bridge configura­tion window located in the configuration space of the internal non-transparent bridge endpoint.

PES16NT2 User Manual 6 - 4 April 15, 2008

IDT SMBus Interfaces

Notes

Base Address Value

PCI Configuration Space

Upstream Port A 0x0000

Downstream Port C 0x2000

Internal Non-Transparent Bridge Endpoint 0x3000

External Non-Transparent Bridge Endpoint 0x3800

Table 6.4 Base Addresses for PCI Configuration Spaces in the PES16NT2

used to form CSR

System Address

Since configuration blocks are used to store only the value of those registers that are initialized, a serial
EEPROM much smaller than the total size of all of the configuration spaces may be used to initialize the
device.

Any serial EEPROM compatible with those listed in Table 6.5 may be used to store PES16NT2 initializa­tion values. Some of these devices are larger than the total size of all of the PCI configuration spaces in the
PES16NT2 that may be initialized and thus may not be fully utilized.

Serial EEPROM Size

24C32 4 KB

24C64 8 KB
24C128 16 KB
24C256 32 KB
24C512 64 KB

Table 6.5 PES16NT2 Compatible Serial EEPROMs

During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial
EEPROM address zero. These bytes are interpreted as configuration blocks and sequential reading of the
serial EEPROM continues until the end of a configuration done block is reached or the serial EEPROM
address rolls over from 0xFFFF to 0x0.

All register initialization performed by the serial EEPROM is performed in double word quantities. There
are three configuration block types that may be stored in the serial EEPROM. The first type is a single
double word initialization sequence. A double word initialization sequence occupies six byes in the serial
EEPROM and is used to initialize a single double word quantity in the PES16NT2.

A single double word initialization sequence consists of three fields and its format is shown in Figure 6.2.
The CSR_SYSADDR field contains the double word CSR system address of the double word to be initial­ized. The actual CSR system address, which is a byte address, equals this value with two lower zero bits
appended. The next field is the TYPE field that indicates the type of the configuration block. For single
double word initialization sequence, this value is always 0x0. The final DATA field contains the double word
initialization value.

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IDT SMBus Interfaces

Notes

Bit

7

Byte 0 CSR_SYSADDR[7:0]

Byte 1

Byte 2 DATA[7:0]

Byte 3 DATA[15:8]

Byte 4 DATA[23:16]

Byte 5 DATA[31:24]

TYPE

0x0

5

6

3

4

CSR_SYSADDR[13:8]

2

0

1

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Figure 6.2 Single Double Word Initialization Sequence Format

The second type of configuration block is the sequential double word initialization sequence. It is similar
to a single double word initialization sequence except that it contains a double word count that allows
multiple sequential double words to be initialized in one configuration block.

A sequential double word initialization sequence consists of four required fields and one to 65535
double word initialization data fields. The format of a sequential double word initialization sequence is
shown in Figure 6.3. The CSR_SYSADDR field contains the starting double word CSR system address to
be initialized. The next field is the TYPE field that indicates the type of the configuration block. For sequen­tial double word initialization sequences, this value is always 0x1. The NUMDW field specifies the number
of double words initialized by the configuration block. This is followed by the number of DATA fields speci­fied in the NUMDW field.

Bit

6

7

Byte 0 CSR_SYSADDR[7:0]

Byte 1

Byte 2 NUMDW[7:0]

Byte 3 NUMDW[15:8]

Byte 4 DATA0[7:0]

Byte 5 DATA0[15:8]

Byte 6 DATA0[23:16]

Byte 7 DATA0[31:24]

TYPE

0x1

...

Byte 4n+4 DATAn[7:0]

Byte 4n+ 5 DATAn[15:8]

Byte 4n+6 DATAn[23:16]

Byte 4n+7 DATAn[31:24]

4

5

CSR_SYSADDR[13:8]

...

2

3

0

1

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Figure 6.3 Sequential Double Word Initialization Sequence Format

PES16NT2 User Manual 6 - 6 April 15, 2008

IDT SMBus Interfaces

Notes

The final type of configuration block is the configuration done sequence which is used to signify the end
of a serial EEPROM initialization sequence. If during serial EEPROM initialization, an attempt is made to
initialize a register that is not defined in a configuration space (i.e., does not appear in Table 9.5 in trans­parent mode or in Tables 10.6, 10.7, 10.7 in non-transparent mode), then the Unmapped Register Initializa­tion Attempt (URIA) bit is set in the SMBUSSTS register and the write is ignored.

The configuration done sequence consists of two fields and its format is shown in Figure 6.3. The
CHECKSUM field contains the checksum of all of the bytes in all of the fields read from the serial EEPROM
from the first configuration block to the end of this done sequence. The second field is the TYPE field which
is always 0x3 for configuration done sequences.

Bit

7

Byte 0 CHECKSUM[7:0]

Byte 1

0x3

5

6

3

4

ReservedTYPE

(must be zero)

2

0

1

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Figure 6.4 Configuration Done Sequence Format

The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa­tion to be verified. Since uninitialized EEPROMs typically have a value of all ones, initialization from an
uninitialized serial EEPROM will result in a checksum mismatch. The checksum is computed in the
following manner. An 8-bit counter is initialized to zero and the 8-bit sum is computed over the configuration
bytes stored in the serial EEPROM, including the entire contents of the configuration done sequence, with

the checksum field initialized to zero.

1

The 1’s complement of this sum is placed in the checksum field.

The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is
computed over the bytes read from the serial EEPROM, including the entire contents of the configuration

done sequence.

2

The correct result should always be 0xFF (i.e., all ones). Checksum checking may be
disabled by setting the Ignore Checksum Errors (ICHECKSUM) bit in the port A SMBus Control
(PA_SMBUSCTL) register.

If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM is
aborted and the RSTHAL T bit is set in the PA_SWCTL register. This allows debugging of the error condition
via the slave SMBus interface but prevents normal system operation with a potentially incorrectly initialized
device. Error information is recorded in the PA_SMBUSSTS register. Once serial EEPROM initialization
completes, or when an error is detected, the EEPROM Done (EEPROMDONE) bit is set in the port A
SMBus Status (PA_SMBSTS) register.

A summary of possible errors during serial EEPROM initialization and specific action taken when
detected is summarized in Table 6.6.

1.

This includes the byte containing the TYPE field.

2.

This includes the checksum byte as well as the byte that contains the type and reserved field.

PES16NT2 User Manual 6 - 7 April 15, 2008

IDT SMBus Interfaces

Notes

Error Action Taken

Configuration Done Sequence checksum
mismatch with that computed by the
PES16NT2

Serial EERPOM address roll-over from
0xFFFF to 0x0000

Invalid configuration block type
(only invalid type is 0x2)

An unexpected NACK is observed during a
master SMBus transaction

Master SMBus interface loses 16 consecu­tive arbitration attempts

A misplaced START or STOP condition is
detected by the master SMBus interface

Table 6.6 Serial EEPROM Initialization Errors

- Set RSTHALT bit in PA_SWCTL register

- ICSERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- ICSERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- ICSERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- NAERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- LAERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- OTHERERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

Programming the Serial EEPROM

The serial EEPROM may be programmed prior to board assembly or in-system via the slave SMBus
interface or a PCIe® root. Programming the serial EEPROM via the slave SMBus is described in section
Serial EEPROM Read or Write Operation on page 6-12. A PCIe root may read and write the serial
EEPROM by performing configuration read and write transactions to the port A Serial EEPROM Interface
(PA_EEPROMINTF) register.

To read a byte from the serial EEPROM, the root should configure the Address (ADDR) field in the
PA_EEPROMINTF register with the byte address of the serial EEPROM location to be read and the Opera­tion (OP) field to “read.” The Busy (BUSY) bit should then be checked. If the EEPROM is not busy, the read
operation may be initiated by performing a write to the Data (DATA) field. When the serial EEPROM read
operation completes, the Done (DONE) bit in the PA_EEPROMINTF register is set and the busy bit is
cleared. When this occurs, the DATA field contains the byte data of the value read from the serial EEPROM.

To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of
the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy
(i.e., the BUSY bit is cleared), the write operation may be initiated by writing the value to be written to the
DATA field. When the write operation completes, the DONE bit is set and the busy bit is cleared.

Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results.
SMBus errors may occur when accessing the serial EEPROM. If an error occurs, it is reported in the port A
SMBus Status (PA_SMBUSSTS) register. Software should check for errors before and after each serial
EEPROM access.

Slave SMBus Interface

The slave SMBus interface provides the PES16NT2 with a configuration, management and debug inter­face. Using the slave SMBus interface, an external master can read or write any software visible register in
the device.

PES16NT2 User Manual 6 - 8 April 15, 2008

IDT SMBus Interfaces

Notes

Initialization

Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
2-7). During the fundamental reset initialization sequence, the address is specified by the
SSMBADDR[5,3:1] signals as shown in Table 6.7.

Address

Bit

1 SSMBADDR[1]
2 SSMBADDR[2]
3 SSMBADDR[3]
40
5 SSMBADDR[5]
61
71

Table 6.7 Slave SMBus Address When a Static Address is Selected.

Address Bit Value

SMBus Transactions

The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
See the SMBus 2.0 specification for a detailed description of these transactions.

– Byte and Word Write/Read
– Block Write/Read

Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces
undefined results. Associated with each of the above transactions is a command code. The command code
format for operations supported by the slave SMBus interface is shown in Figure 6.5 and described in Table

6.8.

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

ENDSTARTFUNCTIONSIZEPEC

Figure 6.5 Slave SMBus Command Code Format

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IDT SMBus Interfaces

Notes

Bit

Field

0 END End of transaction indicator. Setting both START and END signifies a

1 START Start of transaction indicator. Setting both START and END signifies

4:2 FUNCTION This field encodes the type of SMBus operation.

6:5 SIZE This field encodes the data size of the SMBus transaction.

7 PEC This bit controls whether packet error checking is enabled for the cur-

Name Description

single transaction sequence
0 - Current transaction is not the last read or write sequence.
1 - Current transaction is the last read or write sequence.

a single transaction sequence
0 - Current transaction is not the first of a read or write sequence.
1 - Current transaction is the first of a read or write sequence.

0 - CSR register read or write operation
1 - Serial EEPROM read or write operation
2 through 7 - Reserved

0 - Byte
1 - Word
2 - Block
3 - Reserved

rent SMBus transaction.
0 - Packet error checking disabled for the current SMBus transaction.
1 - Packet error checking enabled for the current SMBus transaction.

Table 6.8 Slave SMBus Command Code Fields

The FUNCTION field in the command code indicates if the SMBus operation is a CSR register read/
write or a serial EEPROM read/write operation. Since the format of these transactions is different. They will
be described individually in the following sections.

If a command is issued while one is already in progress or if the slave is unable to supply data associ­ated with a command, the command is NACKed. This indicates to the master that the transaction should be
retried.

CSR Register Read or Write Operation

Table 6.9 indicates the sequence of data as it is presented on the slave SMBus following the byte
address of the Slave SMBus interface.

PES16NT2 User Manual 6 - 10 April 15, 2008

IDT SMBus Interfaces

Notes

Byte

Position

Field

Name Description

0 CCODE Command Code. Slave Command Code field described in Table 6.8.
1BYTCNTByte Count. The byte count field is only transmitted for block type

SMBus transactions. SMBus word and byte accesses do not contain
this field. The byte count field indicates the number of bytes following
the byte count field when performing a write or setting up for a read.
The byte count field is also used when returning data to indicate the
number of following bytes (including status). Note that the byte count

field does not include the PEC byte if PEC is enabled.

2CMDCommand. This field encodes fields related to the CSR register read

or write operation.

3 ADDRL Address Low. Lower 8-bits of the doubleword CSR system address

of register to access.

4 ADDRU Address Upper. Upper 6-bits of the doubleword CSR system

address of register to access. Bits 6 and 7 in the byte must be zero

and are ignored by the hardware.
5 DATALL Data Low Low. Bits [7:0] of data doubleword.
6 DATALM Data Low Middle. Bits [15:8] of data doubleword.
7 DATAUM Data Upper Middle. Bits [23:16] of data doubleword.
8 DATAUU Data Upper Upper. Bits [31:24] of data doubleword.

Table 6.9 CSR Register Read or Write Operation Byte Sequence

The format of the CMD field is shown in Figure 6.6 and described in Table 6.10.

Bit

7

Bit

Field

Name Type Description

0 BELL Read/Write Byte Enable Lower Lower. When set, the byte enable for bits [7:0] of

1 BELM Read/Write Byte Enable Lower Middle. When set, the byte enable for bits [15:8]

2 BEUM Read/Write Byte Enable Upper Middle. When set, the byte enable for bits

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Figure 6.6 CSR Register Read or Write CMD Field Format

the data word is enabled.

of the data word is enabled.

[23:16] of the data word is enabled.

Bit

0

BELLBELMWERR BEUMBEUUOPRERR 0

3 BEUU Read/Write Byte Enable Upper Upper. When set, the byte enable for bits [31:24]

of the data word is enabled.

Table 6.10 CSR Register Read or Write CMD Field Description (Part 1 of 2)

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IDT SMBus Interfaces

Notes

Bit

Field

Name Type Description

4 OP Read/Write CSR Operation. This field encodes the CSR operation to be per-

formed.
0 - CSR write

1 - CSR read
5 0 0 Reserved. Must be zero
6 RERR Read-Only

and Clear

Read Error. This bit is set if the last CSR read SMBus transaction was

not claimed by a device. Success indicates that the transaction was

claimed and not that the operation completed without error.
7 WERR Read-Only

and Clear

Write Error. This bit is set if the last CSR write SMBus transaction was

not claimed by a device. Success indicates that the transaction was

claimed and not that the operation completed without error.

Table 6.10 CSR Register Read or Write CMD Field Description (Part 2 of 2)

Serial EEPROM Read or Write Operation

Table 6.11 indicates the sequence of data as it is presented on the slave SMBus following the byte

address of the Slave SMBus interface.

Byte

Position

Field

Name Description

0 CCODE Command Code. Slave Command Code field described in Table 6.8.
1BYTCNTByte Count. The byte count field is only transmitted for block type

SMBus transactions. SMBus word and byte accesses do not contain
this field. The byte count field indicates the number of bytes following
the byte count field when performing a write or setting up for a read.
The byte count field is also used when returning data to indicate the
number of following bytes (including status).

2CMDCommand. This field contains information related to the serial

EEPROM transaction

3 EEADDR Serial EEPROM Address. This field specifies the address of the

Serial EEPROM on the Master SMBus when the USA bit is set in the
CMD field. Bit zero must be zero and thus the 7-bit address must be

left-justified.
4 ADDRL Address Low. Lower 8-bits of the Serial EEPROM byte to access.
5 ADDRU Address Upper. Upper 8-bits of the Serial EEPROM byte to access.
6DATAData. Serial EEPROM value read or to be written.

Table 6.11 Serial EEPROM Read or Write Operation Byte Sequence

The format of the CMD field is shown in Figure 6.7 and described in Table 6.12

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

OPUSA0 NAERRLAERROTHERERR 0

Figure 6.7 Serial EEPROM Read or Write CMD Field Format

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IDT SMBus Interfaces

Notes

Bit

Field

Name Type

1

Description

0 OP RW Serial EEPROM Operation. This field encodes the serial EEPROM

operation to be performed.
0 - Serial EEPROM write
1 - Serial EEPROM read

1USA RWUse Specified Address. When this bit is set the serial EEPROM

SMBus address specified in the EEADDR is used instead of that

specified in the MSMBADDR field in the SMBUSSTS register.
2 Reserved Reserved field.
3 NAERR RC No Acknowledge Error. This bit is set if an unexpected NACK is

observed during a master SMBus transaction when accessing the

serial EEPROM. This bit has the same function as the NAERR bit in

the PA_SMBUSSTS register.

The setting of this bit may indicate the following: that the addressed

device does not exist on the SMBus (i.e., addressing error), data is

unavailable or the device is busy, an invalid command was detected

by the slave, invalid data was detected by the slave.
4 LAERR RC Lost Arbitration Error. This bit is set if the master SMBus interface

loses 16 consecutive arbitration attempts when accessing the serial

EEPROM. This bit has the same function as the LAERR bit in the

PA_SMBUSSTS register.
5 OTHERERR RC Other Error. This bit is set if a misplaced START or STOP condition is

detected by the master SMBus interface when accessing the serial

EEPROM. This bit has the same function as the OTHERERR bit in

the PA_SMBUSSTS register.

7:6 Reserved 0 Reserved. Must be zero

Table 6.12 Serial EEPROM Read or Write CMD Field Description

1.

See Table 2 in the About section for a definition of these abbreviations.

Sample Slave SMBus Operation

This section illustrates sample Slave SMBus operations. Shaded items are driven by the PES16NT2’s

slave SMBus interface and non-shaded items are driven by an SMBus host.

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

Wr A

Wr A

Wr A

ADDRU

Figure 6.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled

A

CCODE

START,END

CCODE

START,END

CCODE

START,END

BYTCNT=3

A

(PES16NT2 not ready with data)

N

P

PES16NT2 Slave

A

S

SMBus Address

DATALMDATALL

A A P

CMD=read

A

BYTCNT=7

A

Rd

DATAUM

ADDRL

A

A A A

DATAUU

A

A

N

ADDRU

A P

ADDRLCMD (status)

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IDT SMBus Interfaces

Notes

PES16NT2 Slave

S

SMBus Address

Wr A A

CCODE

START,END

BYTCNT=4

CMD=read

A

EEADDR

A

ADDRL

A

A

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

ADDRU

ADDRL

Wr A

Wr A

A

A

P

CCODE

START,END

CCODE

START,END

(PES16NT2 not ready with data)

N

P

PES16NT2 Slave

A

S

SMBus Address

DATAADDRU

A P

N

BYTCNT=5

Rd

A

A A A

EEADDRCMD (status)

Figure 6.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC Disabled

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

Wr A

Wr A

Wr A

CCODE

START,END

CCODE

START,END

CCODE

START,END

(PES16NT2 busy with previous command, not ready for a new command)

N P

(PES16NT2 busy with previous command, not ready for a new command)

N P

A

BYTCNT=7

CMD=write

A

ADDRL

A

A

ADDRU

A

DATALL

DATALM

A

DATAUM

A

DATAUU

A

A P

Figure 6.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled

PES16NT2 Slave

S

SMBus Address

Wr A A

ADDRU

A

CCODE

START,END

DATA

A P

BYTCNT=5

CMD=write

A

EEADDR

A

ADDRL

A

Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled

PES16NT2 Slave

S

SMBus Address

Wr A

ADDRU

A

CCODE

START,END

DATA

BYTCNT=5

A

PEC

A P

A

A

CMD=write

EEADDR

A

ADDRL

A

Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled

A

A

PES16NT2 User Manual 6 - 14 April 15, 2008

IDT SMBus Interfaces

Notes

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave
SMBus Address

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

Wr A A

Wr A

Wr

Wr A

Rd

Wr

Rd

Wr

Rd

CCODE

START, Word

CCODE

END, Byte

CCODE

A

START,Word

CCODE

START,Word

A

CCODE

A

Byte

ADDRU

AS

CCODE

A

Word

A A

CMD=read

ADDRU

A

N

P

A

A

(PES16NT2 not ready with data)

A

ADDRLCMD (status)

A N

A

A P

A

DATALMDATALL

N

ADDRL

A

P

P

P

P

PES16NT2 Slave

S

SMBus Address

PES16NT2 Slave

S

SMBus Address

Wr

Rd

CCODE

A

END, Word

A A

A

DATAUUDATAUM

N

P

Figure 6.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled

PES16NT2 User Manual 6 - 15 April 15, 2008

IDT SMBus Interfaces

Notes

PES16NT2 User Manual 6 - 16 April 15, 2008

Chapter 7

NTB Upstream Port Failover

®

Notes

Introduction

The PES16NT2 supports an NTB upstream port failover mechanism that enables the construction of

fault tolerant systems.

The NTB upstream port failover usage model is illustrated in Figure 7.1. In this usage there is a primary
root and a secondary root. Both roots are active and may communicate using transactions flowing through
the NTB, mechanisms provided by the NTB for interprocessor communications, or an out-of-band commu­nications channel. In normal mode, the primary root is responsible for configuring and managing the internal
PCIe hierarchy (i.e., the PCIe hierarchy consisting of upstream port A, P2P bridges, and the internal NTB
endpoint).

NTB upstream port failover enables the swapping of the upstream port (i.e., port A) with the NTB port
(i.e., port C). When a hardware or software failure is detected in the primary root, the PES16NT2 may be
directed to operate in a failover mode. In failure mode, the secondary root (i.e., the root associated with port
C) becomes the root responsible for configuring and managing the internal PCIe hierarchy and the primary
root becomes the root of the external NTB hierarchy.

Primary

Root

Port A

(Upstream Port)

Secondary

Root

Port C

(NTB Port)

Primary

Root

Port A

(NTB Port)

Secondary

Root

Port C

(Upstream Port)

PES16NT2

(a) Normal Mode Operation (b) Failover Mode Operation

Figure 7.1 NTB Upstream Port Failover Usage Model

PES16NT2

The PES16NT2 NTB upstream port failover architecture is shown in Figure 7.2. The two main compo­nents of this device are switch logic and a SerDes switch. The PES16NT2 switch logic implements a two
port non-transparent switch that does not support NTB upstream port failover. It consists of PCIe stacks, a
switch core and NTB logic. The SerDes switch enables SerDes lanes associated with port A and C to be
passed through unmodified or swapped.

In normal mode, the SerDes switch operates in a pass-through configuration. This connects the external
SerDes lanes associated with port A with the internal port A upstream port of the switch logic and the
SerDes lanes associated with port C with the internal port C NTB port. In failover mode, the SerDes switch
operates in a swapped configuration. This connects the SerDes lanes associated with port A to the internal
port C NTB port and the external SerDes lanes associated with port C to the internal port A upstream port.

In failover mode, the device associated with port C SerDes assumes all of the resources and responsi­bilities of the internal port A upstream port and visa versa. This means that the root associated with port C
has direct access to all port A upstream port registers, receives internal PCIe hierarchy messages (e.g.,
error and INTx), and so on.

PES16NT2 User Manual 7 - 1 April 15, 2008

IDT NTB Upstream Port Failover

Notes

Port A Port C

PES16NT2

SerDes Switch

Internal Port A

(Upstream Port)

PES16NT2 Switch

Logic

Configuration Header

PCI-PCI

Transparent

Type 1

Bridge

Internal Port C

(NTB Port)

External Type 0

Configuration Header

Non-Transparent

Bridge

Internal Type 0

Configuration Header

PCI-PCI

Transparent

Bridge

Type 1

Configuration Header

Virtual PCI Bus

Type 1

Configuration Header

PCI-PCI

Transparent

Bridge

Figure 7.2 PES16NT2 NTB Upstream Port Failover Architecture

Failover

An upstream NTB port failover may be initiated statically through a fundamental reset or dynamically
while the system is running.

A static NTB upstream port failover occurs when the state of the switch mode (SWMODE[3:0]) signals is
modified and a fundamental reset is initiated. This results in the PES16NT2 operating in the mode selected
by the switch mode signals in the boot configuration vector (i.e., a non-transparent mode or a non-trans­parent mode with failover). Since a fundamental reset is initiated in a static failover, it results in a complete
loss of system state.

Dynamic NTB upstream port failover allows the operating mode of the PES16NT2 to be modified from
normal to failover or failover to normal while the system is running and without a fundamental reset.
Dynamic NTB upstream port failover may be configured to operate in a state-preserving manner. See
section System State Preservation on page 7-4 for information on preserving system state during an a
Dynamic upstream port failover.

PES16NT2 User Manual 7 - 2 April 15, 2008

IDT NTB Upstream Port Failover

Notes

When a dynamic failover occurs, upstream and NTB port data queued in the switch, data being trans­mitted, and data in the replay buffers may be lost. Thus, some interruption of PCIe traffic should be
expected with a failover. While it may be possible to design a system in which no PCIe traffic is lost or
corrupted during a failover, such an implementation is beyond the scope of this specification.

Registers used to manage failover are located in the address space of the external NTB endpoint. Thus,
they may be accessed by the primary or secondary roots. They may also be accessed by any PCIe device
in the internal or external PCIe hierarchies when NTB endpoint configuration space is memory mapped
using BAR4.

The current failover state (i.e., normal mode or failover mode) may be determined by reading the
Current Failover Mode (CFMODE) field in the Failover Status (FOVRSTS) register. Whenever, a dynamic
upstream port failover is initiated (i.e., starts), the Failover Mode Change Initiated (FMODECI) bit is set in
the FOVRSTS register. When a dynamic failover completes, the Failover Mode Change Completed
(FMODECC) bit is set in the FOVRSTS register. These bits are sticky and thus their status is preserved
across a hot-reset. The operation of the upstream port failover mechanism is unaffected by a hot-reset.
Once a failover is initiated, the failover sequence runs to completion and can only be aborted by a funda­mental reset.

Static Upstream Port Failover

A static upstream port failover requires a fundamental reset to be initiated whenever a failover mode
change is required. Since the initial failover mode is selected by the switch mode in the boot configuration
vector, the static upstream port failover feature may be viewed as nothing more than the ability to select the
failover mode during a fundamental reset.

An static upstream port failover consists of the following steps:

– Assert the PCIe fundamental reset signal (PERSTN)
– Modify the switch mode (SWMODE) signals to the selected failover mode (i.e., normal mode or

failover mode).

– Negate the PCIe fundamental reset signal (PERSTN)

Since initiation of an upstream port failover requires a fundamental reset of the internal PCIe hierarchy
and external NTB endpoint, many systems may require the use of dynamic upstream port failover.

Dynamic Upstream Port Failover

Dynamic upstream port failover allows a failover to occur while the system is live and in a manner that
preserves the system state.

When a dynamic upstream port failover is initiated, PES16NT2 takes the following actions.

– The LTSSM associated with the upstream port (i.e., port A) and the NTB port (i.e., port C) imme-

diately transition to the Detect state and the data link layer transitions to the DL_Down state. This
causes data in the replay buffer associated with ports A and C to be discarded and may cause
data queued in the switch core for these ports to be discarded.

– The state of the SerDes switch is modified as selected by the failover mode (i.e., pass through or

swapped).

– The L TSSM initiates link training on the upstream port (i.e., port A) and the NTB port (i.e., port C).

The PxLINKUP and PxLINKDN bits in the INTSTS registers associated with both the internal and
external NTB endpoints are not set during a dynamic upstream port failover. The link down and later link up
associated with a dynamic upstream port failover are masked from causing these bits from being set. See
section Link Status on page 3-5 for a description of the PxLINKUP and PxLINKDN bits.

In most systems it is expected that only one failover mechanism will be enabled at a time. If a failover of
the same type (i.e., software, signal, or watchdog timer) is initiated while one is already in progress, the
second initiation will be lost. If a failover of a different type is initiated while one is in progress, the failover
will be performed once the one in progress completes. Software may utilize the Failover Mode Change
(FMODECC) and Failover Mode Change Initiated (FMODECI) bits in the FOVRSTS register to avoid
failover race conditions.

PES16NT2 User Manual 7 - 3 April 15, 2008

IDT NTB Upstream Port Failover

Notes

The following sections describe the manner in which a dynamic upstream port failover may be initiated.

Software Initiated Failover

A failover may be initiated by modifying the state of the NTB Upstream Port Failover Mode Select
(FOVRMSEL) field in the Failover Control (FOVRCTL) register. A software initiated failover may be insti­tuted by software running on the primary or secondary root, software running on a device that writes to the
USPSEL field via the SMBus, or via serial EEPROM initialization. The FOVRMSEL field should not be
modified during an NTB upstream port failover (i.e., failover requests are not queued).

Signal Initiated Failover

An upstream port failover may be initiated by a change in the state of the NTB Upstream Port Failover
(FAILOVERP) signal. Such a failover is initiated when the Signal Failover Enable (SIGFEN) bit is set in the
Failover Control (FOVRCTL) register and the state of the FAILOVERP signal differs from the current
failover mode reported in the CFMODE field of the FOVRSTS register.

The FAILOVERP signal is an alternate function of GPIO[5]. The state of the FAILOVERP signal always
reflects the state of the GPIO[5] pin regardless of whether or not GPIO[5] is configured to operate as an
alternate function. When FAILOVERP is negated (low), normal mode is selected. When FAILOVERP is
asserted (high), failover mode is selected. The state of the FAILOVERP signal should not b e modified more
frequently than once per second. The behavior of the PES16NT2 is undefined when the F AILOVERP signal
is modified more frequently than this rate.

Watchdog Timer Initiated Failover

An NTB upstream port failover may be initiated as the result of an expiration of a watchdog timer. Such
a failover is initiated when the Timer Failover Enable (TIMFEN) bit is set in the Failover Control (FOVRCTL)
register, and the Watchdog Timer Count (COUNT) field in the Failover W atchdog T imer (FOVR TIMER) tran­sitions from a one to a zero.

When non-zero, the COUNT field in the USPFTIMER is decremented once per microsecond (1 µS).
This provides a maximum watchdog timer interval of over one hour. Decrementing of the COUNT field
ceases when zero is reached. The COUNT field may be written by software at any time. Modifying the
count field is used to rearm the watchdog timer. If not expired, the watchdog timer continues to decrement
across a hot-reset.

When a watchdog timer failover is initiated, the failover mode selected is the one not reported in the
CFMODE field in the FOVERSTS register. For example, if the current mode is normal mode, then the mode
following a watchdog timer initiated failover is failover mode.

System State Preservation

The PES16NT2 contains mechanisms that allow system state of the internal and/or external PCIe hier­archy domains to be preserved across a dynamic failover. They may also be used to inhibit the propagation
of reset due to a link down or reception of TS1 ordered-sets indicating a hot reset.

– When the Internal Hierarchy Disable Link Down Hot Reset (IDLDHRST) bit is set in the FOVRCTL

register, the resetting of the internal and external NTB domains is inhibited due to a Port A link
down condition (i.e., a transition to DL_Down).

– When the External Hierarchy Disable Link Down Hot Reset (EDLDHRST) bit is set in the

FOVRCTL register, the resetting of the external NTB domain is inhibited due to a Port C link down
condition.

– When the Disable Failover Hot Reset (DFHRST) bit is set in the FOVRCTL register , the resetting

of the internal and external NTB domains is inhibited due to Port A and C link down conditions
resulting from a dynamic failover. Port A and C link down resulting from any other condition
continues to generate a hot reset unless masked by the IDLDHRST or EDLDHRST bits.

– When the Internal Hierarchy Disable Hot Reset Propagation (IDHRSTPROP) bit is set in the

FOVRCTL register, reception of TS1 ordered-sets on the upstream port indicating a hot reset is
ignored.

– When the External Hierarchy Disable Hot Reset Propagation (EDHRSTPROP) bit is set in the

FOVRCTL register, reception of TS1 ordered-sets on port C indicating a hot reset is ignored.

PES16NT2 User Manual 7 - 4 April 15, 2008

IDT NTB Upstream Port Failover

Notes

PES16NT2 User Manual 7 - 5 April 15, 2008

IDT NTB Upstream Port Failover

Notes

PES16NT2 User Manual 7 - 6 April 15, 2008

Chapter 8

General Purpose I/O

®

Notes

Introduction

The PES16NT2 has eight General Purpose I/O (GPIO) pins that may be individually configured as:
general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the
General Purpose I/O Control and Status (GPIOCS) register located in upstream port A’s PCI configuration
space (see Table 8.1).

GPIO Registers

Bit

Field

7:0 GPIOFUNC RW 0x0 GPIO Function. Each bit in this field controls the corre-

15:8 GPIOCFG RW 0x0 GPIO Configuration. Each bit in this field controls the cor-

Field

Name

Type

Default

Value

Description

sponding GPIO pin. When set to a one, the corresponding
GPIO pin operates as the alternate function as defined in
Table 8.2. When a bit is cleared to a zero, the correspond­ing GPIO pin operates as a general purpose I/O pin.

responding GPIO pin. When a bit is configured as a gen­eral purpose I/O pin and the corresponding bit in this field
is set, the pin is configured as a GPIO output. When a bit
is configured as a general purpose I/O pin and the corre­sponding bit in this field is zero, the pin is configured as an
input. When the pin is configured as an alternate function,
the behavior of the pin is defined by the alternate function.

23:16 GPIOD RW HWINIT GPIO Data. Each bit in this field controls the correspond-

ing GPIO pin. Reading this field returns the current value
of each GPIO pin regardless of GPIO pin mode (i.e., alter­nate function or GPIO pin). Writing a value to this field
causes the corresponding pins which are configured as
GPIO outputs to change state to the value written.

31:24 Reserved RO 0x0 Reserved field.

Table 8.1 General Purpose IO Registers

As shown in Table 8.2, GPIO pins [1,2,4,5] are shared with other on-chip functions. The GPIO Function
(GPIOFUNC) field in the GPIOCS register controls whether a GPIO bit operates as a general purpose I/O
or as the specified alternate function.

PES16NT2 User Manual 8 - 1 April 15, 2008

IDT General Purpose I/O

Notes

sampled no more frequently than once every 128 ns and may be treated as asynchronous inputs.

with the pin is held in an inactive state by internal logic. Care should be exercised when configuring the
GPIO pins as outputs since an incorrect configuration could cause damage to external components as well
as the PES16NT2.

GPIO Configuration

GPIO

Pin

Alternate

Function

Pin Name

1 PECRSTN Reset output for downstream port C Output
2 PALINKUPN Port A link up status output Output
4 PCLINKUPN Port C link up status output Output
5 FAILOVERP NTB Upstream port failover input Input

Table 8.2 General Purpose I/O Pin Alternate Function

Alternate Function Description

Alternate

Function
Pin Type

After reset, all GPIO pins default to the GPIO input function. GPIO pins configured as GPIO inputs are

When a GPIO pin is configured to use the GPIO function, the unneeded alternate function associated

Each bit in the GPIOFUNC, GPIOCFG and GPIOD fields in the GPIOCS register is associated with the
corresponding GPIO pin. Table 8.3 summarizes the configuration of GPIO pins.

GPIOFUNC GPIOCFG Pin Function

0 0 GPIO input
0 1 GPIO output
1 don’t care Alternate function

Table 8.3 GPIO Pin Configuration

GPIO Pin Configured as an Input

When configured as an input in the GPIOCFG field and as a GPIO function in the GPIOFUNC field, the
GPIO pin is sampled and registered in the GPIOD field. The value of the input pin can be determined at any
time by reading the GPIOD field. Note that the value in this field corresponds to the value of the pin irre­spective of whether the pin is configured as a GPIO input, GPIO output or alternate function.

GPIO Pin Configured as an Output

When configured as an output in the GPIOCFG field and as a GPIO function in the GPIOFUNC field, the
value in the corresponding bit position of the GPIOD field is driven on the pin. System designers should
treat the GPIO outputs as asynchronous outputs. The actual value of the output pin can be determined by
reading the GPIOD field.

GPIO Pin Configured as an Alternate Function

When configured as an alternate function in the GPIOFUNC field, the pin behaves as an described by
the section associated with that function. The value of the alternate function pin can be determined at any
time by reading the GPIOD field.

PES16NT2 User Manual 8 - 2 April 15, 2008

Chapter 9

Transparent Mode Operation

®

Notes

Introduction

This chapter discusses the operation of Port A. The following chapter, Chapter 11, discusses Port C
which is configured as a non-transparent port. When the PES16NT2 is configured during a fundamental
reset to operate in transparent mode or transparent mode with serial EEPROM initialization, the device
functionally operates as illustrated in Figure 9.1. In this mode, the PES16NT2 may logically viewed as
consisting of two PCI-PCI transparent bridges, one per port, and an internal virtual PCI bus.

Associated with each port is a 4 KB configuration space and a Type 1 configuration header. The organi­zation of these configuration spaces is described in section section Port Configuration Space Organization
on page 9-5. The functional operation of the PES16NT2 in transparent mode is fully consistent with that
described in the PCI Express® Base Specification, revision 1.0a for a three port switch.

Port A

(Upstream Port)

Type 1

Configuration Header

PCI-PCI

Transparent

Bridge

Virtual PCI Bus

Type 1

Configuration Header

PCI-PCI

Transparent Bridge

(Device 1)

Port C

(Downstream Port)

Figure 9.1 PES16NT2 Functional Block Diagram in Transparent Mode

As shown in Figure 9.1, port A is configured as the upstream port and port C as the downstream port.
Port C resides on the internal PCI Bus at Device 1, Function 0.

PES16NT2 User Manual 9 - 1 April 15, 2008

IDT Transparent Mode Operation

Notes

End-to-End CRC

PCIe® defines an optional end-to-end CRC associated with TLPs. The PES16NT2 fully supports ECRC
for all TLPs that pass through the switch except for transactions utilizing gathered and routed to root
complex implicit routing. For transactions received with this routing type, the ECRC is discarded and not
checked and the resulting gathered message is generated without an ECRC. The only standard defined
message that utilizes this method of routing is the PME_TO_Ack message.

The PES16NT2 does not support ECRC for TLPs that it generates (e.g., configuration responses, INTx
messages, etc.). Also, it does not support ECRC for TLPs it consumes (e.g., configuration requests).
However; if a TLP is received with an ECRC, the CRC is discarded and not checked and the transaction is
performed.

Interrupts

The PCI-to-PCI bridges associated with ports A and C do not support generation of legacy interrupts or
MSIs.

Error Detection and Handling

This section describes error detection performed by an ingress or egress stack when the switch is
configured to operate in transparent mode. Table 9.1 lists error checks performed by the physical layer and
action taken when an error is detected.

PCIe Base

Error Condition

1.0a

Specification

Section

Action Taken

Invalid symbol or running disparity error
detected.

Any TLP or DLLP framing rule violation. 4.2.2.1 Correctable error processing
8b/10b decode error 4.2.4.4 Correctable error processing
Any violation of the link initialization or

training protocol

Table 9.1 Physical Layer Errors

4.2.1.3 Correctable error processing

4.2.4 Uncorrectable error processing

Table 9.2 lists error checks performed by the data link layer and action taken when an error is detected.

PCIe Base

Error Condition

TLP ending in ENDB with LCRC that
does not match inverted calculated LCRC

TLP received with incorrect LCRC 3.5.3.1 Correctable error processing
TLP received with sequence number not

equal to NEXT_RCV_SEQ and this is not
a duplicate TLP

Bad DLLP

1

1.0a

Specification

Section

3.5.3.1 TLP discarded

3.5.3.1 Correctable error processing

3.5.2.1 Correctable error processing

Action Taken

Table 9.2 Data Link Layer Errors

PES16NT2 User Manual 9 - 2 April 15, 2008

IDT Transparent Mode Operation

Notes

PCIe Base

Error Condition

Replay time-out 3.5.2.1 Correctable error processing
REPLAY NUM rollover 3.5.2.1 Correctable error processing
Violation of flow control initialization pro-

tocol
Sequence number specified by

AckNak_Seq does not correspond to an
unacknowledged TLP or to the value in
ACKD_SEQ

1.

A bad DLLP is a DLP with a bad LCRC.

Table 9.2 Data Link Layer Errors

1.0a

Specification

Section

3.3.1 Uncorrectable error processing

3.5.2.1 Uncorrectable error processing

Action Taken

Table 9.3 lists error checks performed by the transaction link layer and action taken when an error is
detected.

PCIe Base

Error Condition

1.0a

Specification

Section

Action Taken

ECRC check failure 2.7.1 None. The PES16NT2 does not check ECRC for

transactions that terminate in the switch.
Malformed TLP - Fatal error processing.
Flow control protocol error 2.6.1 Not applicable. The PES16NT2 does not check

for any flow control errors.
Receiver overflow 2.6.1.2 None.
Completer abort

Completion time-out
Unsupported request

Unsupported request 2.3.1 See section Switch Core Errors on page 4-7.
Unexpected completion 2.3.2 Non-fatal error processing.

Table 9.3 Transaction Layer Errors

2.3.1

2.8

Not applicable. The PES16NT2 never generates

non-posted transactions.

Table 9.4 lists the error checks performed by the transaction layer for malformed TLPs. TLP error
checks are only performed when a TLP is received by the switch (i.e., by the stack associated with the port
on which the switch receives the TLP). No checks are made for malformed TLPs inside the switch.

PES16NT2 User Manual 9 - 3 April 15, 2008

IDT Transparent Mode Operation

Notes

All LENGTH < Max_Payload_Size (i.e., MPS field in

I/O read request LENGTH = 1 (doubleword)

I/O write request LENGTH = 1 (doubleword)

Configuration read request LENGTH = 1 (doubleword)

Configuration write request LENGTH = 1 (doubleword)

TLP Type Error Check

PCIEDCTL register)

TC = 0,
ATTR = 0
The actual packet length is correct (4 doublewords
when CRC is present, 3doublewords otherwise)

TC = 0
ATTR = 0
The actual packet length is correct (5 doublewords
when CRC is present, 4 doublewords otherwise)

TC = 0,
ATTR = 0
The actual packet length is correct (4 doublewords
when CRC is present, 3doublewords otherwise)

TC = 0
ATTR = 0
The actual packet length is correct (5 doublewords
when CRC is present, 4 doublewords otherwise)

Memory read request (32- and 64-bit address
mode)

Memory write request (32- and 64-bit address
mode)

Table 9.4 Malformed TLP Error Checks (Part 1 of 2)

The packet length is correct.
32-bit address mode: 3 doublewords when ECRC
is present, 4 doublew ords otherwise
64-bit address mode: 4 doublewords when ECRC
is present, 5 doublew ords otherwise

The packet length is correct.
32-bit address mode:

- Number of doublewords received equals
LENGTH + 4 when ECRC is present

- Number of doublewords received equals
LENGTH + 3 when a packet does not contain
ECRC
64-bit address mode:

-Number of doublewords received equals LENGTH
+ 5 when ECRC is present

- Number of doublewords received equals
LENGTH + 4 when a packet does not contain
ECRC

PES16NT2 User Manual 9 - 4 April 15, 2008

IDT Transparent Mode Operation

Notes

TLP Type Error Check

Completion with data The packet length is correct.

- Number of doublewords received equals
LENGTH + 3 when a packet does not contain
ECRC

- Number of doublewords received equals
LENGTH + 4 when ECRC is present

- Number of doublewords received is not greater
then MaxPayloadSize + 3/4

Message or message with data The actual packet length is correct:

- Number of received double words equals
LENGTH + 4 when a packet does not contain
ECRC

- Number of received double words equals
LENGTH + 5 when ECRC is present

- Number of received doublewords is not greater
then MaxPayloadSize + 4/5

Interrupt messages
Power management messages
Error signalling messages
Unlock message
Set slot power limit message

Table 9.4 Malformed TLP Error Checks (Part 2 of 2)

TC = 0 (a message of this type is considered a
malformed TLP if it uses a traffic class designator
other than TC0)

Configuration Requests

The PCI-PCI bridges associated with ports A and C all have configuration registers that may be
accessed with Type 0 configuration read and write requests. PCIe allows multiple outstanding configuration
read and write requests. The PCI-PCI bridges in the PES16NT2 each support a maximum of four
outstanding configuration requests. Issuing more than four outstanding configuration requests to any of
these entities may result in configuration requests being dropped.

Configuration accesses to different entities within the PES16NT2 may complete out-of-order and may
limit the utility of multiple outstanding PCIe configuration accesses. For example, a configuration access
that modifies a secondary or subordinate bus number which is immediately followed by a Type 1 configura­tion access that relies on the modified value for routing may result in an error when issued concurrently, but
execute properly when issued in sequence. Configuration accesses to any particular entity always
complete in order.

Port Configuration Space Organization

The organization of ports A and C configuration space is shown in Figure 9.2. While both ports share the
same basic layout, only port A (the upstream port) has switch control and status registers and only port C
(downstream port) has an MSI capability structure (refer to Figure 10.7 on page 10-55).

PES16NT2 User Manual 9 - 5 April 15, 2008

IDT Transparent Mode Operation

Notes

0x000

Type 1

Configuration Header

0x040

PCI Express

Capability Structure

0x070

0x0A0

0x0F4

0x100

0x200

PCI Power Management

Capability Structure

Switch Control

& Status Registers

*** Port A Only ***

Extended Cfg. Access &

INTx Status

Virtual Channel

Capability Structure

Phy Layer Control

& Status Registers

Reserved

PCI

Configuration Space

(64 DWords)

PCI Express Extended

Configuration Space

(960 DWords)

0xFFF

Figure 9.2 Port Configuration Space Organization

PES16NT2 User Manual 9 - 6 April 15, 2008

IDT Transparent Mode Operation

Notes

Upstream Port A Configuration Space Registers

All configuration space locations not listed in Table 9.5 return a value of zero when read. Writes to these
locations are ignored and have no side-effects. Port A configuration space registers may be read and
written via the slave SMBus interface and initialized from the serial EEPROM using the CSR system
address formed by adding the base address 0x0000 to the PCI configuration space offset address.

Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.

Cfg.

Offset

0x000 Word PA_VID PA_VID - Vendor Identification (0x000) on page 9-9
0x002 Word PA_DID PA_DID - Device Identification (0x002) on page 9-9
0x004 Word PA_PCICMD PA_PCICMD - PCI Command (0x004) on page 9-9
0x006 Word PA_PCISTS PA_PCISTS - PCI Status (0x006) on page 9-10
0x008 Byte PA_RID PA_RID - Revision Identification (0x008) on page 9-11

0x009 3 Bytes PA_CCODE PA_CCODE - Class Code (0x009) on page 9-12
0x00C Byte PA_CLS PA_CLS - Cache Line Size (0x00C) on page 9-12
0x00D Byte PA_PLTIMER PA_PLTIMER - Primary Latency Timer (0x00D) on page 9-12

Size

Register

Mnemonic

Register Definition

0x00E Byte PA_HDR PA_HDR - Header Ty pe (0x00E) on page 9-12
0x00F Byte PA_BIST PA_BIST - Built-in Self Test (0x00F) on page 9-12

0x010 DWord PA_BAR0 PA_BAR0 - Base Address Register 0 (0x010) on page 9-13

0x014 DWord PA_BAR1 PA_BAR1 - Base Address Register 1 (0x014) on page 9-13

0x018 Byte PA_PBUSN PA_PBUSN - Primary Bus Number (0x018) on page 9-13

0x019 Byte PA_SBUSN PA_SBUSN - Secondary Bus Number (0x019) on page 9-13
0x01A Byte PA_SUBUSN PA_SUBUSN - Subordinate Bus Number (0x01A) on page 9-13
0x01B Byte PA_SLTIMER PA_SLTIMER - Secondary Latency Timer (0x01B) on page 9-13
0x01C Byte PA_IOBASE PA_IOBASE - I/O Base (0x01C) on page 9-14
0x01D Byte PA_IOLIMIT PA_IOLIMIT - I/O Limit (0x01D) on page 9-14
0x01E Word PA_SECSTS PA_SECSTS - Secondary Status (0x01E) on page 9-14

0x020 Word PA_MBASE PA_MBASE - Memory Base (0x020) on page 9-15

0x022 Word PA_MLIMIT PA_MLIMIT - Memory Limit (0x022) on page 9-15

0x024 Word PA_PMBASE PA_PMBASE - Prefetchable Memory Base (0x024) on page 9-

15

0x026 Word PA_PMLIMIT PA_PMLIMIT - Prefetchable Memory Limit (0x026) on page 9-

16

0x028 DWord PA_PMBASEU PA_PMBASEU - Prefetchable Memory Base Upper (0x028) on

page 9-16

0x02C DWord PA_PMLIMITU PA_PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on

page 9-16

0x030 Word PA_IOBASEU PA_IOBASEU - I/O Base Upper (0x030) on page 9-17

Table 9.5 Upstream Port A Configuration Space Registers (Part 1 of 3)

PES16NT2 User Manual 9 - 7 April 15, 2008

IDT Transparent Mode Operation

Notes

Cfg.

Offset

0x032 Word PA_IOLIMITU PA_IOLIMITU - I/O Limit Upper (0x032) on page 9-17

0x034 Byte PA_CAPPTR PA_CAPPTR - Capabilities Pointer (0x034) on page 9-17

0x038 DWord PA_EROMBASE PA_EROMBASE - Expansion ROM Base Address (0x038) on

0x03C Byte PA_INTRLINE PA_INTRLINE - Interrupt Line (0x03C) on page 9-17
0x03D Byte PA_INTRPIN PA_INTRPIN - Interrupt PIN (0x03D) on page 9-18
0x03E Word PA_BCTRL PA_BCTRL - Bridge Control (0x03E) on page 9-18

0x040 DWord PA_PCIECAP PA_PCIECAP - PCI Express Capability (0x040) on page 9-19

0x044 DWord PA_PCIEDCAP PA_PCIEDCAP - PCI Express Device Capabilities (0x044) on

0x048 Word PA_PCIEDCTL PA_PCIEDCTL - PCI Express Device Control (0x048) on page

0x04A Word PA_PCIEDSTS PA_PCIEDSTS - PCI Express Device Status (0x04A) on page

0x04C DWord PA_PCIELCAP PA_PCIELCAP - PCI Express Link Capabilities (0x04C) on

0x050 Word PA_PCIELCTL PA_PCIELCTL - PCI Express Link Control (0x050) on page 9-

0x052 Word PA_PCIELSTS PA_PCIELSTS - PCI Express Link Status (0x052) on page 9-23

0x070 DWord PA_PMCAP PA_PMCAP - PCI Power Management Capabilities (0x070) on

0x074 DWord PA_PMCSR PA_PMCSR - PCI Power Management Control and Status

Size

Register

Mnemonic

Register Definition

page 9-17

page 9-19

9-20

9-21

page 9-22

23

page 9-26

(0x074) on page 9-27

0x078 DWord PA_PMPC PA_PMPC - PCI Power Management Proprietary Control

(0x078) on page 9-27

0x0A0 DWord PA_SWSTS PA_SWSTS Switch Status (0x0A0) on page 9-30
0x0A4 DWord PA_SWCTL PA_SWCTL - Switch Control (0x0A4) on page 9-31
0x0A8 DWord PA_GPIOCS PA_GPIOCS - General Purpose I/O Control and Status (0x0A8)

on page 9-32

0x0AC DWord PA_SMBUSSTS PA_SMBUSSTS - SMBus Status (0x0AC) on page 9-33

0x0B0 DWord PA_SMBUSCTL PA_SMBUSCTL - SMBus Control (0x0B0) on page 9-34
0x0B4 DWord PA_EEPROMINTF PA_EEPROMINTF - Serial EEPROM Interface (0x0B4) on page

9-35

0x0F4 Word PA_INTSTS PA_INTSTS - Interrupt Status (0x0F4) on page 9-36
0x0F8 DWord PA_ECFGADDR PA_ECFGADDR - Extended Configuration Space Access

Address (0x0F8) on page 9-36

0x0FC DWord PA_ECFGDATA PA_ECFGDATA - Extended Configuration Space Access Data

(0x0FC) on page 9-37

0x100 DWord PA_PCIEVCECAP PA_PCIEVCECAP - PCI Express Virtual Channel Enhanced

Capability Header (0x100) on page 9-37

0x104 DWord PA_PVCCAP1 PA_PVCCAP1- Port VC Capability 1 (0x104) on page 9-37

Table 9.5 Upstream Port A Configuration Space Registers (Part 2 of 3)

PES16NT2 User Manual 9 - 8 April 15, 2008

IDT Transparent Mode Operation

Notes

Cfg.

Offset

0x110 DWord PA_VCR0CAP PA_VCR0CAP- VC Resource 0 Capability (0x110) on page 9-38
0x114 DWord PA_VCR0CTL PA_VCR0CTL- VC Resource 0 Control (0x114) on page 9-38
0x118 DWord PA_VCR0STS PA_VCR0STS - VC Resource 0 Status (0x118) on page 9-39
0x120 DWord PA_VCR0TBL0 PA_VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0

0x124 DWord PA_VCR0TBL1 PA_VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1

0x200 DWord PA_SERDESCTL PA_SERDESCTL - SerDes Control (0x200) on page 9-42

0x204 —

0x61C

Size

Table 9.5 Upstream Port A Configuration Space Registers (Part 3 of 3)

Register

Mnemonic

Register Definition

(0x120) on page 9-40

(0x124) on page 9-41

Reserved

PA_VID - Vendor Identification (0x000)

Bit

Field

15:0 VID RO 0x111D Vendor Identification. This field contains the 16-bit ven-

Field

Name

Type

Default

Value

Description

dor ID value assigned to IDT. See section Vendor ID on
page 1-4.

PA_DID - Device Identification (0x002)

Bit

Field

15:0 DID RO - Device Identification. This field contains the 16-bit device

Field

Name

Type

Default

Value

Description

ID assigned by IDT to this transparent bridge. See section
section Device ID on page 1-4.

PA_PCICMD - PCI Command (0x004)

Bit

Field

0IOAERW0x0I/O Access Enable. When this bit is cleared, the bridge

1MAERW0x0Memory Access Enable. When this bit is cleared, the

Field

Name

Type

Default

Value

Description

does not respond to I/O accesses from the primary bus
specified by IOBASE and IOLIMIT.
0x0 - (disable) Disable I/O space.
0x1 - (enable) Enable I/O space.

bridge does not respond to memory and prefetchable
memory space access from the primary bus specified by
MBASE, MLIMIT, PMBASE and PMLIMIT.
0x0 -(disable) Disable memory space.
0x1 - (enable) Enable memory space.

PES16NT2 User Manual 9 - 9 April 15, 2008

IDT Transparent Mode Operation

Notes

Bit

Field

2BMERW0x0Bus Master Enable. When this bit is cleared, the bridge

3SSERO0x0Special Cycle Enable. Not applicable.
4MWIRO0x0Memory Write Invalidate. Not applicable.
5VGASRO0x0VGA Palette Snoop. Not applicable.
6 PERRE RW 0x0 Parity Error Enable. The Master Data Parity Error bit is

7ADSTEPRO0x0Address Data Stepping. Not applicable.

Field

Name

Type

Default

Value

Description

does not issue requests (e.g., memory, I/O and MSIs since
they are in-band writes) on behalf of subordinate devices
and responds to non-posted transactions with a Unsup­ported Request (UR) completion. This bit does not affect
completions in either direction or the forwarding of non
memory or I/O requests.
0x0 - (disable) Disable request forwarding.
0x1 - (enable) Enable request forwarding.

set in the PCI Status register (PCISTS) if this bit is set and
the bridge receives a poisoned completion or a poisoned
write. If this bit is cleared, then the Master Data Parity Error
bit in the PCI Status register is never set.
0x0 - (disable) Disable Master Parity Error bit reporting.
0x1 - (enable) Enable Master Parity Error bit reporting.

8 SERRE RW 0x0 SERR Enable. Non-fatal and fatal errors detected by the

bridge are reported to the Root Complex when this bit is set
or the bits in the PCI Express Device Control register are
set (see PA_PCIEDCTL - PCI Express Device Control
(0x048)).
0x0 - (disable) Disable non-fatal and fatal error reporting if

also disabled in Device Control register.

0x1 - (enable) Enable non-fatal and fatal error reporting.

9FB2BRO0x0Fast Back-to-Back Enable. Not applicable.

10 INTXD RW 0x0 INTx Disable. Controls the ability of the PCI-PCI bridge to

generate an INTx interrupt message.

15:11 Reserved RO 0x0 Reserved field.

PA_PCISTS - PCI Status (0x006)

Bit

Field

2:0 Reserved RO 0x0 Reserved field.

3INTSRO0x0INTx Status. This bit is set when an INTx interrupt is pend-

Field

Name

Type

Default

Value

Description

ing from the device.
INTx emulation interrupts forwarded by switch ports from
devices downstream of the bridge are not reflected in this
bit.
For all ports, this field is always zero.

PES16NT2 User Manual 9 - 10 April 15, 2008

IDT Transparent Mode Operation

Notes

Bit

Field

4 CAPL RO 0x1 Capabilities List. This bit is hardwired to one to indicate

5C66MHZRO0x066 MHz Capable. Not applicable.
6 Reserved RO 0x0 Reserved field.
7FB2BRO0x0Fast Back-to-Back (FB2B). Not applic abl e.
8 MDPED RW1C 0x0 Master Data Parity Error Detected. This bit is set when

10:9 DEVT RO 0x0 DEVSEL# Timing. Not applicable.

11 STAS RO 0x0 Signalled Target Abort. Not applicable since a target

12 RTAS RO 0x0 Received Target Abort. Not applicable.
13 RMAS RO 0x0 Received Master Abort. Not applicable.

Field

Name

Type

Default

Value

Description

that the bridge implements an extended capability list item.

the PERRE bit is set in the PCI Command register and the
bridge receives a poisoned completion or poisoned write
request on the primary side of the bridge.
0x0 -(noerror) no error.
0x1 - (error) Poisoned write request or completion received

on primary side.

abort is never signalled.

14 SSE RW1C 0x0 Signalled System Error. This bit is set when the bridge

sends a ERR_FATAL or ERR_NONFATAL message and
the SERR Enable (SERRE) bit is set in the PCICMD regis­ter.
0x0 - (noerror) no error.
0x1 - (error) This bit is set when a fatal or non-fatal error is

signalled.

15 DPE RW1C 0x0 Detected Parity Error. This bit is set by the bridge when-

ever it receives a poisoned TLP on the primary side regard­less of the state of the PERRE bit in the PCI Command
register.
For downstream ports, this bit is also set when a internal
switch parity error is detected. See section Data Integrity
on page 4-4.

PA_RID - Revision Identification (0x008)

Bit

Field

7:0 RID RWL — Revision ID. This field contains the revision identification

Field

Name

Type

Default

Value

Description

number for the device.
See section Revision ID on page 1-5.

PES16NT2 User Manual 9 - 11 April 15, 2008

IDT Transparent Mode Operation

Notes

PA_CCODE - Class Code (0x009)

Bit

Field

7:0 INTF RO 0x00 Interface. This value indicates that the device is a PCI-

15:8 SUB RO 0x04 Sub Class Code. This value indicates that the device is a

23:16 BASE RO 0x06 Base Class Code. This value indicates that the device is a

Field

Name

Type

Default

Value

Description

PCI bridge that does not support subtractive decode.

PCI-PCI bridge.

bridge.

PA_CLS - Cache Line Size (0x00C)

Bit

Field

7:0 CLS RW 0x00 Cache Line Size. This field has no effect on the bridge’s

Field

Name

Type

Default

Value

Description

functionality but may be read and written by software.
This field is implemented for compatibility with legacy soft­ware.

PA_PLTIMER - Primary Latency Timer (0x00D)

Bit

Field

7:0 PLTIMER RO 0x00 Primary Latenc y Timer. Not applicable.

Field

Name

Type

Default

Value

Description

PA_HDR - Header Type (0x00E)

Bit

Field

7:0 HDR RO 0x01 Header Type. This value indicates a type 1 header with a

Field

Name

Type

Default

Value

Description

single function bridge layout.

PA_BIST - Built-in Self Test (0x00F)

Bit

Field

7:0 BIST RO 0x0 BIST. This value indicates that the bridge does not imple-

Field

Name

Type

Default

Value

Description

ment BIST.

PES16NT2 User Manual 9 - 12 April 15, 2008

IDT Transparent Mode Operation

Notes

PA_BAR0 - Base Address Register 0 (0x010)

Bit

Field

31:0 BAR RO 0x0 Base Address Register. Not applicable.

Field

Name

Type

Default

Value

Description

PA_BAR1 - Base Address Register 1 (0x014)

Bit

Field

31:0 BAR RO 0x0 Base Address Register. Not applicable.

Field

Name

Type

Default

Value

Description

PA_PBUSN - Primary Bus Number (0x018)

Bit

Field

7:0 PBUSN RW 0x0 Primary Bus Number. This field is used to record the bus

Field

Name

Type

Default

Value

Description

number of the PCI bus segment to which the primary inter­face of the bridge is connected.

PA_SBUSN - Secondary Bus Number (0x019)

Bit

Field

7:0 SBUSN RW 0x0 Secondary Bus Number. This field is used to record the

Field

Name

Type

Default

Value

Description

bus number of the PCI bus segment to which the second­ary interface of the bridge is connected.

PA_SUBUSN - Subordinate Bus Number (0x01A)

Bit

Field

7:0 SUBUSN RW 0x0 Subordinate Bus Number. The Subordinate Bus Number

Field

Name

Type

Default

Value

Description

register is used to record the bus number of the highest
numbered PCI bus segment which is behind (or subordi­nate to) the bridge.

PA_SLTIMER - Secondary Latency Timer (0x01B)

Bit

Field

Field

Name

Type

Default

Value

Description

7:0 SLTIMER RO 0x0 Secondary Latency Timer. Not applicable.

PES16NT2 User Manual 9 - 13 April 15, 2008

IDT Transparent Mode Operation

Notes

PA_IOBASE - I/O Base (0x01C)

Bit

Field

0IOCAPRWL0x1I/O Capability. Indicates if the bridge supports 16-bit or 32-

3:1 Reserved RO 0x0 Reserved field.
7:4 IOBASE RW 0xF I/O Base. The IOBASE and IOLIMIT registers are used to

Field

Name

Type

Default

Value

Description

bit I/O addressing.
0x0 - (io16) 16-bit I/O addressing.
0x1 - (io32) 32-bit I/O addressing.

control the forwarding of I/O transactions between the pri­mary and secondary interfaces of the bridge. This field con­tains A[15:12] of the lowest I/O address aligned on a 4KB
boundary that is below the primary interface of the bridge.

PA_IOLIMIT - I/O Limit (0x01D)

Bit

Field

0IOCAPRO0x1I/O Capability. Indicates if the bridge supports 16-bit or 32-

Field

Name

Type

Default

Value

Description

bit I/O addressing. This bit always reflects the value of the

IOCAP field in the IOBASE register.
3:1 Reserved RO 0x0 Reserved field.
7:4 IOLIMIT RW 0x0 I/O Limit. The IOBASE and IOLIMIT registers are used to

control the forwarding of I/O transactions between the pri-

mary and secondary interfaces of the bridge. This field con-

tains A[15:12] of the highest I/O address, with A[11:0]

assumed to be 0xFFF, that is below the primary interface

of the bridge.

PA_SECSTS - Secondary Status (0x01E)

Bit

Field

7:0 Reserved RO 0x0 Reserved field.

8 MDPED RW1C 0x0 Master Data Parity Error. This bit is set when the PERRE

10:9 DVSEL RO 0x0 Not applicable.

11 STAS RO 0x0 Signalled Target Abort Status. Not applicable.

Field

Name

Type

Default

Value

Description

bit is set in the PCI Command register and the bridge

receives a poisoned completion or generates a poisoned

write request on the secondary side of the bridge.

0x0 - (noerror) no error.

0x1 - (error) poisoned write request or completion received

on primary side.

12 RTAS RO 0x0 Received Target Abort Status. Not applicable.
13 RMAS RO 0x0 Received Master Abort Status. Not applicable.

PES16NT2 User Manual 9 - 14 April 15, 2008