IDT 89HPES12N3 User Manual

IDT™ 89HPES12N3

PCI Express® Switch

User Manual

June 2006

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: [phone] • [phone] • FAX: [phone]

©2006 Integrated Device Technology, Inc.

Printed in U.S.A.

Integrated Device Technology, Inc. reserves t he right to make changes to its produc ts or specifications at any time, without notice, in order to improve design or perf or mance
and to supply th e best possible product. IDT does not assume any responsibility for use of any circui try described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use . N o license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

GENERAL DISCLAIMER

Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
at your own risk. IDT MAKES NO REPRESENTA TIONS OR W AR RANTIE S OF ANY KIND CONCERNI NG THE NONINFR INGEMENT, QUALIT Y, SAFET Y OR SUITABILITY
OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITA T ION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICU­LAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REP RESENTA TI ONS OR W ARRANTI ES AS T O THE TRUT H, ACCURACY OR COMPLETENES S
OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR
THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR
SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code
examples also ma y b e s ubj ec t t o Uni te d S ta tes ex po rt c on trol l aw s an d m ay b e s ubj ect t o the e xpo r t or im por t la ws of ot her co un tries and it i s your re sponsi bilit y to comply with
any applicable l aws or regulations .

Integrated Device Technology's products are not authorized for use as cr itical components in life support devi ces or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intend ed for su rgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly us ed in accordance with instructions for use provid ed in the labeling, can be reasonably expected to res ult in a significant injury to the user.

2. A critical co mpo nent is an y com pon en ts of a lif e sup por t dev ice or system whose fai lu re t o perform can be re aso na bl y exp ect ed to cause the failure of the life support device
or system, or to affect its safety or effectiveness.

The IDT logo is a re gi st ere d tr ad emar k of Int eg rat ed Dev ice Tec hn olog y , Inc . I DT, I nter pr ise , R ISCo nt rol le r, R ISCo r e, RC 30 41 , R C3 05 2, RC 3081, R C32 134, RC 32 332, RC 32 333, RC 323 34 , RC3 23 36 , RC3 23 55,
RC32351, RC32 365, RC 3243 4, RC 32438, RC3 2364, R C361 00, R C4700, RC46 40, RC64145 , RC 4650, RC500 0, RC 6447 4, RC6 4475, 89TT M55x, 89TS F5xx a re tra demark s of Integ rated Devic e Tech nolo gy, I nc.
.

Powering What's N ext a nd Ena bli ng A Dig it all y C onnec te d W or ld ar e serv ice mark s of I nteg rat e d D evi ce Tec hn olo gy, Inc. Q, QS I, Sy nch r oSwit ch an d Tu rbo cloc k ar e reg iste r ed tr ade ma rk s of Q u alit y Sem ic ondu c­tor, a wholly-owned subsidiary of Integrated Device Technology, Inc.

CODE DISCLAIMER

LIFE SUPPORT POLICY

About This Manual

Notes

Introduction

This user manual includes hardware and software information on the 89HPES12N3, a member of IDT’s
PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan­dard.

Finding Additional Information

Information not included in this manual such as mechanicals, package pin-outs, and electrical character­istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.

Content Summary

Chapter 1, “PES12N3 Device Overview,” provides a complete introduction to the performance capa­bilities of the 89HPES12N3. Included in this chapter is a summary of features for the device as well as a
system block diagram and pin description.

Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer­ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.

Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.

Chapter 4, “Switch Operation,” discusses the procedure for forwarding PCIe® TLPs between switch
ports.

Chapter 5, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-PCI bridge in the PES12N3.

Chapter 6, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in
the PES12N3.

Chapter 7, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES12N3.

Chapter 8, “General Purpose I/O,” describes how the eight General Purpose I/O (GPIO) pins may be

individually configured as general purpose inputs, general purpose outputs, or alternate functions

Chapter 9, “Transparent Mode Operation,” describes how the PES12N3 can be configured during a
fundamental reset to operate in transparent mode or transparent mode with serial EEPROM initialization.

Chapter 10, “T est and Debug,” discusses the six test modes, in addition to the normal operating mode,
associated with the PES12N3.

Chapter 11, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.

Signal Nomenclature

To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. T he term negate or negation
is used to indicate that a signal is inactive or false.

PES12N3 User Manual 1 June 7, 2006

IDT About This Manual Numeric Representations

Notes

To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ s hould be i nter­preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. To
define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the
right. No leading zeros will be included.

Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.

single clock cycle

1 2 3 4

high-to-low

transition

low-to-high

transition

Figure 1 Signal Transitions

Numeric Representations

To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.

Data Units

The following data unit terminology is used in this document.

Term Words Bytes Bits

Byte 1/2 1 8

Word 1 2 16

Doubleword (Dword) 2 4 32

Quadword (Qword) 4 8 64

Table 1 Data Unit Terminology

In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double­words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the leas t significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.

The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.

PES12N3 User Manual 2 June 7, 2006

IDT About This Manual Register Terminology

Notes

bit 0bit 31

0 1 2 3

Address of Bytes within Words: Big Endian

bit 0bit 31

3 2 1 0

Address of Bytes within Words: Little Endian

Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

Register Terminology

Software in the context of this register terminology refers to modifications made by PCIe root configura­tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial­ization. See Table 2.

Type Abbreviation Description

Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms

such as pin strapping or serial EEPROM. (System firmware hard­ware initialization is only allowed for system integrated devices.) Bits
are read-only after initialization and can only be reset (for write-once
by firmware) with reset.

Read Only and Clear RC Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.

Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.

Reserved Reserved The value read from a reserved register/bit is undefined. Thus, soft-

ware must deal correctly with fields that are reserved. On reads, soft­ware must use appropriate masks to extract the defined bits and not
rely on reserved bits being any particular value. On writes, software
must ensure that the values of reserved bit positions are preserved.
That is, the values of reserved bit positions must first be read,
merged with the new values for other bit positions and then written
back.

Read Only RO Software can only read registers/bits with this attribute. Contents are

hardwired. Writing to a RO location has no effect.

Read Only and set by
Hardware

ROS Software can only read registers/bits with this attribute. Contents are

set by hardware and may change. Writing to a ROS location has no
effect.

Read and Write RW Software can both read and write bits with this attribute.

Table 2 Register Terminology (Sheet 1 of 2)

PES12N3 User Manual 3 June 7, 2006

IDT About This Manual Use of Hypertext

Notes

Type Abbreviation Description

Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. How-

ever, writing a value of zero to a bit with this attribute has no effect. A
RW1C bit can only be set to a value of 1 by a hardware event. To
clear a RW1C bit (i.e., change its value to zero) a value of one must
be written to the location. An RW1C bit is never cleared by hardware.

Read and Write when
Unlocked

Zero Zero A zero register or bit must be written with a value of zero and returns

RWL Software can read the register/bits with this attribute. Writing to regis-

ter/bits with this attribute will only cause the value to be modified if
the REGUNLOCK bit in the SWCNTL register is set. When the
REGUNLOCK bit is cleared, writes are ignored and the register/bits
are effectively read-only

a value of zero when read.

Table 2 Register Terminology (Sheet 2 of 2)

Use of Hypertext

In Chapter 9 there are tables which contain register names and page numbers highlighted in blue under
the Register Definition column. In pdf files, users can jump from the source table directly to the registers by
clicking on the register name in the source table. Each register name in the table is linked directly to the
appropriate register in the register section of the chapter. To return to the source table after having jumped
to the register section, click on the same register name (in blue) in the register section.

Revision History

February 8, 2006: Initial Publication.

June 7, 2006: Added revision YC information in Chapters 1 and 9.

PES12N3 User Manual 4 June 7, 2006

Table of Contents

Notes

About This Manual

Introduction.....................................................................................................................................1

Finding Additional Information...............................................................................................1

Content Summary...........................................................................................................................1

Signal Nomenclature ......................................................................................................................1

Numeric Representations...............................................................................................................2

Data Units.......................................................................................................................................2

Register Terminology......................................................................................................................3

Use of Hypertext.............................................................................................................................4

Revision History..............................................................................................................................4

1 PES12N3 Device Overview

Introduction..................................................................................................................................1-1

Features.......................................................................................................................................1-3

System Identification....................................................................................................................1-4

Vendor ID...........................................................................................................................1-4

Device ID............................................................................................................................1-4

Revision ID.........................................................................................................................1-5

JTAG ID.............................................................................................................................. 1-5

Logic Diagram..............................................................................................................................1-6

Pin Description.............................................................................................................................1-7

Pin Characteristics.....................................................................................................................1-11

2 Clocking, Reset, and Initialization

Introduction..................................................................................................................................2-1

Initialization..................................................................................................................................2-1

Reset ...........................................................................................................................................2-3

Fundamental Reset............................................................................................................2-5

Hot Reset...........................................................................................................................2-6

3 Link Operation

Introduction..................................................................................................................................3-1

Polarity Inversion.........................................................................................................................3-1

Link Width Negotiation.................................................................................................................3-1

Lane Reversal..............................................................................................................................3-1

Link Retraining.............................................................................................................................3-3

Link Down....................................................................................................................................3-3

Slot Power Limit Support.............................................................................................................3-3

PES12N3 User Manual i June 7, 2006

IDT Table of Contents

Notes

4 Switch Operation

Introduction..................................................................................................................................4-1

Routing........................................................................................................................................4-3

Data Integrity...............................................................................................................................4-4

Switch Time-Outs ........................................................................................................................ 4-5

Locking........................................................................................................................................4-5

Interrupts......................................................................................................................................4-7

Switch Core Errors.......................................................................................................................4-8

5 Power Management

Introduction..................................................................................................................................5-1

PME Messages..................................................................................................................5-2

Link States...................................................................................................................................5-2

Active State Power Management................................................................................................5-3

6 Hot-Plug and Hot-Swap

Introduction..................................................................................................................................6-1

Hot-Plug with Downstream Port(s) Connected to a Slot....................................................6-3

Hot-Plug with Switch on an Add-In Card............................................................................6-6

Hot-Swap.....................................................................................................................................6-7

7 SMBus Interfaces

Introduction..................................................................................................................................7-1

SMBus Registers.........................................................................................................................7-2

Master SMBus Interface..............................................................................................................7-4

Initialization ........................................................................................................................7-4

Serial EEPROM .................................................................................................................7-4

Hot-Plug I/O Expander.......................................................................................................7-8

Slave SMBus Interface................................................................................................................7-9

Initialization ........................................................................................................................7-9

SMBus Transactions..........................................................................................................7-9

8 General Purpose I/O

Introduction..................................................................................................................................8-1

GPIO Registers............................................................................................................................8-1

GPIO Configuration .....................................................................................................................8-2

GPIO Pin Configured as an Input.......................................................................................8-2

GPIO Pin Configured as an Output....................................................................................8-2

GPIO Pin Configured as an Alternate Function .................................................................8-2

9 Transparent Mode Operation

Introduction..................................................................................................................................9-1

End-to-End CRC..........................................................................................................................9-2

Interrupts......................................................................................................................................9-2

Error Detection and Handling ......................................................................................................9-2

PES12N3 User Manual ii June 7, 2006

IDT Table of Contents

Notes

Configuration Requests......................................................................................................9-6

Port Configuration Space Organization.......................................................................................9-6

Upstream Port A Configuration Space Registers ........................................................................9-8

Register Specialization.....................................................................................................9-10

Downstream Port B Configuration Space Registers..................................................................9-11

Register Specialization.....................................................................................................9-13

Downstream Port C Configuration Space Registers..................................................................9-14

Register Specialization.....................................................................................................9-16

Generic PCI to PCI Bridge Register Definition ..........................................................................9-17

Type 1 Configuration Header Registers...........................................................................9-17

PCI Express Capability Structure.....................................................................................9-26

Power Management Capability Structure.........................................................................9-36

Message Signaled Interrupt Capability Structure.............................................................9-39

Switch Control and Status Registers................................................................................9-40

Extended Configuration Space Access and INTx Status Registers.................................9-49

PCI Express Virtual Channel Capability...........................................................................9-50

Test Mode Registers ........................................................................................................9-55

System Integrity ...............................................................................................................9-60

10 T est and Debug

Device Test Modes....................................................................................................................10-1

10-bit Loopback Test Mode (SWMODE[3:0] = 0x8).........................................................10-1

Internal Pseudo Random Bit Stream Self-Test Test Mode (SWMODE[3:0] = 0xA)..........10-2

External Pseudo Random Bit Stream Self-Test Test Mode (SWMODE[3:0] = 0xB).........10-3

SerDes Broadcast Test Mode (SWMODE[3:0] = 0xD).....................................................10-3

SerDes Test Clock.....................................................................................................................10-5

11 JTAG Boundary Scan

Introduction................................................................................................................................11-1

Test Access Point......................................................................................................................11-1

Signal Definitions.......................................................................................................................11-1

Boundary Scan Chain................................................................................................................11-3

Test Data Register (DR).............................................................................................................11-4

Boundary Scan Registers ................................................................................................11-4

Instruction Register (IR).............................................................................................................11-6

EXTEST...........................................................................................................................11-7

SAMPLE/PRELOAD ........................................................................................................11-7

BYPASS...........................................................................................................................11-7

CLAMP.............................................................................................................................11-8

DEVICEID........................................................................................................................11-8

VALIDATE ........................................................................................................................11-8

RESERVED......................................................................................................................11-8

UNUSED..........................................................................................................................11-8

Usage Considerations ...............................................................................................................11-9

PES12N3 User Manual iii June 7, 2006

IDT Table of Contents

Notes

PES12N3 User Manual iv June 7, 2006

List of Tables

Notes

Table 1.1 PES12N3 Offset Device IDs.............................................................................................1-4

Table 1.2 PES12N3 Revision IDs.....................................................................................................1-5

Table 1.3 PCI Express Interface Pins...............................................................................................1-7

Table 1.4 SMBus Interface Pins.......................................................................................................1-8

Table 1.5 General Purpose I/O Pins.................................................................................................1-8

Table 1.6 System Pins......................................................................................................................1-9

Table 1.7 Test Pins.........................................................................................................................1-10

Table 1.8 Power and Ground Pins..................................................................................................1-10

Table 1.9 Pin Characteristics..........................................................................................................1-11

Table 2.1 Reference Clock Mode Encoding.....................................................................................2-1

Table 2.2 Boot Configuration Vector Signals....................................................................................2-2

Table 2.3 Reset Conditions and Their Effect....................................................................................2-3

Table 4.1 PES12N3 Buffer Sizes......................................................................................................4-2

Table 4.2 PES12N3 Advertised Flow Control Credits ......................................................................4-3

Table 4.3 Switch Routing Methods...................................................................................................4-4

Table 4.4 PCI Compatible INTx Aggregation....................................................................................4-7

Table 4.5 PES12N3 Upstream Port Bridge Interrupt Mapping......................................................... 4-8

Table 5.6 PES12N3 Power Management State Transition Diagram................................................5-2

Table 6.7 Downstream Ports B and C Hot Plug Signals...................................................................6-3

Table 6.8 SMBus I/O Expander Signals...........................................................................................6-4

Table 6.9 Upstream Port A Hot Plug Signals....................................................................................6-6

Table 7.1 SMBUSSTS - SMBus Status............................................................................................7-2

Table 7.2 SMBUSCTL - SMBus Control...........................................................................................7-3

Table 7.3 Serial EEPROM SMBus Address.....................................................................................7-4

Table 7.4 Base Addresses for PCI Configuration Spaces in the PES12N3 .....................................7-5

Table 7.5 PES12N3 Compatible Serial EEPROMs..........................................................................7-5

Table 7.6 Serial EEPROM Initialization Errors .................................................................................7-8

Table 7.7 Slave SMBus Address When a Static Address is Selected..............................................7-9

Table 7.8 Slave SMBus Command Code Fields ............................................................................7-10

Table 7.9 CSR Register Read or Write Operation Byte Sequence ................................................7-11

Table 7.10 CSR Register Read or Write CMD Field Description......................................................7-11

Table 7.11 Serial EEPROM Read or Write Operation Byte Sequence.............................................7-12

Table 7.12 Serial EEPROM Read or Write CMD Field Description..................................................7-13

Table 8.1 General Purpose IO Registers..........................................................................................8-1

Table 8.2 General Purpose I/O Pin Alternate Function....................................................................8-2

Table 8.3 GPIO Pin Configuration....................................................................................................8-2

Table 9.1 Transparent Mode Port B and C Interrupts.......................................................................9-2

Table 9.2 Physical Layer Errors........................................................................................................9-3

Table 9.3 Data Link Layer Errors......................................................................................................9-3

Table 9.4 Transaction Layer Errors..................................................................................................9-4

Table 9.5 Malformed TLP Error Checks...........................................................................................9-4

Table 9.6 Upstream Port A Configuration Space Registers.............................................................9-8

Table 9.7 Downstream Port B Configuration Space Registers.......................................................9-11

Table 9.8 Downstream Port C Configuration Space Registers.......................................................9-14

Table 10.1 PRBS LFSR Symbol Output...........................................................................................10-2

Table 10.2 SerDes Broadcast Test Mode Operation Transmit Delay Operation ..............................10-4

Table 11.1 JTAG Pin Descriptions....................................................................................................11-2

Table 11.2 Boundary Scan Chain.....................................................................................................11-3

Table 11.3 Instructions Supported by PES12N3’s JTAG Boundary Scan........................................11-6

PES12N3 User Manual v June 7, 2006

IDT List of Tables

Notes

Table 11.4 System Controller Device Identification Register............................................................11-8

PES12N3 User Manual vi June 7, 2006

List of Figures

Notes

Figure 1.1 PES12N3 Functional Block Diagram ................................................................................ 1-2

Figure 1.2 PES12N3 Architectural Block Diagram ............................................................................. 1-3

Figure 1.3 PES12N3 Logic Diagram ..................................................................................................1-6

Figure 2.1 Fundamental Reset in Transparent Mode with Serial EEPROM initialization ...................2-6

Figure 3.1 Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[1:0]=0x2) .......................3-2

Figure 3.2 Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[1:0]=0x1) .......................3-2

Figure 4.1 PES12N3 Switch Data Flow and Buffering .......................................................................4-1

Figure 5.1 PES12N3 Power Management State Transition Diagram ................................................ 5-1

Figure 5.2 PES12N3 ASPM Link Sate Transitions ............................................................................ 5-3

Figure 6.1 Hot-Plug on Switch Downstream Slots Application ...........................................................6-1

Figure 6.2 Hot-Plug with Switch on Add-In Card Application .............................................................6-2

Figure 6.3 Hot-Plug with Carrier Card Application ............................................................................. 6-2

Figure 7.1 SMBus Interface Configuration Examples ........................................................................ 7-1

Figure 7.2 Single Double Word Initialization Sequence Format .........................................................7-6

Figure 7.3 Sequential Double Word Initialization Sequence Format ..................................................7-6

Figure 7.4 Configuration Done Sequence Format ............................................................................. 7-7

Figure 7.5 Slave SMBus Command Code Format ............................................................................. 7-9

Figure 7.6 CSR Register Read or Write CMD Field Format .............................................................7-11

Figure 7.7 Serial EEPROM Read or Write CMD Field Format .........................................................7-12

Figure 7.8 CSR Register Read Using SMBus Block Write/Read Transactions

with PEC Disabled .......................................................................................................... 7-13

Figure 7.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions

with PEC Disabled .......................................................................................................... 7-14

Figure 7.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ..........7-14

Figure 7.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ....... 7-14

Figure 7.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled .......7-14

Figure 7.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ...7-15

Figure 9.1 PES12N3 Functional Block Diagram in Transparent Mode ..............................................9-1

Figure 9.2 Port Configuration Space Organization ............................................................................ 9-7

Figure 10.1 10-bit Loopback Test Mode ............................................................................................10-1

Figure 10.2 Internal Pseudo Random Bit Stream Self-Test ............................................................... 10-2

Figure 10.3 External Pseudo Random Bit Stream Self-Test ..............................................................10-3

Figure 11.1 Diagram of the JTAG Logic ............................................................................................. 11-1

Figure 11.2 State Diagram of PES12N3’s TAP Controller .................................................................11-2

Figure 11.3 Diagram of Observe-only Input Cell ................................................................................11-4

Figure 11.4 Diagram of Output Cell ...................................................................................................11-5

Figure 11.5 Diagram of Output Enable Cell ....................................................................................... 11-5

Figure 11.6 Diagram of Bidirectional Cell ........................................................................................... 11-6

Figure 11.7 Device ID Register Format .............................................................................................. 11-8

PES12N3 User Manual vii June 7, 2006

IDT List of Figures

Notes

PES12N3 User Manual viii June 7, 2006

Register List

Notes

BAR0 - Base Address Register 0 (0x010)................................................................................................9-20

BAR1 - Base Address Register 1 (0x014)................................................................................................9-20

BCTRL - Bridge Control (0x03E)..............................................................................................................9-26

BIST - Built-in Self Test (0x00F)...............................................................................................................9-20

CAPPTR - Capabilities Pointer (0x034) ...................................................................................................9-25

CCODE - Class Code (0x009) .................................................................................................................9-19

CLS - Cache Line Size (0x00C)...............................................................................................................9-20

DID - Device Identification (0x002)...........................................................................................................9-17

ECFGADDR - Extended Configuration Space Access Address (0x0F8).................................................9-49

ECFGDATA - Extended Configuration Space Access Data (0x0FC).......................................................9-50

EEPROMINTF - Serial EEPROM Interface (0x0B4)................................................................................9-47

EROMBASE - Expansion ROM Base Address (0x038)...........................................................................9-25

GPIOCS - General Purpose I/O Control and Status (0x0A8)...................................................................9-45

HDR - Header Type Register (0x00E)...................................................................................................... 9-20

INTRLINE - Interrupt Line (0x03C)...........................................................................................................9-25

INTRPIN - Interrupt PIN (0x03D)..............................................................................................................9-25

INTSTS - Interrupt Status (0x0F4).............................................................................................. .............9-49

IOBASE - I/O Base (0x01C).....................................................................................................................9-21

IOBASEU - I/O Base Upper (0x030)........................................................................................................9-24

IOEXPINTF - I/O Expander Interface (0x0B8) .........................................................................................9-48

IOLIMIT - I/O Limit (0x01D)......................................................................................................................9-22

IOLIMITU - I/O Limit Upper (0x032).........................................................................................................9-25

MBASE - Memory Base (0x020)..............................................................................................................9-23

MLIMIT - Memory Limit (0x022)...............................................................................................................9-23

MSIADDR - Message Signaled Interrupt Address (0x080)......................................................................9-39

MSICAP - Message Signaled Interrupt Capability and Control (0x07C)..................................................9-39

MSIMDATA - Message Signaled Interrupt Message Data (0x088)..........................................................9-40

MSIUADDR - Message Signaled Interrupt Upper Address (0x084).........................................................9-40

PA_PCIECAP - PCI Express Capability (0x040)......................................................................................9-10

PB_PCIECAP - PCI Express Capability (0x040)......................................................................................9-13

PBUSN - Primary Bus Number (0x018)...................................................................................................9-21

PC_PCIECAP - PCI Express Capability (0x040)......................................................................................9-16

PCICMD - PCI Command (0x004)...........................................................................................................9-17

PCIECAP - PCI Express Capability (0x040).............................................................................................9-26

PCIEDCAP - PCI Express Device Capabilities (0x044)...........................................................................9-27

PCIEDCTL - PCI Express Device Control (0x048)...................................................................................9-28

PCIEDSTS - PCI Express Device Status (0x04A)....................................................................................9-29

PCIELCAP - PCI Express Link Capabilities (0x04C)................................................................................9-30

PCIELCTL - PCI Express Link Control (0x050)........................................................................................9-30

PCIELSTS - PCI Express Link Status (0x052).........................................................................................9-31

PCIESCAP - PCI Express Slot Capabilities (0x054)................................................................................9-32

PCIESCTL - PCI Express Slot Control (0x058)........................................................................................9-33

PCIESSTS - PCI Express Slot Status (0x05A) ........................................................................................9-35

PCIEVCECAP - PCI Express Virtual Channel Enhanced Capability Header (0x100)..............................9-50

PCISTS - PCI Status (0x006)...................................................................................................................9-18

PLTIMER - Primary Latency Timer (0x00D).............................................................................................9-20

PMBASE - Prefetchable Memory Base (0x024).......................................................................................9-23

PMBASEU - Prefetchable Memory Base Upper (0x028).........................................................................9-24

PMCAP - PCI Power Management Capabilities (0x070)..........................................................................9-36

PES12N3 User Manual ix June 7, 2006

IDT Register List

Notes

PMCSR - PCI Power Management Control and Status (0x074)..............................................................9-36

PMLIMIT - Prefetchable Memory Limit (0x026)........................................................................................9-24

PMLIMITU - Prefetchable Memory Limit Upper (0x02C)..........................................................................9-24

PMPC - PCI Power Management Proprietary Control (0x078)................................................................9-37

PVCCAP1- Port VC Capability 1 (0x104).................................................................................................9-50

RID - Revision Identification (0x008)........................................................................................................9-19

SBUSN - Secondary Bus Number (0x019) ..............................................................................................9-21

SECSTS - Secondary Status (0x01E)......................................................................................................9-22

SLTIMER - Secondary Latency Timer (0x01B)........................................................................................9-21

SMBUSCTL - SMBus Control (0x0B0).....................................................................................................9-46

SMBUSSTS - SMBus Status (0x0AC) .....................................................................................................9-45

SUBUSN - Subordinate Bus Number (0x01A).........................................................................................9-21

SWCTL - Switch Control (0x0A4).............................................................................................................9-42

SWSICTL - Switch System Integrity Control (0x500)...............................................................................9-60

SWSIPECNT - Switch System Integrity Parity Error Count (0x504) ........................................................9-61

SWSITDCNT - Switch System Integrity Time-Out Drop Count (0x508)...................................................9-61

SWSTS Switch Status (0x0A0)................................................................................................................9-40

TMCNT0 - Test Mode Count 0 (0x0CC)...................................................................................................9-59

TMCNT1 - Test Mode Count 1 (0x0D0)...................................................................................................9-59

TMCNT2 - Test Mode Count 2 (0x0D4)...................................................................................................9-60

TMCNTCFG - Test Mode Count Configuration (0x0C8)..........................................................................9-57

TMCTL - Test Mode Control (0x0BC)......................................................................................................9-55

TMFSTS - Test Mode Fail Status (0x0C0)............................................................................................... 9-56

TMSSTS - Test Mode Synchronization Status (0x0C4)...........................................................................9-56

VCR0CAP- VC Resource 0 Capability (0x110)........................................................................................9-51

VCR0CTL- VC Resource 0 Control (0x114).............................................................................................9-51

VCR0STS - VC Resource 0 Status (0x118).............................................................................................9-52

VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120)...............................................................9-53

VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124)...............................................................9-54

VID - Vendor Identification (0x000)..........................................................................................................9-17

PES12N3 User Manual x June 7, 2006

Chapter 1

PES12N3 Device Overview

Notes

Introduction

The 89HPES12N3 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions
offering the next-generation I/O interconnect standard. The PES12N3 is a 12 lane, 3-port peripheral chip
that performs PCI Express Base switching with a feature set optimized for high performance applications
such as servers, storage, and communications/networking. It provides high-performance I/O connectivity
and switching functions between a PCI Express upstream port and two downstream ports or peer-to-peer
switching between downstream ports.

Utilizing standard PCI Express interconnect, the PES12N3 provides the most efficient high-performance
I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. It provides 6 GBps (48 Gbps) of aggregate sw itching capacity
through 12 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of
bandwidth in both directions. The PES12N3 is fully compliant with PCI Express Base specification 1.0a.

The PES12N3 is based on a flexible and efficient layered architecture. The PCI Express layer consists
of SerDes, Physical, Data Link and Transaction layers in compliance wi th PCI Express Base speci fication
Revision 1.0a. The PES12N3 can operate either as a store and forward or cut-through switch and is
designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management. This includes system selectable algorithms such
as round robin and weighted round-robin schemes guaranteeing bandwidth allocation and/or latency for
critical traffic classes in applications such as high throughput 10 Gigabit I/Os, streaming media for graphics,
TV tuners, and cameras.

Figure 1.1 provides a functional block diagram while Figure 1.2 illustrates the architecture of the device.

PES12N3 User Manual 1 - 1 June 7, 2006

IDT PES12N3 Device Overview Introduction

Notes

Port A

(Upstream Port)

Type 1

Configuration Header

PCI-PCI

Transparent

Bridge

Virtual PCI Bus

Type 1

Configuration Header

PCI-PCI

Transparent Bridge

(Device 0)

Port B

(Downstream Port)

Type 1

Configuration Header

PCI-PCI

Transparent Bridge

(Device 1)

Port C

(Downstream Port)

Figure 1.1 PES12N3 Functional Block Diagram

As shown in Figure 1.1, port A is configured as the upstream port and ports B and C as the downstream
ports. Port B resides on the internal PCI Bus at Device 0, Function 0. Port C resides on the internal PCI Bus
at Device 1, Function 0.

PES12N3 User Manual 1 - 2 June 7, 2006

IDT PES12N3 Device Overview Features

Notes

3-Port Switch Core

Egress

Scheduler

Input Fra m e B uf fe r

PT NP CP

Transaction

Layer

Data Link

Layer

Physical

Layer MAC/PCS

SerDes

Port Arbiter

Route

Map

Table

Retry

Buffer

Egress

Scheduler

Input Fra m e B uf fe r

PT NP CP

Transaction

Layer

Data Link

Layer

Physical

Layer MAC/PCS

SerDes

Port Arbiter

Route

Map

Table

Retry

Buffer

Egress

Scheduler

Input Fra m e Bu f fe r

PT NP CP

Transaction

Layer

Data Link

Layer

Physical

Layer MAC/PCS

SerDes

Port Arbiter

Route

Map

Table

Retry

Buffer

GPIO

Controller

Hot-Plug

Controller

Master
SMBus

Interface

Slave

SMBus

Interface

Port A

Upstream Port

Port B

Downstream Port

Port C

Downstream Porrt

Figure 1.2 PES12N3 Architectural Block Diagram

Features



High Performance PCI Express Switch

– Three x4 ports with 12 PCI Express lanes total
– Delivers 6 GBps (48 Gbps) aggregate switching capacity
– Low latency cut-through switch architecture
– Supports 128 to 2048 byte maximum payload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant



Flexible Architecture with Numerous Configuration Options

– Port arbitration schemes utilizing round robin or weighted round robin algorithms
– Supports automatic per port link with negotiation (x4, x2, or x1)
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy software
– Ability to load device configuration from serial EEPROM



Highly Integrated Solution

– Requires no external components
– Incorporates on-chip internal memory for packet buffering and queueing
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/decoder (no separate transceivers

needed)



Reliability, Availability, and Serviceability (RAS) Features

– Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not

implement end-to-end CRC (ECRC)

PES12N3 User Manual 1 - 3 June 7, 2006

IDT PES12N3 Device Overview System Identification

Notes

– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug

• Compatible with Hot-Plug I/O expanders used on PC motherboards

– Supports Hot-Swap



Power Management

– Supports PCI Express Power Management Interface specification, Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI)

supporting active link state



Testability and Debug Features

– Supports IEEE 1149.6 JTAG
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters



Two SMBus Interfaces

– Slave interface provides full access to all software-visible registers by an external SMBus master
– Master interface provides connection for an optional serial EEPROM used for initialization
– Master interface is also used by an external Hot-Plug

I/O expander

– Master and slave interfaces may be tied together so the PES12N3 can act as both master and

slave



8 General Purpose Input/Output pins



Packaged in 19x19mm 324 ball BCG with 1mm ball spacing

System Identification

Vendor ID

All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech­nology, Inc.

Device ID

The device IDs for the PES12N3 are shown in Table 1.1.

PCI Device

Transparent bridge associ­ated with Ports A, B, and C

Table 1.1 PES12N3 Offset Device IDs

Offset

Device ID

0x8018

PES12N3 User Manual 1 - 4 June 7, 2006

IDT PES12N3 Device Overview System Identification

Notes

Revisio n ID

All revision IDs in the PES12N3 are set to the same value. The value of the revision ID is determined in
one place and is easily modified during a metal mask change. The revision ID shall be incremented with
each all layer or metal mask change.

Revision ID Description

0x1 Corresponds to YA silicon
0x2 Corresponds to YB silicon
0x4 Corresponds to YC silicon

Table 1.2 PES12N3 Revision IDs

JTAG ID

The JTAG ID is:

– Version: Same value as Revision ID. See the Revision ID section above.
– Part number: Same value as base Device ID. See the Device ID section above.
– Manufacture ID: 0x33
– LSB: 0x1

PES12N3 User Manual 1 - 5 June 7, 2006

IDT PES12N3 Device Overview Logic Diagram

Notes

Logic Diagram

Reference

Clock

PCI Express

Switch

SerDes Input

Port A

PCI Express

Switch

SerDes Input

Port B

PEREFCLKP
PEREFCLKN

REFCLKM

PEALREV
PEARP[0]
PEARN[0]

PEARP[1]
PEARN[1]

PEARP[3]
PEARN[3]

PEBLREV
PEBRP[0]
PEBRN[0]

PEBRP[1]
PEBRN[1]

PEBRP[3]
PEBRN[3]

...

...

2
2

PEATP[0]
PEATN[0]

PEATP[1]
PEATN[1]

PCI Express

Switch

SerDes Output

Port A

PEATP[3]
PEATN[3]

PEBTP[0]
PEBTN[0]

PCI Express

Switch

SerDes Output

Port B

...

PEBTP[1]
PEBTN[1]

PEBTP[3]
PEBTN[3]

PCI Express

Switch

SerDes Input

Port C

Master

SMBus Interface

Slave

SMBus Interface

System

Pins

PECLREV

PECRP[0]
PECRN[0]

PECRP[1]
PECRN[1]

PECRP[3]
PECRN[3]

MSMBADDR[4:1]

MSMBCLK
MSMBDAT

SSMBADDR[5,3:1]

SSMBCLK
SSMBDAT

TSTRSVD

MSMBSMODE

CCLKDS
CCLKUS

RSTHALT

PERSTN

SWMODE[3:0]

PES12N3

...

4

4

4

Figure 1.3 PES12N3 Logic Diagram

8

......

PECTP[0]
PECTN[0]

PECTP[1]
PECTN[1]

PECTP[3]
PECTN[3]

GPIO[7:0]

JTAG _ T CK
JTAG _ T DI
JTAG _ T DO
JTAG _ T MS
JTAG _ T RST_N

VDDCORE
V

IO

DD

V

PE

DD

V

APE

DD

V

SS

VTTPE

PCI Express

Switch

SerDes Output

Port C

General Purpose

I/O

JTAG Pins

Power/Ground

PES12N3 User Manual 1 - 6 June 7, 2006

IDT PES12N3 Device Overview Pin Description

Notes

Pin Description

The following tables lists the functions of the pins provided on the PES12N3. Some of the functions
listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being
active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select
lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal Type Name/Description

PEALREV I PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of

PCI Express Port A are reversed. This value may be overridden by modify­ing the value of the PALREV bit in the PA_SWCTL register.

PEARP[3:0]
PEARN[3:0]

PEATP[3:0]

PEATN[3:0

PEBLREV I PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of

PEBRP[3:0]
PEBRN[3:0]

PEBTP[3:0]
PEBTN[3:0]

I PCI Express Port A Serial Data Receive. Differential PCI Express receive

pairs for port A.

O PCI Express Port A Serial Data Transmit. Differential PCI Express trans-

mit pairs for port A

PCI Express Port B are reversed. This value may be overridden by modify­ing the value of the PBLREV bit in the PA_SWCTL register.

I PCI Express Port B Serial Data Receive. Differential PCI Express receive

pairs for port B.

O PCI Express Port B Serial Data Transmit. Differential PCI Express trans-

mit pairs for port B

PECLREV I PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of

PCI Express Port C are reversed. This value may be overridden by modify­ing the value of the PCLREV bit in the PA_SWCTL register.

PECRP[3:0]
PECRN[3:0]

PECTP[3:0]
PECTN[3:0]

REFCLKP[1:0]
REFCLKN[1:0]

REFCLKM I PCI Express Reference Clock Mode Select. These signals select the fre-

I PCI Express Port C Serial Data Receive. Differential PCI Express receive

pairs for port C.

O PCI Express Port C Serial Data Transmit. Differential PCI Express trans-

mit pairs for port C

I PCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif­ferential reference clock is determined by the REFCLKM signal.

quency of the reference clock input.

0x0 - 100 MHz
0x1 - 125 MHz

Table 1.3 PCI Express Interface Pins

PES12N3 User Manual 1 - 7 June 7, 2006

IDT PES12N3 Device Overview Pin Description

Notes

Signal Type Name/Description

MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

Table 1.4 SMBus Interface Pins

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[1] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[2] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN
Alternate function pin type: Input
Alternate function: Hot-Plug I/O expander interrupt input

GPIO[3] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PAABN
Alternate function pin type: Input
Alternate function: Port A attention button Input

GPIO[4] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PAAIN
Alternate function pin type: Output
Alternate function: Port A attention indicator output

GPIO[5] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PAPIN
Alternate function pin type: Output
Alternate function: Port A power indicator output

GPIO[6] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Table 1.5 General Purpose I/O Pins

PES12N3 User Manual 1 - 8 June 7, 2006

IDT PES12N3 Device Overview Pin Description

Notes

Signal Type Name/Description

CCLKDS I Common Cloc k Downstream. The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be override by modifying the SCLK bit in the PB_PCIELSTS
or PC_PCIELSTS register.

CCLKUS I Commo n Cloc k Upstrea m. The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.

MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the

master SMBus should operate at 100 KHz instead of 400 kHz. This value
may not be overridden.

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the

PES12N3 and initiates a PCI Express fundamental reset.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, the PES12N3 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera­tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.

TSTRSVD I Reserved. Reserved for future test mode. Must be tied to ground.

SWMODE[3:0] I Switch Mode. These configuration pins determine the PES12N3 switch

operating mode.

0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - 10-bit loopback test mode
0x9 - Reserved
0xA - Internal pseudo random bit stream self-test test mode
0xB - External pseudo random bit stream self-test test mode
0xC - Reserved
0xD - SerDes broadcast test mode
0xE - 0xF Reserved

Table 1.6 System Pins

PES12N3 User Manual 1 - 9 June 7, 2006

IDT PES12N3 Device Overview Pin Description

Notes

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 1.7 Test Pins

Signal Type Name/Description

V

CORE I Core VDD. Power supply for core logic.

DD

V

IO I I/O VDD. LVTTL I/O buffer power supply.

DD

VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital

power of the SerDes.

VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL

and bias generator.

V

PE I PCI Express Termination Power.

TT

V

SS

I Ground.

Table 1.8 Power and Ground Pins

PES12N3 User Manual 1 - 10 June 7, 2006

IDT PES12N3 Device Overview Pin Characteristics

Notes

Pin Characteristics

Some input pads of the PES12N3 do not contain internal pull-ups or pull-downs. Unused inputs should
be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left
floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in
power consumption.

Function Pin Name Type Buffer

PCI Express Inter­face

PEALREV I LVTTL Input pull-down
PEARN[3:0] I LVDS Serial link
PEARP[3:0] I LVDS Serial link
PEATN[3:0] O LVDS Serial link
PEATP[3:0] O LVDS Serial link
PEBLREV I LVTTL Input pull-down
PEBRN[3:0] I LVDS Serial link
PEBRP[3:0] I LVDS Serial link
PEBTN[3:0] O LVDS Serial link
PEBTP[3:0] O LVDS Serial link

I/O

Type

Internal

Resistor

Notes

PECLREV I LVTTL Input pull-down
PECRN[3:0] I LVDS Serial link
PECRP[3:0] I LVDS Serial link
PECTN[3:0] O LVDS Serial link
PECTP[3:0] O LVDS Serial link
PEREFCLKN[1:0] I LVDS Serial link
PEREFCLKP[1:0] I LVDS Serial link
REFCLKM I LVTTL Input pull-down

SMBus MSMBADDR[4:1] I LVTTL Input pull-up

MSMBCLK I/O LVTTL STI
MSMBDAT I/O LVTTL STI
SSMBADDR[5,3:1] I LVTTL Input pull-up
SSMBCLK I/O LVTTL STI
SSMBDAT I/O LVTTL STI

General Purpose I/O GPIO[7:0] I/O LVTTL Input,

High Drive

Table 1.9 Pin Characteristics (Part 1 of 2)

pull-up

PES12N3 User Manual 1 - 11 June 7, 2006

IDT PES12N3 Device Overview Pin Characteristics

Notes

Function Pin Name Type Buffer

System Pins CCLKDS I LVTTL Input pull-up

CCLKUS I LVTTL Input pull-up
MSMBSMODE I LVTTL Input pull-down
PERSTN I LVTTL Input
RSTHALT I LVTTL Input pull-down
TSTRSVD I LVTTL Input pull-down External pull-

SWMODE[3:0] I LVTTL Input pull-up

JTAG JTAG_TCK I LVTTL STI pull-up

JTAG_TDI I LVTTL STI pull-up
JTAG_TDO O LVTTL Low Drive
JTAG_TMS I LVTTL STI pull-up
JTAG_TRST_N I LVTTL STI pull-up External pull-

Table 1.9 Pin Characteristics (Part 2 of 2)

I/O

Type

Internal

Resistor

Notes

down

down

PES12N3 User Manual 1 - 12 June 7, 2006

Chapter 2

Clocking, Reset, and

Initialization

Notes

Introduction

The PES12N3 has two differential reference clock inputs that are used internally to generate all of the
clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both
reference clock input pairs be driven from a common clock source. There are no skew requirements
between the reference clock inputs.The frequency of the reference clock inputs may be selected by the
Reference Clock Mode Select (REFCLKM) input.

REFCLKM Description

0 100 MHz reference clock input.
1 125 MHz reference clock input.

Table 2.1 Reference Clock Mode Encoding

Each of the reference clock differential inputs feeds six on-chip PLLs. Each PLL generates a 2.5 GHz
clock which is used by four SerDes lanes and produces a 250 MHz core clock.The 250 MHz core clock
output from one of the six internal PLLs is used as the system clock for internal switch logic.

Initialization

A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES12N3
during a fundamental reset when PERSTN is negated. The boot configuration vector defines essential
parameters for switch operation.

While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require configuration via an external serial EEPROM. The external serial EEPR OM allows
modification of any bit in any software visible register. See Chapter 7, SMBus Interfaces, for more informa­tion on the serial EEPROM.

The external serial EEPROM and slave SMBus interface may be used to override the function of some
of the signals in the boot configuration vector during a fundamental reset. The signals that may be over­ridden are noted in Table 2.2.

The state of all of the boot configuration signals in Table 2.2 sampled during the most recent cold reset
may be determined by reading the PA_SWSTS register.

PES12N3 User Manual 2 - 1 June 7, 2006

IDT Clocking, Reset, and Initialization Initialization

Notes

Signal

CCLKDS Y Common Clock Downstream. The assertion of this pin indi-

CCLKUS Y Common Clock Upstream. The assertion of this pin indicates

MSMBSMODE N Master SMBus Slow Mode. The assertion of this pin indicates

PEALREV Y PCI Express Port A Lane Reverse. When this pin is asserted,

PEBLREV Y PCI Express Port B Lane Reverse. When this pin is asserted,

May Be

Overridden

Description

cates that all downstream ports are using the same clock source
as that provided to downstream devices.This pin is used as the
initial value of the Slot Clock Configuration bit in all of the Link
Status Registers for downstream ports. The value may be over­ridden by modifying the SCLK bit in the PB_PCIELSTS or
PC_PCIELSTS register.

that the upstream port is using the same clock source as the
upstream device. This pin is used as the initial value of the Slot
Clock Configuration bit in the Link Status Register for the
upstream port. The value may be overridden by modifying the
SCLK bit in the PA_PCIELSTS register.

that the master SMBus should operate at 100 KHz instead of
400 KHz.

the lanes of PCI Express Port A are reversed. This value may
be overridden by modifying the value of the PALREV bit in the
PA_SWCTL register.

the lanes of PCI Express Port B are reversed. This value may
be overridden by modifying the value of the PBLREV bit in the
PA_SWCTL register.

PECLREV Y PCI Express Port C Lane Reverse. When this pin is asserted,

the lanes of PCI Express Port C are reversed. This value may
be overridden by modifying the value of the PCLREV bit in the
PA_SWCTL register.

REFCLKM N PCI Express Reference Clock Mode Select. These signals

select the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz

Table 2.2 Boot Configuration Vector Signals (Part 1 of 2)

PES12N3 User Manual 2 - 2 June 7, 2006

IDT Clocking, Reset, and Initialization Reset

Notes

Signal

May Be

Overridden

Description

RSTHALT Y Reset Halt. When this signal is asserted during a PCI Express

fundamental reset, the PES12N3 executes the reset procedure
and remains in a reset state with the Master and Slave
SMBuses active. This allows software to read and write regis­ters internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT bit
is cleared in the PA_SWCTL register through the SMBus.

The value may be overridden by modifying the RSTHALT bit in
the PA_SWCTL register.

TSTRSVD N Reserved. Reserved for future test mode. Must be tied to

ground.

SWMODE[3:0] N Switch Mode. These configuration pins determine the

PES12N3 switch operating mode.
0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - 10-bit loopback test mode
0x9 - Reserved
0xA - Internal pseudo random bit stream self-test test mode
0xB - External pseudo random bit stream self-test test mode
0xC - Reserved
0xD - SerDes broadcast test mode
0xE - Reserved
0xF - Reserved

Table 2.2 Boot Configuration Vector Signals (Part 2 of 2)

Reset

PCI Express® defines two reset categories: fundamental reset and hot reset. A fundamental reset
causes all associated logic to be returned to an initial state. A hot reset causes all associated logic to be
returned to an initial state, but does not cause the state of register fields denoted as “sticky” to be modified.

There are two sub-categories of fundamental reset: cold reset and warm reset. A cold reset occurs
following a device being powered on and assertion of PERSTN. A warm reset i s a fundamental reset that
occurs without removal of power.

A summary of reset conditions and their effect is exhibited in Table 2.3.

Global

Fund.
Reset

Hot

Reset to

Entire

Device

Master SMBus Y N N N
Slave SMBus Y N N N
Serial EEPROM Initial-

ization

Y

if mode

NNN

requires it

Global

Hot
Reset to
Downstr

eam

Ports

Local

Hot

Reset

Table 2.3 Reset Conditions and Their Effect (Part 1 of 2)

PES12N3 User Manual 2 - 3 June 7, 2006

IDT Clocking, Reset, and Initialization Reset

Notes

Global

Fund.
Reset

Hot

Reset to

Entire

Device

Switch Core Y Y N (flush

Global

Hot
Reset to
Downstr

eam

Ports

Local

Hot

Reset

N

buffer

only)

Port A All Registers Y N N N
Port A All Registers

YYNN
Except Those of Type
Sticky or RWL

Port A Transaction Layer Y Y N N
Port A Data Link Layer Y Y N N
Port A Phy Layer Y Y N N
Port B All Registers Y N N N
Port B All Registers

YYYN
Except Those of Type
Sticky or RWL

Port B Transaction Layer Y Y Y N
Port B Data Link Layer Y Y Y Y if

selected

Port B Phy Layer Y Y Y Y if

selected

Port B Downstream Hot
Reset Req.

NYYY if

selected
Port C All Registers Y N N N
Port C All Registers

YYYN
Except Those of Type
Sticky or RWL

Port C Transaction Layer Y Y Y N
Port C Data Link Layer Y Y Y Y if

selected

Port C Phy Layer Y Y Y Y if

selected

Port C Downstream Hot
Reset Req.

NYYY if

selected

Table 2.3 Reset Conditions and Their Effect (Part 2 of 2)

PES12N3 User Manual 2 - 4 June 7, 2006

IDT Clocking, Reset, and Initialization Reset

Notes

Fundamental R eset

A fundamental reset of the entire device may be initiated by one of three conditions:

– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input

pin.

– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power

is on.

– A warm reset initiated by the writing of a one to the Reset (RST) bit in the Port A Switch Control

(PA_SWCTL) register.

When the device is configured to operate in a test mode, then the reset sequence described in section
Device Test Modes on page 10-1 is executed. Otherwise, when configured to operate in normal mode, the
following reset sequence is executed.

1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN).

2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.2.

3. On negation of PERSTN, the SWMODE[3:0] signals are examined to determine the switch operating
mode.

4. The PLL is initialized.

5. SerDes CDR Locking and Link training begins. While this is in progress, proceed to step 6.

6. If the Reset Halt (RSTHALT) pin is asserted, the RSTHALT bit in the PA_SWSTS register is set.

7. If the switch operating mode is not a test mode, then the reset to the PCI Express stacks and asso­ciated logic is negated but they are held in a quasi-reset state in which the following actions occur.

All links enter an active Link Training state within 80ms of the clearing of the fundamental reset
condition.

Within 100ms of the clearing of the fundamental reset condition, all of the stacks are able to pro­cess configuration transactions and respond to these transactions with a configuration request retry
status completion. All other transactions are ignored.

8. The master SMBus operating frequency is initialized.

The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is ini­tialized to operate at 100 KHz rather than 400 KHz.

9. The slave SMBus is taken out of reset and initialized.

10. The master SMBus is taken out of reset and initialized.

11. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then
the contents of the serial EEPROM are read and the appropriate PES12N3 registers are updated.

If a one is written by the serial EEPROM to the Link Retrain (LRET) bit in any PCI Express Link
Control (PCIELCTL) register, then link retraining is initiated on that port using the current link
parameters. Note that link retraining may be forced on the upstream port when the REGUNLOCK
bit is set in the PA_SWCTL register.

If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM is
aborted and the RSTHALT bit is set in the PA_SWCTL register. Error information is recorded in the
PA_SMBUSSTS register.

When serial EEPROM initialization completes or when an error is detected, the DONE bit in the

PES12N3 User Manual 2 - 5 June 7, 2006

IDT Clocking, Reset, and Initialization Reset

Notes

PA_SMBUSSTS register is set.

12. Wait for link training on all ports to complete or fail.

1

13. If the Reset Halt (RSTHALT) bit is set in the PA_SWCTL register, all of the logic is held in a reset
state except the master and slave SMBuses, the control/status registers, and the stacks which
continue to be held in a quasi-reset state and respond to configur ation transactions with a retry. The
device remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an
external agent may read and write any internal control and status registers and may access the
external serial EEPROM via the PA_EEPROMINTF register.

14. Normal device operation begins.

The PCIe® standard specifies that normal operation should begin within 1.0 second after a fundamental
reset of a device. The reset sequence above guarantees that normal operation will begin within thi s period
as long as the serial EEPROM initialization process completes within 200 ms. Under normal circumstances,
200 ms is more than adequate to initialize every register in the device even with a Master SMBus operating
frequency of 100 KHz.

Serial EEPROM initialization may cause writes to register fiel ds that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.

The operation of a fundamental reset in Transparent mode with serial EEPROM initialization (i.e.,
SWMODE[3:0] = 0x1) is illustrated in Figure 2.1.

Device ready for
normal operation

Ready for Normal Operation

ReadySerial EEPROM Init ialization

REFCLK*

Vdd

PERSTN

RSTHALT

SerDes
Stacks

Master SMBus

Slave SMBus

Tpvperl

* Clock not shown to scale

Boot vector sampled

1.01 ms

PLL Reset an d Lock

< 100 ms

up to 12 µs

CDR Reset & Lock Ready for Normal Operation

Quasi Reset Mode

< 1 sec

Link Training

Ready

Figure 2.1 Fundamental Reset in Transparent Mode with Serial EEPROM initialization

Hot Reset

A hot reset may be initiated globally to the entire device, globally to downstream ports or locally to down­stream port(s).

Globally Initiated Hot Reset To Entire Device

A hot reset is initiated globally to the entire device when any of the following conditions occur.

– Reception of TS1 ordered-sets on the upstream port indicating a hot reset.
– Data link layer of the upstream port transitions to the DL_Down state.

1.

While link training is in progress, a stack responds to configuration retry requests with a configuration request
retry status completion and ignores all other transactions. This process stops when link training successfully
completes, a device is not detected on the link, or when link training fails 16 times.

PES12N3 User Manual 2 - 6 June 7, 2006

IDT Clocking, Reset, and Initialization Reset

Notes

Hot reset is only propagated downstream. TS1 ordered-sets indicating a hot reset received on a down-

stream port do not result in a hot reset of the downstream port or any function inside the switch.

When a globally initiated hot reset occurs, all of the logic associated with the transparent bridges, stacks
and the switch core are reset except for the PLLs, SerDes, master SMBus interface, slave SMBus interface,
and some registers. Regardless of the switch operating mode, a hot-reset does not result in reloading of the
serial EEPROM.

The value of register fields denoted as “sticky” or as Read and Write when Unlocked (i.e., RWL) are
preserved in all ports across a hot-reset. All other register fields in all ports are reset to their initial values.

When a hot reset is initiated globally, each downstream port shall send a hot-reset message to its link
partner prior to being reset.

Globally Initiated Hot Reset To Downstream Ports

A hot reset is initiated globally to downstream ports when the following condition occurs

– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (port A) Bridge

Control Register (BCTRL). See BCTRL - Bridge Control (0x03E) on page 9-25.

When a globally initiated hot reset is initiated to downstream ports, all of the logic associated with the
transparent bridges, stacks and FIFOs in the switch core associated with the downstream ports are reset
except for the PLLs, SerDes, master SMBus interface, slave SMBus interface, and some registers. Regard­less of the switch operating mode, it does not result in reloading of the serial EEPROM.

The value of register fields denoted as “sticky” or as Read and Write when Unlocked (i.e., RWL) in
downstream ports are preserved. All other register fields are reset to their initial values.

When a hot reset is initiated globally to downstream ports, each downstream port shall send a hot-reset
message to its link partner prior to being reset.

Unlike a globally initiated hot reset to the entire device, a globally initiated hot reset to downstream ports
does not affect the state of the upstream port’s configuration register except those required to update port
status.

Locally Initiated Hot Reset to a Downstream Port

A hot reset is initiated locally to a downstream port by writing to the SRESET bit of a downstream port’s
BCTRL registers. When this occurs, a hot-reset message is sent on that port to its link partner. After the
message is sent, the phy layer is effectively reset.

A locally initiated hot reset does not affect the state of any port (i.e., transparent bridge) configuration
register except those required to update port status.

PES12N3 User Manual 2 - 7 June 7, 2006

IDT Clocking, Reset, and Initialization Reset

Notes

PES12N3 User Manual 2 - 8 June 7, 2006

Chapter 3

Link Operation

Notes

Introduction

The PES12N3 contains three ports. The default link width of each port is x4 and the SerDes lanes are
statically assigned to a port.

Polarity Inversion

Each port of the PES12N3 supports automatic polarity inversion as required by the PCIe® specification.
Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its data.
During link training, the receiver examines symbols six through 16 of the TS1 and TS2 ordered sets for
inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receiving lane
automatically inverts received data.

Polarity inversion is a lane and not a link function. Therefore, it is possible for some lanes of link to be
inverted and for others to not be inverted.

Link Width Negotiation

The PES12N3 supports the option link variable width negotiation feature outlined in the PCIe specifica­tion. During link training, Each of the x4 ports is capable of negotiating to a x4, x2 or x1 link width. The
negotiated width of each link may be determined from the Link Width (LW) field in the corresponding port’s
PCI Express® Link Status (PCIELSTS) register.

The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCA P)
register contains the maximum link width of the port. This field is of RWL type and may be modified when
the REGUNLOCK bit is set in the PA_SWCTL register. Modification of this field allows the maximum link
width of the port to be configured. The new link width takes effect the next time link training occurs.

To force a link width to x2 despite a link partner’s ability to negotiate to x4, the MAXLNKWDTH field
could be configured through Serial EEPROM initialization and link retraining forced. Assuming the link
partner has a link width greater than or equal to x2 and the capability to negotiate to a width of x2, the link
width will negotiate to x2.

When a link negotiates to a width less than x4, the unused lanes are put in a low power state (i.e. L1
state).

Lane Reversal

The PCIe specification describes an optional lane reversal feature. The PES12N3 does not support the
automatic lane reversal feature outlined in the PCIe specification. How ever, it does support static lane
reversal on a per port basis.

Associated with each PES12N3 switch port is a lane reversal signal. The lane reversal s ignal for port A
is PEALREV, for port B is PEBLREV, and port C is PECLREV. The status of the lane reversal s ignals
sampled during a fundamental reset may be determined from the PALREV, PBLREV and PCLREV fields in
the PA_SWSTS register.

The port lane reversal signals are sampled during a fundamental reset and used as the initial value of
the PALREV, PBLREV and PCLREV fields in the PA_SWCTL register. When these bits are set, then the
lanes of the corresponding port(s) are reversed during link training.

Lane reversal mapping for the various non-trivial maximum link width configurations is illustrated in
Figures 3.1 and 3.2.

PES12N3 User Manual 3 - 1 June 7, 2006

IDT Link Operation Lane Reversal

Notes

PES12N3

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

lane 0
lane 1
lane 2
lane 3

(a) x4 Port with PExLREV negated

PES12N3

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

lane 0
lane 1

(c) x2 Port with PExLREV negated

lane 0

PES12N3

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES12N3

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

lane 3
lane 2
lane 1
lane 0

(b) x4 Port with PExLREV asserted

PExRP[0]

PES12N3

PExRP[1]
PExRP[2]
PExRP[3]

lane 1
lane 0

(d) x2 Port with PExLREV asserted

PExRP[0]

PES12N3

PExRP[1]
PExRP[2]
PExRP[3]

lane 0

(e) x1 Port with PExLREV negated

(f) x1 Port with PExLREV asserted

Figure 3.1 Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[1:0]=0x2)

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

PES12N3

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

lane 0
lane 1

(a) x2 Port with PExLREV negated

lane 0

PES12N3

PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]

(c) x1 Port with PExLREV negated

PES12N3

(b) x2 Port with PExLREV asserted

PES12N3

(d) x1 Port with PExLREV asserted

lane 1
lane 0

lane 0

Figure 3.2 Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[1:0]=0x1)

PES12N3 User Manual 3 - 2 June 7, 2006

IDT Link Operation Link Retraining

Notes

When link training occurs, the corresponding lane reversal bits in the PA_SWCTL register are examined.
If a bit is set, then the lanes associated with that link are revered. This mechanism may be used to configure
lane reversal via the serial EEPROM, slave SMBus, or root.

Link Retraining

Link retraining should not cause either a downstream component or an upstream component to reset or
revert to default values.

Link Down

When a link goes down, all TLPs received by the port and queued in the switch are discarded and all
TLPs received by other ports and destined to the port whose link is down are treated as Unsupported
Requests (UR). While a link is down, it is possible to perform configuration read and write operations to the
PCI-PCI bridge associated with the link. However, it is possible to lose configuration read or write comple-

tions when TLPs queued in the switch are discarded.
with the transaction(s) will time-out and the transaction will be retired.

When a link comes up, flow control credits for the configured size of the IFB FIFOs are advertised.

1

If this occurs, the root’s completion timer associated

Slot Power Limit Support

The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream
switch port (i.e., ports B or C) to the upstream port of a connected device or switch. A
Set_Slot_Power_Limit message is set by downstream switch ports when either of the following events
occurs:

– A configuration write is performed to the corresponding PCIESCAP register when the link associ-

ated with the downstream port is up.

– A link associated with the downstream port transitions from a non-operational state to an opera-

tional (i.e., up) state.

1.

In the case of a configuration write that causes link retraining or a secondary bus reset, a completion corre-

sponding to the configuration write is always returned and never lost.

PES12N3 User Manual 3 - 3 June 7, 2006

IDT Link Operation Slot Power Limit Support

Notes

PES12N3 User Manual 3 - 4 June 7, 2006

Chapter 4

Switch Operation

Notes

Introduction

The PES12N3 utilizes an input buffered cut-through switch to forward PCIe® TLPs between sw itch
ports. At a high level the switch may be viewed as consisting of three PCIe s tacks and a switch core. The
PCIe stacks are each responsible for performing the per port Phy, data link and transaction layer functions
defined in the PCIe specification. The switch core is responsible for maintaining routing information in route
map tables, maintaining per port ingress and egress flow control information, buffering TLPs, and
forwarding TLPs between stacks.

An architectural block diagram of the PES12N3 and switch core is provided in Figure 1.2 of Chapter 1.
The buffering and data flow of the switch is graphically depicted in Figure 4.1 below.

Note that an ingress stack can transfer a TLP to its own egress stack through the switch core. This path
is necessary since all transactions in the PES12N3 are routed through the switch core, even those that
could be satisfied locally, due to the fact that the switch core is responsible for maintaining flow control infor­mation.

Port A

Link

Input

Port A Stack

Ingress Functions

Posted FIFO

Non-Posted FIFO

Completion FIFO

Port A Stack

Egress Functions

Replay Buffer

Port A

Link

Output

Port B

Link

Input

Port C

Link

Input

Port B Stack

Ingress Functions

Port C Stack

Ingress Functions

Posted FIFO

Non-Posted FIFO

Completion FIFO

Posted FIFO

Non-Posted FIFO

Completion FIFO

Port B Stack

Egress Functions

Replay Buffer

Port C Stack

Egress Functions

Replay Buffer

Port B

Link

Output

Port C

Link

Output

Figure 4.1 PES12N3 Switch Data Flow and Buffering

TLPs are received by a port stack and passed to the switch core. Associated with each port in the switch
core are three input buffers. One for posted transactions, one for non-posted transactions and one for
completions. The size of each of these buffers is shown in T able 4.1. Associated with each TLP in a buffer is
a descriptor. Thus, a buffer has a limitation on the total number of TLPs that can be stored as well as on the
number of bytes.

PES12N3 User Manual 4 - 1 June 7, 2006

IDT Switch Operation Introduction

Notes

Buffer Size and Limitations

Posted FIFO 4 KB and up to 32 TLPs

Non-posted FIFO 1 KB and up to 32 TLPs

Completions FIFO 4 KB and up to 32 TLPs

Egress Stack Replay Buffer

1

5120 bytes and up to 15 TLPs

1.

Stored with each TLP is a 32-bit LCRC as well as other information.

Table 4.1 PES12N3 Buffer Sizes

A flow control mechanism exists between the switch buffers and the transaction layer in the ingress
stack to prevent overflows. This flow c ontrol mechanism forms the basis of the PCIe flow control credits
advertised by the stack to the ingress port’s link partner. When a TLP is sent to the switch core from an
ingress stack, its header is looked-up in a routing map table and the TLP is queued in a buffer that corre­sponds to the TLP type (i.e., posted, non-posted or completion).

Scheduling of a TLP to be forwarded from an input buffer to an egress stack is performed by an egress
scheduler and port arbiter associated with each egress stack. Thus, the PES12N3 has three egress sched­uler and three port arbiters. A flow control mechanism exists between the egress scheduler and the trans­action layer in the egress stack. This flow control mechanism ensures that only TLPs which may be
accepted by the egress stack’s link partner are forwarded through the switch.

TLPs are routed in a cut-through manner through the PES12N3 if the ingress link width is greater than
or equal to the egress link width. If the ingress link width is less than the egress link width, then the entire
TLP must be received before it is forwarded. The egress scheduler selects the TLP from each ingress port
that may be forwarded to the associated egress port. If multiple ingress ports have TLPs which may be
forwarded to the same egress port, the port scheduler selects the ingress port from which a TLP is
forwarded.

Associated with each TLP in an input buffer is a timestamp. An egress scheduler always selects the TLP
in the input buffer that contains the oldest timestamp. If that TLP is destined for a different egress port, then
the egress scheduler makes no selection for that input port (i.e., TLPs are always forwarded from an
ingress port in chronological order). TLP timestamps are also used to discard any TLP from the head of an
input buffer that is more than 50 ms old. See section Switch Time-Outs on page 4-5 for additional details.

In making its selection, the egress scheduler considers the PCIe ordering rules. The PES12N3 supports
relaxed ordering for requests as well as completions. When the Disable Relaxed Ordering (DRO) bit is set
in the port A Switch Control (SWCTL) register, the switch strongly orders all transactions regardless of the
state of the relaxed ordering bit in TLPs.

The port scheduler associated with each egress port in the PES12N3 supports hardwired round robin
and weighted round robin with 32 phases. Both of these algorithms only arbitrate TLP requests and do not
consider bandwidth consumption.

In addition to the input buffers in the switch core, each egress stack contains a replay FIFO. When the
replay buffer fills, backpressure is provided to the switch core and no TLPs are forwarded to that egress
port. Table 4.2 enumerates the default flow control credits advertised by each port of the switch core.

PES12N3 User Manual 4 - 2 June 7, 2006

IDT Switch Operation Routing

Notes

Flow Control

Category

Posted Header 30 credits Each credit represents 20 bytes (i.e., 5 doublewords) for a max-

Posted Data 204 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-

Non-Posted Header 30 credits Each credit represents 20 bytes (i.e., 5 doublewords) for a max-

Non-Posted Data 30 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-

Completion Header 30 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-

Completion Data 204 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-

Default

Advertised

Credits

imum of 600 bytes

imum of 3264 bytes

imum of 600 bytes

imum of 480 bytes (note that non-posted data is assumed to
consists of only one doubleword per header)

imum of 480 bytes

imum of 3264 bytes

Table 4.2 PES12N3 Advertised Flow Control Credits

Notes

Each header credit is allocated 20 bytes (3 double doublewords) in a FIFO regardless of whether or not
a credit represents 16 or 20 bytes. Each posted and completion data credit is allocated 16 bytes (2 double
doublewords) in a FIFO. Non-posted data credits are allocated 8 bytes (one double doubleword). Two
header and data credits are reserved in each FIFO for TLPs generated by the switch (e.g., configuration
read completions).

The header and data flow control credits advertised may be configured on a per port basis via the Flow
Control Credit Posted Configuration (FCPTCFG), Flow Control Credit Non-Posted Configuration
(FCNPCFG) and Flow Control Credit Completion Configuration (FCCPCFG) registers. These registers may
only be modified using the serial EEPROM or during initialization via the SMBus when the RSTHALT bit is
set in the PA_SWCTL register. Modifying these registers in a running system produces undefined results.

Routing

The PES12N3 supports routing of all transaction types defined in the PCIe specification. This includes
routing using in specification defined transactions as well as those that may be used in vendor defined
messages and in future revisions of the PCIe specifications.

Specifically, the PES12N3 supports the following type of routing:

– Address routing with 32-bit or 64-bit format
– ID based routing using bus, device and function numbers.
– Implicit routing utilizing

Route to root
Broadcast from root
Local - terminate at receiver
Gathered and routed to root

– A summary of TLP types that use the above routing methods is provided in Table 4.3.

PES12N3 User Manual 4 - 3 June 7, 2006

IDT Switch Operation Data Integrity

Notes

Routing Method

Route by Address MRd, MrdLk, MWr, IORd, IOWr, Msg, MsgD
ID Based Routing CfgRd0, CfgWr0, CfgRd1, CfgWr1, Cpl, CpdD, CplLk, CplDLk,

Msg, MsgD
Imlicit Routing - Route to Root Msg, MsgD
Implicit Routing - Broadcast from Root
Implicit Routing - Local Msg, MsgD

1

Msg, MsgD

TLP Type Using Routing Method

Implicit Routing - Gathered and Routed to
Root

1.

Broadcast from root messages are only accepted from the root port (i.e., port A). An unsupported request is generated

if a TLP with this routing method is received from any other port.

Only supported for PME_TO_Ack messages in response to a

root initiated PME_Turn_Off message.

Table 4.3 Switch Routing Methods

Data Integrity

PCI Express® provides reliable hop-by-hop communication between interconnected devices, such as
roots, switches, and endpoints, by utilizing a 32-bit Link CRC (LCRC), sequence numbers, and a link level
retransmission protocol. While this mechanism provides reliable communication between interconnected
devices, it does not protect against corruption that may occur inside of a device. PCI Express defines an
optional end-to-end data integrity mechanism that consists of appending a 32-bit end-to-end CRC (ECRC)
computed at the source over the invariant fields of a Transaction Layer Packet (TLP) that is checked at the
ultimate destination of the TLP. While this mechanism provides end-to-end error detection, unfortunately it
is an optional PCI Express feature and has not been implemented in some North bridges and endpoints. In
addition, the ECRC mechanism does not cover variant fields within a TLP.

Since deep sub-micron devices are known to be susceptible to single-event-upsets, a mechanism is
desired that detects errors that occur within a PCI express switch. The PES12N3 parity protects all TLPs in
the switch, thus enabling corruption that may occur inside of the device to be detected and reported even in

systems that do not implement ECRC.

Associated with each port of the PES12N3 is a PCI-PCI bridge. Located in the switch integrity region in
extended configuration space of each PCI-PCI bridge are the Switch System Integrity Control (SWSICTL)
and Switch System Integrity Parity Error Count (SWSIPECNT) registers. These registers provide control
and status over switch errors associated with that switch port and may be read by a root or via the slave
SMBus interface.

1

Data flowing into the PES12N3 is protected by the LCRC. Within the Data Link (DL) layer of the switch
ingress port, the LCRC is checked and 32-bit Doubleword (DWord) even parity is computed on the received
TLP data. If an LCRC error is detected at this point, the link level retransmission protocol is used to recover
from the error by forcing a retransmission by the link partner. As the TLP flows through the switch, its align­ment or contents may be modified. In all such cases, parity is updated and not recomputed. Hence, any
error that occurs is propagated and not masked by a parity regeneration. When the TLP reaches the DL
layer of the switch egress port, parity is checked and in parallel a LCRC is computed. If the TLP is parity
error free, then the LCRC and TLP contents are known to be correct and the LCRC is used to protect the
packet through the lower portion of the DL layer, PHY layer, and link transmission.

If a parity error is detected by the DL layer of an egress port, then the TLP is null ified by inverting the
computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by the link-partner are
discarded. In addition to nullifying the TLP, the PES12N3 performs the following when a parity error is
detected: sends an error non-fatal (ERR_NONFATAL) message (if this message reporting is enabled) to the

1.

Nullified TLPs are not parity protected and no parity errors are reported for nullified TLPs since these TLPs are

discarded.

PES12N3 User Manual 4 - 4 June 7, 2006

IDT Switch Operation Switch Time-Outs

Notes

root; increments the End-to-End Parity Error Count (EEPERRC) field in the SWS IPECNT register associ­ated with the port on which the error was detected; and sets the Detected Parity Error (DPE) bit in the
PCISTS register if the error was detected by a downstream port or sets DPE bit in the PCI Secondary
Status (SECSTS) register if the error was detected by an upstream port.

To prevent error flooding, error messages are not sent to the root once the EEPERRC field saturates.
Since PCI Express switches do not normally generate ERR_NONFATAL messages, the Silent End-to-End
Parity Checking bit (SEEPC) bit in the SWSICTL register is provided to disable generation of error
messages and setting of the Detected Parity Error bit when internal corruption is detected.

The default state of the switch following a fundamental reset is to enabl e this error reporting. (Note that
the Device Control register in the PCI Express capability structure also has a bit that enables generation of
ERR_NONFATAL messages and that the default value of this bit is to disable these messages.)

In addition to TLPs that flow through the switch, cases exist in which TLPs are produced and consumed
by the switch (e.g., a configuration requests and responses). Whenever a TLP is produced by the switch,
parity is computed as the TLP is generated. Thus, error protection is provided on produced TLPs as they
flow through the switch. In addition, parity is checked on all consumed TLPs. If an error is detected, the TLP
is discarded and an error is reported using the mechanism described above.

This means that a parity error reported at a switch port cannot be definitively used to identify the location
at which the error occurred as the error may have occurred when parity as generated at another port, in the
switch core, or may have been generated locally (i.e., for ingress TLPs to the switch core which are
consumed by the port such as Type 0 configuration read requests on the root port).

Switch Time-Outs

The switch discards any TLP that reaches the head of an input buffer and is more than 50ms old.

For non-posted and completion TLPs, the requester’s completion time-out mechanism will detect
discarded TLPs. No similar mechanism exists in PCIe for posted TLPs. Therefore, whenever a posted TLP
is discarded by the switch due to a time-out, an error non-fatal (ERR_NONFATAL) message (if this
message reporting is enabled) is sent to the root.

Whenever a TLP is discarded from a posted input buffer, the Posted TLP Time-out Count (PTLPTOC)
field is incremented in the Switch System Integrity Time-Out Drop Count (SWSITDCNT) register in the port
on which the TLP was received. This is a saturating counter that is automatically cleared when read. When­ever a TLP is discarded from a non-posted input buffer, the Non-Posted TLP Time-out Count (NPTLPTOC)
field is incremented in this register and whenever a TLP is discarded from a completion input buffer, the
Completion TLP Time-out Count (NPTLPTOC) field is incremented.

To prevent error flooding, error messages are not sent to the root once the PTLPTOC counter saturates.
Since PCI Express switches do not normally generate ERR_NONFATAL mess ages, the Silent Posted TLP
Time-out (SPTLPTO) bit in the SWSICTL register is provided to disable generation of error non-fatal
messages. When this bit is set, ERR_NONFATAL messages are not generated when posted transactions
received on the corresponding port are discarded. The PTLPTOC field however is always updated.

Locking

The PES12N3 supports locked transactions, allowing legacy software to run without modification on
PCIe. Only one locked transaction sequence may be in progress at a time. A locked transaction sequence
is requested by the root by issuing a Memory Read Request - Locked (MRdLk) transaction. A lock is estab­lished when a lock request is successfully completed with a Completion with Data - Locked (CplDLk). A lock
is released with an Unlock message (Msg).

PES12N3 User Manual 4 - 5 June 7, 2006

IDT Switch Operation Locking

Notes

When the PES12N3 receives a MRdLk transaction on its root port destined for a down-stream port, it
forwards the MRdLK transaction to the downstream port and locks the downstream port so that all subse­quent TLPs destined to the downstream port from ports other than the root are blocked until the lock is
released.

– The MRdLK transaction obeys PCI ordering rules meaning that all queued posted requests for the

downstream port are completed prior to the MRdLK being transmitted. The MRdLK is allowed by
bypass queued non-posted requests and completions.

– When only the downstream port is locked, no transactions destined to any other port are blocked

(e.g., transactions from the other downstream ports to the upstream port are not blocked)•

When a CplDLk is returned by the locked downstream port, the upstream port becomes locked causing
all transactions destined to the upstream port from sources other than the locked downstream port (e.g., the
other downstream port) to be blocked. If the lock is unsuc cessful, then a CPlLk is returned by the down­stream port and the upstream port does not become locked.

– The CplDLk transaction obeys PCI ordering rules

1

meaning that all queued posted requests at the
locked downstream port destined to the upstream port are completed prior to the CplDLk being
transmitted. The CplDLk is allowed by bypass queued non-posted requests and completions.

– When a CplDLk is returned by the locked downstream port and the upstream port becomes

locked, the entire switch becomes locked. This means that only transactions between the
upstream and the locked downstream port are allowed to progress. All other transactions, such
as transactions from the other downstream port, hot plug messages, MSI/INT messages, etc. are
blocked until the switch is unlocked.

– While the switch is locked, any register in the switch may be read or written via the SMBus
– While the switch is locked, it is illegal to read or write any of the PCIe configuration space headers

in the switch since the switch can not generate a completion until the switch is unlocked. This
means that the LOCKMODE field in the PA_SWSTS register can only be read via the SMBus
when the switch is locked.

– The behavior of the switch is undefined when any transaction other than a MWr, MRdLk, and

Unlock message is received on the upstream port when the switch is locked.

– The behavior of the switch is undefined when any transaction other than a CplLk and a CplDLk is

received on the locked downstream port when the switch is locked.

Once the switch is locked, it is possible for the root to perform subsequent reads from the locked device
by issuing a MRdLk requests to the locked device and receiving a CplDLk or CplLk response from the
locked device. These transactions do not change the state of the switch when the switch is locked. There­fore, a CplLk completion once the switch is locked in no way “unlocks” the switch.

Once the switch is locked, it is possible for the root to perform subsequent writes to the locked device by
issuing MWr requests to the locked device. These transactions in no way change the state of the switch
when the switch is locked.

When an Unlock message is received on the upstream port, the switch is unlocked. This causes the
Unlock message to be forwarded to the locked downstream port and the unblocking of transactions
destined to the upstream and previously locked downstream port.

When a TLP from a downstream port is blocked from being forwarded due to a locked switch, then the
TLP is delayed until the switch is unlocked. If the switch is locked for an extended period, this may cause
TLPs to be discarded due to switch time-outs (see section Switch Time-Outs on page 4-5).

When a MRdLk TLP is received on the upstream port, then the TLP is dropped due to a lock violation
and the lock drop (LOCKDROP) bit is set i n the PA_SWSTS register. If error reporting is enabled, an
ERR_NON_FATAL message is sent to the root when the switch is unlocked.

When the upstream port is locked with a downstream port and a TLP is received by slipstream port that
is destined to the unlocked downstream port, then the TLP is dropped, the Lock Discarded (LOCKDIS) bit is
set in the PA_SWSTS register. If error reporting is enabled, an ERR_NON_FATAL message is sent to the
root when the switch is unlocked.

1.

The relaxed ordering is ignored.

PES12N3 User Manual 4 - 6 June 7, 2006

IDT Switch Operation Interrupts

Notes

The PME Lock Error (PMELOCK) bit in the PA_SWSTS register is set and the transaction is dropped
when a PME_Turn_Off message is received by a locked downstream PCI-PC I bridge (i.e., that associated
with port B or C). If error reporting is enabled, an ERR_NON_FATAL message is sent to the root when the
switch is unlocked.

The locked status of the switch may be determined by examining the Lock Mode (LOCK-MODE) bit in
the PA_SWSTS register

Interrupts

The PES12N3 supports legacy PCI INTx emulation where x is A, B, C or D. Rather than use sideband
INTx signals, PCIe defines two messages that indicate the assertion and negation of an interrupt signal. An
Assert_INTx message is used to signal the assertion of an interrupt signal and an Deassert_INTx message
is used to signal its negation.

The PES12N3 maintains an aggregated INTx state for each of the four interrupt signals (i.e., A through
D). The value of the INTA, INTB, INTC and INTD aggregated state may be determined by examining the
corresponding fields in the PA_SWSTS register . The aggregated INTx state of each port for each of the four
interrupt signals (i.e., A through D) on the primary side of its PCI to PCI bridge may be determined by exam­ining the state of the INTA, INTB, INTC and INTD fields in the corresponding port’s Interrupt Status
(PA_INTSTS, PB_INTSTS, and PC_INTSTS) register.

An Assert_INTx message is sent to the root by the upstream port (i.e., port A), when the aggregated
state of the corresponding interrupt in the switch transitions from a negated to an asserted state. A
Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the corre­sponding interrupt transitions from an asserted to a negated state.

Table 4.4 exhibits the interrupt sources that are aggregated by the switch.

PCI Compatible

INTx

INTA - External downstream port B

- External downstream port C

- Port B PCI-PCI bridge (hot-plug)

INTB - External downstream port B

- External downstream port C

- Port C PCI-PCI bridge (hot-plug)

INTC - External downstream port B

- External downstream port C

INTD - External downstream port B

-External downstream port C

Table 4.4 PCI Compatible INTx Aggregation

Interrupt Sources

PCI to PCI bridges must map interrupts on the secondary side of the bridge according to the device
number of the device on the secondary side of the bridge. No mapping is performed for the PCI to PCI
bridges corresponding to downstream ports as these ports only connect to device zero. A mapping is
performed for the upstream port (i.e., port A).This mapping is summarized in Table 4.6 for the PES12N3.

PES12N3 User Manual 4 - 7 June 7, 2006

IDT Switch Operation Switch Core Errors

Notes

Port A Interrupt Interrupt Sources

INTA Port B INTA

Port C INTD

INTB Port B INTB

Port C INTA

INTC Port B INTC

Port C INTB

INTD Port B INTD

Port C INTC

Table 4.5 PES12N3 Upstream Port Bridge Interrupt Mapping

1.

Port X INTy corresponds to external downstream generated INTy interrupts and hot-

plug INTy interrupts generated by the port.

If a Downstream Port goes to DL_Down status, the INTx virtual wires associated with that port are deas­serted, and the port A aggregates are updated accordingly. This may result in the upstream port generating
a Deassert_Intx message.

1

Switch Core Errors

This section lists error conditions that are checked by the switch core. Due to limited buffering of Unsup­ported Request (UR) completions, it is possible for the PES12N3 to discard UR completions if errors are
generated faster than UR completions can be transmitted. Even when UR completions are discarded, error
status bits are always correctly updated and an error message is generated.

Due to limited buffering, error messages may be collapsed if errors are generated faster than error
messages can be transmitted. This means that multiple error conditions may result in only a single error
message being generated. However, under no circumstances are error messages discarded.

Port arbitration should never be configured to starve a port. If a port arbitration table configuration
results in port starvation, then TLPs generated by the port may be dropped (e.g., error messages, inter­rupts, configuration completions, etc.).

The following events received by the switch core from the upstream port are treated as Unsupported
Requests (UR), and for non-posted transactions, result in a Unsupported Request (UR) completion being
returned to the upstream port.

– Reception of a CfgRd0 or CfgWr0 TLP. All CfgRd0 and CfgWr0 TLPs should have been received

and processed by the upstream stack. Therefore, the upstream stack should never pass a CfgRd0
or CfgWr0 to the switch core.

– Reception of a CfgRd1 or CfgWr1 TLP that is transformed into a CfgRd0 or CfgWr0 TLP destined

to the link partner of a downstream port and in which the device number is non-zero (covers condi­tion outlined in PCIe base 1.0a Section 7.3.1). The device number must be zero in CfgRd0 and
CfgWr0 transactions to a downstream link partner.

– Reception of Msg or MsgD TLPs with route by address routing prior to initialization of the PCI-PCI

bridge. Prior to initialization of the PCI-PCI bridge, no transactions should be routed to the switch
core.

– Reception of route by address TLPs whose address matches an upstream port’s memory or I/O

base/limit pair and does not match a downstream ports’ memory or I/O base/limit pair. TLPs that
have no route (i.e., not destined for any upstream or downstream port) should be treated as
unsupported requests.

– Reception of route by address TLPs destined to the upstream port. There are no route by address

TLPs that should have been destined to the upstream port since the upstream port does not
process these types of TLPs.

PES12N3 User Manual 4 - 8 June 7, 2006

IDT Switch Operation Switch Core Errors

Notes

– Reception of TLPs that have no route (i.e., do not match an address or ID route through the

switch). TLPs that have no route should be treated as unsupported requests.

– Reception of a TLP destined to a disabled downstream port (link down or MAE/IOAE bit cleared

in PA_PCICMD register). TLPs destined to a disabled downstream port should be treated as
unsupported requests.

– Reception of a TLP that matches a VGA region and the VGA Enable (VGAEN) bit is set in the

upstream port but the TLP does not map to either downstream port (i.e., VGAEN is cleared in both
downstream ports and the transaction does not map to any of the base/limit pairs associated with
the downstream ports).

The following events received by the switch core from the downstream ports are treated as Unsupported
Requests (UR) and for non-posted transactions, result in a Unsupported Request (UR) completion to be
returned to the port on which the TLP was received.

– Reception of Msg or MsgD TLPs with route by address routing prior to initialization of the PCI-PCI

bridge. Prior to initialization of the PCI-PCI bridge, no transactions should be routed to the switch
core.

– Reception of Msg or MsgD TLPs with route by ID to the PCI-PCI bridge primary bus number after

bus enumeration has completed. There are no entities that generate accept messages on the
virtual PCI bus within the switch (i.e., the primary bus number).

– Reception of route by address TLPs whose address matches an upstream port’s memory or I/O

base/limit pair and does not match a downstream ports’ memory or I/O base/limit pair. TLPs that
have no route (i.e., not destined for any upstream or downstream port) should be treated as
unsupported requests.

– Reception of TLPs that have no route (i.e., do not match an address or ID route through the

switch). TLPs that have no route should be treated as unsupported requests.

– Reception of any configuration TLP . Configuration requests can only be generated by the root and

received on the upstream port.

– Reception of a route by ID TLP to a port that has its primary bus number set to its secondary bus

number. Such a port is uninitialized.

– Reception of a TLP that utilizes implicit routing - broadcast from root. Such a TLP can only be

received by the upstream port.

– Reception of a TLP that matches a VGA region in a downstream port when the downstream port’s

VGA Enable (VGAEN) bit is set in its Bridge Control (BCTRL) register.

– Reception of a TLP destined to a disabled downstream port (link down or MAE/IOAE bit cleared

in PCICMD register) or the upstream port when the Bus Master Enable (BME) bit is not set in the
PCICMD register. TLPs destined to a disabled downstream port should be treated as unsupported
requests.

PES12N3 User Manual 4 - 9 June 7, 2006

IDT Switch Operation Switch Core Errors

Notes

PES12N3 User Manual 4 - 10 June 7, 2006

Chapter 5

Power Management

Notes

Introduction

A power management capability structure is located in the configuration space of each PCI-PCI bridge
in the PES12N3. The structure associated with a PCI-PCI bridge of a downstream port only affects that
port. Entering the D3

The power management capability structure associated with the root port (i.e., port A) affects the entire
device. When the root port enters a low power state and the PME_TO_Ack messages are received, then
the entire device is placed into a low power state. The PES12N3 supports the following device power
management states: D0 Uninitialized, D0 Active, D3

ment state from D3
values.

A power management state transition diagram for the states supported by the PES12N3 is provided in
Figure 5.1 and described in Table 5.6.

state allows the link associated with the bridge to enter the L1 state.

hot

hot

to D0

uninitialized

Power-On Reset

, and D3

hot

does not result in any logic being reset or re-initialization of register

D0

Uninitialized

D0

Active

. Transitioning a port’s power manage-

cold

D3

hot

D3

cold

Figure 5.1 PES12N3 Power Management State Transition Diagram

PES12N3 User Manual 5 - 1 June 7, 2006

IDT Power Management Link States

Notes

From State To State Description

Any D0 Uninitialized Power-on fundamental reset.

D0 Uninitialized D0 Active PCI-PCI bridge configured by software

D0 Active D3

D3

D3

hot

hot

D0 Uninitialized The Power Management State (PMSTATE) field in the PCI Power

D3

Table 5.6 PES12N3 Power Management State Transition Diagram

hot

cold

The Power Management State (PMSTATE) field in the PCI Power
Management Control and Status (PMCSR) register is written with
the value that corresponds to the D3

Management Control and Status (PMCSR) register is written with
the value that corresponds to D0 state.

Power is removed from the device.

hot

state.

PME Messages

The PES12N3 does not support generation of PME messages from the D3

state. Downstream ports

cold

(i.e., PCI-PCI bridges associated with ports B and C) support the generation of hot-plug PME events (i.e., a
PM_PME power management message) from the D3

stream port is in the D3

state or the entire switch is in the D3

hot

state. This includes both the case when the down-

hot

state. The generation of a PME message

hot

by downstream ports necessitates the implementation of a PME service time-out mechanism to ensure that
PME messages are not lost.

Link States

The PES12N3 supports the following link states:

– L0 — Fully operational link state
– L0s — Automatically entered low power state with shortest exit latency
– L1 — Lower power state than L0s. May be automatically entered or directed by software by

placing the device in the D3

– L2/L3 Ready — The L2/L3 state is entered after the acknowledgement of a PM_Turn_Off

Message. There is no TLP or DLLP communications over a link in this state.

– L3 — Link is completely unpowered and off.

Link states are shown in Figure 5.2.

hot

state.

PES12N3 User Manual 5 - 2 June 7, 2006

IDT Power Management Active State Power Management

Notes

L0s L1

L0

L2/L3 Ready

L3

Figure 5.2 PES12N3 ASPM Link Sate Transitions

Active State Power Management

The operation of Active State Power Management (ASPM) is orthogonal to power management. Once
enabled by the ASPM field in the PCI Express® Link Control (PCIE LCTL) register, ASPM link state transi­tions are initiated by hardware without software involvement. The PES12N3 ASPM supports the required
L0s state as well as the optional L1 state.

The L0s Entry Timer (L0SET) field in the PCI Power Management Proprietary Control (PMPC) register
controls the amount of time L0s entry conditions must be met before the hardware transitions the link to the
L0s state. The L1 Entry Timer (L1SET) field in the PCI Power Management Proprietary Control (PMPC)
register controls the amount of time L1 entry conditions must be met before the hardware transitions the link
to the L1 state. If these conditions are met and the link is in the L0 or L0s states, then the hardware will
request a transition to the L1 state from its link partner. Note that L1 entry requests are only made by the
PES12N3 upstream port. If the link partner acknowledges the transition, then the L1 state is entered. Other­wise the L0s state is entered.

PES12N3 User Manual 5 - 3 June 7, 2006

IDT Power Management Active State Power Management

Notes

PES12N3 User Manual 5 - 4 June 7, 2006

Chapter 6

Hot-Plug and Hot-Swap

Notes

Introduction

As illustrated in Figures 6.1 through 6.3, a PCIe® switch may be used in one of three hot- plug configura­tions.

Figure 6.1 illustrates the use of the PES12N3 in an application in which the two downstream ports are
connected to slots into which add-in cards may be hot-plugged.

Figure 6.2 illustrates the use of the PES12N3 in an add-in card application. Here the two downstream
ports are hardwired to devices on the add-in card and the upstream port serves as the add-in card’s PCIe
interface. In this application the upstream port may be hot-plugged into a slot on the main system.

Finally, Figure 6.3 illustrates the use of the PES12N3 in a carrier card application. In this application, the
two downstream ports are connected to slots which may be hot-plugged and the entire assembly may be
hot-plugged into a slot on the main system. Since this application requires nothing more than the function­ality illustrated in both Figure 6.1 and Figure 6.2, it will not be discussed further.

Upstream

Link

Port A

PES12N3

Master
SMBus

Port B

Port B

Slot

Figure 6.1 Hot-Plug on Switch Downstream Slots Application

Port C

Port C

Slot

SMBus I/O

Expander

Hot-Plug Signals

PES12N3 User Manual 6 - 1 June 7, 2006

IDT Hot-Plug and Hot-Swap Introduction

Notes

Upstream

Link

Add-In Card

Port A

GPIO

Hot-Plug Signals

PES12N3

Port B Port C

PCI Express

Device

PCI Express

Device

Figure 6.2 Hot-Plug with Switch on Add-In Card Application

Upstream

Link

Carrier

Card

Port A

GPIO

Hot-Plug Signals

PES12N3

Master
SMBus

Port B

Port B

Slot

Port C

Port C

Slot

SMBus I/O

Expander

Hot-Plug Signals

Figure 6.3 Hot-Plug with Carrier Card Application

PES12N3 User Manual 6 - 2 June 7, 2006

IDT Hot-Plug and Hot-Swap Introduction

Notes

The PCI Express® Base Specification revision 1.0a allowed a hot-plug attention indicator, power indi­cator, and attention button to be located on the board on which the slot is implemented or on the add-in
board. When located on the add-in board, state changes are communicated between the hot-plug controller
associated with the slot and the add-in card via hot-plug messages. This capability was removed in revision

1.1 of the PCI Express Base Specification.

Therefore, there are differences in the behavior of a PCIe 1.0a hot-plug capable switch and a PCIe1.1
hot-plug capable switch. The Hot Plug Mode (HPMODE) bit in the upstream port’s Switch Control
(PA_SWCTL) register selects the operating mode of the hot-plug functionality in the PES12N3. Differences
in operation are noted in the following sections.

Hot-Plug with Downstream Port(s) Connected to a Slot

This section discusses the use of the PES12N3 in which one or both the of the downstream ports are
used in an application in which an add-in card may be hot-plugged into a downstream slot. Associated with
each downstream port in the PES12N3 is a hot-plug controller. The hot-plug controller may be enabled by
setting the HPC bit in the PCI Express Slot Capabilities (PCIESCAP) register during configuration (e.g., via
serial EEPROM).

The PES12N3 allows sensor inputs and indicator outputs to be located next to the slot or on the plug in
module. When implemented on the slot, the appropriate bits should be set during configuration in the P CI
Express Slot Capabilities (PCIESCAP) register. Table 6.7 lists the hot-plug inputs and outputs that may be
associated with a slot. When enabled during configuration in the PCIESCAP register, these inputs and
outputs are made available to external logic using an external I/O expander located on the master SMBus
interface.

The PES12N3 only supports presence detect signalling via a pin assertion. It does not support in-band
presence detect.

Signal Type Name/Description

1

PxAPN I Port x
PxPDN I Port x Presence Detect Input.
PxPFN I Port x Power Fault Input.

PxMRLN I Port x Manually-operated Retention Latch (MRL) Input.

PxAIN O Port x Attention Indicator Output.
PxPIN O Port x Power Indicator Output.

PxPEP O Port x Power Enable Output.

PxINTERLOCKP O Port x Electromechanical Interlock.

1.

x corresponds to downstream port B or C.

Table 6.7 Downstream Ports B and C Hot Plug Signals

Attention Push button Input.

Hot-Plug I/O Expander

The PES12N3 utilizes an external SMBus/I2C-bus I/O expander connected to the master SMBus inter­face for hot-plug related signals associated with downstream ports. It is not possible to utilize EEPROM
commands to toggle the I/O expander outputs due to conflicting usage of the master SMBus. SMBus writes
or configuration writes can be used to control the I/O expander outputs.

The PES12N3 is designed to work with P hillips PCA9555 compatible I/O expanders. See the Phillips
PCA9555 data sheet for details on the operation of this device.

The external SMBus I/O expander provides 16 bit I/O pins that may be configured as inputs or outputs.
The mapping of downstream port B and C hot-plug signals listed in Table 6.7 to these I/O pins is exhibited
in Table 6.8.

PES12N3 User Manual 6 - 3 June 7, 2006

IDT Hot-Plug and Hot-Swap Introduction

Notes

The port B and C electromechanical interlock outputs are only used in PCIe 1.1 mode (i.e., HPMODE bit
set). These signals are driven to their negated state in PCIe 1.0a mode.

SMBus I/O

Expander

Bit

0 (I/O-0.0)

1 (I/O-0.1) I PBPDN
2 (I/O-0.2) I PBPFN
3 (I/O-0.3) I PBMRLN
4 (I/O-0.4) O PBAIN
5 (I/O-0.5) O PBPIN
6 (I/O-0.6) O PBPEP
7 (I/O-0.7) O PBINTERLOCKP

8 (I/O-1.0) I PCAPN
9 (I/O-1.1) I PCPDN
10 (I/O-1.2) I PCPFN

11 (I/O-1.3) I PCMRLN

1

Type Signal

I PBAPN

2

12 (I/O-1.4) O PCAIN
13 (I/O-1.5) O PCPIN
14 (I/O-1.6) O PCPEP

15 (I/O-1.7) O PCINTERLOCKP

1.

2.

Table 6.8 SMBus I/O Expander Signals

I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
Not used in PCIe 1.0a mode (i.e., HPMODE bit cleared).

2

During configuration of the PES12N3, the SMBus/I2C-bus address of the hot-plug I/O expander should
be written to the Hot-plug I/O Expander Master SMBus Address (IOEADDR) field in the SMBUS status
(PA_SMBUSSTS) register.

SMBus write transactions are issued to the I/O expander by the PES12N3 to configure the device when­ever the value of the IOEADDR field is modified. Outputs for downstream ports that are disabled are set to
their negated value (e.g., the power indicator is turned off).

The I/O expander configuration sequence issued by the PES12N3 is as follows:

– write value 0x50 to I/O expander register 2
– write value 0x50 to I/O expander register 3
– write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– write value 0x0 to I/O expander register 5 (no inversion in IO-1)
– write value 0x0F to I/O expander register 6 (bits 4, 5, 6 and 7 are outputs of IO-0)
– write value 0x0F to I/O expander register 7 (bits 4, 5, 6 and 7 are outputs of IO-1)
– read value of I/O expander register 0 to obtain the current state of the I/O IO-0 inputs.
– read value of I/O expander register 1 to obtain the current state of the I/O IO-I inputs.

Whenever a hot-plug output from port B or C needs to change state, a master SMBus transaction is initi­ated to update the state of the I/O expander. This write operation causes the I/O expander to change the
state of its output(s). Port B output values are written to I/O expander register 2 and Port C values are
written to I/O expander register 3.

PES12N3 User Manual 6 - 4 June 7, 2006

IDT Hot-Plug and Hot-Swap Introduction

Notes

The I/O expander has an open drain interrupt output that is asserted when a pin configured as an input
changes state from the value previously read. The interrupt output from the SMBus I/O expander should be
connected to GPIO[2], and GPIO[2] should be initialized during configuration to operate in alternate function
mode as the Hot-plug I/O expander interrupt input. See Chapter 8, General Purpose I/O.

Whenever a input to the I/O expander changes state from the value previously read, the interrupt output
of the I/O expander connected to GPIO[2] is asserted. This causes the PES12N3 to issue a master SMBus
transaction to read the updated state of the I/O expander inputs.

Regardless of the state of the interrupt output of the I/O expander, the PES12N3 will not issue a master
SMBus transaction to read the updated state of the I/O expander inputs more frequently than once every 40
milliseconds. This delay in sampling may be used to eliminate external debouncing circuitry. The 40 milli­second sampling frequency also applies to the Hot Plug Port A Attention Button (PAABN) GPIO alternate
function.

Port B input values are read from I/O expander register 0 and Port C values are read from I/O expander
register 1. The I/O expander interrupt request output is negated whenever the input values are read or
when the input pin changes state back to the value previously read. Any errors detected during I/O
expander SMBus read or write transactions is reflected in the status bits of the SMBus Status
(PA_SMBUSSTS) register. The I/O Expander Interface (PA_IOEXPINTF) register allows direct testing and
debugging of the I/O expander functionality.

The Port B Hot-Plug Signals (PBHPS) and the Port C Hot-Plug Signals (PCHPS) fields in the
PA_IOEXPINTF register reflect the current state, as viewed by the PES12N3, of all of the I/O expander
inputs and outputs.

Writing a one to the Reload I/O Expander Signals (RELOADIOEX) bit in the PA_IOEXPINTF register
causes the PES12N3 to generate SMBus write and read transactions to the I/O expander, causing the
value in the PBHPS and PCHPS fields to reflect the state of the I/O expander signals. This feature may be
used to aid in debugging hot-plug operation. For example, a user who neglects to configure GPIO[2] as an
alternate function may use this feature to determine that master SMBus transactions to the I/O expander
function properly and that the issue is with the interrupt logic.

The I/O Expander Test Mode (IOEXTM) bit in the PA_IOEXPTINF register allows an I/O expander test
mode to be entered. Normally, hot-plug outputs which are generated by ports B and C first update the
PBHPS and PCHPS fields before being written to the I/O expander. When this bit is set, these hot-plug
outputs are blocked from updating the fields. Instead, values written directly to the PBHPS and PCHPS
fields will be sent to the I/O expander. In this mode, the PES12N3 issues a transaction to update the state of
the I/O expander whenever a bit corresponding to a hot-plug controller output in these fields changes state
due to a configuration write.

Hot-Plug Messages

The PCI Express Base Specification revision 1.0a allows the attention i ndicator, power indicator and
attention button to be implemented on an add-in card instead of the board on which the slot is located. To
support this, the specification defines messages that implement virtual wires between the add-in card and
the hot-plug controller associated with the slot. The PCI Express Base Specification revision 1.1 removed
this capability.

When the Hot Plug Mode (HPMODE) bit is set in the Switch Control (PS_SWCTL) register, the hot-plug
controllers operate in PCIe revision 1.1 mode and no downstream messages are generated by the por t B or
C hot-plug controllers. In addition, if a hot-plug message is received on these ports in this mode, it is silently
discarded.

If the HPMODE bit is cleared (default value), then hot-plug messages are generated and processed
when received by the port B and C hot-plug controllers.

A downstream ATTENTION_INDICATOR_ON, ATTENTION_INDICATOR_BLINK, or
ATTENTION_INDICATOR_OFF message is sent down on port B or C when the hot-plug controller associ­ated with the port is enabled and the state of the Attention Indicator Control (AIC) field is modified in the
PB_PCIESCTL or PC_PCIESCTL register.

PES12N3 User Manual 6 - 5 June 7, 2006

IDT Hot-Plug and Hot-Swap Introduction

Notes

A downstream POWER_INDICATOR_ON, POWER_INDICATOR_BLINK, or
POWER_INDICATOR_OFF message is sent down on port B or C when the hot-plug controller associated
with the port is enabled and the state of the Power Indicator Control (PIC) field is modified in the
PB_PCIESCTL or PC_PCIESCTL register.

An attention button pressed event and the Attention Button Pressed (ABP) bit in the PCI Express Slot
Status (PCIESST) register is set when the hot plug controller associated with the port is enabled and an
ATTENTION_BUTT ON_PRESSED message is received on port B or C. ATTENTION_BUTTON PRESSED
messages are always consumed by the PES12N3 and not passed to the upstream port.

Hot-Plug Interrupts and Wake-up

The hot-plug controller associated with a downstream slot may generate an interrupt or wake up event.

Hot-plug interrupts are only generated when the Hot Plug Interrupt Enable (HPIE) bit is set in the corre­sponding port’s PCI Express Slot Control (PCIESCTL) register.

The following bits, when set in the PCI Express Slot Status (PCIESSTS) register, generate an interrupt if
not masked by the corresponding bit in the PCI Express Slot Control (PCIESCTL) register or by the HPIE
bit: the Attention Button Pressed (ABP), Power Fault Detected (PFD), MRL Sensor Changed (MRLSC),
Presence Detected Changed (PDC), and Command Completed (CC).

When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable
(EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command
(PCICMD) register.

When the downstream port or the entire switch is in a D3

state, then the hot-plug controller generates

hot

a wake-up event using a PM_PME message instead of an interrupt if the event interrupt is not masked in
the slot control (PCIESCTL) register and hot-plug interrupts are disabled by the HPIE bit. If the event inter­rupt is not masked and hot-plug interrupts are enabled, then both a PM_PME and an interrupt are gener­ated. If the event interrupt is masked, then neither a PM_PME or interrupt are generated. Note that a
command completed (CC bit) interrupt will not generate a wake-up event.

Hot-Plug with Swi t ch on an Add-In Card

This section discusses the use of the PES12N3 in add-in card applications in which the upstream port
may be hot-plugged into a slot.

The PCI Express Base Specification revision 1.0a allows the attention i ndicator, power indicator and
attention button to be implemented on an add-in card instead of board containing the slot. To support this,
the specification defines messages that implement virtual wires between the add-in card and the down­stream port hot-plug controller. The PCI Express Base Specification revision 1.1 removed this capability.

When the Hot Plug Mode (HPMODE) bit is set in the Switch Control (PS_SWCTL) register, the hot-plug
controllers operate in PCIe revision 1.1 mode. In this mode, all hot plug messages received on the
upstream port are silently discarded and no hot-plug messages are sent on the upstream port.

If the HPMODE bit is cleared (default value), then hot-plug messages are generated and processed on
the upstream port.

Hot plug signals associated with the upstream port of the switch are listed in Table 6.9 and are alternate
functions of GPIO pins. See Chapter 8, General Purpose I/O.

Signal Type Name/Description

PAABN I Port A Attention Button Input.

PAAIN O Port A Attenti on Indicator Output.
PAPIN O Port A Power Indicator Output.

Table 6.9 Upstream Port A Hot Plug Signals

PES12N3 User Manual 6 - 6 June 7, 2006

IDT Hot-Plug and Hot-Swap Hot-Swap

Notes

Association of a power indicator output with the upstream port of the PES12N3 is enabled by setting the
Power Indicator Present (PIP) bit in the PCI Express Device Capabilities (PCIEDCAP) register of the
upstream port. When this bit is set and GPIO[5] is configured as an alternate function, then the state of the
PAPIN output is modified by POWER_INDICATOR_ON, POWER_INDICATOR_BLINK, and
POWER_INDICATOR_OFF messages received on the upstream port. These messages are consumed by
the upstream port.

Association of an attention indicator output with the upstream port of the PES12N3 is enabled by setting
the Attention Indicator Present (AIP) bit in the PCI Express Device Capabilities (PCIEDCAP) register of the
upstream port. When this bit is set and GPIO[4] is configured as an alternate function, then the state of the
PAAIN output is modified by ATTENTION_INDICATOR_ON, ATTENTION_INDICATOR_BLINK, and
ATTENTION_INDICATOR_OFF messages received on the upstream port. These messages are consumed
by the upstream port.

Association of a attention push button input with the upstream port of the PES12N3 is enabled by setting
the Attention Button Present (ABP) bit in the PCI Express Device Capabilities (PCIEDCAP) register of the
upstream port. When this bit is set and GPIO[3] is configured as an alternate function, the assertion of the
PAABN signal results in an ATTENTION_BUTTON_PRESSED message being sent on the upstream port
of the switch.

The PES12N3 will not sample the state of the PAABN input more frequently than once every 40 millisec­onds. This delay in sampling may be used to eliminate external debouncing circuitry.

Hot-Swap

The PES12N3 is hot-swap capable and meets the following requirements:

– All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.)
– All I/O cells function predictably from early power. Th is means that the device is able to tolerate a

non-monotonic ramp-up as well as a rapid ramp-up of the DC power.

– All I/O cells are able to tolerate a precharge voltage
– Since no clock is present during physical connection, the device will maintain all outputs in a high-

impedance state even when no clock is present.

– The I/O cells meet VI requirements for hot-swap.
– The I/O cells respect the required leakage current limits over the entire input voltage range.

In summary, the PES12N3 meets all of the I/O requirements necessary to build a PICMG compliant hot­swap board or system. The hot-swap I/O buffers of the PES12N3 may also be used to construct proprietary
hot-swap systems. For a detailed specification of I/O buffer characteristic, see the 89HP

Sheet on the IDT web site.

ES12N3 Data

PES12N3 User Manual 6 - 7 June 7, 2006

IDT Hot-Plug and Hot-Swap Hot-Swap

Notes

PES12N3 User Manual 6 - 8 June 7, 2006

Chapter 7

SMBus Interfaces

Notes

Introduction

The PES12N3 contains two SMBus interfaces. The slave SMBus interface provides full access to all
software visible registers in the PES12N3, allowing every register in the device to be read or written by an
external SMBus master. The slave SMBus may also be used to initialize the serial EEPROM used for initial­ization. The Master SMBus interface provides connection for an optional external serial EEPROM used for
initialization and an optional I/O expander used for hot-plug signals.

Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an
SMBus data pin, and 4 SMBus address pins. As shown in Figure 7.1, the master and slave S MBuses may
be used in a unified or split configuration.

PES12N3

SSMBCLK
SSMBDAT

MSMBCLK
MSMBDAT

Processor

SMBus
Master

Serial

EEPROM

(a) Unified Configuration

Hot-Plug

I/O

Expander

...

Other

SMBus

Devices

PES12N3

MSMBCLK
MSMBDAT

SSMBCLK
SSMBDAT

Processor

SMBus
Master

Serial

EEPROM

...

Hot-Plug

Expander

Other

SMBus

Devices

I/O

(b) Split Configuration

Figure 7.1 SMBus Interface Configuration Examples

In the unified configuration, shown in Figure 7.1(a), the master and slave SMBuses are tied together and
the PES12N3 acts both as an SMBus master as well as an SMBus slave on this bus. This requires that the
external SMBus master or processor that has access to PES12N3 registers support SMBus arbitration. In

PES12N3 User Manual 7 - 1 June 7, 2006

IDT SMBus Interfaces SMBus Registers

Notes

some systems, this external SMBus master interface may be implemented using general purpose I/O pins
on a processor or microcontroller, and thus may not support SMBus arbitration. To support these systems,
the PES12N3 may be configured to operate in a split configuration as shown in Figure 7.1(b).

In the split configuration, the master and slave SMBuses operate as two independent buses and thus
multi-master arbitration is not required.

SMBus Registers

Bit

Field

0 Reserved RO 0x0 Reserved field.

7:1 SSMBADDR RO HWINIT Slave SMBus Address. This field contains the SMBus

8 Reserved RO 0x0 Reserved field.

15:9 MSMBADDR RO HWINIT Master SMBus Address. This field contains the SMBus

16 Reserved RO 0x0 Reserved field.

23:17 IOEADDR RWL 0x0 Hot-plug I/O Expander Master SMBus Address. This

Field

Name

Type

Default

Value

Description

address assigned to the slave SMBus interface.

address assigned to the master SMBus interface.

field contains SMBus address assigned to the hot-plug I/O
expander on the master SMBus interface.

24 EEPROM-

DONE

25 NAERR RW1C 0x0 No Acknowledge Error. This bit is set if an unexpected

26 LAERR RW1C 0x0 Lost Arbitration Error. When the master SMBus inter-

27 OTHERERR RW1C 0x0 Other Error. This bit is set if a misplaced START or STOP

28 ICSERR RW1C 0x0 Initialization Checksum Error. This bit is set if an invalid

29 URIA RW1C 0x0 Unmapped Register Initialization Attempt. This bit is se t

RO 0x0 Serial EEPROM Initialization Done. When the switch is

configured to operate in a mode in which serial EEPROM
initialization occurs during a fundamental reset, this bit is
set when serial EEPROM initialization completes or when
an error is detected.

NACK is observed during a master SMBus transaction.
The setting of this bit may indicate the following: that the
addressed device does not exist on the SMBus (i.e.,
addressing error); data is unavailable or the device is
busy; an invalid command was detected by the slave; or
invalid data was detected by the slave.

face loses arbitration for the SMBus, it automatically re­arbitrates for the SMBus. If the master SMBus interface
loses 16 consecutive arbitration attempts, then the trans­action is aborted and this bit is set.

condition is detected by the master SMBus interface.

checksum is computed during Serial EEPROM initializa­tion or when a configuration done command is not found in
the serial EEPROM.

if an attempt is made to initialize via serial EEPROM a reg­ister that is not defined in the corresponding PCI configu­ration space.

31:30 Reserved RO 0x0 Reserved field.

Table 7.1 SMBUSSTS - SMBus Status

PES12N3 User Manual 7 - 2 June 7, 2006

IDT SMBus Interfaces SMBus Registers

Notes

Bit

Field

Field

Name

Type

Default

Value

Description

15:0 MSMBCP RW HWINIT Master SMBus Clock Prescalar. This field contains a

clock prescalar value used during master SMBus transac­tions. The prescalar clock period is equal to 32 ns multi­plied by the value in this field. When the field is cleared to
zero or one, the clock is stopped.
The initial value of this field is 0x0139 when the master
SMBus is configured to operate in slow mode (i.e., 100
KHz) in the boot configuration and to 0x0053

1

when it is

configured to operate in fast mode (i.e., 400 KHz).

16 MSMBIOM RW 0x0 Master SMBus Ignore Other Masters. When this bit is

set, the master SMBus proceeds with transactions regard­less of whether it won or lost arbitration.

17 ICHECKSUM RW 0x0 Ignore Checksum Errors. When this bit is set, serial

EEPROM initialization checksum errors are ignored (i.e.,
the checksum always passes).

19:18 SSMBMODE RW 0x0 Slave SMBus Mode. The slave SMBus contains internal

glitch counters on the SSMBCLK and SSMBDAT signals
that wait approximately 1uS before sampling or driving
these signals. This field allows the glitch counter time to be
reduced or entirely removed. In some systems, this may
permit high speed slave SMBus operation.
0x0 - (normal) Slave SMBus normal mode. Glitch

counters operate with 1uS delay.

0x1 - (fast) Slave SMBus interface fast mode. Glitch

counters operate with 100nS delay.

0x2 - (disabled) Slave SMBus interface with glitch

counters disabled. Glitch counters operate with
zero delay which effectively removes them.

0x3 - reserved.

21:20 MSMBMODE RW 0x0 Master SMBus Mode. The master SMBus contains inter-

nal glitch counters on the MSMBCLK and MSMBDAT sig­nals that wait approximately 1uS before sampling or
driving these signals. This field allows the glitch counter
time to be reduced or entirely removed. In some systems,
this may permit high speed master SMBus operation.
0x0 - (normal) Master SMBus normal mode. Glitch

counters operate with 1uS delay.

0x1 - (fast) Master SMBus interface fast mode. Glitch

counters operate with 100nS delay.

0x2 - (disabled) Master SMBus interface with glitch

counters disabled. Glitch counters operate with
zero delay which effectively removes them.

0x3 - reserved.

31:22 Reserved RO 0x0 Reserved field.

Table 7.2 SMBUSCTL - SMBus Control

1.

The MSMBCLK lo w m ini mum p ulse w idth is equ al t o h alf the pe riod pr ogra mmed in this field. The va lue of 0x5 3, whic h c orr e­sponds to ~373 KHz, allow s the min low pulse width to be satisfie d. In systems wh ere this timing par ameter is not critic al, the
operating frequency may be increased.

PES12N3 User Manual 7 - 3 June 7, 2006

IDT SMBus Interfaces Master SMBus Interface

Notes

Master SMBus Interface

The master SMBus interface is used during a fundamental reset to load configuration values from an

optional serial EEPROM. It is also used to support an optional I/O expander for hot-plug signals.

Initialization

Master SMBus initialization occurs during a fundamental reset (see Fundamental Reset on page 2-5).

During a fundamental reset initialization sequence, the state of the Master SMBus Slow Mode (MSMB­SMODE) signal is examined. If this signal is asserted, then the Master SMBus Clock Prescalar (MSMBCP)
field in the port A SMBus Control (PA_SMBUSCTL) register is initialized to support 100 KHz SMBus opera­tion. If the signal is negated, then the MSMBCP field is initialized for 400 KHz SMBus operation.

Serial EEPROM

During a fundamental reset, an optional serial EEPROM may be used to initialize any software visible
register in the device.

Serial EEPROM loading occurs if the Switch Mode (SWMODE[3:0]) field selects an operating mode that
performs serial EEPROM initialization (e.g., transparent mode with serial EEPROM initialization).

The address used by the SMBus interface to access the serial EEPROM is specified by the
MSMBADDR[4:1] signals as shown in Table 7.3.

Address

Bit

Address Bit Value

1 MSMBADDR[1]
2 MSMBADDR[2]
3 MSMBADDR[3]
4 MSMBADDR[4]
51
60
71

Table 7.3 Serial EEPROM SMBus Address

Device Initialization from a Serial EEPROM

During initialization from the optional serial EEPROM, the master SMBus interface reads configuration
blocks from the serial EEPROM and updates corresponding registers in the PES12N3.

Any PES12N3 software visible register in the upstream port or downstream port(s) may be initialized
with values stored in the serial EEPROM.

Each software visible register in the PES12N3 has a CSR system address which is formed by adding
the PCI configuration space offset value of the register to the base address of the configuration space in
which the register is located. Configuration blocks stored in the serial EEPROM use this CSR system
address shifted right two bits (i.e., configuration blocks in the serial EEPROM use doubleword CSR system
addresses and not byte CSR system addresses). Base addresses for the PCI configuration spaces in the
PES12N3 are listed in Table 7.4.

PES12N3 User Manual 7 - 4 June 7, 2006

IDT SMBus Interfaces Master SMBus Interface

Notes

Base Address Value

PCI Configuration Space

Upstream Port A 0x0000

Downstream Port B 0x1000

Downstream Port C 0x2000

Table 7.4 Base Addresses for PCI Configuration Spaces in the PES12N3

Since configuration blocks are used to store only the value of those registers that are initialized, a serial
EEPROM much smaller than the total size of all of the configuration spaces may be used to initialize the
device.

Any serial EEPROM compatible with those listed in Table 7.5 may be used to store PES12N3 initializa­tion values. Some of these devices are larger than the total size of all of the PCI configuration spaces in the
PES12N3 that may be initialized and thus may not be fully utilized.

Serial EEPROM Size

used to form CSR

System Address

24C32 4 KB

24C64 8 KB
24C128 16 KB
24C256 32 KB
24C512 64 KB

Table 7.5 PES12N3 Compatible Serial EEPROMs

During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial
EEPROM address zero. These bytes are interpreted as configuration blocks and sequential reading of the
serial EEPROM continues until the end of a configuration done block is reached or the serial EEPROM
address rolls over from 0xFFFF to 0x0.

All register initialization performed by the serial EEPROM is performed in double word quantities. There
are three configuration block types that may be stored in the serial EEPROM. The first type is a single
double word initialization sequence. A double word initialization sequence occupies six byes in the serial
EEPROM and is used to initialize a single double word quantity in the PES12N3.

A single double word initialization sequence consists of three fields and its format is shown in Figure 7.2.
The CSR_SYSADDR field contains the double word C SR system address of the double word to be initial­ized. The actual CSR system address, which is a by te address, equals this value w ith two lower zero bits
appended. The next field is the TYPE field that indicates the type of the configuration block. For single
double word initialization sequence, this value is always 0x0. The final DATA field contains the double word
initialization value.

PES12N3 User Manual 7 - 5 June 7, 2006

IDT SMBus Interfaces Master SMBus Interface

Notes

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

6

7

Byte 0 CSR_SYSADDR[7:0]

Byte 1

Byte 2 DATA[ 7:0]

Byte 3 DATA[15:8]

Byte 4 DATA[23:16]

Byte 5 DATA[31:24]

TYPE

0x0

4

5

CSR_SYSADDR[13:8]

2

3

Figure 7.2 Single Double Word Initialization Sequence Format

The second type of configuration block is the sequential double word initialization sequence. It is similar
to a single double word initialization sequence except that it contains a double word count that allows
multiple sequential double words to be initialized in one configuration block.

A sequential double word initialization sequence consists of four required fields and one to 65535
double word initialization data fields. The format of a sequential double word initialization sequence is
shown in Figure 7.3. The CSR_SYSADDR field contains the starting double word CSR system address to
be initialized. The next field is the TYPE field that indicates the type of the configuration block. For sequen­tial double word initialization sequences, this value is always 0x1. The NUMDW field specifies the number
of double words initialized by the configuration block. This is followed by the number of DATA fields speci­fied in the NUMDW field.

0

1

Bit

7

Byte 0 CSR_SYSADDR[7:0]

Byte 1

Byte 2 NUMDW[7:0]

Byte 3 NUMDW[15:8]

Byte 4 DATA0[7:0]

Byte 5 DATA0[1 5:8]

Byte 6 DATA0[23:16]

Byte 7 DATA0[31:24]

TYPE

0x1

5

6

...

Byte 4n+4 DATAn[7:0]

Byte 4n+ 5 DATAn[15:8]

Byte 4n+6 DATAn[23:16]

Byte 4n+7 DATAn[31:24]

3

4

CSR_SYSADDR[13:8]

...

2

0

1

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Figure 7.3 Sequential Double Word Initialization Sequence Format

The final type of configuration block is the configuration done sequence w hich is used to signify the end
of a serial EEPROM initialization sequence.

PES12N3 User Manual 7 - 6 June 7, 2006

IDT SMBus Interfaces Master SMBus Interface

Notes

If during serial EEPROM initialization, an attempt is made to initialize a register that is not defined in a
configuration space (i.e., does not appear in Tables 9.6, 9.7, or 9.8), then the Unmapped Register Initializa­tion Attempt (URIA) bit is set in the SMBUSSTS register and the write is ignored.

The configuration done sequence consists of two fields and its format is shown in Figure 7.3. The
CHECKSUM field contains the checksum of all of the bytes in all of the fields read from the serial EEPROM
from the first configuration block to the end of this done sequence. The second field is the TYPE field which
is always 0x3 for configuration done sequences.

Bit

7

Byte 0 CHECKSUM[7:0]

Byte 1

0x3

5

6

4

ReservedTYPE

(must be zero)

3

2

0

1

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Figure 7.4 Configuration Done Sequence Format

The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa­tion to be verified. Since uninitialized EEPROMs typically have a value of all ones, initialization from an
uninitialized serial EEPROM will result in a checksum mismatch.

The checksum is computed in the following manner.An 8-bit counter is initialized to zero and the 8-bit
sum is computed over the configuration bytes stored in the serial EEPROM, including the entire contents of

the configuration done sequence, with the checksum field initialized to zero.

1

The 1’s complement of this

sum is placed in the checksum field.

The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is
computed over the bytes read from the serial EEPROM, including the entire contents of the configuration

done sequence.

2

The correct result should always be 0xFF (i.e., all ones). Checksum checking may be
disabled by setting the Ignore Checksum Errors (ICHECKSUM) bit in the port A SMBus Control
(PA_SMBUSCTL) register.

If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM is
aborted and the RSTHALT bit is set in the PA_SWCTL register. This allows debugging of the error condition
via the slave SMBus interface but prevents normal system operation with a potentially incorrectly initialized
device. Error information is recorded in the PA_SMBUSSTS register. Once serial EEPROM initialization
completes, or when an error is detected, the EEPROM Done (EEPROMD ONE) bit is set in the port A
SMBus Status (PA_SMBSTS) register.

A summary of possible errors during serial EEPROM initialization and specific action taken when
detected is summarized in Table 7.6.

1.

This includes the byte containing the TYPE field.

2.

This includes the checksum byte as well as the byte that contains the type and reserved field.

PES12N3 User Manual 7 - 7 June 7, 2006

IDT SMBus Interfaces Master SMBus Interface

Notes

Error Action Taken

Configuration Done Sequence checksum
mismatch with that computed by the
PES12N3

Serial EERPOM address roll-over from
0xFFFF to 0x0000

Invalid configuration block type
(only invalid type is 0x2)

An unexpected NACK is observed during a
master SMBus transaction

Master SMBus interface loses 16 consecu­tive arbitration attempts

A misplaced START or STOP condition is
detected by the master SMBus interface

Table 7.6 Serial EEPROM Initialization Errors

- Set RSTHALT bit in PA_SWCTL register

- ICSERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- ICSERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- ICSERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- NAERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- LAERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

- Set RSTHALT bit in PA_SWCTL register

- OTHERERR bit is set in the PA_SMBUSSTS register

- Abort initialization, set DONE bit in the PA_SMBUSSTS register

Programming the Serial EEPROM

The serial EEPROM may be programmed prior to board assembly or in-system via the slave SMBus
interface or a PCIe® root. Programming the serial EEPROM via the slave SMBus is described in section
Serial EEPROM Read or Write Operation on page 7-12. A PCIe root may read and write the serial
EEPROM by performing configuration read and write transactions to the port A Serial EEPROM Interface
(PA_EEPROMINTF) register.

To read a byte from the serial EEPROM, the root should configure the Address (ADDR) field in the
PA_EEPROMINTF register with the byte address of the serial EEPROM location to be read and the Opera­tion (OP) field to “read.” The Busy (BUSY) bit should then be checked. If the EEPROM is not busy, then the
read operation may be initiated by performing a write to the Data (DATA) field. When the serial EEPROM
read operation completes, the Done (DONE) bit in the PA_EEPROMINTF register is set and the busy bit is
cleared. When this occurs, the DAT A field contains the byte data of the value read from the serial EEPROM.

To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of
the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy
(i.e., the BUSY bit is cleared), then the write operation may be initiated by writing the val ue to be w ritten to
the DATA field. When the write operation completes, the DONE bit is set and the busy bit is cleared.

Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results.
SMBus errors may occur when accessing the serial EEPROM. If an error occurs, then it is reported in the
port A SMBus Status (PA_SMBUSSTS) register. Software should check for errors before and after each
serial EEPROM access.

Hot-Plug I/O Expander

The PES12N3 utilizes an external SMBus/I2C-bus I/O expander connected to the master SMBus inter­face for hot-plug related signals associated with downstream ports. See section Hot-Plug I/O Expander on
page 6-3 for information on the operation of the hot-plug I/O expander.

PES12N3 User Manual 7 - 8 June 7, 2006

IDT SMBus Interfaces Slave SMBus Interface

Notes

Slave SMBus Interface

The slave SMBus interface provides the PES12N3 with a configuration, management and debug inter­face. Using the slave SMBus interface, an external master can read or write any software visible register in
the device.

Initialization

Slave SMBus initialization occurs during a fundamental reset (see Fundamental Reset on page 2-5).
During the fundamental reset initialization sequence, the address is specified by the SSMBADDR[5,3:1]
signals as shown in Table 7.7.

Address

Bit

1 SSMBADDR[1]
2 SSMBADDR[2]
3 SSMBADDR[3]
40
5 SSMBADDR[5]
61
71

Address Bit Value

Table 7.7 Slave SMBus Address When a Static Address is Selected.

SMBus Transactions

The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
See the SMBus 2.0 specification for a detailed description of these transactions.

– Byte and Word Write/Read
– Block Write/Read

Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces
undefined results.

Associated with each of the above transactions is a command code. The command code format for
operations supported by the slave SMBus interface is shown in Figure 7.5 and described in Table 7.8.

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Figure 7.5 Slave SMBus Command Code Format

Bit

1

Bit

0

ENDSTARTFUNCTIONSIZEPEC

PES12N3 User Manual 7 - 9 June 7, 2006

IDT SMBus Interfaces Slave SMBus Interface

Notes

Bit

Field

0 END End of transaction indicator. Setting both START and END signifies a

1 START Start of transaction indicator. Setting both START and END signifies

4:2 FUNCTION This field encodes the type of SMBus operation.

6:5 SIZE This field encodes the data size of the SMBus transaction.

7 PEC This bit controls whether packet error checking is enabled for the cur-

Name Description

single transaction sequence
0 - Current transaction is not the last read or write sequence.

1 - Current transaction is the last read or write sequence.

a single transaction sequence
0 - Current transaction is not the first of a read or write sequence.
1 - Current transaction is the first of a read or write sequence.

0 - CSR register read or write operation
1 - Serial EEPROM read or write operation
2 through 7 - Reserved

0 - Byte
1 - Word
2 - Block
3 - Reserve d

rent SMBus transaction.
0 - Packet error checking disabled for the current SMBus transaction.
1 - Packet error checking enabled for the current SMBus transaction.

Table 7.8 Slave SMBus Command Code Fields

The FUNCTION field in the command code indicates if the SMBus operation is a CSR register read/
write or a serial EEPROM read/write operation. Since the format of these transactions is different. They will
be described individually in the following sections.

If a command is issued while one is already in progress or if the slave is unable to supply data associ­ated with a command, then the command is NACKed. This indicates to the master that the transaction
should be retried.

CSR Register Read or Write Operation

Tabl e 7.9 indicates the sequence of data as it is presented on the slave SMBus following the byte
address of the Slave SMBus interface.

PES12N3 User Manual 7 - 10 June 7, 2006

IDT SMBus Interfaces Slave SMBus Interface

Notes

Byte

Position

0CCODECommand Cod e. Slave Command Code field described in Table 7.8.
1 BYTCNT Byte Count. The byte count field is only transmitted for block type

2CMDCommand. This field encodes fields related to the CSR register read

3 ADDRL Address Low. Lower 8-bits of the doubleword CSR system address

4 ADDRU Address Upper. Upper 6-bits of the doubleword CSR system

5 DATALL Data Low Low. Bits [7:0] of data doubleword.
6 DATALM Data Low Middle. Bits [15:8] of data doubleword.

Field

Name Description

SMBus transactions. SMBus word and byte accesses do not contain
this field. The byte count field indicates the number of bytes following
the byte count field when performing a write or setting up for a read.
The byte count field is also used when returning data to indicate the
number of following bytes (including status). Note that the byte count

field does not include the PEC byte if PEC is enabled.

or write operation.

of register to access.

address of register to access. Bits 6 and 7 in the byte must be zero
and are ignored by the hardware.

7 DATAUM Data Upper Middle. Bits [23:16] of data doubleword.
8 DATAUU Data Upper Upper. Bits [31:24] of data doubleword.

Table 7.9 CSR Register Read or Write Operation Byte Sequence

The format of the CMD field is shown in Figure 7.6 and described in Table 7.10.

Bit

7

Bit

Field Name Type Description

0 BELL Read/Write Byte Enable Lower Lower. When set, the byte enable for bits [7:0] of

1 BELM Read/Write Byte Enable Lower Middle. When set, the byte enable for bits [15:8]

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Figure 7.6 CSR Register Read or Write CMD Field Format

the data word is enabled.

of the data word is enabled.

Bit

0

BELLBELMWERR BEUMBEUUOPRERR 0

2 BEUM Read/Write Byte Enable Upper Middle. When set, the byte enable for bits

[23:16] of the data word is enabled.

3 BEUU Read/Write Byte Enabl e Upper Up per. When set, the byte enable for bits [31:24]

of the data word is enabled.

Table 7.10 CSR Register Read or Write CMD Field Description (Part 1 of 2)

PES12N3 User Manual 7 - 11 June 7, 2006

IDT SMBus Interfaces Slave SMBus Interface

Notes

Bit

Field Name Type Description

4 OP Read/Write CSR Operation. This field encodes the CSR operation to be per-

formed.
0 - CSR write

1 - CSR read
5 0 0 Reserved. Must be zero
6 RERR Read-Only

and Clear

Read Error. This bit is set if the last CSR read SMBus transaction was

not claimed by a device. Success indicates that the transaction was

claimed and not that the operation completed without error.
7 WERR Read-Only

and Clear

Write Error. This bit is set if the last CSR write SMBus transaction was

not claimed by a device. Success indicates that the transaction was

claimed and not that the operation completed without error.

Table 7.10 CSR Register Read or Write CMD Field Description (Part 2 of 2)

Serial EEPROM Read or Write Operation

Tabl e 7.11 indi cates the sequence of data as it is presented on the slave SMBus following the byte

address of the Slave SMBus interface.

Byte

Position

Field

Name Description

0CCODECommand Cod e. Slave Command Code field described in Table 7.8.
1 BYTCNT Byte Count. The byte count field is only transmitted for block type

SMBus transactions. SMBus word and byte accesses do not contain
this field. The byte count field indicates the number of bytes following
the byte count field when performing a write or setting up for a read.
The byte count field is also used when returning data to indicate the
number of following bytes (including status).

2CMDCommand. This field contains information related to the serial

EEPROM transaction

3 EEADDR Serial EEPROM Address. This field specifies the address of the

Serial EEPROM on the Master SMBus when the USA bit is set in the
CMD field. Bit zero must be zero and thus the 7-bit address must be

left-justified.
4 ADDRL Address Low. Lower 8-bits of the Serial EEPROM byte to access.
5 ADDRU Address Upper. Upper 8-bits of the Serial EEPROM byte to access.
6DATAData. Serial EEPROM value read or to be written.

Table 7.11 Serial EEPROM Read or Write Operation Byte Sequence

The format of the CMD field is shown in Figure 7.7 and described in Table 7.12

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

OPUSA0 NAERRLAERROTHERERR 0

Figure 7.7 Serial EEPROM Read or Write CMD Field Format

PES12N3 User Manual 7 - 12 June 7, 2006

IDT SMBus Interfaces Slave SMBus Interface

Notes

Bit

Field Name Type

1

Description

0 OP RW Serial EEPROM Operation. This field encodes the serial EEPROM

operation to be performed.
0 - Serial EEPROM write
1 - Serial EEPROM read

1USA RWUse Specified Address. When this bit is set the serial EEPROM

SMBus address specified in the EEADDR is used instead of that

specified in the MSMBADDR field in the SMBUSSTS register.
2 Reserved
3 NAERR RC No Acknowledge Error. This bit is set if an unexpected NACK is

observed during a master SMBus transaction when accessing the

serial EEPROM. This bit has the same function as the NAERR bit in

the PA_SMBUSSTS register.

The setting of this bit may indicate the following: that the addressed

device does not exist on the SMBus (i.e., addressing error), data is

unavailable or the device is busy, an invalid command was detected

by the slave, invalid data was detected by the slave.
4 LAERR RC Lost Arbitration Error. This bit is set if the master SMBus interface

loses 16 consecutive arbitration attempts when accessing the serial

EEPROM. This bit has the same function as the LAERR bit in the

PA_SMBUSSTS register.
5 OTHERERR RC Other Error. This bit is set if a misplaced START or STOP condition is

detected by the master SMBus interface when accessing the serial

EEPROM. This bit has the same function as the OTHERERR bit in

the PA_SMBUSSTS register.

7:6 Reserved 0 Reserved. Must be zero

Table 7.12 Serial EEPROM Read or Write CMD Field Description

1.

See Table Table 1.2 in Chapter 1 for a definition of these abbreviations.

Sample Slave SMBus Operation

This section illustrates sample Slave SMBus operations. Shaded items are driven by the PES12N3’s

slave SMBus interface and non-shaded items are driven by an SMBus host.

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

Wr A A

Wr A N

Wr A A

ADDRU

Figure 7.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled

A

CCODE

START,END

CCODE

START,END

CCODE

START,END

BYTCNT=3

(PES12N3 not ready with data)

P

PES12N3 Slave

S

SMBus Address

DATALMDATALL

A N P

CMD=read

A

BYTCNT=7

A

Rd

DATAUM

ADDRL

A

A A A

DATAUU

A

A

N

ADDRU

A P

ADDRLCMD (status)

PES12N3 User Manual 7 - 13 June 7, 2006

IDT SMBus Interfaces Slave SMBus Interface

Notes

PES12N3 Slave

S

SMBus Address

Wr A

CCODE

START,END

A

BYTCNT=4

CMD=read

A

EEADDR

A

ADDRL

A

A

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

ADDRU

ADDRL

P

A

Wr A N

Wr A A

CCODE

START,END

CCODE

START,END

A

(PES12N3 not ready with data)

P

PES12N3 Slave

S

SMBus Address

DATAADDRU

A P

N

BYTCNT=5

Rd

A

A A A

EEADDRCMD (status)

Figure 7.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC Disabled

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

Wr A

Wr A

Wr A A

CCODE

START,END

CCODE

START,END

CCODE

START,END

(PES12N3 busy with previous command, not ready for a new command)

N

P

(PES12N3 busy with previous command, not ready for a new command)

N

P

BYTCNT=7

A

CMD=write

ADDRL

A

A

ADDRU

A

DATALL

DATALM

A

DATAUM

A

DATAUU

A

A P

Figure 7.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled

PES12N3 Slave

S

SMBus Address

Wr A

ADDRU

A

CCODE

START,END

DATA

A

A P

BYTCNT=5

CMD=write

A

EEADDR

A

ADDRL

A

Figure 7.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled

PES12N3 Slave

S

SMBus Address

Wr A A

ADDRU

A

CCODE

START,END

DATA

BYTCNT=5

A P

PEC

A

A

CMD=write

EEADDR

A

ADDRL

A

Figure 7.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled

A

A

PES12N3 User Manual 7 - 14 June 7, 2006

IDT SMBus Interfaces Slave SMBus Interface

Notes

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

PES12N3 Slave
SMBus Address

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

A

A

A

AS

A

CCODE

STAR T, Word

CCODE

END, Byte

CCODE

START,Word

CCODE

START,Word

CCODE

Byte

ADDRU

CCODE

Word

Wr A

Wr A A

Wr

Wr A

Rd

Wr

Rd A P

Wr

A

N P

A

A N

A

A

Rd A A

CMD=read

ADDRU

ADDRL

A

A

P

(PES12N3 not ready with data)

ADDRLC M D (s tatus)

DATALMDATALL

P

N

P

A

P

PES12N3 Slave

S

SMBus Address

PES12N3 Slave

S

SMBus Address

Wr

Rd A A

A

CCODE

END, Word

A

DATAUUDATAUM

N

P

Figure 7.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled

PES12N3 User Manual 7 - 15 June 7, 2006

IDT SMBus Interfaces Slave SMBus Interface

Notes

PES12N3 User Manual 7 - 16 June 7, 2006

Chapter 8

General Purpose I/O

Notes

Introduction

The PES12N3 has eight General Purpose I/O (GPIO) pins that may be individually configured as:
general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the
General Purpose I/O Control and Status (GPIOCS) register located in upstream port A’s PCI configuration
space (see Table 8.1).

GPIO Registers

Bit

Field

7:0 GPIOFUNC RW 0x0 GPIO Function. Each bit in this field controls the corre-

15:8 GPIOCFG RW 0x0 GPIO Configuration. Each bit in this field controls the cor-

Field

Name

Type

Default

Value

Description

sponding GPIO pin. When set to a one, the corresponding
GPIO pin operates as the alternate function as defined in
Table 8.2. When a bit is cleared to a zero, the correspond­ing GPIO pin operates as a general purpose I/O pin.

responding GPIO pin. When a bit is configured as a gen­eral purpose I/O pin and the corresponding bit in this field
is set, then the pin is configured as a GPIO output. When a
bit is configured as a general purpose I/O pin and the cor­responding bit in this field is zero, then the pin is config­ured as an input. When the pin is configured as an
alternate function, the behavior of the pin is defined by the
alternate function.

23:16 GPIOD RW HWINIT GPIO Data. Each bit in this field controls the correspond-

ing GPIO pin. Reading this field returns the current value
of each GPIO pin regardless of GPIO pin mode (i.e., alter­nate function or GPIO pin). Writing a value to this field
causes the corresponding pins which are configured as
GPIO outputs to change state to the value written.

31:24 Reserved RO 0x0 Reserved field.

Table 8.1 General Purpose IO Registers

As shown in Table 8.2, GPIO pins [5:0] are shared with other on-chip functions. The GPIO Function
(GPIOFUNC) field in the GPIOCS register controls whether a GPIO bit operates as a general purpose I/O
or as the specified alternate function.

PES12N3 User Manual 8 - 1 June 7, 2006

IDT General Purpose I/O GPIO Configuration

Notes

GPIO

Pin

Alternate

Function

Pin Name

2 IOEXPINTN Hot-plug I/O expander interrupt Input

3 PAABN Hot-plug port A attention button Input
4 PAAIN Hot-plug port A attention indicator output Output
5 PAPIN Hot-plug port A power indicator output Output

Table 8.2 General Purpose I/O Pin Alternate Function

Alternate Function Description

Alternate

Function
Pin Type

After reset, all GPIO pins default to the GPIO input function. GPIO pins configured as GPIO inputs are
sampled no more frequently than once every 128 ns and may be treated as asynchronous inputs.

When a GPIO pin is configured to use the GPIO function, the unneeded alternate function associated
with the pin is held in an inactive state by internal logic. Care should be exercised when configuring the
GPIO pins as outputs since an incorrect configuration could cause damage to external components as well
as the PES12N3.

GPIO Configuration

Each bit in the GPIOFUNC, GPIOCFG and GPIOD fields in the G PIOCS register is ass ociated wi th the
corresponding GPIO pin. Table 8.3 summarizes the configuration of GPIO pins.

GPIOFUNC GPIOCFG Pin Function

0 0 GPIO input
0 1 GPIO output
1 don’t care Alternate function

Table 8.3 GPIO Pin Configuration

GPIO Pin Config ured as an Inpu t

When configured as an input in the GPIOCFG field and as a GPIO function in the GPIOFUNC field, the
GPIO pin is sampled and registered in the GPIOD field. The value of the input pin can be determined at any
time by reading the GPIOD field. Note that the value in this field corresponds to the value of the pin irre­spective of whether the pin is configured as a GPIO input, GPIO output or alternate function.

GPIO Pin Configured as an Output

When configured as an output in the GPIOCFG field and as a GPIO function in the GPIOFUNC field, the
value in the corresponding bit position of the GPIOD field is driven on the pin. System designers should
treat the GPIO outputs as asynchronous outputs. The actual value of the output pin can be determined by
reading the GPIOD field.

GPIO Pin Configured as an Alternat e Function

When configured as an alternate function in the GPIOFUNC field, the pin behaves as an described by
the section associated with that function. The value of the alternate function pin can be determined at any
time by reading the GPIOD field.

PES12N3 User Manual 8 - 2 June 7, 2006

Chapter 9

Transparent Mode Operation

Notes

Introduction

When the PES12N3 is configured during a fundamental reset to operate in transparent mode or trans­parent mode with serial EEPROM initialization, the device functionally operates as illustrated in Figure 9.1.
In this mode, the PES12N3 may logically viewed as consisting of three PCI-PCI transparent bridges, one
per port, and an internal virtual PCI bus.

Associated with each port is a 4 KB configuration space and a Type 1 configuration header. The organi­zation of these configuration spaces is described in section Port Configuration Space Organization on page
9-6. The functional operation of the PES12N3 in transparent mode is fully consistent with that described in
the PCI Express® Base Specification, revision 1.0a for a three port switch.

Port A

(Upstream Port)

Type 1

Configuration Header

PCI-PCI

Transparent

Bridge

Virtual PCI Bus

Type 1

Configuration Header

PCI-PCI

Transparent Bridge

(Device 0)

Port B

(Downstream Port)

Figure 9.1 PES12N3 Functional Block Diagram in Transparent Mode

Type 1

Configuration Header

PCI-PCI

Transparent Bridge

(Device 1)

Port C

(Downstream Port)

As shown in Figure 9.1, port A is configured as the upstream port and ports B and C as the downstream
ports. Port B resides on the internal PCI Bus at Device 0, Function 0. Port C resides on the internal PCI Bus
at Device 1, Function 0.

PES12N3 User Manual 9 - 1 June 7, 2006

IDT Transparent Mode Operation End-to-End CRC

Notes

End-to-End CRC

PCIe® defines an optional end-to-end CRC associated with TLPs.

The PES12N3 fully supports ECRC for all TLPs that pass through the switch except for transactions
utilizing gathered and routed to root complex implicit routing. For transactions received with this routing
type, the ECRC is discarded and not checked and the resulting gathered message is generated without an
ECRC. The only standard defined message that utilizes this method of routing is the PME_TO_Ack
message.

The PES12N3 does not support ECRC for TLPs that it generates (e.g., configuration responses, INTx
messages, etc.). Also, it does not support ECRC for TLPs it consumes (e.g., configuration requests).
However; if a TLP is received with an ECRC, the CRC is discarded and not checked and the transaction is
performed.

Interrupts

The upstream port, port A, does not support generation of legacy interrupts or MSIs. The downstream
ports, ports B and C, do support generation of legacy interrupts and MSIs by their corresponding hot-plug
controllers. When configured to generate INTx messages, only INTA is used.

When an unmasked hot-plug interrupt condition occurs (see section Hot-Plug Interrupts and Wake-up
on page 6-6), then an MSI or interrupt message is generated by the corresponding port as described in
Table 9.1. The removal of the interrupt condition occurs when unmasked hot-plug status bits are masked or
cleared.

Unmasked

Hot-Plug

Interrupt

Asserted 1 X MSI message generated

Negated 1 X None

EN bit in

MSICAP

Register

0 0 Assert_INTA message request generated to switch

01None

0 0 Deassert_INTA message request generated to

01None

Table 9.1 Transparent Mode Port B and C Interrupts

INTXD bit

in PCICMD

Register

Action

core

switch core

Error Detection and Handling

This section describes error detection performed by an ingress or egress stack when the switch is
configured to operate in transparent mode. Table 9.2 lists error checks performed by the physical layer and
action taken when an error is detected.

PES12N3 User Manual 9 - 2 June 7, 2006

IDT Transparent Mode Operation Error Detection and Handling

Notes

PCIe Base

Error Condition

1.0a

Specification

Section

Action Taken

Invalid symbol or running disparity error
detected.

Any TLP or DLLP framing rule violation. 4.2.2.1 Correctable error processing
8b/10b decode error 4.2.4.4 Correctable error processing
Any violation of the link initialization or

training protocol

Table 9.2 Physical Layer Errors

4.2.1.3 Correctable error processing

4.2.4 Uncorrectable error processing

Table 9.3 lists error checks performed by the data link layer and action taken when an error is detected.

PCIe Base

Error Condition

TLP ending in ENDB with LCRC that
does not match inverted calculated LCRC

TLP received with incorrect LCRC 3.5.3.1 Correctable error processing
TLP received with sequence number not

equal to NEXT_RCV_SEQ and this is not
a duplicate TLP

Bad DLLP

1

1.0a

Specification

Section

3.5.3.1 TLP discarded

3.5.3.1 Correctable error processing

3.5.2.1 Correctable error processing

Action Taken

Replay time-out 3.5.2.1 Correctable error processing
REPLAY NUM rollover 3.5.2.1 Correctable error processing
Violation of flow control initialization pro-

tocol
Sequence number specified by

AckNak_Seq does not correspond to an
unacknowledged TLP or to the value in
ACKD_SEQ

1.

A bad DLLP is a DLP with a bad LCRC.

Table 9.3 Data Link Layer Errors

3.3.1 Uncorrectable error processing

3.5.2.1 Uncorrectable error processing

Tabl e 9.4 lists error checks performed by the transaction link layer and action tak en when an error is
detected.

PES12N3 User Manual 9 - 3 June 7, 2006

IDT Transparent Mode Operation Error Detection and Handling

Notes

PCIe Base

Error Condition

ECRC check failure 2.7.1 None. The PES12N3 does not check ECRC

Malformed TLP - Fatal error processing.
Flow control protocol error 2.6.1 Not applicable. The PES12N3 does not

Receiver overflow 2.6.1.2 None.

1.0a

Specification

Section

Action Taken

for transactions that terminate in the switch.

check for any flow control errors.

Completer abort
Completion time-out
Unsupported request

Unsupported request 2.3.1 See section Switch Core Errors on page 4-

Unexpected completion 2.3.2 Non-fatal error processing.

Table 9.4 Transaction Layer Errors

2.3.1

2.8

Not applicable. The PES12N3 never gener­ates non-posted transactions.

8.

Table 9.5 lists the error checks performed by the transaction layer for malformed TLPs. TLP error
checks are only performed when a TLP is received by the switch (i.e., by the stack associated with the port
on which the switch receives the TLP). No checks are made for malformed TLPs inside the switch.

TLP Type Error Check

All LENGTH < Max_Payload_Size (i.e., MPS field in

PCIEDCTL register)

I/O read request LENGTH = 1 (doubleword)

TC = 0,
ATTR = 0
The actual packet length is correct (4 doublewords
when CRC is present, 3doublewords otherwise)

I/O write request LENGTH = 1 (doubleword)

TC = 0
ATTR = 0
The actual packet length is correct (5 doublewords
when CRC is present, 4 doublewords otherwise)

Configuration read request LENGTH = 1 (doubleword)

TC = 0,
ATTR = 0
The actual packet length is correct (4 doublewords
when CRC is present, 3doublewords otherwise)

Configuration write request LENGTH = 1 (doubleword)

TC = 0
ATTR = 0
The actual packet length is correct (5 doublewords
when CRC is present, 4 doublewords otherwise)

Table 9.5 Malformed TLP Error Checks (Part 1 of 2)

PES12N3 User Manual 9 - 4 June 7, 2006

IDT Transparent Mode Operation Error Detection and Handling

Notes

TLP Type Error Check

Memory read request (32- and 64-bit address
mode)

Memory write request (32- and 64-bit address
mode)

Completion with data The packet length is correct.

The packet length is correct.
32-bit address mode: 3 doublewords when ECRC

is present, 4 doublewords otherwise
64-bit address mode: 4 doublewords when ECRC

is present, 5 doublewords otherwise
The packet length is correct.

32-bit address mode:

- Number of doublewords received equals
LENGTH + 4 when ECRC is present

- Number of doublewords received equals
LENGTH + 3 when a packet does not contain
ECRC

64-bit address mode

-Number of doublewords received equals LENGTH
+ 5 when ECRC is present

- Number of doublewords received equals
LENGTH + 4 when a packet does not contain
ECRC

- Number of doublewords received equals
LENGTH + 3 when a packet does not contain
ECRC

- Number of doublewords received equals
LENGTH + 4 when ECRC is present

- Number of doublewords received is not greater
then MaxPayloadSize + 3/4

Message or message with data The actual packet length is correct:

- Number of received double words equals
LENGTH + 4 when a packet does not contain
ECRC

- Number of received double words equals
LENGTH + 5 when ECRC is present

- Number of received doublewords is not greater
then MaxPayloadSize + 4/5

Interrupt messages
Power management messages
Error signalling messages
Unlock message
Set slot power limit message

Table 9.5 Malformed TLP Error Checks (Part 2 of 2)

TC = 0 (a message of this type is considered a
malformed TLP if it uses a traffic class designator
other than TC0)

PES12N3 User Manual 9 - 5 June 7, 2006

IDT Transparent Mode Operation Port Configuration Space Organization

Notes

Configuration Requests

The PCI-PCI bridges associated with ports A, B and C all have configuration registers that may be
accessed with Type 0 configuration read and write requests. PCIe allows multiple outstanding configuration
read and write requests. The PCI-PCI bridges in the PES12N3 each support a maximum of four
outstanding configuration requests. Issuing more than four outstanding configuration requests to any of
these entities may result in configuration requests being dropped.

Configuration accesses to different entities within the PES12N3 may complete out-of-order and may
limit the utility of multiple outstanding PCIe configuration accesses. For example, a configuration access
that modifies a secondary or subordinate bus number which is immediately followed by a Type 1 configura­tion access that relies on the modified value for routing may result in an error when issued concurrently , but
execute properly when issued in sequence. Configuration accesses to any particular entity always
complete in order.

Port Configuration Space Organization

The organization of port A, B and C configuration space is shown in Figure 9.2. While all three ports
share the same basic layout, only port A (the upstream port) has switch control and status registers and
only ports B and C (downstream ports) have an MSI capability structure. Port A does not contain an MSI
capability structure since it does not have an associated hot-plug controller that generates interrupts.

PES12N3 User Manual 9 - 6 June 7, 2006

IDT Transparent Mode Operation Port Configuration Space Organization

Notes

0x000

Type 1

Configuration Header

0x040

PCI Express

Capability Structure

0x070

0x07C

0x0A0

0x0F4

0x100

0x200

PCI Power Management

MSI Capability Structure

*** Ports B & C Only ***

Extended Cfg. Access &

Capability Structure

PCI

Configuration Space

(64 DWords)

Switch Control

& Status Registers

*** Port A Only ***

INTx Status

Virtual Channel

Capability Structure

Reserved

PCI Express Extended

Configuration Space

(960 DWords)

0x500

0x600
0xFFF

Switch Integrity Control

& Status Registers

Reserved

Figure 9.2 Port Configuration Space Organization

PES12N3 User Manual 9 - 7 June 7, 2006

IDT Transparent Mode Operation Upstream Port A Configuration Space Registers

Notes

Upstream Port A Configuration Space Registers

All configuration space locations not listed in Table 9.6 return a value of zero when read. Writes to these
locations are ignored and have no side-effects.

Port A configuration space registers may be read and written via the slave SMBus interface and initial­ized from the serial EEPROM using the CSR system address formed by adding the base address 0x0000
to the PCI configuration space offset address.

Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.

Cfg.

Offset

0x000 Word PA_VID VID - Vendor Identification (0x000) on page 9-17
0x002 Word PA_DID DID - Device Identification (0x002) on page 9-17
0x004 Word PA_PCICMD PCICMD - PCI Command (0x004) on page 9-17
0x006 Word PA_PCISTS PCISTS - PCI Status (0x006) on page 9-18
0x008 Byte PA_RID RID - Revision Identification (0x008) on page 9-19
0x009 3 Bytes PA_CCODE CCODE - Class Code (0x009) on page 9-19
0x00C Byte PA_CLS CLS - Cache Line Size (0x00C) on page 9-20
0x00D Byte PA_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-20

Size

Register

Mnemonic

Register Definition

0x00E Byte PA_HDR HDR - Header Type Register (0x00E) on page 9-20
0x00F Byte PA_BIST BIST - Built-in Self Test (0x00F) on page 9-20
0x010 DWord PA_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-20
0x014 DWord PA_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-20
0x018 Byte PA_PBUSN PBUSN - Primary Bus Number (0x018) on page 9-21
0x019 Byte PA_SBUSN SBUSN - Secondary Bus Number (0x019) on page 9-21
0x01A Byte PA_SUBUSN SUBUSN - Subordinate Bus Number (0x01A) on page 9-21
0x01B Byte PA_SLTIMER SLTIMER - Secondary Latency Timer (0x01B) on page 9-21
0x01C Byte PA_IOBASE IOBASE - I/O Base (0x01C) on page 9-21
0x01D Byte PA_IOLIMIT IOLIMIT - I/O Limit (0x01D) on page 9-22
0x01E Word PA_SECSTS SECSTS - Secondary Status (0x01E) on page 9-22
0x020 Word PA_MBASE MBASE - Memory Base (0x020) on page 9-23
0x022 Word PA_MLIMIT MLIMIT - Memory Limit (0x022) on page 9-23
0x024 Word PA_PMBASE PMBASE - Prefetchable Memory Base (0x024) on page 9-23
0x026 Word PA_PMLIMIT PMLIMIT - Prefetchable Memory Limit (0x026) on page 9-24
0x028 DWord PA_PMBASEU PMBASEU - Prefetchable Memory Base Upper (0x028) on page

9-24

0x02C DWord PA_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on page

9-24

0x030 Word PA_IOBASEU IOBASEU - I/O Base Upper (0x030) on page 9-24

Table 9.6 Upstream Port A Configuration Space Registers (Part 1 of 3)

PES12N3 User Manual 9 - 8 June 7, 2006

IDT Transparent Mode Operation Upstream Port A Configuration Space Registers

Notes

Cfg.

Offset

0x032 Word PA_IOLIMITU IOLIMITU - I/O Limit Upper (0x032) on page 9-25
0x034 Byte PA_CAPPTR CAPPTR - Capabilities Pointer (0x034) on page 9-25
0x038 DWord PA_EROMBASE EROMBASE - Expansion ROM Base Address (0x038) on page

0x03C Byte PA_INTRLINE INTRLINE - Interrupt Line (0x03C) on page 9-25
0x03D Byte PA_INTRPIN INTRPIN - Interrupt PIN (0x03D) on page 9-25
0x03E Word PA_BCTRL BCTRL - Bridge Control (0x03E) on page 9-26
0x040 DWord PA_PCIECAP PA_PCIECAP - PCI Express Capability (0x040) on page 9-10
0x044 DWord PA_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page

0x048 Word PA_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 9-28
0x04A Word PA_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 9-29
0x04C DWord PA_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 9-

0x050 Word PA_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 9-30
0x052 Word PA_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 9-31
0x070 DWord PA_PMCAP PMCAP - PCI Power Management Capabilities (0x070) on page

Size

Register

Mnemonic

Register Definition

9-25

9-27

30

9-36

0x074 DWord PA_PMCSR PMCSR - PCI Power Management Control and Status (0x074)

on page 9-36

0x078 DWord PA_PMPC PMPC - PCI Power Management Proprietary Control (0x078) on

page 9-37

0x0A0 DWord PA_SWSTS SWSTS Switch Status (0x0A0) on page 9-40
0x0A4 DWord PA_SWCTL SWCTL - Switch Control (0x0A4) on page 9-42
0x0A8 DWord PA_GPIOCS GPIOCS - General Purpose I/O Control and Status (0x0A8) on

page 9-45

0x0AC DWord PA_SMBUSSTS SMBUSSTS - SMBus Status (0x0AC) on page 9-45

0x0B0 DWord PA_SMBUSCTL SMBUSCTL - SMBus Control (0x0B0) on page 9-46
0x0B4 DWord PA_EEPROMINTF EEPROMINTF - Serial EEPROM Interface (0x0B4) on page 9-

47

0x0B8 DWord PA_IOEXPINTF IOEXPINTF - I/O Expander Interface (0x0B8) on page 9-48

0x0BC DWord PA_TMCTL TMCTL - Test Mode Control (0x0BC) on page 9-55

0x0C0 DWord PA_TMFSTS TMFSTS - Test Mode Fail Status (0x0C0) on page 9-56
0x0C4 DWord PA_TMSSTS TMSSTS - Test Mode Synchronization Status (0x0C4) on page

9-56

0x0C8 DWord PA_TMCNTCFG TMCNTCFG - Test Mode Count Configuration (0x0C8) on page

9-57

0x0CC DWord PA_TMCNT0 TMCNT0 - Test Mode Count 0 (0x0CC) on page 9-59

0x0D0 DWord PA_TMCNT1 TMCNT1 - Test Mode Count 1 (0x0D0) on page 9-59

Table 9.6 Upstream Port A Configuration Space Registers (Part 2 of 3)

PES12N3 User Manual 9 - 9 June 7, 2006

IDT Transparent Mode Operation Upstream Port A Configuration Space Registers

Notes

Cfg.

Offset

0x0D4 DWord PA_TMCNT2 TMCNT2 - Test Mode Count 2 (0x0D4) on page 9-60
0x0F4 Word PA_INTSTS INTSTS - Interrupt Status (0x0F4) on page 9-49
0x0F8 DWord PA_ECFGADDR ECFGADDR - Extended Configuration Space Access Address

0x0FC DWord PA_ECFGDATA ECFGDATA - Extended Configuration Space Access Data

0x100 DWord PA_PCIEVCECAP PCIEVCECAP - PCI Express Virtual Channel Enhanced Capa-

0x104 DWord PA_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x104) on page 9-50
0x110 DWord PA_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x110) on page 9-51
0x114 DWord PA_VCR0CTL VCR0CTL- VC Resource 0 Control (0x114) on page 9-51
0x118 DWord PA_VCR0STS VCR0STS - VC Resource 0 Status (0x118) on page 9-52
0x120 DWord PA_VCR0TBL0 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120)

0x124 DWord PA_VCR0TBL1 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124)

0x200 —

0x414

Size

Register

Mnemonic

Register Definition

(0x0F8) on page 9-49

(0x0FC) on page 9-50

bility Header (0x100) on page 9-50

on page 9-53

on page 9-54

Reserved

0x500 Dword PA_SWSICTL SWSICTL - Switch System Integrity Control (0x500) on page 9-

60

0x504 Dword PA_SWSIPECNT SWSIPECNT - Switch System Integrity Parity Error Count

(0x504) on page 9-61

0x508 Dword PA_SWSITDCNT SWSITDCNT - Switch System Integrity Time-Out Drop Count

(0x508) on page 9-61

0x510 —

0x61C

Table 9.6 Upstream Port A Configuration Space Registers (Part 3 of 3)

Reserved

Register Specialization

PA_PCIECAP - PCI Express Capability (0x040)

Bit

Field

7:0 CAPID — — PCIECAP - PCI Express Capability (0x040) on page 9-26

15:8 NXTPTR — — PCIECAP - PCI Express Capability (0x040) on page 9-26

19:16 VER — — PCIECAP - PCI Express Capability (0x040) on page 9-26

Field

Name

Type

Default

Value

Description

23:20 TYPE RO 0x5 Port Type. Upstream port of a PCI-Express switch.

PES12N3 User Manual 9 - 10 June 7, 2006

IDT Transparent Mode Operation Downstream Port B Configuration Space Registers

Notes

Bit

Field

24 SLOT RWL 0x0 Slot Implemented. This bit is set when the PCI Express

29:25 IMN — — PCIECAP - PCI Express Capability (0x040) on page 9-26
31:30 Reserved RO 0x0 Reserved field.

Field

Name

Type

Default

Value

Description

link associated with this Port is connected to a slot. Does
not apply to the upstream port and should be set to zero.

Downstream Port B Configuration Space Registers

All configuration space locations not listed in Table 9.7 return a value of zero when read. Writes to these
locations are ignored and have no side-effects. Port B configuration space registers may be read and
written via the slave SMBus interface and initialized from the serial EEPROM using the CSR system
address formed by adding the base address 0x1000 to the PCI configuration space offset address.

Cfg.

Offset

0x000 Word PB_VID VID - Vendor Identification (0x000) on page 9-17
0x002 Word PB_DID DID - Device Identification (0x002) on page 9-17
0x004 Word PB_PCICMD PCICMD - PCI Command (0x004) on page 9-17

Size

Register

Mnemonic

Register Definition

0x006 Word PB_PCISTS PCISTS - PCI Status (0x006) on page 9-18
0x008 Byte PB_RID RID - Revision Identification (0x008) on page 9-19
0x009 3 Bytes PB_CCODE CCODE - Class Code (0x009) on page 9-19
0x00C Byte PB_CLS CLS - Cache Line Size (0x00C) on page 9-20
0x00D Byte PB_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-20
0x00E Byte PB_HDR HDR - Header Type Register (0x00E) on page 9-20
0x00F Byte PB_BIST BIST - Built-in Self Test (0x00F) on page 9-20
0x010 DWord PB_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-20
0x014 DWord PB_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-20
0x018 Byte PB_PBUSN PBUSN - Primary Bus Number (0x018) on page 9-21
0x019 Byte PB_SBUSN SBUSN - Secondary Bus Number (0x019) on page 9-21
0x01A Byte PB_SUBUSN SUBUSN - Subordinate Bus Number (0x01A) on page 9-21
0x01B Byte PB_SLTIMER SLTIMER - Secondary Latency Timer (0x01B) on page 9-21
0x01C Byte PB_IOBASE IOBASE - I/O Base (0x01C) on page 9-21
0x01D Byte PB_IOLIMIT IOLIMIT - I/O Limit (0x01D) on page 9-22
0x01E Word PB_SECSTS SECSTS - Secondary Status (0x01E) on page 9-22
0x020 Word PB_MBASE MBASE - Memory Base (0x020) on page 9-23
0x022 Word PB_MLIMIT MLIMIT - Memory Limit (0x022) on page 9-23
0x024 Word PB_PMBASE PMBASE - Prefetchable Memory Base (0x024) on page 9-23
0x026 Word PB_PMLIMIT PMLIMIT - Prefetchable Memory Limit (0x026) on page 9-24

Table 9.7 Downstream Port B Configuration Space Registers (Part 1 of 3)

PES12N3 User Manual 9 - 11 June 7, 2006

IDT Transparent Mode Operation Downstream Port B Configuration Space Registers

Notes

Cfg.

Offset

0x028 DWord PB_PMBASEU PMBASEU - Prefetchable Memory Base Upper (0x028) on page

0x02C DWord PB_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on page

0x030 Word PB_IOBASEU IOBASEU - I/O Base Upper (0x030) on page 9-24
0x032 Word PB_IOLIMITU IOLIMITU - I/O Limit Upper (0x032) on page 9-25
0x034 Byte PB_CAPPTR CAPPTR - Capabilities Pointer (0x034) on page 9-25
0x038 DWord PB_EROMBASE EROMBASE - Expansion ROM Base Address (0x038) on page

0x03C Byte PB_INTRLINE INTRLINE - Interrupt Line (0x03C) on page 9-25
0x03D Byte PB_INTRPIN INTRPIN - Interrupt PIN (0x03D) on page 9-25
0x03E Word PB_BCTRL BCTRL - Bridge Control (0x03E) on page 9-26
0x040 DWord PB_PCIECAP PB_PCIECAP - PCI Express Capability (0x040) on page 9-13
0x044 DWord PB_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page

0x048 Word PB_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 9-28
0x04A Word PB_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 9-29
0x04C DWord PB_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 9-

Size

Register

Mnemonic

Register Definition

9-24

9-24

9-25

9-27

30

0x050 Word PB_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 9-30
0x052 Word PB_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 9-31
0x054 DWord PB_PCIESCAP PCIESCAP - PCI Express Slot Capabilities (0x054) on page 9-

32

0x058 Word PB_PCIESCTL PCIESCTL - PCI Express Slot Control (0x058) on page 9-33
0x05A Word PB_PCIESSTS PCIESSTS - PCI Express Slot Status (0x05A) on page 9-35
0x070 DWord PB_PMCAP PMCAP - PCI Power Management Capabilities (0x070) on page

9-36

0x074 DWord PB_PMCSR PMCSR - PCI Power Management Control and Status (0x074)

on page 9-36

0x078 DWord PB_PMPC PMPC - PCI Power Management Proprietary Control (0x078) on

page 9-37

0x07C DWord PB_MSICAP MSICAP - Message Signaled Interrupt Capability and Control

(0x07C) on page 9-39

0x080 DWord PB_MSIADDR MSIADDR - Message Signaled Interrupt Address (0x080) on

page 9-39

0x084 DWord PB_MSIUADDR MSIUADDR - Message Signaled Interrupt Upper Address

(0x084) on page 9-40

0x088 DWord PB_MSIMDATA MSIMDATA - Message Signaled Interrupt Message Data

(0x088) on page 9-40

0x0F4 Word PB_INTSTS INTSTS - Interrupt Status (0x0F4) on page 9-49

Table 9.7 Downstream Port B Configuration Space Registers (Part 2 of 3)

PES12N3 User Manual 9 - 12 June 7, 2006

IDT Transparent Mode Operation Downstream Port B Configuration Space Registers

Notes

Cfg.

Offset

0x0F8 DWord PB_ECFGADDR ECFGADDR - Extended Configuration Space Access Address

0x0FC DWord PB_ECFGDATA ECFGDATA - Extended Configuration Space Access Data

0x100 DWord PB_PCIEVCECAP PCIEVCECAP - PCI Express Virtual Channel Enhanced Capa-

0x104 DWord PB_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x104) on page 9-50
0x110 DWord PB_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x110) on page 9-51
0x114 DWord PB_VCR0CTL VCR0CTL- VC Resource 0 Control (0x114) on page 9-51
0x118 DWord PB_VCR0STS VCR0STS - VC Resource 0 Status (0x118) on page 9-52
0x120 DWord PB_VCR0TBL0 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120)

0x124 DWord PB_VCR0TBL1 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124)

0x200 —

0x414
0x500 Dword PB_SWSICTL SWSICTL - Switch System Integrity Control (0x500) on page 9-

Size

Register

Mnemonic

Register Definition

(0x0F8) on page 9-49

(0x0FC) on page 9-50

bility Header (0x100) on page 9-50

on page 9-53

on page 9-54

Reserved

60

0x504 Dword PB_SWSIPECNT SWSIPECNT - Switch System Integrity Parity Error Count

(0x504) on page 9-61

0x508 Dword PB_SWSITDCNT SWSITDCNT - Switch System Integrity Time-Out Drop Count

(0x508) on page 9-61

0x510 —

0x61C

Table 9.7 Downstream Port B Configuration Space Registers (Part 3 of 3)

Reserved

Register Specialization

PB_PCIECAP - PCI Express Capability (0x040)

Bit

Field

7:0 CAPID — — PCIECAP - PCI Express Capability (0x040) on page 9-26

15:8 NXTPTR — — PCIECAP - PCI Express Capability (0x040) on page 9-26
19:16 VER — — PCIECAP - PCI Express Capability (0x040) on page 9-26
23:20 TYPE RO 0x6 Port Type. Downstream port of a PCI-Express switch.

24 SLOT RWL 0x0 Slot Implemented. This bit is set when the PCI Express

Field

Name

Type

Default

Value

Description

link associated with this Port is connected to a slot.
29:25 IMN — — PCIECAP - PCI Express Capability (0x040) on page 9-26
31:30 Reserved RO 0x0 Reserved field.

PES12N3 User Manual 9 - 13 June 7, 2006

IDT Transparent Mode Operation Downstream Port C Configuration Space Registers

Notes

Downstream Port C Configuration Space Registers

All configuration space locations not listed in Table 9.8 return a value of zero when read. Writes to these

locations are ignored and have no side-effects.

Port C configuration space registers may be read and written via the slave SMBus interface and initial­ized from the serial EEPROM using the CSR system address formed by adding the base address 0x2000
to the PCI configuration space offset address.

Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.

Cfg.

Offset

0x000 Word PC_VID VID - Vendor Identification (0x000) on page 9-17
0x002 Word PC_DID DID - Device Identification (0x002) on page 9-17
0x004 Word PC_PCICMD PCICMD - PCI Command (0x004) on page 9-17
0x006 Word PC_PCISTS PCISTS - PCI Status (0x006) on page 9-18
0x008 Byte PC_RID RID - Revision Identification (0x008) on page 9-19
0x009 3 Bytes PC_CCOD E CCODE - Class Code (0x009) on page 9-19
0x00C Byte PC_CLS CLS - Cache Line Size (0x00C) on page 9-20
0x00D Byte PC_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-20

Size

Register

Mnemonic

Register Definition

0x00E Byte PC_HDR HDR - Header Type Register (0x00E) on page 9-20
0x00F Byte PC_BIST BIST - Built-in Self Test (0x00F) on page 9-20
0x010 DWord PC_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-20
0x014 DWord PC_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-20
0x018 Byte PC_PBUSN PBUSN - Primary Bus Number (0x018) on page 9-21
0x019 Byte PC_SBUSN SBUSN - Secondary Bus Number (0x019) on page 9-21
0x01A Byte PC_SUBUSN SUBUSN - Subordinate Bus Number (0x01A) on page 9-21
0x01B Byte PC_SLTIMER SLTIMER - Secondary Latency Timer (0x01B) on page 9-21
0x01C Byte PC_IOBASE IOBASE - I/O Base (0x01C) on page 9-21
0x01D Byte PC_IOLIMIT IOLIMIT - I/O Limit (0x01D) on page 9-22
0x01E Word PC_SECSTS SECSTS - Secondary Status (0x01E) on page 9-22
0x020 Word PC_MBASE MBASE - Memory Base (0x020) on page 9-23
0x022 Word PC_MLIMIT MLIMIT - Memory Limit (0x022) on page 9-23
0x024 Word PC_PMBASE PMBASE - Prefetchable Memory Base (0x024) on page 9-23
0x026 Word PC_PMLIMIT PMLIMIT - Prefetchable Memory Limit (0x026) on page 9-24
0x028 DWord PC_PMBASEU PMBASEU - Prefetchable Memory Base Upper (0x028) on

page 9-24

0x02C DWord PC_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on

page 9-24

0x030 Word PC_IOBASEU IOBASEU - I/O Base Upper (0x030) on page 9-24

Table 9.8 Downstream Port C Configuration Space Registers (Part 1 of 3)

PES12N3 User Manual 9 - 14 June 7, 2006

IDT Transparent Mode Operation Downstream Port C Configuration Space Registers

Notes

Cfg.

Offset

0x032 Word PC_IOLIMITU IOLIMITU - I/O Limit Upper (0x032) on page 9-25
0x034 Byte PC_CAPPTR CAPPTR - Capabilities Pointer (0x034) on page 9-25
0x038 DWord PC_EROMBASE EROMBASE - Expansion ROM Base Address (0x038) on

0x03C Byte PC_INTRLINE INTRLINE - Interrupt Line (0x03C) on page 9-25
0x03D Byte PC_INTRPIN INTRPIN - Interrupt PIN (0x03D) on page 9-25
0x03E Word PC_BCTRL BCTRL - Bridge Control (0x03E) on page 9-26
0x040 DWord PC_PCIECAP PC_PCIECAP - PCI Express Capability (0x040) on page 9-16
0x044 DWord PC_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on

0x048 Word PC_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 9-

0x04A Word PC_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 9-

0x04C DWord PC_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page

0x050 Word PC_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 9-30
0x052 Word PC_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 9-31

Size

Register

Mnemonic

Register Definition

page 9-25

page 9-27

28

29

9-30

0x054 DWord PC_PCIESCAP PCIESCAP - PCI Express Slot Capabilities (0x054) on page

9-32

0x058 Word PC_PCIESCTL PCIESCTL - PCI Express Slot Control (0x058) on page 9-33
0x05A Word PC_PCIESSTS PCIESSTS - PCI Express Slot Status (0x05A) on page 9-35
0x070 DWord PC_PMCAP PMCAP - PCI Power Management Capabilities (0x070) on

page 9-36

0x074 DWord PC_PMCSR PMCSR - PCI Power Management Control and Status

(0x074) on page 9-36

0x078 DWord PC_PMPC PMPC - PCI Power Management Proprietary Control (0x078)

on page 9-37

0x07C DWord PC_MSICAP MSICAP - Message Signaled Interrupt Capability and Control

(0x07C) on page 9-39

0x080 DWord PC_MSIADDR MSIADDR - Message Signaled Interrupt Address (0x080) on

page 9-39

0x084 DWord PC_MSIUADDR MSIUADDR - Message Signaled Interrupt Upper Address

(0x084) on page 9-40

0x088 DWord PC_MSIMDATA MSIMDATA - Message Signaled Interrupt Message Data

(0x088) on page 9-40

0x0F4 Word PC_INTSTS INTSTS - Interrupt Status (0x0F4) on page 9-49
0x0F8 DWord PC_ECFGADDR ECFGADDR - Extended Configuration Space Access

Address (0x0F8) on page 9-49

0x0FC DWord PC_ECFGDATA ECFGDATA - Extended Configuration Space Access Data

(0x0FC) on page 9-50

Table 9.8 Downstream Port C Configuration Space Registers (Part 2 of 3)

PES12N3 User Manual 9 - 15 June 7, 2006

IDT Transparent Mode Operation Downstream Port C Configuration Space Registers

Notes

Cfg.

Offset

0x100 DWord PC_PCIEVCECAP PCIEVCECAP - PCI Express Virtual Channel Enhanced

0x104 DWord PC_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x104) on page 9-50
0x110 DWord PC_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x110) on page 9-51
0x114 DWord PC_VCR0CTL VCR0CTL- VC Resource 0 Control (0x114) on page 9-51
0x118 DWord PC_VCR0STS VCR0STS - VC Resource 0 Status (0x118) on page 9-52
0x120 DWord PC_VCR0TBL0 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120)

0x124 DWord PC_VCR0TBL1 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124)

0x200 —

0x414
0x500 Dword PC_SWSICTL SWSICTL - Switch System Integrity Control (0x500) on page

0x504 Dword PC_SWSIPECNT SWSIPECNT - Switch System Integrity Parity Error Count

0x508 Dword PC_SWSITDCNT SWSITDCNT - Switch System Integrity Time-Out Drop Count

Size

Register

Mnemonic

Register Definition

Capability Header (0x100) on page 9-50

on page 9-53

on page 9-54

Reserved

9-60

(0x504) on page 9-61

(0x508) on page 9-61

0x510 —

0x61C

Table 9.8 Downstream Port C Configuration Space Registers (Part 3 of 3)

Reserved

Register Specialization

PC_PCIECAP - PCI Express Capability (0x040)

Bit

Field

7:0 CAPID — — PCIECAP - PCI Express Capability (0x040) on page 9-26

15:8 NXTPTR — — PCIECAP - PCI Express Capability (0x040) on page 9-26
19:16 VER — — PCIECAP - PCI Express Capability (0x040) on page 9-26
23:20 TYPE RO 0x6 Port Type. Downstream port of a PCI-Express switch.

24 SLOT RWL 0x0 Slot Implemented. This bit is set when the PCI Express

29:25 IMN — — PCIECAP - PCI Express Capability (0x040) on page 9-26.
31:30 Reserved RO 0x0 Reserved field.

Field

Name

Type

Default

Value

Description

link associated with this Port is connected to a slot.

PES12N3 User Manual 9 - 16 June 7, 2006

IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition

Notes

Generic PCI to PCI Bridge Register Definition

Type 1 Configuration Heade r Registers

VID - Vendor Identification (0x000)

Bit

Field

15:0 VID RO 0x111D Vendor Identification. This field contains the 16-bit ven-

DID - Device Identification (0x002)

Bit

Field

15:0 DID RO - Device Identification. This field contains the 16-bit device

PCICMD - PCI Command (0x004)

Field

Name

Field

Name

Type

Type

Default

Value

Default

Value

Description

dor ID value assigned to IDT. See section Vendor ID on
page 1-4.

Description

ID assigned by IDT to this transparent bridge. See section
Device ID on page 1-4.

Bit

Field

0IOAERW0x0I/O Access Enable. When this bit is cleared, the bridge

1MAERW0x0Memory Access Enable. When this bit is cleared, the

2BMERW0x0Bus Master Enable. When this bit is cleared, the bridge

3 SSE RO 0x0 Special Cycle Enable. Not applicable.

Field

Name

Type

Default

Value

Description

does not respond to I/O accesses from the primary bus
specified by IOBASE and IOLIMIT.
0x0 - (disable) Disable I/O space.
0x1 - (enable) Enable I/O space.

bridge does not respond to memory and prefetchable
memory space access from the primary bus specified by
MBASE, MLIMIT, PMBASE and PMLIMIT.
0x0 - (disable) Disable memory space.
0x1 - (enable) Enable memory space.

does not issue requests (e.g., memory, I/O and MSIs since
they are in-band writes) on behalf of subordinate devices
and responds to non-posted transactions with a Unsup­ported Request (UR) completion. This bit does not affect
completions in either direction or the forwarding of non
memory or I/O requests.
0x0 - (disable) Disable request forwarding.
0x1 - (enable) Enable request forwarding.

4MWIRO0x0Memory Write Invalidate. Not applicable.
5VGASRO0x0VGA Palette Snoop. Not applicable.

PES12N3 User Manual 9 - 17 June 7, 2006

IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition

Notes

Bit

Field

6 PERRE RW 0x0 Parity Error Enable. The Master Data Parity Error bit is

7ADSTEPRO0x0Address Data Stepping. Not applicable.
8 SERRE RW 0x0 SERR Enable. Non-fatal and fatal errors detected by the

9FB2BRO0x0Fast Back-to-Back Enable. Not applicable.

10 INTXD RW 0x0 INTx Disable. Controls the ability of the PCI-PCI bridge to

15:11 Reserved RO 0x0 Reserved field.

Field

Name

Type

Default

Value

Description

set in the PCI Status register (PCISTS) if this bit is set and
the bridge receives a poisoned completion or a poisoned
write. If this bit is cleared, then the Master Data Parity Error
bit in the PCI Status register is never set.
0x0 - (disable) Disable Master Parity Error bit reporting.
0x1 - (enable) Enable Master Parity Error bit reporting.

bridge are reported to the Root Complex when this bit is set
or the bits in the PCI Express Device Control register are
set (see PCIEDCTL - PCI Express Device Control
(0x048)).
0x0 - (disable) Disable non-fatal and fatal error reporting

if also disabled in Device Control register.

0x1 - (enable) Enable non-fatal and fatal error reporting.

generate an INTx interrupt message.

PCISTS - PCI Status (0x006)

Bit

Field

2:0 Reserved RO 0x0 Reserved.

3INTSRO0x0INTx Status. This bit is set when an INTx interrupt is pend-

4 CAPL RO 0x1 Capabilities List. This bit is hardwired to one to indicate

5 C66MHZ RO 0x0 66 MHz Capable. Not applicable.
6 Reserved RO 0x0 Reserved.
7FB2BRO0x0Fast Back-to-Back (FB2B). Not applicable.
8 MDPED RW1C 0x0 Master Data Parity Error Detected. This bit is set when

Field

Name

Type

Default

Value

Description

ing from the device.
INTx emulation interrupts forwarded by switch ports from
devices downstream of the bridge are not reflected in this
bit. For ports B and C, this bit is set if an interrupt has been
“asserted” by the corresponding port’s hot-plug controller.
For port A, this field is always zero.

that the bridge implements an extended capability list item.

the PERRE bit is set in the PCI Command register and the
bridge receives a poisoned completion or poisoned write
request on the primary side of the bridge.
0x0 - (noerror) no error.
0x1 - (error) Poisoned write request or completion

received on primary side.

PES12N3 User Manual 9 - 18 June 7, 2006

IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition

Notes

Bit

Field

10:9 DEVT RO 0x0 DEVSEL# Timing. Not applicable.

11 STAS RO 0x0 Signall ed Target Abort. Not applicable since a target

12 RTAS RO 0x0 Received Target Abort. Not applicable.
13 RMAS RO 0x0 Received Master Abort. Not applicable.
14 SSE RW1C 0x0 Signalled System Error. This bit is set when the bridge

15 DPE RW1C 0x0 Detected Parity Error. This bit is set by the bridge when-

Field

Name

Type

Default

Value

Description

abort is never signalled.

sends a ERR_FATAL or ERR_NONFATAL message and
the SERR Enable (SERRE) bit is set in the PCICMD regis­ter.
0x0 - (noerror) no error.
0x1 - (error) This bit is set when a fatal or non-fatal error

is signalled.

ever it receives a poisoned TLP on the primary side regard­less of the state of the PERRE bit in the PCI Command
register.
For downstream ports, this bit is also set when a internal
switch parity error is detected. See section Data Integrity
on page 4-4.

RID - Revision Identification (0x008)

Bit

Field

7:0 RID RWL — Revision ID. This field contains the revision identification

Field

Name

Type

Default

Value

Description

number for the device.
See section Revision ID on page 1-5.

CCODE - Class Code (0x009)

Bit

Field

7:0 INTF RO 0x00 Interface. This value indicates that the device is a PCI-

15:8 SUB RO 0x04 Sub Class Code. This value indicates that the device is a

23:16 BASE RO 0x06 Base Class Code. This value indicates that the device is a

Field

Name

Type

Default

Value

Description

PCI bridge that does not support subtractive decode.

PCI-PCI bridge.

bridge.

PES12N3 User Manual 9 - 19 June 7, 2006

IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition

Notes

CLS - Cache Line Size (0x00C)

Bit

Field

7:0 CLS RW 0x00 Cache Line Size. This field has no effect on the bridge’s

Field

Name

Type

Default

Value

Description

functionality but may be read and written by software.
This field is implemented for compatibility with legacy soft­ware.

PLTIMER - Primary Latency Timer (0x00D)

Bit

Field

7:0 PLTIMER RO 0x00 Primary Latency Timer. Not applicable.

Field

Name

Type

Default

Value

Description

HDR - Header Type Register (0x00E)

Bit

Field

7:0 HDR RO 0x01 Header Type. This value indicates a type 1 header with a

Field

Name

Type

Default

Value

Description

single function bridge layout.

BIST - Built-in Self Test (0x00F)

Bit

Field

7:0 BIST RO 0x0 BIST. This value indicates that the bridge does not imple-

Field

Name

Type

Default

Value

Description

ment BIST.

BAR0 - Base Address Register 0 (0x010)

Bit

Field

31:0 BAR RO 0x0 Base Address Register. Not applicable.

Field

Name

Type

Default

Value

Description

BAR1 - Base Address Register 1 (0x014)

Bit

Field

31:0 BAR RO 0x0 Base Address Register. Not applicable.

Field

Name

Type

Default

Value

Description

PES12N3 User Manual 9 - 20 June 7, 2006