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®
IDT® 89HPEB383
®
PCI Express
Bridge
User Manual
July 2011
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
©2011 Integrated Device Technology, Inc.
Printed in U.S.A.
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
GENERAL DISCLAIMER
Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
at your own risk. IDT MAKES NO REPRESENT ATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY
OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENT ATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY OR COMPLETENESS
OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR
THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, I NCIDENTAL, INDIRECT, PUNITIVE OR
SPECIAL DAMAGES, HOWEVER THEY MAY ARIS E, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code
examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with
any applicable laws or regulations.
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.
CODE DISCLAIMER
LIFE SUPPORT POLICY
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Contents
About this Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 PCIe Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.3 PCI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 PCIe Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 EEPROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6 Power-up Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7 Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
i
3. Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.1 Upstream Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.2 Downstream Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Transaction Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 Upstream Transaction Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Downstream Transaction Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 Upstream Non-posted Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Upstream Posted Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.3 Downstream Non-posted Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.4 Downstream Posted Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5 Prefetching Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6 Short Term Caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 Polarity Inversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4. Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Memory-mapped I/O Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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4.3 Prefetchable Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.5 VGA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.6 ISA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.7 Non-transparent Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7.1 PCIe to PCI Non-prefetchable Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7.2 PCIe to PCI Prefetchable Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7.3 PCI to PCIe Address Remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.8 Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5. Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.1 Type 0 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2.2 Type 1 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2.3 Type 1 to Type 0 Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.4 Type 1 to Type 1 Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.5 Type 1 to Special Cycle Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3 PCIe Enhanced Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4 Configuration Retry Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6. Bridging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2 Flow Control Advertisements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3 Buffer Size and Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4 Assignment of Requestor ID and Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.5 Forwarding of PCIe to PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.5.1 PCIe Memory Write Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.5.2 PCIe Non-posted Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.6 Forwarding of PCI to PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.6.1 PCI Memory Write Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.6.2 PCI Non-posted Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.7 PCI Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.8 PCIe Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.9 Message Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.9.1 INTx Interrupt Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.9.2 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.9.3 Locked Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.9.4 Slot Power Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.9.5 Vendor-defined and Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.10 Transaction Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.11 Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7. PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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7.3 PCI Arbitration Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8. Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.3 Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9. Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2 PCIe as Originating Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.1 Received Poisoned TLPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.2.2 Received ECRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.2.3 PCI Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.2.4 PCI Uncorrectable Address/Attribute Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.2.5 Received Master-Abort on PCI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.2.6 Received Target-Abort On PCI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.3 PCI as Originating Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.3.1 Received PCI Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.3.2 Unsupported Request Completion Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.3 Completer Abort Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.4 Timeout Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.4.1 PCIe Completion Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.4.2 PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.5 Other Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.6 Error Handling Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10. Reset and Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.1 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.1.1 PCIe Link Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.1.2 PCI Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.2 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.2.1 PCIe Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.2.2 PCI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.1.2 Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.2 Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3 Power States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3.1 ASPM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3.2 L0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.3.3 L0s State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.3.4 L1 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.3.5 L2/L3 Ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.3.6 L3 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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11.3.7 LDn State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.3.8 Link State Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.3.9 Device Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.3.10 D0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.3.11 D3
11.3.12 D3
11.3.13 D State Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.3.14 Power Management Event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.3.15 Power State Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.4 Power Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Hot
State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Cold
12. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.2 System Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3 EEPROM Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.4 Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.2 TAP Controller Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.3 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.4 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.5 JTAG Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.6 JTAG Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
13.6.1 Register Access from JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
13.6.2 Write Access to Registers from the JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
13.6.3 Read Access to Registers from JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.7 Dedicated Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.8 Accessing SerDes TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.2 PCI Configuration Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
14.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
14.3.1 PCI Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.3.2 PCI Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.3.3 PCI Class Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.4 PCI Miscellaneous 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.3.5 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.3.6 PCI Secondary Status and I/O Limit and Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.3.7 PCI Memory Base and Limit Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
14.3.8 PCI PFM Base and Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5
14.3.9 PCI PFM Base Upper 32 Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.3.10 PCI PFM Limit Upper 32 Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.3.11 PCI I/O Address Upper 16 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.3.12 PCI Capability Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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14.3.13 PCI Bridge Control and Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.3.14 Secondary Retry Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
14.3.15 PCI Miscellaneous Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
14.3.16 PCI Miscellaneous Clock Straps Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.3.17 Upstream Posted Write Threshold Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.3.18 Completion Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
14.3.19 Clock Out Enable Function and Debug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.3.20 SERRDIS_OPQEN_DTC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14.4 Upstream Non-transparent Address Remapping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
14.4.1 NTMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
14.4.2 NTMA Primary Upper Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14.4.3 NTMA Secondary Lower Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14.4.4 NTMA Secondary Upper Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.4.5 NTMA Secondary Lower Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.4.6 NTMA Secondary Upper Limit Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.5 PCI Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.5.1 SSID/SSVID Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.5.2 SSID Capability Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
14.5.3 SSID ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
14.5.4 PCI Power Management Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
14.5.5 PCI Power Management Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
14.5.6 EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
14.5.7 Secondary Bus Device Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
14.5.8 Short-term Caching Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
14.5.9 Retry Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
14.5.10 Prefetch Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
14.6 PCIe Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
14.6.1 PCIe Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
14.6.2 PCIe Device Capabilities Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.6.3 PCIe Device Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
14.6.4 PCIe Link Capabilities Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
14.6.5 PCIe Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
14.7 Downstream Non-transparent Address Remapping Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
14.7.1 Secondary Bus Non-prefetchable Address Remap Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 184
14.7.2 Secondary Bus Non-prefetchable Upper Base Address Remap Register . . . . . . . . . . . . . . . . . . . . . . 185
14.7.3 Secondary Bus Prefetchable Address Remap Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.7.4 Secondary Bus Prefetchable Upper Base Address Remap Register . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.7.5 Primary Bus Non-prefetchable Upper Base Address Remap Register . . . . . . . . . . . . . . . . . . . . . . . . 186
14.7.6 Primary Bus Non-prefetchable Upper Limit Remap Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.8 Advanced Error Reporting Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
14.8.1 PCIe Advanced Error Reporting Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
14.8.2 PCIe Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
14.8.3 PCIe Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.8.4 PCIe Uncorrectable Error Severity Registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.8.5 PCIe Correctable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
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14.8.6 PCIe Correctable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
14.8.7 PCIe Advanced Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
14.8.8 PCIe Header Log 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
14.8.9 PCIe Header Log 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
14.8.10 PCIe Header Log 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
14.8.11 PCIe Header Log 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
14.8.12 PCIe Secondary Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
14.8.13 PCIe Secondary Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
14.8.14 PCIe Secondary Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
14.8.15 PCIe Secondary Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
14.8.16 PCIe Secondary Header Log 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
14.8.17 PCIe Secondary Header Log 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.8.18 PCIe Secondary Header Log 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
14.8.19 PCIe Secondary Header Log 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
14.8.20 Replay Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.8.21 ACK/NACK Update Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
14.8.22 N_FTS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
14.9 PCIe and SerDes Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.9.1 Base Offset Address Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.9.2 PCIe Per-Lane Transmit and Receive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
14.9.3 PCIe Transmit and Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
14.9.4 PCIe Output Status and Transmit Override Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
14.9.5 PCIe Receive and Output Override Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.9.6 PCIe Debug and Pattern Generator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
14.9.7 PCIe Pattern Matcher Control and Error Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
14.9.8 PCIe SS Phase and Error Counter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.9.9 PCIe Scope Control and Frequency Integrator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
14.9.10 PCIe Clock Module Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
14.9.11 PCIe Control and Level Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
14.9.12 PCIe Control and Level Override Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
15. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
15.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
15.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
15.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
15.4 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
15.5 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
15.6 AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
15.6.1 PCI Interface AC Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
15.6.2 PCIe Differential Transmitter Output Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
15.6.3 PCIe Differential Receiver Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
15.6.4 Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
15.6.5 Boundary Scan Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
15.6.6 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
15.7 AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
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16. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
16.1 Pinouts and Mechanical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
16.1.1 QFP Package Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
16.1.2 QFP Package Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
16.1.3 QFN Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.1.4 QFN Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
16.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.3 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
17. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
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Figures
Figure 1: PEB383 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2: PEB383 Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3: Network Interface Card Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4: DVR Card Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5: Motherboard Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6: ExpressCard Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7: Upstream Data Path[update for PEB383] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8: Downstream Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9: Memory-mapped I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10: 64-bit Prefetchable Memory Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11: I/O Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12: ISA Mode I/O Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13: Memory Window Remapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14: PCIe Configuration Address Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15: PCI Type 0 Configura tion Ad dress Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16: PCI Type 1 Configura tion Ad dress Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17: PCI Arbiter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 18: PCI Arbitration Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 19: Arbitration Pointers – Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 20: Arbitration Pointers – Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 21: Interrupt Handling Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 22: PCIe Flowchart of Device Error Signaling and Logging Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 23: Transaction Error Forwarding with PCIe as Originating Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 24: Transaction Error Forwarding with PCI as Originating Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 25: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 26: PCIe Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 27: PCI Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 28: PCIe Link Power Management States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 29: D State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 30: EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 31: 9-bit EEPROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 32: 16-bit EEPROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 33: 9-bit EEPROM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 34: 16-bit EEPROM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 35: EEPROM WREN Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 36: EEPROM RDSR Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 37: Read/Write Access from JTAG — Serial Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 38: Observe from JTAG — Serial Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 39: PCIe SerDes Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 40: Transmitter Eye Voltage and Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 41: Minimum Receiver Eye Timing and Voltage Compliance Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 42: Weighing Function for RMS Phase Jitter Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
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Figure 43: Input Timing Measurement Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 44: Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 45: PCI TOV (max) Rising Edge AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 46: PCI TOV (max) Falling Edge AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 47: PCI TOV (min) AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
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Tables
Table 1: Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2: PCIe Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3: PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4: EEPROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5: JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6: Power-up Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7: Power Supply Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8: Completion Buffer Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9: Initial Credit Advertisement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10: PCI Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11: PCIe Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 12: Transaction Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 13: Error Forwarding Requirements (Step A to Step B) for Received PCIe Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 14: Bridge Requirements for Transactions Requiring a Completion (Immediate Response) . . . . . . . . . . . . . . . . . . . . 68
Table 15: Error Forwarding Requirements for Received PCI Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 16: Error Forwarding Requirements for PCI Delayed Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 17: ECRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 18: Poisoned TLP Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 19: Malformed TLP Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 20: Link and Flow Control Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 21: Uncorrectable Data/Address Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 22: Received Master/Target Abort Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 24: Request Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 23: Completion Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 25: Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 26: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 27: PCI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 28: PCIe Link States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 29: Power Management State Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 30: Power saving modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 31: EEPROM Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 32: PCI Type 1 Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 33: SSID Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 34: Power Management Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 35: PCIe Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 36: Advanced Error Reporting Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 37: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 38: SerDes Per-lane and Clock Control and Status Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 39: TX_LVL Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 40: Absolute Maximum Ratings – PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 41: Absolute Maximum Ratings – PCIe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 42: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
xi
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Tablesxii
Table 43: PEB383 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 44: PEB383 Power Dissipation per Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 45: DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 46: PCI Clock (PCI_CLK) Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 47: PCIe Differential Transmitter Output Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 48: PCIe Differential Receiver Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 49: Reference Clock (PCIE_REFCLK _n/p) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 0
Table 50: Boundary Scan Test Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 51: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 52: Thermal Specifications — 66MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 53: Thermal Specifications — 33MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
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About this Document
This section discusses the following topics:
• “Scope” on page 1
• “Document Conventions” on page 1
Scope
The PEB383 User Manual discusses the features, configuration requirements, and design architecture
of the PEB383.
Document Conventions
This document uses the following conventions.
1
Non-differential Signal Notation
Non-differential signals are either active-low or active-high. An active-low signal has an active state of
logic 0 (or the lower voltage level), and is denoted by a lowercase “n”. An active-high signal has an
active state of logic 1 (or the higher voltage level), and is not denoted by a special character. The
following table illustrates the non-differential signal naming convention.
State Single-line signal Multi-line signal
Active low NAMEn NAMEn[3]
Active high NAME NAME[3]
Differential Signal Notation
Differential signals consist of pairs of complement positive and negative signals that are measured at
the same time to determine a signal’s active or inactive state (they are denoted by “_p” and “_n”,
respectively). The following table illustrates the differential signal naming convention.
State Single-line signal Multi-line signal
Inactive NAME_p = 0
NAME_n = 1
NAME_p[3] = 0
NAME_n[3] = 1
Active NAME_p = 1
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NAME_p[3] is 1
NAME_n[3] is 0
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About this Document2
Object Size Notation
•A byte is an 8-bit object.
•A word is a 16-bit object.
•A doubleword (Dword) is a 32-bit object.
Numeric Notation
• Hexadecimal numbers are denoted by the prefix 0x (for example, 0x04).
• Binary numbers are denoted by the prefix 0b (for example, 0b010).
• Registers that have multiple iterations ar e denoted by {x..y} in their names; where x is first register
and address, and y is the last register and address. For example, REG{0..1} indicates there are two
versions of the register at different addresses: REG0 and REG1.
Symbols
Tip
This symbol indicates important configuration information or suggestions.
This symbol indicates procedures or operating levels that may result in misuse or damage to
the device.
Specification Status
• Version 0.25 – This specification describes early design and functional inform ation abo ut a devi ce.
It is available at the G2 gate, which precedes the definition and planning phase.
• Version 0.5 – This specification describes early design and functional information about a device.
It is available after the G2 gate, but during the definition and planning phase.
• Version 0.75 – This specification describes the majority of functional information about a device. It
is available at the G3 gate, which precedes the development phase.
• Version 1.0 – This specification describes all the functional information about a device. It is
available at the G4 gate, which precedes the qualification (tape-out) phase.
This symbol indicates a basic design concept or information considered helpful.
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About this Document 3
Revision History
October 22, 2009: Initial publication of PEB383 User Manual.
November 18, 2009: Updated pinouts for QFN and QFP packages.
December 8, 2009: Updated pinouts and package drawings for QFN and QFP packages.
December 18, 2009: Added simulated power numbers to Table 43. Updated Tables 51 and 52 with
simulated Thermal Characteristics values. Updated pinouts and package drawings for QFN and QFP
packages.
January 20, 2010: In Table 7, changed power numbers for Core, PCIe, and PLL from 1.0V to 1.05V in
the Description column and from 1.2V to 1.05V in the Design Rec. column. In Table 42, changed
power numbers for Core, PCIe, and PLL from 1.2V to 1.05V and also changed minimum and
maximum values for these 3 parameters. In Table 43, changed power numbers for Core, PCIe, and PLL
from 1.0V to 1.05V.
March 29, 2010: In Table 3, changed pull-up resistor values from 2.4K to 8.2K for Interrupts A, B, C,
and D.
May 5, 2010: In Table 42, changed TA min and max temperatures to 0 and 70 respectively. In Section
15.3, updated old Table 43 and added new Table 44 for Power Dissipation values.
May 28, 2010: In Chapter 16, Packaging, updated QFP package drawing. Added new Chapter 17,
Ordering Information.
August 3, 2010: In Chapter 17, added Tape and Reel to ordering codes.
November 23, 2010: In Chapter 16, replaced existing QFN package drawing with revised PSC-4327.
January 5, 2011: In Chapter 13, section 13.7, deleted last bullet containing reference to
TEST_BIDIR_CTRL.
March 7, 2011: In Chapter 14, changes bit types labeled RE to RWL, added description for RWL in
section 14.1, revised description for bits 0 and 1 in register CLKOUT_ENB_FUNC_DBG, and
changed Reset Value in RID field to 0x01 in register PCI_CLSS. In Chapter 16, section 16.1.2, added
revised 128-pin QFP package drawing.
May 17, 2011: In Chapter 14, section 14.5.1, added text to the third paragraph that starts with “Note
that...”. Added ZB silicon to Order page in Chapter 17.
o
May 26, 2011: In Chapter 15, Table 42, changed maximum ambient temperature from 70 to 85
C.
June 21, 2011: In Chapter 2, Table 3, changed pull-up for PCI_INTA-D pins from 8.2K to 2.4K.
July 25, 2011: In Chapter 2, Table 3, revised text in Design Recommendation for PCIE_REFCLK pins.
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About this Document4
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1. Functional Overview
Topics discussed include the following:
• “Overview”
• “Features”
• “Device Architecture”
• “Typical Applications”
1.1 Overview
The IDT PEB383 is a high-performance bus bridge that connects the PCI Express (PCIe) protocol to
the PCI bus standard (see Figure 1).
The PEB383’s PCIe Interface supports a x1 lane PCIe configuration. This enables the bridge to offer
exceptional throughput performance of up to 2.5 Gbps per transmit and receive direction. The device’s
PCI Interface can operate up to 66 MHz. This interface offers designers extensive flexibility by
supporting the flowing addressing modes: transparent, and non-transparent.
5
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Figure 1: PEB383 Block Diagram
1. Functional Overview > Features6
1.2 Features
The PEB383’s key features are listed in the following sub-sections.
1.2.1 General Features
• Forward bridge, PCIe to PCI
• Single store and forward for optimal latency performance
• Supports two modes of addressing:
— Transparent: For eff icient, flow-through configurations
— Non-transparent: For address remapping of the PCIe and the PCI domains
• Compliant to the following specifications:
— PCI Express Base Specification (Revision 1.1)
— PCI Express-to-PCI/PCI-X Bridge Specification (Revision 1.0)
— PCI-to-PCI Bridge Specification (Revision 1.2)
— PCI Local Bus Specification (Revision 3.0)
— PCI Bus Power Management Interface Specification (Revision 1.2)
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1. Functional Overview > Features 7
• 3.3V PCI I/Os with 5V tolerant I/Os
• Support for four external PCI bus masters through an integrated arbiter
• Support for external PCI bus arbiter
• Support for Masquerade mode (can overwrite vendor and device ID from EEPROM)
• JTAG IEEE 1149.1, 1149.6
• Support for D0, D3 hot, D3 cold power management states
• Support for Subsystem ID (SSID) and Subsystem Vendor ID (SSVID)
• Legacy mode support for subtractive decode
• Exclusive access using PCI_LOCKn
• Packaged in a 14x14mm 128 pin TQFP and a 10x10mm 132 pin QFN.
1.2.2 PCIe Features
• 1 lane
• 128-byte maximum payload
• Advanced error reporting capability
• End-to-end CRC (ECRC) check and generation
• Up to four outstanding memory reads
• 512-byte read completion buffer
• ASPM L0s link state power management
•ASPM L1
• Legacy interrupt signaling
1.2.3 PCI Features
• 32/64-bit addressing
• 32-bit data bus
•5V tolerant
• Exclusive access using PCI_LOCKn
• 25-, 33-, 50-, and 66-MHz operation
• Up to four outstanding read requests
• 1-KB read completion buffer
• Clock outputs for four PCI devices
• Short-term caching support
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1.3 Device Architecture
A high-level, architectural diagram of the PEB383 is displayed in Figure 2. For more information about
data flow through the device, see “Upstream Data Path” and “Downstream Data Path”.
Figure 2: PEB383 Device Architecture
PCIe (Primary Interface)
Rx PH Y
SERDES
Data Link Layer
Tr ansa ct i on La ye r
Flow co ntrol
ACK/noACK
1. Functional Overview > Device Architecture8
Tx P HY
SERDES
Dat a L ink Lay e r
Transaction Layer
CLK/
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PC I In te r fa c e (Se c ond ary In te r face )
Packets received on the PCIe Interface are processed by the data link layer and transaction layer, if
applicable. If a packet is destined for the transaction layer, its address is decoded and forwarded to the
appropriate destination:
• Configuration register
• Downstream posted write buffer
• Downstream read request queue
• Downstream read completion buffer
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1. Functional Overview > Device Architecture 9
PCI data that is destined for the PCIe fabric are subject to PCIe ordering rules. Data is pulled from the
appropriate queue:
• Configuration register
• Upstream posted write buffer
• Upstream read request queue
• Upstream read completion buffer
PCI transactions that are decoded for the PCIe address space are forwarded to the appropriate queue:
• Upstream read request queue
• Upstream posted write buffer
Transactions destined for downstream devices on the PCI bus, are subject to PCI ordering rul es. Data is
pulled form the appropriate queue:
• Downstream posted write buffer
• Downstream read request queue
PCIe is a serialized protocol at the physical layer, and a packetized protocol at the data link layer. The
PCIe lane operates at 2.5 Gb symbol rate, or at 2.0 Gb data rate; the difference is a result of the 8/10b
coding process. The PEB383 uses the following processes to ensure the accurate and timely delivery of
data through the data link layer:
• Credit-based flow control – Prevents data loss and congestion
• ACK/noACK protocol and End-to-End CRC (ECRC) – Ensures reliable data delivery if bit errors
occur
• Replay buffer – Replays packets that are not acknowledged by the receiver (NAK)
In contrast, PCI is a parallel data interface at the physical layer. PCI is a non-packetized protocol.
When a bus master starts a read or a write transaction, it indicates only the starting transaction address
to the target, and not the size of the read or write. In the case of a PCI write, which is initiated on the
PCI Interface and is destined for the root complex, the data is written into an upstream posted write
buffer in the PEB383. The end of the write transaction is signaled by the master on the PCI bus. Once
the write is completed the data can be forwarded to the PCIe Interface. If the posted write buffer is
about to overflow, the PEB383 indicates a retry/disconnect on the PCI bus. Once the posted write
buffer empties, the PEB383 can accept additional write transactions. The PEB383 will split write
transactions as required to meet PCIe constraints: to prevent a write crossing a 4-KB boundary; if byte
enables are used throughout the transaction; or if the quantity of data exceeds the maximum payload
size (see MAX_SIZE in “PCIe Device Capabilities Register”). The upstream posted write buffer is
managed as a simple FIFO.
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1. Functional Overview > Typical Applications10
A read initiated on the PCI bus that is decoded for an upstream target is handled as a delayed
transaction by the PEB383. The bridge latches the read transaction and attempts to reserve buffer space
in its upstream read completion buffer. If space is successfully reserved in the buffer, the PEB383
initiates a read on the PCIe Interface. When the read data is returned from the root comple x, it is store d
in the upstream read completion buffer. PCI-initiated reads, however, do not define the amount of data
to read. Once the master on the PCI bus retries the read transaction, the transaction is checked to
determine if the read data is returned. If it has the read data, the PEB383 responds as the target and
transfers the read data to the PCI bus. Note the upstream read completion buffer is not a simple FIFO,
as the order that masters on the PCI bus retry is not deterministic. If the complet io n buffer becomes
empty prior to the transaction completing, the PEB383 disconnects from the PCI bus. When the read
transaction is completed, the PEB383 discards any prefetched data that is not used and frees up the
buffer . The maximum number of outstanding read requests per master is controlled by DTL[7:0] bits in
“Secondary Retry Count Register”.
A write initiated on the PCIe Interface with the target on the downstream PCI bus is written into the
downstream posted write buffer. The PEB383 acts as the master for the transaction and arbitrates for
the PCI bus and initiates the write transaction. The downstream posted write buffer is managed as a
FIFO. There will always be space available in the buffer to accept packet data because of the flow
control method used by the PCIe data link layer. If the downstream posted write buffer is about to
overflow , the upstream device will be informed of this by its lack of credits and will not send any more
write data to the PEB383.
A read initiated on the PCIe Interface with the target on the downstream PCI bus is written into the
downstream read request queue. The downstream read request queue is managed with flow control
credits to prevent overflowing. The PEB383 latches the read transaction and attempts to reserve space
in the downstream read completion buffer. If space is successfully reserved in the buffer, the PEB383
acts as the master for the transaction and initiates a read transaction on the PCI bus.Programmable
address decoders instruct the PEB383 which transactions on the PCI bus to forward upstream, and
which transactions on the PCIe link to forward downstream.
1.4 Typical Applications
This section illustrates some typical applications for the PEB383.
Figure 3: Network Interface Card Application
Integrated
CPU
PEB383
32-bit,
66-MHz
PCIx1 PCIe
FE
GbE
USB
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1. Functional Overview > Typical Applications 11
Figure 4: DVR Card Application
Camera
Camera
Camera
Camera
Video
Decoder
Video
Decoder
PCI Bus
PEB383
x1 PCIe
Figure 5: Motherboard Application
PCI Slot
PCI Slot
PCI
PEB383
PCIe
Video
Decoder
10x10 mm footprint
Supports up to four
PCI devices off x1 PCIe
Video
Decoder
80E2000_TA002_01
Graphics
Memory
80E2040_TA001_01
PCIe Slot
Processor
Chipset
Peripherals
CPU
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Figure 6: ExpressCard Application
1. Functional Overview > Typical Applications12
x1 PCIe
PEB383
PCI
I/O Controller
80E2010_TA001_01
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2. Signal Descriptions
Topics discussed include the following:
• “Overview”
• “PCIe Interface Signals”
• “PCI Interface Signals”
• “EEPROM Interface Signals”
• “JTAG Interface Signals”
• “Power-up Signals”
• “Power Supply Signals”
2.1 Overview
13
Signals are classified according to the types defined in the following table.
Table 1: Pin Types
Pin Type Definition
3.3 OD 3.3V CMOS open-drain output
3.3 3-state 3.3V CMOS tri-state output
3.3 Bidir 3.3V CMOS bi-directional
3.3 Bidir PU 3.3V CMOS bi-directional with 265K (+/- 45K) pull-up resistor
3.3 Bidir OD 3.3V CMOS bi-directional open-drain
3.3 In 3.3V CMOS input
3.3 In PU 3.3V CMOS input with 265K (+/- 45K) pull-up resistor
3.3 Out 3.3V CMOS output
PCI Bidir PCI bi-directional
PCI Bidir OD PCI bi-directional open-drain
PCI In PCI input
PCI Out PCI output
PCI OD PCI output open-drain
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Table 1: Pin Types (Continued)
Pin Type Definition
PCIE Diff Out PCIe differential output
PCIE Diff In PCIe differential input
2.2 PCIe Interface Signals
Table 2: PCIe Interface Signals
Name Pin Type Description Design Recommendation
2. Signal Descriptions > PCIe Interface Signals14
PCIE_PERSTn 3.3 In Master reset in:
0 = PEB383 in reset
1 = PEB383 in normal mode
PCIE_TXD_n
PCIE_TXD_p
PCIE_RXD_n
PCIE_RXD_p
PCIE_REFCLK_n
PCIE_REFCLK_p
PCIE_REXT Analog - This signal must be connected to VSS
PCIE Diff Out Transmit Data. These differential pair
signals send PCIe 8b/10b encoded
symbols and an embedded clock to the
link partner.
PCIE Diff In Receive Data. These differential pair
signals receive PCIe 8b/10b encoded
symbols and an embedded clock from
the link partner.
PCIE Diff In Reference Clock. 100-MHz differential
reference clock.
Direct connect to the PERST# signal.
DC blocking capacitors must be placed
in the link between the transmitter and
the receiver. Place a 0603 or 0402
0.075uF to 0.1uF ceramic capacitor on
each TXD_n, TXD_p signal.
DC blocking capacitors must be placed
in the link between the transmitter and
the receiver; however, the DC blocking
capacitors are normally placed near the
transmitter. When designing an add-in
card, capacitors are not required on this
link. When designing a system board,
the DC blocking capacitors should be
placed near the transmitter.
Refer to Board Design Guidelines.
with a 191-ohm (1%) resistor.
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2. Signal Descriptions > PCI Interface Signals 15
2.3 PCI Interface Signals
Table 3: PCI Interface Signals
Name Pin Type Description Design Recommendation
PCI_AD[31:0] PCI Bidir Address/Data Bus. These multiplexed
signals provide a 32/64-bit address a nd
32-bit data bus.
PCI_CBEn[3:0] PCI Bidir Command/Byte Enables. These
multiplexed signals indicate the current
transaction type.
PCI_CLK PCI In PCI Input Clock. This signal provides
timing for the PEB383, either from an
external clock or from one of the
PCI_CLKO[4:0] signals (see
“Clocking”).
PCI_CLKO[4:0] PCI Out PCI Output Clocks
(see “Clocking”).
PCI_DEVSELn PCI Bidir Device Select. A target device asserts
this signal when it decodes its address
on the bus. The master samples the
signal at the beginning of a transaction,
and the target rescinds it at the end of
the transaction.
PCI_FRAMEn PCI Bidir Frame. The current initiator drives this
signal to indicate the start and duration
of a transaction, and the bus target
samples it. The bus master rescinds the
signal at the end of the transaction.
None.
None.
None.
Point-to-point connection to PCI device.
IDT recommends a 33 Ohm series
termination resistor. In Master clocking
mode, PCI_CLKO[4] should be
connected to PCI_CLK.
Pull up (8.2K) to VIO_PCI.
Pull up (8.2K) to VIO_PCI.
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Table 3: PCI Interface Signals (Continued)
Name Pin Type Description Design Recommendation
2. Signal Descriptions > PCI Interface Signals16
PCI_GNTn[3:0] PCI Bidir / PCI
Out
PCI_INTDn PCI In Interrupt D. Pull-up (2.4K) to VIO_PCI.
PCI_INTCn PCI In Interrupt C. Pull-up (2.4K) to VIO_PCI.
PCI_INTBn PCI In Interrupt B. Pull-up (2.4K) to VIO_PCI.
Bus Grant. The PEB383 uses these
multifunction signals to grant access to
the PCI bus; however, they are used
differently depending on whether or not
the PEB383 PCI arbiter is used. If the
arbiter is used, then PCI_GNTn[3:0] are
outputs used by the PEB383 to grant
access to the bus (see “PCI
Arbitration”).
If an external arbiter is used,
PCI_GNTn[0] is an input that is driven
by the arbiter to grant the PEB383
access to the bus. The remaining pins,
PCI_GNTn[3:1], remain as outputs.
The input/output mode is controlled by
bit[9] of “PCI Miscellaneous 0 Register”
on page 129.
Note: The PCI bus arbiter can be placed
on the last bus master by bit[8] of “PCI
Miscellaneous 0 Register” on page 129.
PCI_GNTn[3:0] outputs connect directly
to the PCI device’s PCI_GNTn inputs.
Pull ups are not required on unused
outputs.
PCI_INTAn PCI In Interrupt A. Pull-up (2.4K) to VIO_PCI.
PCI_IRDYn PCI Bidir Initiator Ready. The bus master asserts
this signal to indicate it is ready to
complete the current transaction.
PCI_LOCKn PCI OD Lock. This signal is used by the bus
master to lock the currently addressed
memory target during a series of
exclusive access transactions (see
“Exclusive Access”).
Pull-up (8.2K) to VIO_PCI.
Pull up (8.2K) to VIO_PCI.
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2. Signal Descriptions > PCI Interface Signals 17
Table 3: PCI Interface Signals (Continued)
Name Pin Type Description Design Recommendation
PCI_M66EN PCI In 66-MHz Enable. This signal enables the
PCI Interface for 66-MHz operation.
0 = 33-MHz operation
1 = 66-MHz operation
PCI_PAR PCI Bidir Parity. This signal carries even parity
across PCI_AD[31:0] and
PCI_CBEn[3:0]. The bus master
asserts this signal for the address and
write data phases. The bus target
asserts it for read data phases.
PCI_PERRn PCI Bidir Parity Error. This signal indicates a
parity error occurred during the current
data phase. The bus target that
receives the data asserts this signal.
PCI_PMEn PCI In Power Management Event. This signal
indicates a power management event
occurred (see “Power Management”).
PCI_M66EN is used only in master
clocking mode.
Embedded designs
Tied to ground for 33-MHz operation;
otherwise, pull up to VIO_PCI.
Bused designs using PCI slots for add-
in cards
Place a 10K pull-up resistor (to
VIO_PCI) on PCI_M66EN and route the
signal from slot to slot.
In slave clocking mode, PCI_M66EN
can be tied to ground.
No pull-up or pull-down resistor is
required.
Pull up (8.2K) to VIO_PCI.
Pull up (8.2K) to VIO_PCI.
PCI_REQn[3:0] PCI In
PCI Bidir
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Bus Request. These signals are used to
request access to the PCI bus. They are
used differently, however, depending on
whether or not the PEB383 PCI arbiter
is used. If the PCI arbiter is used, then
PCI_REQn[3:0] are inputs used by
external masters to request access to
the bus.
If an external arbiter is used,
PCI_REQn[0] is an output used by the
PEB383 to request access to the bus,
while PCI_REQn[3:1] should be pulled
high, as they are still inputs.
The input/output mode is controlled by
bit[9] of “PCI Miscellaneous 0 Register”
on page 129.
Note: The PCI bus arbiter can be placed
on the last bus master by bit[8] of “PCI
Miscellaneous 0 Register” on page 129.
Pull up (8.2K) to VIO_PCI.
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Table 3: PCI Interface Signals (Continued)
Name Pin Type Description Design Recommendation
2. Signal Descriptions > EEPROM Interface Signals18
PCI_RSTn PCI Out PCI reset: This signal reset s all device s
on the PC bus.
PCI_SERRn PCI Bidir OD System Error. This signal indicates an
address or attribute phase parity error
occurred.
PCI_STOPn PCI Bidir Stop. A bus target asserts this signal to
indicate it wants to stop the current
transaction on the current data phase.
PCI_TRDYn PCI Bidir Target Ready. The bus target asserts
this signal to indicate it is ready to
complete the current data phase.
2.4 EEPROM Interface Signals
Table 4: EEPROM Interface Signals
Name Pin Type Description Design Recommendation
SR_CLK 3.3 Out Serial ROM clock: This signal is derived
from REFCLKn/p (see “System
Diagram”).
SR_CSn 3.3 Out Serial ROM chip select: This active-low
signal activates the chip-select (CS) on
the external EEPROM.
No pull-up or pull-down resistor is
required.
Pull-up (8.2K) to VIO_PCI.
Pull-up (8.2K) to VIO_PCI.
Pull-up (8.2K) to VIO_PCI.
No pull-up or pull-down resistor is
required.
SR_DIN 3.3 Out Serial ROM data in: This signal
transfers output data from the PEB383
to the EEPROM.
SR_DOUT 3.3 In PU Serial ROM data out: This signal
transfers input data from the EEPROM
to the PEB383.
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2. Signal Descriptions > JTAG Interface Signals 19
2.5 JTAG Interface Signals
Table 5: JTAG Interface Signals
Name Pin Type Description Design Recommendation
JTAG_TCK 3.3 In Test Clock. This signal clocks state
information and data into and out of th e
PEB383 during boundary scan.
JTAG_TDI 3.3 In PU Test Data Input. This signal, in
conjunction with JTAG_TCK, shifts dat a
and instructions into the TAP controller
in a serial bit stream.
JTAG_TDO 3.3 Out Test Data Output. This signal, in
conjunction with JTAG_TCK, shifts dat a
and instructions from the T AP control ler
in a serial bit stream.
JTAG_TMS 3.3 In PU Test Mode Set. This signal controls the
state of the TAP controller.
JTAG_TRSTn 3.3 In PU Test Reset. This signal forces the TAP
controller into an initiali z e d state . Th is
signal must be pulsed or pulled low
externally to reset the TAP controller.
TEST_BCE 3.3 In Test Boundary Scan Compatibility
Enabled. This input aids 1149.6 testing
and Scope function of PHYs.
Connect to 3.3V using a 2K pull-up
resistor.
Connect to 3.3V using a 2K pull-up
resistor.
If JT AG is not used, leave unconnecte d.
Connect to 3.3V using a 2K pull-up
resistor.
If JTAG i s not used, connect this pin to a
2K pull-down resistor. If JTAG is used,
connect to output of AND gate where
inputs are TRST# and PERST#.
For more information, see the PEB383
Evaluation Board User Manual.
For 1149.1 Boundary Scan testing, this
pin must be low. For 1149.6 Boundary
Scan testing, this pin must be high.
TEST_ON 3.3 In This signal controls scan shift enable. Pull down for normal operation.
2.6 Power-up Signals
Table 6: Power-up Signals
Name Pin Type Description Design Recommendation
PWRUP_PLL_
BYPASS
3.3 In PLL bypass. This signal bypasses the
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PLL in the PCI clock generation (see
“PCI Clocking”).
0 = Normal operation
1 = PLL bypass
This signal should always be tied low.
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2.7 Power Supply Signals
Table 7: Power Supply Signals
2. Signal Descriptions > Power Supply Signals20
Name Pin Type Description Design Recommendation
VDD Core power 1.05V core power None.
VDD_PCI I/O power 3.3 volt I/O power for PCI and 3.3V I/O
power for CMOS
VDD_PCIE Core power 1.05V power for SerDes Connect these signals to the 1.05V
VDDA_PCIE Analog power 3.3V analog power for SerDes Connect these signals to the 3.3V
VDDA_PLL Analog power 1.05V analog power for PLL Connect these signals to the 1.05V
VIO_PCI I/O power 5.0 I/O power, for 5.0V I/O compliance.
This signal can also be tied to 3.3V if
5.0V compliance is not required.
VSS GND GND, core power None.
VSS_IO GND GND, I/O power None.
VSSA_PLL GND GND, analog PLL power None.
a. For filtering and decoupling information for these signals, see “Power Supply Filtering and Decoupling” in the PEB383 Board
Design Guidelines.
b. For more information, see “Analog Power Supply Filtering” in the PEB383 Board Design Guidelines.
None.
source through a ferrite bead.
source through a ferrite bead.
source through a ferrite bead.
Connect these signals to a 3.3V or 5V
source depending on the PCI devices
attached to the PEB383 PCI bus.
a
b
b
b
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3. Data Path
Topics discussed include the following:
• “Overview”
• “Transaction Management”
• “Buffer Structure”
• “Flow Control”
• “Prefetching Algorithm”
• “Short Term Caching”
• “Polarity Inversion”
3.1 Overview
21
The PEB383 uses two buffering methods for transferring data between its PCIe and PCI ports:
• Two-stage buffering for its upstream data path
• One-stage buffering in its downstream data path
These buffering methods are summarized in the following sub-sections.
3.1.1 Upstream Data Path
Two-stage buffering in the upstream path consists of two different sized buffers for each transaction
type: posted, non-posted, and completion (see Figure 7).
The first-stage buffering in the PCI Core, which supports the store and forward method, meets the
synchronization requirements of PCI and PCIe. This buffer design also provides optimized throughput
and improved latencies.
The second-stage buffering in the PCIe Core, which supports the cut-through method, handles the
possible backpressure due to scaled down link, lack of flow control credits, and replay. Posted and
completion buffers allow the PEB383 to accept a few more cycles of data transfer even after the
assertion of stall which indicates to the initiator in the PCI Core to stop the data transfer. This buffer
design ensures idle cycles are not inserted in data cycles while forwarding TLPs to its egress block.
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Figure 7: Upstream Data Path[update for PEB383]
3. Data Path > Overview22
A ddress
Decoder
Claim
Cycle
1stStage Buffering
Store and Forwa rd
Posted Buffer (512 bytes)
T
a
r
g
Non P osted Queue
e
t
I
n
t
e
r
f
a
c
e
M
a
s
t
e
r
I
n
t
e
r
f
a
c
e
8 E ntri es
Dow n s tre am Re ad
Completion Buffer
(51 2 byte s)
PCI Cor e
Device Core
Int erface
Posted Request
Non-Posted
Request
Com p let ions
PME_n
CS R
EHU
2ndStage Bufferi n g
Cut thr o ug h
Posted FIFO
( 512 bytes)
Non Posted FIFO
4 E ntries
Completion FIFO
(64 b yte s)
PME
Mesaa g e
TLP
PMC
Erro r Messa ge TLP
Retry Bu ffer (1 KB)
PCIe Core
S
c
r
a
m
b
l
e
r
3.1.2 Downstream Data Path
In the downstream path, the PEB383 uses one-stage buffering for each type of transaction (see
Figure 8). These buffers support the store and forward method, receive flow control, protocol
differences, synchronization, and error handling requirements.
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3. Data Path > Transaction Management 23
Figure 8: Downstream Data Path
Device Core Interface
Rec eive Fl ow
Contro l Buffe rs
Posted Buf fer
(512 Bytes)
Pac ket
Decoder
B
y
D
R
x
S
E
R
D
E
S
t
e
e
U
-
s
n
c
-
r
s
a
t
m
r
i
b
p
l
e
e
r
r
LC RC
Checker
Address
Decoder
EC RC
Che cke r
T LP
E rror
De t e ct e r
Reques t
Generator
Non-Posted Queue
4 Entries
Upstream Read
Completion Buffer
(1 K B)
A
r
b
i
t
e
r
Delayed Completion
M
a
s
t
e
r
I
n
t
e
r
f
a
c
e
P
C
I
I
n
t
e
r
f
a
c
e
T
a
r
g
e
t
I
n
t
e
r
f
a
c
e
PC Ie Cor e
3.2 Transaction Management
The following sub-sections describe how the PEB383 handles upstream and downstream transactions.
3.2.1 Upstream Transaction Management
Transactions that originate on the PCI Interface that are de stined for the PCIe Interface ar e stored in the
respective queues or buffers in the PCI clock domain, and are then forwarded to the PCIe Core (see
Figure 7). PCI buffer logic decomposes the received transactions as per the PCIe constraints (for
example, MAX_RD_SIZE, MAX_PAY_SIZE, RCB, and 4-KB address boundary). Three sets of data
and control signals for the three types of transactions (posted, non-posted, and completions) are used
between the PCI and PCIe Cores.
Transactions are stored temporarily in the PCIe Core buffers before they are used to construct TLPs,
and are then made visible to TLP arbiter. The TLPs are processed by the TLP arbiter only after
ordering rules are satisfied. The TLP arbiter selects one of the five input TLPs (error message, PME
message, posted, completion, and non-posted TLPs) in a round-robin mode if sufficient credits and
retry buffer space is available for the specific TLPs. The TLP arbiter continues to check the available
credit and retry buffer space against each of the active inputs, and selects the one that meets the
constraint. The ECRC adder calculates and appends a 32-bit ECRC value to the end of the TLP
selected by the arbiter if ECRC generation is enabled by software, and then forwards the TLP to the
Data link layer.
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The Data link layer applies a sequence number to the TLP received from transaction layer block, and
then calculates and appends a 32-bit LCRC value to ensure integrity during the transmission across the
physical lanes. A copy of the TLP sent to the physical layer is stored in the retry buffer for future replay
if there is negative acknowledgement from the other end component. The Retry buffer replays the
stored unacknowledged TLPs if it receives a NAK or replay timer expiration.
The Byte striper block of the physical layer unit appends start and end characters to the TLP received
from Data link layer, and then multiplexes the bytes of the packet onto the lanes. These bytes on the
lanes are scrambled using LFSR to eliminate repetitive bit patterns in the bit stream. The scrambled
8-bit characters are sent to the SerDes to convert to a 10-bit character in order to transmit it in a serial
bit stream on the physical lanes.
3.2.2 Downstream Transaction Management
In the downstream path, the physical layer unit converts the incoming serial bit stream into a parallel
symbol stream, de-scrambles the bytes in the transmit path, assembles packets, and then sends them to
the Data link layer unit (see Figure 8).
The Data link layer unit checks for LCRC and sequence number errors for packets received from the
physical layer unit. If there are no errors, LCRC and sequence number fields are stripped and resultant
TLP is sent to Transaction layer unit.
3. Data Path > Buffer Structure24
The Transaction layer unit checks for ECRC errors and framing violations based on header fields and
ECRC fields in the TLP received from the Data link layer unit. It extracts routing information based on
the header fields and determines whether to forward or reject the TLP. The ECRC field is stripped and
the resulting information in the TLP header, payload, and any detected error information, is sent to the
PCI Core.
The PEB383 uses receive flow control buffers in the PCI Core instead of in the PCIe Core to store
downstream requests or completions to be forwarded on the PCI Interface.
3.3 Buffer Structure
The following sub-sections describe the three PEB383 buffer structures:
• Upstream non-posted buffer
• Upstream posted buffer
• Downstream non-posted buffer
• Downstream posted buffer
3.3.1 Upstream Non-posted Buffer
There are four entries in the upstream read request queue. The 1-KB completion buffer is split up into
4 x 256-byte segments. When a read occurs on the PCI bus a read request is FIFO queued in one of the
4 entry non-posted request queue, if there is space. The PCI transaction is retried so that the master will
return when the bridge has fetched the data. If there are unallocated completion buffers (equal or
greater than the programed allocation size) a PCIe read request is sent upstream, requesting the
programed allocation amount of data.
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3. Data Path > Buffer Structure 25
By default the programed allocation amount of buffers that are allocated is equal to the prefetch size. In
order to prevent one device from consuming all the buffers, the allocation size can be programmed to
be less than the prefetch size. For example, if the prefetch size was set to 1 KB, then only one
outstanding request would result, as once all the buffers are allocated no more requests can be sent. The
allocation size can be programmed to be 512 bytes (or 256, 128) so that 1, 2, or 4 outstanding requests
are possible (see MAX_BUF_ALOC bits in the “Upstream Posted Write Threshold Register”).
Table 8: Completion Buffer Allocation
MAX_BUF_ALOC
Bit setting
----->
0b11 0b10 0b01 0b11
Prefetch ALOC
1024 bytes 1024 1 512 2 256 4 256 4
512 bytes 512 2 512 2 256 4 256 4
256 bytes 256 4 256 4 256 4 256 4
128 bytes 128 4 128 4 128 4 128 4
a. Completion buffer allocation in bytes.
b. Number of Out standing Read Requests.
a
The requests are sent in order — small requests do not pass large requests — as completion buffers are
unallocated. Otherwise, this would cause unfairness since smaller requests could block larger requests.
The completions can occur out of order; that is, the bridge always responds with completion data if it is
in the buffers. This is done to improve throughput when there are multiple outstanding read requests.
3.3.1.1 Non-posted Write Buffer
The PEB383 supports one non-posted write transaction. Similar to read requests, its request
information is stored in one of the eight request queue entries, and its data is stored in a 32-bit register.
Non-posted write requests are forwarded onto the PCIe Core in two PCIe clock cycles. Request
information is forwarded in the first cycle, while 32-bit data is forwarded in the second cycle.
ORR
b
ALOC ORR ALOC ORR ALOC ORR
3.3.2 Upstream Posted Buffer
The upstream posted buffer is a FIFO of size 512 bytes that stores mem ory writ e transactions that
originate on the PCI Interface and are destined to devices on PCIe Interface. The PEB383 completes
the posted transactions on the originating bus before forwarding them to the PCIe Interface. Unlike the
read buffers, the amount of space assigned to ea ch transac tion is dynamic. A single transaction can use
512 bytes of buffer space. The PEB383 translates all types of memory write transactions from the PCI
Interface to memory write requests on the PCIe Interface. The PEB383 terminates a new transaction
with retry and an active transaction with disconnect if sufficient buffer space is not available.
The PEB383 uses an 8-deep request FIFO to store the request information, including first and last
Dwords byte enables of the received transactions.
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Memory write transactions can contain any or al l in valid payload bytes, where as memory write and
invalidate (MWI) transactions carry all the valid payload bytes. The PEB383 decomposes the received
transactions with non-contiguous byte enables on 32-byte boundaries while writing into the request
FIFO.
The PCI Core makes a request to the PCIe Core if one of the following conditions is met:
• All data bytes of the transaction are received and are stored in the data buffer
• Received data bytes count exceeds the programmed threshold value (see UPST_PWR_THRES in
“Upstream Posted Writ e Threshold Register”)
• Received data bytes count exceeds the PCIe maximum payload size (see MAX_PAY_SIZE in
“PCIe Device Control and Status Register”)
• Address plus received data bytes count exceeds 4 KB
• Data with non-contiguous byte enables
3.3.3 Downstream Non-posted Buffer
The 512-byte, downstream non-posted buffer stores the data returned for the non-posted requests that
originate on the PCIe Interface and are destined for PCI devices.
3. Data Path > Flow Control26
A single completion of up to 512-bytes can be stored here. A single outstanding read is issued to the
PCI side.
3.3.4 Downstream Posted Buffer
The 512-byte downstream posted write buffer stores the payload of memory write transactions that
originate on the PCIe Interface and are destined for PCI devices. The amount of space assigned to each
transaction is dynamic.
The PEB383 uses an 8-deep request FIFO to store the request information, including the first and last
Dwords byte enables. The PEB383 initiates a transaction on the PCI Interface only after a complete
packet is stored in the buffer. The PEB383 attempts another outstanding transaction only if the current
transaction is either successfully completed or terminated with either master or target abort.
3.4 Flow Control
The PEB383 handles packet-based protoc ol on its PCIe Interface, and transaction-based protocol on its
PCI Interface. PCI requesters initiate transactions without prior knowledge on receiver buffer status.
As a result, flow control is managed through retries and disconnects that can waste bus bandwidth. In
comparison, PCIe requesters initiate requests while having prior knowledge on receiver buffer
availability status, and therefore, eliminate the wasteful effects of unnecessary retries and disconnects.
The PEB383 does not issue retries or disconnects on the PCI Interface for completions returned for a
downstream read request, but may issue retries or disconnects for a posted or non-posted transaction on
the PCI Interface based on the buffer space availability.
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3. Data Path > Prefetching Algorithm 27
The PEB383 uses flow control buffers in the PCI Core for three categories of downstream traffic. The
amount of flow control buffer space availability is conveyed to the other end of the component using
flow control credits. The PEB383 advertises infinite credits for completions as it ensures enough buffer
space is available to store the returned completion data before initiating a read request. The PEB383
advertises initial flow control credits as follows. Each credit of data is 16 bytes.
Table 9: Initial Credit Advertisement
Credit Type Initial Advertisement
Posted Header (PH) 0x08
Posted Data (PD) 0x020
Non-Posted Header (NPH) 0x04
Non-Posted Data (NPD) 0x01
Completion Header (CPLH) 0x00 (Infinite)
Completion Data (CPLD) 0x000 (Infinite)
3.5 Prefetching Algorithm
The PEB383 prefetches the data by default for the transaction that uses Memory Read Line or Memory
Read Multiple command. The PEB383 does not prefetch the data by default for the transaction that
uses the memory read command sinc e t he bri dge do es not know whether or not the transaction addre ss
falls in prefetchable region.
The prefetch algorithm is configured for various commands as follows:
• Memory read – Controlled by P_MR, MRL_66 and MRL_33 of the “Prefetch Control Register”.
The default value of these bits indicates that either one Dword in 32-bit bus mode or two Dwords
in 64-bit bus mode is prefetched.
• Memory read line – Controlled by P_MRL, MRL_66 and MRL_33 of the “Prefetch Control
Register”. The default value of these bits indicates that either 128 bytes in 32-bit bus mode or
256 bytes in 64-bit bus mode is prefetched. The PEB383 prefetches one cacheline if P_MRL is set
to 0.
• Prefetch algorithm for memory read multiple command is controlled by P_MRM, MRM_66 and
MRM_33 of the “Prefetch Control Register”. The default value of these bits indicates that either
256 bytes in 32-bit bus mode or 384 bytes in 64-bit bus mode is prefetched. The PEB383
prefetches two cachelines if P_MRM is set to 0.
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3.6 Short Term Caching
This feature provides performance improvements in situations where upstream devices are not able to
stream data continuously to meet the prefetching needs of the PEB383. As defined in the PCI-to-PCI
Bridge Specification (Revision 1.2), when the bus master completes a transaction, the bridge is required
to discard the balance of any data that was prefetched for the master. To prevent performance impac ts
when dealing with devices between requester and completer that can only stream data of 128 to 512
bytes due to buffering constraints, the PEB383 uses “Short Term Caching.” This feature provides a
time-limited read data cache in which the PEB383 will not discard prefetched read data after the
request completes on the initiating bus.
To enable Short Term Caching, set the STC_EN bit in the “PCI Miscellaneous Control and Status
Register”. When enabled, the PEB383 does not discard the additional prefetched data when the read
transaction completes on the initiating bus. The PEB383 then continues t o prefet ch data up to the
amount specified in the “Prefetch Control Register”. If the initiator generates a new transaction that
requests the previously prefetched data, the PEB383 returns that data.
The PEB383 discards data after some of the data for a request is returned to the initiator and one of the
following conditions is met:
• Short-term discard timer is expired before the initiator has requested additional data (see
“Short-term Caching Period Register”).
3. Data Path > Short Term Caching28
• An upstream posted transaction is received on the PCI Interface
Short-term caching should only be used in systems that can ensure the data provided to the
master has not been modified since the initial transaction.
3.7 Polarity Inversion
The PEB383 supports polarity inversion. For information on how to use this feature, see the PEB383
Board Design Guidelines.
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4. Addressing
Topics discussed include the following:
• “Overview”
• “Memory-mapped I/O Space”
• “Prefetchable Space”
• “I/O Space”
• “VGA Addressing”
• “ISA Addressing”
• “Non-transparent Addressing”
• “Legacy Mode”
29
4.1 Overview
This chapter discusses the various types of address decoding performed by the PEB383 when it
forwards transactions upstream and downstream. The memory and I/O address ranges are defined
using a set of base and limit registers in the bridge’s confi g uration header. The base and limit address
registers define the address ranges that a bridge forwards downstream transactions. These registers are
effectively inversely decoded to determine the address ranges on the PCI Interface for transactions that
are forwarded upstream to the PCIe Interface.
4.2 Memory-mapped I/O Space
Memory transactions are forwarded across the PEB383 when their address falls within a window
defined by one of the following registers:
• “PCI Memory Base and Limit Register”
• “PCI PFM Base and Limit Register”
The memory-mapped I/O address spacing maps memory address ranges of devices that are not
prefetchable. For PCI to PCIe reads, prefetching occurs in this space only if the Memory Read Line or
Memory Read Multiple commands are issued on the PCI bus. When either of these commands is use d,
the quantity of data prefetched is determined by the prefetching algorithm defined in “Prefetching
Algorithm”. For PCIe-to-PCI, the number of bytes to read is determined by the Memory Read Request
TLP.
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4. Addressing > Memory-mapped I/O Space30
The response of the bridge to memory-mapped I/O transactions is controlled by the following:
•MS bit in “PCI Control and Status Register” – This bit must be set to allow memory transactions to
be forwarded downstream. If not set, all memory transactions on the PCI bus are forwarded to the
PCIe link. In addition, if not set, all memory requests on the PCIe Interface are completed with an
Unsupported Request status.
• BM bit in “PCI Control and Status Register” – This bit must be set to allow memory transactions to
be forwarded upstream. If this bit is not set, all memory transactions on the PCI bus are ignored.
• VGA_EN bit in “PCI Bridge Control and Interrupt Register”
The PEB383 forwards memory transactions downstream from its PCIe Interface to its PCI Interface if
a memory address is in the range defined by the Memory Base and Memory Limit registers (when the
base is less than or equal to the limit), as shown in Figure 9. A memory transaction on the PCI Interface
that is within this address range, however, is not be forwarded upstream to the PCIe Interface. Any
memory transactions on the PCI Interface that are outside this address range are forwarded upstream to
the PCIe Interface (provided they are not in the address range defined by the set of prefetchable
memory address registers).
Figure 9: Memory-mapped I/O Address Space
Upstream
Upstream
rimary Interface
rimary Interface
Downstream
Downstream
Memory Base
Memory Base
Memory Limit
Memory Limit
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4. Addressing > Prefetchable Space 31
The memory-mapped I/O address range that is defined by the Base and Limit registers are always
aligned to a 1-MB boundary and has a size granularity of 1 MB.
4.3 Prefetchable Space
The prefetchable address space maps memory address ranges of devices that are prefetchable; that is,
devices that do not have side-effects during reads. For PCI-to-PCIe reads, prefetching occurs in this
space for all memory read commands (MemRd, MemRdLine, MemRdMult) issued on the PCI bus. For
these Read commands, the PEB383 prefetches data according to prefetching algorithm defined in
“Prefetching Algorithm”. For PCIe-to-PCI reads, the number of bytes to be read is determined by the
Memory Read Request.
The Prefetchable Memory Base, Prefetchable Memory Limit, Prefetchable Base Upper 32 Bits, and
Prefetchable Limit Upper 32 Bits registers in the bridge configuration header specify an address range
that is used by the bridge to determine whether to forward PCIe and PCI memory read and memory
write transactions across the bridge. The prefetchable memory address range defined by these registers
is always aligned to a 1-MB boundary and has a size granularity of 1 MB. If the address specified by
the Prefetchable Memory Base and Prefetchable Base Upper 32 Bits registers is set to a value higher
than the address specified by the Prefetchable Memory Limit and Prefetchable Limit Upper 32 Bits
registers, the address range is disabled.
Following register bits effect the response by the bridge to memory transactions:
• Memory Enable bit in “PCI Control and Status Register”
• Bus Master Enable bit in “PCI Control and Status Register”
• VGA Enable bit in “PCI Bridge Control and Interrupt Register”
The PEB383 forwards memory transactions downstream from its PCIe Interface to its PCI Interface if
a memory address is in the range defined by the Prefetchable Memory Base and Prefetchable Memory
Limit registers. Conversely, a memory transaction on the PCI Interface that is within this address range
is not be forwarded upstream to the PCIe Interface. Any memory transactions on the PCI Interface that
are outside this address range are forwarded upstream to the PCIe Interface (provided they are not in
the address range defined by the memory-mapped I/O address range registers).
If the Prefetchable Memory Base is programmed to have a value greater than the Prefetchable Memory
Limit, then the prefetchable memory range is disabled. In this case, all memory transaction forwarding
is determined by the memory-mapped I/O base and limit registers. Note that all four prefetchable base
and limit registers must be considered when disabling the prefetchable range.
Unlike non-prefetchable memory-mapped I/O memory, Prefetchable memory can be located below,
above, or span across the first 4-GB address boundary. Figure 10 illustrates a prefetchable memory
window that spans across the 4-GB address boundary. Memory locations above 4 GB are accessed
using 64-bit addressing. PCIe memory transactions that use the Short Address (32-bit) format can
target a non-prefetchable memory window or the portion of a prefetchable memory window that is
below the first 4-GB address boundary. Memory transactions that use the Long Address (64-bit) format
can target the portion of a prefetchable memory window that is at or above the first 4-GB address
boundary.
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Figure 10: 64-bit Prefetchable Memory Address Range
Upstream
Upstream
Downstream
Downstream
Secondary Interface
rimary Interface
rimary Interface
Prefetchable Memory
GB Boundary 4 GB Boundary
GB Boundary 4 GB Boundary
Prefetchable Memory
Secondary Interface
4. Addressing > I/O Space32
4.4 I/O Space
I/O Base, I/O Limit, I/O Base Upper 16 Bits, and I/O Limit Upper 16 Bits registers in the PEB383
configuration header specify an address range that is used by the br idge to de termine whether to
forward I/O read and I/O write transactions across the bridge. If the address specified by the I/O Base
and I/O Base Upper 16 Bits registers is set to a value greater than the address specified by the I/O Limit
and I/O Limit Upper 16 Bits registers, the address range is disabled.
The response of the bridge to I/O transactions is controlled by the following configuration register bits:
• I/O Space Enable bit in “PCI Control and Status Register”
• Bus Master Enable bit in “PCI Control and Status Register”
• ISA Enable bit in “PCI Bridge Control and Interrupt Register”
• VGA Enable bit in “PCI Bridge Control and Interrupt Register”
The I/O Enable bit must be set for any I/O transaction to be forwarded downstream. If this bit is not set,
all I/O transactions on the PCI bus are forwarded to the PCIe link. If this bit is not set, all PCIe
Interface I/O requests are completed with Unsupported Request status.
Memory Mapped I/O
Memory Mapped I/O
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4. Addressing > I/O Space 33
The Bus Master Enable bit must be set for any I/O transaction to be forwarded upstream. If this bi t is
not set, all I/O transactions on the PCI bus are ignored.
If ISA Enable bit is set, the bridge does not forward any I/O transactions downstream that are in the top
768 bytes of each 1-KB block within the first 64 KB of address space. Only transactions in the bottom
256 bytes of each 1-KB block are forwarded downstream. If the ISA Enable bit is clear, then all
addresses within the range defined by the I/O base and limit registers are forwarded downstream. I/O
transactions with addresses above 64 KB are forwarded according to the range defined by th e I/O base
and limit registers. If the ISA Enable bit is set, the bridge forwards upstream any I/O transactions on
the PCI bus that are in the top 768 bytes of each 1-KB block within the first 64 KB of address space,
even if the address is within the I/O base and limit. All other transactions on the PCI bus are forwarded
upstream if they fall outside the range defined by the I/O base and limit registers. If the ISA Enable bit
is clear, then all PCI bus I/O addresses outside the range defined by the I/O base and limit registers are
forwarded upstream.
A bridge uses the I/O Base and I/O Limit registers to determine whether to forward I/O transactions
across the bridge, as shown in Figure 11. The I/O address range defined by these registers is always
aligned to a 4-KB boundary and has a size granularity of 4 KB. A bridge forwards I/O read and I/O
write transactions from its PCIe Interface to its PCI Interface if the address is in the range defined by
the I/O base and I/O limit registers (when the base is less than or equal to the limit) . Conversely, I/O
transactions on the PCI bus in the address range defined by these registers are not forwarded upstream
by the bridge. I/O transactions on the PCI bus that are outside the defined address range are forwarded
upstream.
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Figure 11: I/O Addre ss Space
Upstream
Upstream
Downstream
Downstream
rimary Interface
rimary Interface
0x0_C000 – 0x0_FFFF
0x0_C000 – 0x0_FFFF
0x0_B000 – 0x0_BFFF
0x0_B000 – 0x0_BFFF
0x0_A000 – 0x0_AFFF
0x0_A000 – 0x0_AFFF
0x0_9000 – 0x0_9FFF
0x0_9000 – 0x0_9FFF
0x0_8000 – 0x0_8FFF
0x0_8000 – 0x0_8FFF
Secondary Interface
Secondary Interface
4. Addressing > VGA Addressing34
0x0_0000 – 0x0_7FFF
0x0_0000 – 0x0_7FFF
4.5 VGA Addressing
The PEB383 supports VGA addressing. The VGA_EN bit in the “PCI Bridge Control and Interrupt
Register” controls the response by the bridge to both VGA frame buffer addresses and to VGA register
addresses. If the VGA Enable bit is set, the bridge decodes and forwards memory accesses to VGA
frame buffer addresses and I/O accesses to VGA registers from the PCIe Interface to the PCI Interface
(and block forwarding from PCI to PCIe of these same accesses).
The VGA_16BIT_EN bit in the “PCI Bridge Control and Interrupt Reg ister” selects between 10-bit
and 16-bit VGA I/O address decoding, and is applicable when the VGA Enable bit is 1.
VGA memory addresses are 0x0A_0000 through 0x0B_FFFF
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4. Addressing > ISA Addressing 35
VGA I/O Addresses (Address bits 15:10 are not decoded when the VGA 16-Bit Decode bit is 0b) are:
• Address bits 9:0 = 0x3B0 through 0x3BB and 0x3C0 through 0x3DF (VGA 16-Bit Decode bit is
0b)
• Address bits 15:0 = 0x03B0 through 0x03BB and 0x03C0 through 0x03DF (VGA 16-bit Decode
bit is 1b)
The VGA Palette Snoop Enable bit is implemented as read-only with a value of zero.
4.6 ISA Addressing
The PEB383 supports ISA addressing through ISA Enable bit in the “PCI Bridge Control and Interrupt
Register”. The ISA Enable affects only I/O addresses that are in the bridge’s I/O range (as defined by
the I/O Base, I/O Base Upper 16 Bits, I/O Limit, and I/O Limit Upper 16 Bits) and in the first 64 KB of
PCI I/O Space (0000 0000h to 0000 FFFFh). If this bit is set and the I/O address meets the stated
constraints, the PEB383 blocks the forwarding of I/O transactions downstream if the I/O address is in
the top 768 bytes of each naturally aligned 1-KB block. If the ISA Enable bit is clear, the PEB383
forwards downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit
registers.
If the ISA Enable bit is set, I/O transactions on the PCI bus in the top 768 bytes of any 1-KB address
block within the first 64 KB of PCI I/O space is forwarded upstream, even if the address is between the
I/O base and I/O limit addresses. Figure 12 illustrates this mapping for a 4-KB range.
The ISA Enable bit only affects the I/O address decoding behavior of the bridge. It does not affect the
bridge's prefetching, posting, ordering, or error handling behavior.
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Figure 12: ISA Mode I/O Addressing
Upstream
Upstream
Downstream
Downstream
rimary Interface
rimary Interface
0x0_xD000 – 0x0_xFFF
0x0_xD000 – 0x0_xFFF
0x0_xC00 – 0x0_xCFF
0x0_xC00 – 0x0_xCFF
0x0_x900 – 0x0_x9FF
0x0_x900 – 0x0_x9FF
0x0_x800 – 0x0_x8FF
0x0_x800 – 0x0_x8FF
Secondary Interface
Secondary Interface
4. Addressing > ISA Addressing36
0x0_x500 – 0x0_x7FF
0x0_x500 – 0x0_x7FF
0x0_x400 – 0x0_x4FF
0x0_x400 – 0x0_x4FF
0x0_x100 – 0x0_x3FF
0x0_x100 – 0x0_x3FF
0x0_x000 – 0x0_x0FF
0x0_x000 – 0x0_x0FF
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4. Addressing > Non-transparent Addressing 37
4.7 Non-transparent Addressing
At power-up, the host processor discovers the need for non-transparent bridging and enables the
address remapping of prefetchable, non-prefetchable, and I/O ranges through configuration. Before
enabling address remapping of the base and limit values, the remapped address ranges need to be
programmed. The “Downstream Non-transparent Address Remapping Registers” allow downstream
accesses to be mapped to arbitrary positions in PCI memory space. While the Memory Base and Limit
registers always define the range of addresses to be claimed on the PCIe link and forwarded to the PCI
bus, cycles that are claimed have their addresses modified because of the difference in the base
addresses of the windows on the two buses.
4.7.1 PCIe to PCI Non-prefetchable Address Remapping
Downstream transactions that fall within the address window defined by the “PCI Memory Base and
Limit Register” are remapped according to the address window defined by the “Secondary Bus
Non-prefetchable Address Remap Control Register” and “Secondary Bus Non-prefetchable Upper
Base Address Remap Register”. The following equations describe the address remapping process:
• PriSecNPDiff = PriNPBase - SecNPBase, where
— PriSecNPDiff: Defines the difference between the Primary Non-prefetchable Base and the
Secondary Non-prefetchable Base.
— PriNPBase: Defined in the previous paragraph.
— SecNPBase: Defined by “Secondary Bus Non-prefetchable Address Remap Control Register”
and “Secondary Bus Non-prefetchable Upper Base Address Remap Register”.
• SecNPA ddr = PriNPAddr - PriSecNPDiff, where
— SecNPAddr: Defines the remapped address that the PEB383 presents on the PCI bus.
— PriNPAddr: Defines the address presented to the PEB383 that falls within the registers
described in the previous paragraph.
— PriSecNPDiff: See previous bullet.
4.7.2 PCIe to PCI Prefetchable Address Remapping
Downstream transactions that fall within the address window defined by the “PCI PFM Base and Limit
Register”, “PCI PFM Base Upper 32 Address Register”, and “PCI PFM Limit Upper 32 Address
Register”are remapped according to the address window defined by the “Secondary Bus Prefetchable
Address Remap Control Register” and “Secondary Bus Prefetchable Upper Base Address Remap
Register”. The following equations describe the address remapping process:
• PriSecPFDiff = PriPFBase - SecPFBase, where
— PriSecPFDiff: Defines the difference between the Primary Prefetchable Base and the
Secondary Prefetchable Base.
— PriPFBase: Defined by the registers listed above.
— SecPFBase: Defined by “Secondary Bus Prefetchable Address Remap Control Register” and
“Secondary Bus Prefetchable Upper Base Address Remap Register”.
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• SecPFAddr = PriPFAddr - PriSecPFDiff, where
— SecPFAddr: Defines the remapped address the PEB383 presents on PCI bus.
— PriPFAddr: Defines the address presented to the PEB383 that falls within the registers
described in the previous paragraph.
— PriSecPFDiff: See previous bullet.
4.7.3 PCI to PCIe Address Remapping
Because the addresses of the downstream memory windows on the PCI bus have been shifted from
their locations on the PCIe link, the address range of cycles that a bridge will not claim on the PCI bus
must also be shifted. Therefore, memory cycles with addresses from SecNPBase (see “Secondary Bus
Non-prefetchable Address Remap Control Register” and “Secondary Bus Non-prefetchable Upper
Base Address Remap Register”) to SecNPLimit or from SecFPBase (see “Secondary Bus Prefetchable
Address Remap Control Register” and “Secondary Bus Prefetchable Upper Base Address Remap
Register”) to SecFPLimit will not be claimed by the bridge on the PCI bus.
The Secondary Bus Non-prefetchable Limit is described in the following equation:
• SecNPLimit = PriNPLimit - PriSecNPDiff, where
4. Addressing > Non-transparent Addressing38
— PriNPLimit: Defined by “PCI Memory Base and Limit Register” and the additional “Primary
Bus Non-prefetchable Upper Limit Remap Register”.
— PriSecNPDiff: Defines the difference between the Primary Non-prefetchable Base and the
Secondary Non-prefetchable Base.
The Secondary Prefetchable Limit is described in the following equation:
• SecPFLimit = PriPFLimit - PriSecPFDiff, where
— PriPFLimit: Defined by “PCI PFM Base and Limit Register” and “PCI PFM Base Upper 32
Address Register”.
— PriSecPFDiff: Defines the difference between the Primary Prefetchable Base and the
Secondary Prefetchable Base.
Once the address is claimed as defined above, a memory cycle is forwarded from the PCI bus to the
PCIe link with its address modified according to the Non-transparent Address (NTMA) remapping
windows (see offsets 0x68 to 0x7C):
• NTMA window remapping
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4. Addressing > Non-transparent Addressing 39
The NTMA Secondary Base (see “NTMA Secondary Lower Base Register” and “NTMA Secondary
Upper Base Register”) and NTMA Secondary Limit (see “NTMA Secondary Lower Limit Register”
and “NTMA Secondary Upper Limit Register”) define memory windows in the PCI bus memory space
that are mapped to arbitrary positions on the PCIe link. The resulting location of the NTMA window on
the PCIe link is defined by the following equations:
• PriSecNTMADiff = PriNTMABase - SecNTMABase, where
— PriNTMABase: Defined by “NTMA Control Register” and “NTMA Primary Upper Base
Register”.
— SecNTMABase: Defined by “NTMA Secondary Lower Base Register” and “NTMA
Secondary Upper Base Register”.
• PriNTMALimit = SecNTMALimit + PriSecNTMADiff, where
— SecNTMALimit: Defined by “NTMA Secondary Lower Limit Register” and “NTMA
Secondary Upper Limit Register”.
— PriSecNTMADiff: See previous bullet.
A memory cycle whose address falls within a NTMA window on the PCI bus will have its address on
the PCIe link modified by the following equati on:
• PriNTMAAddr = SecNTMAAddr + PriSecNTMADiff, where
— SecNTMAAddr: Secondary NTMA Address, which must fall within the window defined by
the NTMA Secondary Base and Limit registers.
— PriSecNTMADiff: See previous bullet.
Transactions that are claimed on PCI Interface, and which are outside the NTMA window, are
forwarded upstream without address remapping. Software should ensure that the location of the NTMA
window on the PCI bus is outside of the PCI bus memory windows, and that the NTMA window on the
PCIe link is outside of the PCIe link memory windows, or undefined operation may result. Figure 13
displays an example of memory window remapping.
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Figure 13: Memory Window Remapping Example
PCIe Address Space PCI Address Space
4. Addressing > Non-transparent Addressing40
C_FFFF_FFFF
C_C000_0000
A_FFFF_FFFF
9_C00_0000
BFFF_FFFF
8000_0000
NTMA Window
Prefetchable Window
Non-prefetchable Window
Prefetchable Window
NTMA Window
Non-prefetchable Window
1_FFFF_FFFF
C000_0000
7FFF_FFFF
4000_0000
3FFF_FFFF
0000_0000
I/O Address Remapping
The “PCI I/O Address Upper 16 Register” in the PEB383 configuration space indicates the number of
upper bits of the I/O address that are not used when forwarding downstream I/O space cycles to the PCI
bus. This allows I/O addresses to be translated down into the address range that is available on the PCI
bus. There is no enable bit for I/O address remapping; any non-zero value in this register remaps the
I/O transactions to a different address location, as described in this section.
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4. Addressing > Legacy Mode 41
4.8 Legacy Mode
When the PEB383 is in Legacy mode it supports subtractive decode. This is a non-standard feature that
is enabled through the LEGACY bit in the “PCI Miscellaneous Clock Straps Register”.
When the PEB383 is in legacy mode, all MWr, MRd, IOWr, and IORd transactions received on the
upstream port (PCIe) that do not decode to an internal address are forwarded to the PCI Interface.
When the device is not in legacy mode, TLPs that do not fall between the base and limit registers are
handled as Unsupported Requests (UR).
When the LEGACY bit is set, the PROG field of “PCI Class Register” is changed to 0x1, indicating to
software that a subtractive bridge is present.
When the LEGACY bit is set all PCIe capabilities are hidden from software, and the following occurs:
1. Next pointer in “PCI Power Management Capability Register” is set to 0, indicating it is the last
capability
2. “PCIe Capability Registers” are treated as reserved
3. “Advanced Error Reporting Capability Registers” are treated as reserved
4. Extended configuration registers are treated as reserved
Tip
When the PEB383 is configured in Legacy mode, the PCIe root port must also be configured
to support subtractive decode.
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5. Configuration Transactions
Topics discussed include the following:
• “Overview”
• “Configuration Transactions”
• “PCIe Enhanced Configuration Mechanism”
• “Configuration Retry Mechanisms”
5.1 Overview
Each device in a PCIe or PCI system has a configuration space that is accessed using configuration
transactions in order to define its operational characteristics. This chapter describes how the PEB383
handles PCIe configuration requests.
43
5.2 Configuration Transactions
There are two types of configuration transactions: Type 0 and Type 1. Type 0 configuration
transactions access the PEB383’s internal configuration registers, while Type 1 configuration
transactions access devices that reside downstream of the PEB383. T ype 1 transactions are converted to
T ype 0 transactions if they target devices that reside on the downstream PEB383 bus. If the transaction
is intended for a device that is downstream of the bus directly below the PEB383, the transaction is
passed through the PEB383 as a Type 1 configuration transaction. If the transaction is not targeted for
the PEB383 or any device below the PEB383, the transaction is rejected. Configuration transactions
are only initiated by the Root Complex in PCIe-based systems.
Configuration address formats are as follows.
Figure 14: PCIe Configuration Address Format
Bus
Bus
Number
Number
Device
Device
Number
Number
Number
Number
ReservedFunction
ReservedFunction
Extended
Extended
Register
Register
Address
Address
Address
Address
1 07 211 815 1218 1623 1931 24
1 07 211 815 1218 1623 1931 24
ReservedRegister
ReservedRegister
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5. Configuration Transactions > Configuration Transactions44
Figure 15: PCI Type 0 Configuration Address Format
31 16
31 16
Reserved
Unique Address (AD[31:16])
Unique Address (AD[31:16])
corresponding to a particular Device
corresponding to a particular Device
Number)
Number)
Reserved
Figure 16: PCI Type 1 Configuration Address Format
31 24
31 24
Reserved
Reserved
Bus Number
Bus Number
5.2.1 Type 0 Configuration Transactions
The PEB383 responds to PCIe Type 0 configuration transactions that address its configuration space.
This type of transaction configures the PEB383 and is not forwarded downstream. The PEB383 ignores
Type 0 configuration transactions that originate on the PCI Interface. If a Type 0 configuration cannot
be processed, the PEB383 handles it as an Unsupported Request.
15 11
15 11
Device
Device
Number
Number
Function
Function
Number
Number
Function
Function
Number
Number
Number
Number
Number
Number
1 07 210 815 11
1 07 210 815 11
00Register
00Register
1 07 210 823 16
1 07 210 823 16
01Register
01Register
5.2.2 Type 1 Configuration Transactions
PCIe Type 1 configuration transactions are used for device configuration in a hierarchical bus system.
The Bus Number field contained in the header of a Type 1 configuration transaction specifies a unique
PCI bus in the PCI bus hierarchy. The PEB383 compares the specified Bus Number with two register
fields — Secondary Bus Number and Subordinate Bus Number in “PCI Bus Number Register” — that
are programmed by system software or firmware to determine whether or not to forward a Type 1
configuration transactions across the bridge.
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5. Configuration Transactions > Configuration Transactions 45
If a T ype 1 configur ation tra nsaction is received on the PCIe Interface, the following sequence of tests
is completed on the Bus Number field to determine how the PEB383 should handle the transaction :
1. If the Bus Number field is equal to the Secondary Bus Number value and the conditions for
converting the transaction into a Special Cycle transaction are met, the PEB383 forwards the
configuration request to its PCI Interface as a Special Cycle transaction. If the conditions are not
met, the PEB383 forwards the configuration request to the PCI Interface as a Type 0 configuration
transaction.
2. If the Bus Number field is not equal to the Secondary Bus Number value but is in the range of the
Secondary Bus Number and the Subordinate Bus Number (inclusive) values, the T ype 1
configuration request is specifying a Bus Number that is located behind the bridge. In this case, the
PEB383 forwards the configuration request to the PCI Interface as a Type 1 configuration
transaction.
3. If the Bus Number field does not satisfy the tests 1 and 2, the Type 1 configuration request
indicates a Bus Number that is not located behind the bridge. In this case, the configuration request
in invalid and PEB383 handles this as an Unsupported Request.
5.2.3 Type 1 to Type 0 Conversion
If a PCIe Type 1 configur ation transaction’s Bus Number field is equal to the Secondary Bus Number
value, and the conditions for conversion to a Special Cycle transaction are not met, the PEB383
forwards the transaction to the PCI bus as a Type 0 configuration transaction. In this case, a device
connected to the PCI Interface of the bridge is the target of the Type 0 configuration transaction.
To translate and convert a PCIe Type 1 configuration transaction to a PCI Type 0 configuration
transaction, the PEB383 does the following:
• Sets address bits PCI_AD[1:0] as 0b00
• Sets address bits PCI_AD[7:2] the same as the PCIe transaction’s Register Address field
• Sets address bits PCI_AD[10:8] the same as PCIe transaction’s Function Number field
• For a Secondary bus operating in PCI mode, it drives value 0b0000 on address PCI_AD[15:11]
• For a Secondary bus operating in PCI, the PEB383 check’s if the received Extended Register
Address field is zero. If this field is non-zero, the PEB383 does not forward the transaction and
treats it as an Unsupported Request on PCIe and a received Master-Abort on th e desti natio n bus . If
the field is zero, the PEB383 decodes the PCIe Device Number field and asserts a single address bit
in the range PCI_AD[31:16] during the address phase (for device numbers in the range 0b0_0000
to 0b0_ 1111b).
5.2.4 Type 1 to Type 1 Forwarding
If a PCIe T ype 1 configuration transaction is received and the value specified by the Bus Number field
is within the range of bus numbers between the Secondary Bus Number (exclusive) and the
Subordinate Bus Number (inclusive), the PEB383 forwards the transaction to its PCI Interface as a
Type 1 configuration transaction. In this case , the target of the transaction does not reside on the PCI
Interface but is located on a bus segment further downstream.
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5. Configuration Transactions > PCIe Enhanced Configuration Mechanism46
To translate the forwarded transaction from a PCIe Type 1 configuration request to a PCI Type 1
configuration transaction, the PEB383 does the following:
• Sets address bits PCI_AD[1:0] as 0b01
• PCI Register Number, Function Number, Device Number, and Bus Number (address bits
PCI_AD[23:2]) are generated directly – th at is, unmodified – from the PCIe configuration
transaction’s Register Address, Function Number, Device Number, and Bus Number fields,
respectively.
• Checks if the received Extended Register Address field is zero. If this field is non-zero, the
PEB383 does not forward the transaction and treats it as an Unsupported Request on PCIe and a
received Master-Abort on the destination bus. If the field is zero, the PEB383 generates
PCI_AD[27:24] as 0b0000.
5.2.5 Type 1 to Special Cycle Forwarding
When the PEB383 receives a PCIe Type 1 configuration write request transaction, it converts it to a
Special Cycle on its PCI Interface when the following conditions are met by the transaction:
• The Bus Number field matches the Secondary Bus Number register value
• The Device Number field is al l one s (eq ua ls 0b1_1111)
• The Function Number field is all ones (equals 0b111)
• The Register Address and Extended Register Address are both all zeros (equal 0b00_0000 and
0b0000, respectively).
5.3 PCIe Enhanced Configuration Mechanism
The PCIe Enhanced Configuration Mechanism adds four additional bits to the Register Address field,
thereby expanding the space to 4096 bytes. The PEB383 forwards configuration transactions only
when the Extended Register Address bits are all zero. This prevents address aliasing on the PCI bus
that does not support Extended Register Addressing. If a configuration transaction targets the PCI bus
and has a non-zero value in the Extended Register Address field, the PEB383 handles the transaction as
if it received a Master-Abort on the PCI bus and then does the following:
• Sets the appropriate status bits for the destination bus, as if the transaction had executed and
resulted in a Master-Abort
• Generates a PCIe completion with Unsupported Request status
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5. Configuration Transactions > Configuration Retry Mechanisms 47
5.4 Configuration Retry Mechanisms
A PCIe-to-PCI bridge is required to return a completion for all configuration requests that cross the
bridge from PCIe to PCI prior to expiration of the Completion Timeout timer in the Root Complex.
This requires that bridges take ownership of all configuration requests forwarded across th e bridge. If
the configuration request to PCI completes successfully prior to the bridge’s timer expiration, the
bridge returns a completion with Normal Status on PCIe for that request. If the configuration request to
PCI encounters an error condition prior to the bridge’s timer expiration, the bridge returns an
appropriate error completion on PCIe. If the configuration request to PCI does not complete either
successfully or with an error, prior to timer expiration, the bridge is required to return a completion
with Configuration Retry Status (CRS) on PCIe for that request.
After the PEB383 returns a completion with CRS on PCIe, it continues to keep the configuration
transaction active on the PCI bus. For PCI, the PEB383 keeps retrying the transaction until it completes
on the PCI bus. When the configuration transaction completes on the PCI bus after the return of a
completion with CRS on PCIe, the PEB383 discards the completion information. Bridges that use this
option are also required to implement Bridge Configuration Retry Enable in the “PCIe Device Control
and Status Register”. If this bit is cleared, the bridge does not return a completion with CRS on behalf
of configuration requests forwarded across the bridge. The lack of a completion results in eventual
Completion Timeout at the Root Complex.
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5. Configuration Transactions > Configuration Retry Mechanisms48
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6. Bridging
Topics discussed include the following:
• “Overview”
• “Flow Control Advertisements”
• “Buffer Size and Management”
• “Assignment of Requestor ID and Tag”
• “Forwarding of PCIe to PCI”
• “Forwarding of PCI to PCIe”
• “PCI Transaction Support”
• “PCIe Transaction Support”
• “Message Transactions”
• “Transaction Ordering”
• “Exclusive Access”
49
6.1 Overview
The PEB383 provides a connection path between a PCI bus and a PCIe link. The main function of the
PEB383 is to allow transactions between a master or a transmitter on one bus\link, and a target or a
receiver on the other bus\link. The PCI Interface can operate in 32-bit PCI mode up to 66 MHz.
Transactions flow through the PEB383 can be classified as follows:
• PCIe-to-PCI
• PCI-to-PCIe
6.2 Flow Control Advertisements
The flow control method on the PCI Interface is managed through retries or disconnects, where as on
the PCIe link it is managed using flow control credi ts.
On the PCI Interface, the PEB383 issues retries to new request transactions and issues a disconnect for
the active transaction if the internal request queues or data storage buffers are full or approaching full.
On PCIe Interface, the PEB383 periodically conveys its available buffer space to the other end
component in terms of flow control credits using flow control packets. The PEB383 advertises flow
control credits as per PCIe protocol requirements.
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6. Bridging > Buffer Size and Management50
6.3 Buffer Size and Management
The PEB383 provides sufficient buffering to satisfy PCIe bridging requirements. The PEB383 does not
overcommit its buffers: it forwards requests onto the other side only when enough buffer space is
reserved to handle the returned completions.
The PEB383 uses 1-KB retry buffering, which is large enough to ensure that under normal operating
conditions upstream traffic is never throttled. Ack latency value, internal processing delays, and
receiver L0s exit latency values, are considered for determining the Retry buffer size.
6.4 Assignment of Requestor ID and Tag
The PEB383 assigns a unique transaction ID for all the non-posted requests forwarded to upstream
devices. The PEB383 takes ownership of the upstream transactions on behalf of origin al requestors,
and stores the transaction-related state information needed to return the completions to the original
requesters. The action of replacing the original transaction’s requester ID and/or Tag fields with the
bridge’s own assigned values is referred to as taking ownership of the transaction.
For upstream non-posted requests, the PEB383 assigns the PCIe requester ID using its secondary bus
number and sets both the device number and function number fields to zero. For the upstream
transactions, the PEB383 sets the Tag field to a request enqueued entry number.
6.5 Forwarding of PCIe to PCI
The PEB383 forwards posted, non-posted, and upstream read completions to the PCI devices, and
stores the non-posted TLPs’ state information to return the completion TLPs to the PCIe Interface.
6.5.1 PCIe Memory Write Request
The PEB383 forwards the received PCIe Memory Write Requests to the PCI Interface with either
Memory Write (MW) or Memory Write and Invalidate (MWI) command. The PEB383 translates the
request into a PCI transaction using the MWI command if it meets the MWI command rules specified
in the PCI Local Bus Specification (Revision 3.0), and the MWI bit is set in the “PCI Control and Status
Register”. An MW command is used for the remaining part of the MWI transact ion if the transact ion is
disconnected such that the remaining request does not meet the MWI command rules. The PEB383
does not support relaxed ordering among the received requests. It forwards all requests in the order
they are received even if the relaxed ordering bit is set for some of the requests.
6.5.2 PCIe Non-posted Requests
The PEB383 translates the PCIe Memory Read Requests into PCI transactions that use a PCI memory
read command (that is, Memory Read, Memory Read Line, or Memory Read Multiple) based on its
cacheline size value, requested byte enables, and prefetchable and non-prefetchable memory windows.
PCIe Read Request command translation is completed as follows:
• Memory Read if the PCIe Request falls into the non-prefetchable address range defined by the
“PCI Memory Base and Limit Register”.
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• Memory Read Line if the PCIe Request falls into the prefetchable range defined by the “PCI PFM
Base and Limit Register” , and the requested data size is less than or equal to the value specified in
Cacheline Size of the “PCI Miscellaneous 0 Register”.
• Memory Read Multiple if the PCIe Request falls into the prefetchable range defined by the “PCI
PFM Base and Limit Register”, and the requested the data size is greater than or equa l to the value
specified in Cacheline Size of the “PCI Miscellaneous 0 Register”.
The PEB383 supports a single outstanding request. It does not attempt to read beyond the requested
length. The PEB383 decomposes the requests if the requested data length is greater than 128 bytes, and
returns the completions in 128-byte boundary fragments.
The PEB383 uses PCI byte enable fields such that the byte enable information is preserved and no
additional bytes are requested for the transactions that fall into the non-prefetchable address range (for
example, Configuration, I/O, and Memory read commands).
6.6 Forwarding of PCI to PCIe
The PEB383 forwards posted and non-posted requests and downstream read completions to PCIe
devices, and stores the non-posted requests’ state information to return the delayed completions to the
requester.
6.6.1 PCI Memory Write Request
The PEB383 translates the received Memory Write (MW) and Memory Write and Invalidate (MWI)
transactions into PCIe Memory Write Requests. The PEB383 uses a 512-byte posted buffer to post the
received transactions. Write requests are fragmented if one of the following PCIe constraints is met:
• Address plus length crosses the 4-KB boundary
• Burst writes with discontinuous byte enables
• Payload size exceeds MAX_PAY_SIZE in “PCIe Device Control and Status Register”
The PEB383 terminates a posted transaction with retry only if the buffers are filled with previously
received memory requests, or if the bridge is locked from the PCIe side (see “Locked Trans a ction”).
For more information on locked accesses, see “Exclusive Access”.
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6.6.2 PCI Non-posted Requests
The PEB383 processes all non-posted transactions as delayed transactions. The PEB383 first
terminates the received non-posted transaction with retry and then forwards it onto the PCIe Interface.
The PEB383 stores the request-related state information while forwarding the request onto the PCIe
Interface. This information tracks the requests repeated by the master and returned completions for the
request. Since PCI read requests do not specify the amount of data to be read, the PEB383 uses a
programmable prefetch algorithm to determine the amount of data to be read on behalf of the original
requester. The PEB383 does not attempt to prefetch past the 4-KB address boundary on behalf of the
original requester. The PEB383 stores the returned completion until the PCI requester repeats the initial
request and terminates the delayed transaction. If short-term caching is enabled (see STC_EN in “PCI
Miscellaneous Control and Status Register”), the PEB383 responds to subsequent requests with the
incremental addresses issued by the master until the programmed number of data bytes are transferred
to the master or the short-term discard timer is expired (see ST_DIST_EN in
“SERRDIS_OPQEN_DTC Register”).
The PEB383 enqueues up to four requests and issues the initial requests on the PCIe Interface in the
order they were received; however, the ordering is not guaranteed for the subsequent requests of
decomposed transactions.
The PEB383 discards the enqueued delayed request if the requested data is not returned before the
completion timeout is expired (see “Completion Timeout Register”), and returns a delayed completion
with target abort to the requester (see DISCARD2 in “PCI Bridge Control and Interrupt Register”). A
delayed completion is discarded if the requester does not repeat the initial request or if the requester
disconnects the delayed completion after few data bytes are transferred.
6. Bridging > Forwarding of PCI to PCIe52
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6. Bridging > PCI Transaction Support 53
6.7 PCI Transaction Support
The following table lists the transactions supported by the PCI Interface.
Table 10: PCI Transaction Support
PCI Interface
Cmd Transaction
0000b Interrupt Acknowledge NA NA
0001b Special Cycle Yes NA
0010b I/O Read Yes Yes
0011b I/O Write Yes Yes
0100b Rsvd NA NA
0101b Rsvd NA NA
0110b Memory Read Yes Yes
0111b Memory Write Yes Yes
1000b Rsvd NA NA
1001b Rsvd NA NA
1010b Configuration Read Yes NA
1011b Configuration Write Yes NA
1100b Memory Read Multiple Yes Yes
a
As a Master As a Target
1101b Dual Address Cycle Yes Yes
1110b Memory Read Line Yes Yes
1111b Memory Write and Invalidate Yes Yes
a. For unsupported transactions, see “PCIe as Originating Interface”.
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6.8 PCIe Transaction Support
The following table lists the transactions supported by the PCIe Interface.
Table 11: PCIe Transaction Support
6. Bridging > PCIe Transaction Support54
PCIe Interface
TLP Type Transaction
MRd Memory Read Request Yes Yes
MRdLk Memory Read Request Locked NA Yes
MWr Memory Write Request Yes Yes
IORd I/O Read Request Yes Yes
IOWr I/O Write Request Yes Yes
CfgRd0 Configuration Read Typ e0 NA Yes
CfgWr0 Configuration Write Type 0 NA Yes
CfgRd1 Configuration Read Typ e1 NA Yes
CfgWr1 Configuration Write Type 1 NA Yes
Msg Message Request Yes Yes
MsgD Message Request with Data Payload NA Yes
MsgD
(Vendor Defined)
Cpl Completion without Data Yes Yes
Vendor-Defined Message
Request With Data Payload
a
As a Transmitter As a Receiver
No No
CplD Completion with Data Yes Yes
CplLk Completion without Data for
MRR- Locked
CplDLk Completion with Data for MRR - Locked Yes NA
a. For unsupported transactions, see “PCIe as Originating Interface”.
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6. Bridging > Message Transactions 55
6.9 Message Transactions
Message transactions are used for in-band communication of events, and therefore, eliminate the need
for sideband signals. PCIe messages are routed depending on specific bit field encodings in the
message request header.
6.9.1 INTx Interrupt Signaling
The PEB383 forwards the INTx interrupts – PCI_INT[A:D]n – generated by PCI devices onto the PCIe
Interface, as PCIe Assert_INTx and Deassert_ INTx messa ges (for more information, see “Interrupt
Handling”).
6.9.2 Power Management
Power management messages support Power Management Events (PME) signaled by sources
integrated into the bridge and for devices downstream of the bridge. The PEB383 forwards the power
management events (PCI_PMEn) from PCI devices onto the PCIe Interface using PCIe PME messages
(for more information, see “Power Management Event”).
6.9.3 Locked Transaction
Unlock messages support locked transaction sequences in the downstream direction. This type of
message indicates the end of a locked sequence. The PEB383 supports locked transactions in the
downstream direction and uses unlocked messages to unlock itself from the PCIe Interface (see
“Exclusive Access”).
6.9.4 Slot Power Limit
These messages are transmitted to downstream devices by the root complex or a switch. The PEB383
copies the set slot power limit payload into the Set Slot Power Limit Scale and Set Slot Power Value
fields of the “PCIe Device Capabilities Register”.
6.9.5 Vendor-defined and Device ID
These messages are used for vendor-specific purposes. The PEB383 does not support forwarding of
these messages. It terminates Device ID message transactions on the PCI Interface with Master-Abort.
It silently discards the Vendor-defined Type 1 message TLPs and hand les the Vendor-defined Type 0
message TLPs as Unsupported Requests.
The PEB383 ignores the receipt of Ignored messages. It handles the receipt of Error signaling messages
as Unsupported Requests. The PEB383 handles the receipt of INTx messages as malformed TLPs.
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6.10 Transaction Ordering
Table 12 defines the transaction ordering rules that are followed by the PEB383. These rules apply
uniformly to all types of transactions, including Memory, I/O, Configurations, and Messages.
In the table, the columns represent a first received transaction while the rows represent a subsequently
received transaction. Each table entry indicates the ordering relationship between the two transactions.
The table entries are defined as follows:
• Yes – The second transaction is allowed to pass the first transaction.
• No – The second transaction is not allowed to pass the first transaction.
The PEB383 does not allow a posted transaction to pass another posted transaction even if the relaxed
ordering attribute bit is set. However, the device allows a Read completion with the relaxed ordering
attribute bit set to pass a posted transaction.
Table entries with 1) and 2) are defined as follows:
1. Indicates the ordering relationship when the relaxed ordering attribute bit is clear in the second
transaction header information.
2. Indicates the ordering relationship when the relaxed ordering attribute bit is set in the second
transaction header information.
6. Bridging > Transaction Ordering56
Table 12: Transaction Ordering
Posted Request Non-Posted Request Completion
Can Row Pass Column?
Memory Write
or Message
Posted
Request
Request
Read Request No Yes Yes Yes Yes
I/O or
Configuration
Request
Non-Posted
Read
Completion
I/O or
Configuration
Completion
Write
Completion
Memory Write or
Message
Request
1) No
2) No
No Yes Yes Yes Yes
1) No
2) Yes
No Yes Yes Yes Yes
Read Request I/O or
Configuration
Write Request
Yes Yes 1) Yes
Yes Yes 1) Yes
Read Completion I/O or
2) Yes
2) Yes
Configuration
Write Completion
1) Yes
2) Yes
Yes
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6. Bridging > Exclusive Access 57
6.11 Exclusive Access
ThePEB383 provides an exclusive access method, which allows non-exclusive accesses to proceed
while exclusive accesses take place. This allows a master to hold a hardware lock across several
accesses without interfering with non-exclusive data transfer. Locked transaction sequences are
generated by the host processor(s) as one or more reads followed by a number of writes to the same
location(s). The PEB383 supports locked transactions only in the downstream direction. Upstream
Lock transactions are handled with the LOCKn signal ignored.
A Lock is established when all the following conditions are met:
• A PCIe device initiates a Memory Read Lock (MRdLk) request to read from a target PCI device
• LOCKn is asserted on the PCI bus
• The target PCI device responds with a TRDYn
The bus is unlocked when the Unlock Message TLP is received on the PCIe link.
ThePEB383 enters into target-lock state when it receives a MRdLk TLP, and enters into full-lock state
when it receives successful completion from the target device. ThePEB383 attempts locked read
request on the PCI bus only after all the requests received prior to the locked request are completed on
the bus. While in target-lock state, thePEB383 handles all the received TLPs with UR but continues to
accept the transactions on the PCI Interface.
When thePEB383 enters into full-lock state, all upstream transactions on the PCI Interface are retried
and all the downstream requests on the PCIe Interface, except Memory transa ctions, are handled as
UR. Requests pending in upstream queues or buffers and internally generated messages are not allowed
to be forwarded to the PCIe Interface until thePEB383 is unlocked from the PCIe Interface. However,
thePEB383 accepts read completions for upstream read requests that were issued before the lock was
established on the PCI bus when they return on the PCIe link.
As soon as the PCI bus is locked, any PCIe cycle to PCI is driven with the PCI_LOCKn pin asserted,
even if that specific cycle is not locked. This is not expected to occur because under the lock, the
upstream component must not send any non-locked transactions downstream.
During the LOCK sequence, when the initial locked read command results in a master or target abort
on the PCI bus, thePEB383 does not establish lock, and it sends a completion packet on the PCIe link
with an error status. In case of a subsequent memory read or memory write receiving a target or master
abort during a LOCK sequence, thePEB383 unlocks only after the unlock message is received on the
PCIe Interface.
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7. PCI Arbitration
Topics discussed include the following:
• “Overview”
• “Block Diagram”
• “PCI Arbitration Scheme”
7.1 Overview
The PCI internal bus arbiter manages access to the PCI bus for up to five requesters, including the
PEB383. The bus arbiter has the following features:
• Supports five requests (four external and one internal, the PEB383)
• Can be programmed to give high and low priorities for requesters
59
• Bus is parked on latest master given grant
7.2 Block Diagram
The bus arbiter handles internal requests from the PCI Core and external requests from devices on the
PCI bus (see Figure 17). When the arbiter is enabled, the PEB383 asserts the grant for PCI devices and
for the PCI Core. When the arbiter is disabled, there must be an external arbiter on the PCI bus that
handles PEB383 requests through the PCI_REQ[0]n signal, and grants bus access using the
PCI_GNT[0] signal.
Grants and Requests are bi-directional pins. PCI_REQ[0]n is output enabled when the internal arbiter
is disabled. Enable of PCI_REQ[3:1]n are always hardcoded to 1’h0. PCI_GNT[0] is an input pin
when the internal arbiter is disabled.
Figure 17: PCI Arbiter Block Diagram
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7.3 PCI Arbitration Scheme
The arbiter can be programmed to enable or disable, and prioritize, each requester using the “PCI
Miscellaneous Control and Status Register”.
The PEB383, by default, is assigned a high priority and the other requesters are assigned a low priority .
Based on the priority setting, requesters are divided into two groups of high and low priority. Within a
group, priority is determined using a round-robin method (see Figure 18). The low-prio rity group is
handled as one member of the high-priority group.
By default, the PCI arbiter initially parks the bus on the PEB383. After servicing the requesters when
the bus is in idle state, the arbiter is parked on the last served requester.
The priority method is shown in Figure 18. Note that any one request input can only be mapped to high
or low priority. If, for example, PCI_REQ2n is mapped to low priority, then the H2 state is skipped
over.
Figure 18: PCI Arbitration Priority
H1
7. PCI Arbitration > PCI Arbitration Scheme60
H2
High
Priority
H3
L
Note: Any device can be high
or low priority; however, a device
can have only one priority
setting as defined by the
PCI_MISC_CSR register.
H0
H-PEB38x
L-PEB38x
L0
L3
Low
Priority
L2
L1
The PEB383 also keeps track of which requestor, in each priority group, was last served. This is
achieved with two arbitration pointers, one for each priority. When a new requestor is granted the bus,
the pointer(s) advance. This gives each requestor a fair chance of being selected first when multiple
requestors request the bus.
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7. PCI Arbitration > PCI Arbitration Scheme 61
This is shown conceptually in Figure 19. Here the last serv ed high priority device is H1, and the last
served low priority device is L2. When the high priority pointer is at H1, the order of priority is H2, H3,
Low , H-PEB383, H0, and H1.
Figure 19: Arbitration Pointers – Example 1
High Priority
H-PEB38x
H0
H1
H2
H3
L
Low Priority
L-PEB38x
L0
L1
L2
L3
When the transaction for device 1 is complete, all input requests are sampled to determine which
device should be granted next. If there are no requests the pointer stays at H1, and no grants are given.
If two requests occur at the same time — in this example, L3 and H1 — then L3 is granted and the
pointers advance as shown in Figure 20.
Figure 20: Arbitration Pointers – Example 2
High Priority
H-PEB38x
H0
H1
H2
H3
L
Low Priority
L-PEB38x
L0
L1
L2
L3
Once L3 is completed, the input requests are sampled again. H0 and H1 are now requesting the bus. H0
would then obtain access to the bus because the new priority ordering is H-PEB383, H0, H1, H2, H3,
L. The initial ordering of the requests is not considered; that is, H1 requested before H0, but H0 wins as
it is first in the priority list. This ensures that all requestors obtain equal access within a priority group.
After asserting the grant, if the bus is in an idle state for M clock cycles grant is de-asserted.
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7. PCI Arbitration > PCI Arbitration Scheme62
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8. Interrupt Handling
Topics discussed include the following:
• “Overview”
• “Interrupt Sources”
• “Interrupt Routing”
8.1 Overview
The PEB383 supports the two types of interrupts that originate on a PCI bus:
• Legacy PCI interrupts, PCI_INT[D:A]n
• Message-based interrupts
— Message Signaled Interrupts (MSI)
63
— Enhanced Message Signaled Interrupts (MSI-X)
The PEB383’s PCI Interface forwards legacy INTx assertion/de-assertions in the form of As sert_INTx
and Deassert_INTx messages on its PCIe link. The PEB383 handles MSI and MSI-X transactions as
PCI memory write transactions. When the bridge receives an MSI/MSI-X transaction on its
PCI Interface, it forwards it as a memory write TLP on its PCIe link. Both INTx messages and
MSI/MSI-X transactions flow through the PEB383’s upstream posted buffer , as displayed in Figure 21.
Figure 21: Interrupt Handling Diagram
Upstream
Posted
Buffer
Interrupt
Message
Generation
PCI Target
Interface
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PCI_INTBn
PCI_INTCn
PCI_INTDn
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The Interrupt Message Generation module connects to the PCI Target Interface, external
PCI_INT[D:A]n interrupts, and the upstream posted buffer (see Figure 21). Assertion and de-assertion
of interrupts are stored in the form of Assert_INTx and Deassert_INTx flags. These flags are kept
asserted until the posted buffer can handle corresponding assert and de-assert messages. If an interrupt
pin is toggled when the PCI Interface is engaged with a PCI-initiated posted transaction, assert or
de-assert message loading into the upstream p ost ed request buffer is stalled until the upstream posted
transaction terminates. Posted transactions are retried on the AD bus while an interrupt message is
loaded into the posted buffer. A De-assert message always follows an Assert message. More then one
interrupt pin can toggle at any point of time; however, a round-robin arbitration schedules the interrupt
message transmission.
There is no buffering for interrupt messages before loading them int o the upstream posted buffer.
Therefore, only one pair of Assert_INTx and Deassert_INTx messages is loaded into the buffer when
allowed. In the worst case, the bridge may send duplicate messages; however, this is permitted
according to the PCI Express Base Specification (Revision 1.1).
8.2 Interrupt Sources
The PEB383 does not have an internal source of interrupts: it forwards legacy PCI_INT[D:A]n
interrupts from the PCI Interface to the PCIe Interface in the form of Assert[D:A] and De -assert[D:A]
messages with PEB383 PCIe transaction IDs.
8. Interrupt Handling > Interrupt Sources64
8.3 Interrupt Routing
Interrupt remapping is not performed by the PEB383. Legacy interrupts, PCI_INT[A:D]n, are routed to
the upstream PCIe port in the form of Assert_INTx and Deassert_INTx [A,B,C,D] messages.
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9. Error Handling
Topics discussed include the following:
• “Overview”
• “PCIe as Originating Interface”
• “PCI as Originating Interface”
• “Timeout Errors”
• “Other Errors”
• “Error Handling Tables”
9.1 Overview
This chapter discusses how the PEB383 handles errors that occur during the processing of upstream
and downstream transactions. For all errors that are detected by the bridge, it sets the appropriate Error
Status bits – PCI Error bit(s) and PCIe Error status bit(s) – and generates an error messa ge on PCIe, if
enabled.
65
Each error condition has an error severity level programmable by software, and a corresponding error
message generated on PCIe. Each detected error condition has a default error severity level (fatal or
non-fatal) and, when enabled, has a corresponding error message generated on PCIe. The error severity
level is software programmable.
PCIe link error message generation is controlled by the following bits:
•SERR_EN in the “PCI Bridge Control and Interrupt Register”
•FTL_ERR_EN in the “PCIe Device Control and Status Register”
• NFTL_ERR_EN in the “PCIe Device Control and Status Register”
• COR_ERR_EN in the “PCIe Device Control and Status Register”
ERR_FATAL PCIe messages are enabled for transmission if either of the following bits is set:
SERR_EN in “PCI Control and Status Register”, or FTL_ERR_EN in “PCIe Device Control and Status
Register”.
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9. Error Handling > Overview66
ERR_NONFATAL messages are enabled for transmission if either of the following bits is set:
SERR_EN in “PCI Control and Status Register”, or NFTL_ERR_EN in “PCIe Device Control and
Status Register”.
ERR_COR messages are enabled for transmission if COR_ERR_EN is set in “PCIe Device Control
and Status Register”.
FTL_ERR_DTD, NFTL_ERR_DTD, and COR_ERR_DTD bits in “PCIe Device Control and Status
Register” are set for the corresponding errors on the PCIe Interface, regardless of the error reporting
enable bits.
The PEB383 also supports Advisory Non-Fatal error messages in the case where a TLP Error detected
is a Advisory Non-Fatal Error and the Advisory Non-Fatal Error mask bit, ANFE, in the “PCIe
Correctable Error Mask Register” is not masked then a Correctable error message is generated instead
of a Non-Fatal error message.
Figure 22 depicts the high-level flowchart for error handling on PCIe. This is taken from Table 6-2 of
the PCI Express Base Specification (Revision 1.1), and includes advanced error handling. Additional
error handling requirements for a PCIe bridge are described in subsequent sections of the specification.
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Figure 22: PCIe Flowchart of Device Error Signaling and Logging Operations
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9.2 PCIe as Originating Interface
This section describes how the PEB383 handles error support for transactions that flow downstream
from PCIe to PCI (see Figure 23).
In the case of reception of a Write Request or Read Completion with a Poisoned TLP, the entire data
payload of the PCIe transaction is considered as corrupt and the parity is inverted on every data phase
forwarded (see Table 13). In the case of reception of a request with ECRC error, the entire TLP is
considered as corrupt and is dropped by the bridge.
Table 13: Error Forwarding Requirements (Step A to Step B) for Received PCIe Errors
9. Error Handling > PCIe as Originating Interface68
Received PCIe Error
(Step A)
Write Request or Read Completion
with Poisoned TLP
Request with ECRC (Optional
Support) Error
Forwarded PCI Error Mode 1
(Parity) (Step B)
Poisoned Data Parity
Do not forward
Figure 23: Transaction Error Forwarding with PCIe as Originating Interface
PC I
Immediate
Requestor
or Delay ed
Transaction
Compl eter
PCI e
(Origi nating I nterface)
St ep A St ep B
Step D St ep C
( D estina ti on I n t e rface)
PEB38x
Completer
Table 14 provides the translation a bridge has to perform when it forwards a non-posted PCIe request
(read or write) to PCI and the request is completed immediately on PCI, either normally or with an
error condition.
Table 14: Bridge Requirements for Transactions Requiring a Completion
(Immediate Response)
Data transfer with uncorrectable data
Data transfer with uncorrectable data
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Immediate PCI Termination PCIe Completion Status
Successful (Poisoned TLP)
error (reads)
Unsupported Request
error (non-posted writes)
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Table 14: Bridge Requirements for Transactions Requiring a Completion
(Immediate Response)
Immediate PCI Termination PCIe Completion Status
Master-Abort Unsupported Request
Target-Abort Completer Abort
In the case of an Advisory Non-Fatal Error detection, the following actions are taken by the PEB383:
1. If the severity of the TLP Error detected in “PCIe Uncorrectable Error Severity Register” is
Non-Fatal then:
a. COR_ERR_DTD is set in the “PCIe Device Control and Status Register”
b. ANFE is set in the “PCIe Correctable Error Status Register”
2. And if the ANFE bit is not masked in the “PCIe Correctable Error Mask Register” then:
a. TLP Error Status bit is set in the “PCIe Uncorrectable Error Status Register”
b. If the corresponding TLP Error Mask bit is clear in the “PCIe Uncorrectable Error Mask
Register” and ERR_PTR is not valid in the “PCIe Advanced Error Capabilities and Control
Register”, then the TLP header is logged in the “PCIe Header Log 1 Register” and ERR_PTR
is updated in the “PCIe Advanced Error Capabilities and Control Register”.
c. If COR_ERR_EN is set in the “PCIe Device Control and Status Register” then it sends a
Correctable error message.
9.2.1 Received Poisoned TLPs
When the bridge receives a poisoned TLP it completes the following while forwarding it to the PCI
Interface:
1. If the severity of the PTLP in the “PCIe Uncorrectable Error Severity Register” is Non-Fatal and
the ANFE Mask bit is clear in “PCIe Correctable Error Mask Register” then:
• A Correctable error message is generated if the COR_ERR_EN bit is set in the “PCIe Device
Control and Status Register”
• ANFE bit is set in the “PCIe Correctable Error Status Register”
• COR_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
• PTLP bit is set in the “PCIe Uncorrectable Error Status Register”
• TLP header is logged in the Header Log register and ERR_PTR is updated if the PTLP Mask
bit in “PCIe Uncorrectable Error Mask Register” is clear and the ERR_PTR is not valid
2. If the severity of the PTLP bit in “PCIe Uncorrectable Error Severity Register” is Non-Fatal and
the ANFE Mask bit is set in “PCIe Correctable Error Mask Register” then:
• No error message is generated
• COR_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
• ANFE bit is set in the “PCIe Correctable Error Status Register”
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9. Error Handling > PCIe as Originating Interface70
3. If it is not an AFNE then:
• Fatal error message is generated if PTLP Mask bit is clear in the “PCIe Uncorrectable Error
Mask Register” and either SERR_EN bit is set in “PCI Control and Status Register” or
FTL_ERR_EN bit is set in the “PCIe Device Control and Status Register”
• FTL_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
• PTLP bit is set in the “PCIe Uncorrectable Error Status Register”
• TLP header is logged in the Header Log register and ERR_PTR is updated if the PTLP Mask
bit is clear and the ERR_PTR is not valid.
• S_SERR bit is set in the “PCI Control and Status Register” if Fatal error message is generated
and the SERR_EN bit is set in the “PCI Control and Status Register”.
4. In all three of the previous cases the following actions are also taken by the PEB383:
• D_PE bit is set in “PCI Control and Status Register”
• MDP_D bit set in “PCI Control and Status Register” if the poisoned TLP is a read completion
and the PERESP bit is set in the “PCI Control and Status Register”
• Parity bit is inverted on the PCI bus with each associated data Dword
• MDP_D bit is set in the “PCI Secondary Status and I/O Limit and Base Register” if the
S_PERESP bit is set in the “PCI Bridge Control and Interrupt Register”, and the bridge sees
the PCI_PERRn pin asserted when forwarding a write request transaction with bad parity to
the PCI bus. The PERR_AD bit in the “PCIe Secondary Uncorrectable Error Status Register”
is set, Secondary Header is Logged and Secondary First Error Pointer is updated if enabled.
No error message is generated when PCI_PERRn is seen asserted by the bridge when
forwarding a Poisoned TLP transaction from PCIe to PCI with bad parity.
9.2.2 Received ECRC Errors
When the PEB383 receives a TLP with ECRC error, it does the following:
1. Drops the transaction
2. D_PE is set in the “PCI Control and Status Register”
3. ECRC bit is set in the “PCIe Uncorrectable Error Status Register”
4. Header is logged in the “PCIe Header Log 1 Register” and the ERR_PTR field is updated in the
“PCIe Advanced Error Capabilities and Control Register” if ECRC Error Mask bit is clear in the
“PCIe Uncorrectable Error Mask Register” and ERR_PTR is not valid.
5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of ECRC bit in
“PCIe Uncorrectable Error Severity Register” if the ECRC Mask bit is clear in “PCIe
Uncorrectable Error Mask Register”, and either SERR_EN bit is set in the “PCI Control and S tatus
Register” or FTL_ERR_EN/NFTL_ERR_EN is set in the “PCIe Device Control and Status
Register”
6. S_SERR bit is set in the “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and SERR_EN bit is set in the “PCI Control and Status Register”
7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
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9. Error Handling > PCIe as Originating Interface 71
9.2.3 PCI Uncorrectable Data Errors
This section describes the bridge requirements for error handling when forwarding downstream
a.non-poisoned PCIe transaction to PCI and the bridge detects an uncorrectable data error. The error is
detected on the PCI Interface.
9.2.3.1 Immediate Reads
When the PEB383 forwards a read request (I/O, Memory, or Configuration) downstream, it does the
following when it detects an uncorrectable data error on the destination interface while receiving an
immediate response from the completer:
1. MDP_D bit is set in the “PCI Secondary S tatus and I/O Limit and Base Register”
if the S_PERESP
bit is set in the “PCI Bridge Control and Interrupt Register”
2. D_PE in the “PCI Control and Status Register” is set
3. PCI_PERRn is asserted on the PCI Interface if the S_PERESP bit is set in the “PCI Bridge Control
and Interrupt Register”
4. UDERR bit is set in “PCIe Secondary Uncorrectable Error Status Register”
5. Header is logged in the “PCIe Secondary Header Log 1 Register” and the SUFEP field is updated
in the “PCIe Secondary Error Capabilities and Control Register” if UDERR Mask bit is clear in the
“PCIe Secondary Uncorrectable Error Mask Register” and SUFEP is not valid
6. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of UDERR bit in
“PCIe Secondary Uncorrectable Error Severity Register” if the UDERR Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in the “PCI Control
and Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in the “PCIe Device Control and
Status Register”
7. S_SERR bit is set in the “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and S_SERR bit is set in the “PCI Control and Status Register”
8. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
For an immediate read transaction, if the PEB383 detects an uncorrectable data error on the destination
bus it continues to fetch data until the byte count is satisfied, or the target on the destination bus ends
the transaction. When the bridge creates the PCIe completion, it forwards it with successful completion
status and poisons the TLP.
9.2.3.2 Non-Posted Writes
When the PEB383 detects PCI_PERRn asserted on the PCI Interface while forwarding a non-poisoned
non-posted write transaction from PCIe, it does the following:
1. If the target completes the transaction immediately with a data transfer, the PEB383 generates a
PCIe completion with Unsupported Request status to report the error to the requester
2. PERR_AD bit is set in the “PCIe Secondary Uncorrectable Error Status Register”
3. MDP_D bit in the “PCI Secondary Status and I/O Limit and Base Register” is set if S_PERESP bit
is set in the “PCI Bridge Control and Interrupt Register”
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4. Header is logged in the “PCIe Secondary Header Log 1 Register” and the SUFEP field is updated
in the “PCIe Secondary Error Capabilities and Control Register” if PERR_AD Mask bit is clear in
the “PCIe Secondary Uncorrectable Error Mask Register” and SUFEP is not valid
5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of PERR_AD bit in
“PCIe Secondary Uncorrectable Error Severity Register” if the PERR_AD Mask bit is clear in
“PCIe Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in the “PCI
Control and Status Register” or FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device
Control and Status Register”
6. S_SERR bit is set in the “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and SERR_EN bit is set in the “PCI Control and Status Register”
7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
9.2.3.3 Posted Writes
When the PEB383 detects PCI_PERRn asserted on the PCI Interface while forwarding a non-poisoned
posted write transaction from PCIe, it does the following:
1. Continues to forward the remainder of the transaction
2. MDP_D bit in the “PCI Secondary Status and I/O Limit and Base Register” is set if S_PERESP bit
is set in the “PCI Bridge Control and Interrupt Register”
9. Error Handling > PCIe as Originating Interface72
3. PERRn Assertion Detected Status bit is set in the “PCIe Secondary Uncorrectable Error Status
Register”
4. Header is logged in the “PCIe Secondary Header Log 1 Register” and the SUFEP field is updated
in the “PCIe Secondary Error Capabilities and Control Register” if PERR_AD Mask bit is clear in
the “PCIe Secondary Uncorrectable Error Mask Register” and SUFEP is not valid
5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of PERR_AD bit in
“PCIe Secondary Uncorrectable Error Severity Register” if the PERR_AD Mask bit is clear in
“PCIe Secondary Uncorrectable Error Mask Register”, and either SERR_EN bit is set in the “PCI
Control and Status Register” or FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device
Control and Status Register”
6. S_SERR bit is set in the “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and SERR_EN bit is set in the “PCI Control and Status Register”
7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
9.2.4 PCI Uncorrectable Address/Attribute Errors
When the PEB383 forwards transactions from PCIe to PCI, address or attribute errors are reported
through the PCI_SERRn pin. When the PEB383 detects PCI_SERRn asserted it does the following:
1. Continues forwarding transaction
2. S_SERR System bit is set in the “PCI Secondary Status and I/O Limit and Base Register”
3. SERR_AD bit is set in the “PCIe Secondary Uncorrectable Error Status Register”
4. In this case Header is not logged but the SUFEP is updated in the “PCIe Secondary Error
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Capabilities and Control Register” if the SUFEP bit is not valid and SERR_AD Mask bit is clear in
the “PCIe Secondary Uncorrectable Error Mask Register”
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5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of SERR_AD bit in
“PCIe Secondary Uncorrectable Error Severity Register” if SERR_AD Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” or SERR_EN bit is set in “PCI Bridge Control and
Interrupt Register”, and either SERR_EN bit is set in “PCI Control and Status Register” or
FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status Register”
6. S_SERR bit is set in the “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and SERR_EN bit is set in the “PCI Control and Status Register”
7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
9.2.5 Received Master-Abort on PCI Interface
This section describes the actions taken by the PEB383 when a Master-Abort is received on the
PCI Interface.
9.2.5.1 Master Abort on a Posted Transaction
When the PEB383 receives a Master-Abort on the PCI bus while forwarding a posted write transa ction
from PCIe, it does the following:
1. Discards the entire transaction
2. R_MA bit is set in “PCI Secondary Status and I/O Limit and Base Register”
3. R_MA bit is set in the “PCIe Secondary Uncorrectable Error Status Register”
4. Header is logged in the “PCIe Secondary Header Log 1 Register” and SUFEP is updated in the
“PCIe Secondary Error Capabilities and Control Register” if R_MA Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of R_MA bit in
“PCIe Secondary Uncorrectable Error Severity Register” if R_MA Mask bit is clear in the “PCIe
Secondary Uncorrectable Error Mask Register” or MA_ERR bit is set in “PCI Bridge Control and
Interrupt Register”, and either SERR_EN bit is set in “PCI Control and Status Register” or
FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status Register”
6. S_SERR bit is set in “PCI Control and Status Register” if the R_MA Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” or MA_ERR bit is set in “PCI Bridge Control and
Interrupt Register” and the SERR_EN bit is set
7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device Control and Status Register”
9.2.5.2 Master-Abort On PCI Interface for Non-Posted Transaction
When the PEB383 receives a Master-Abort on the PCI bus while forwarding a non-posted PCIe
request, it does the following:
1. Returns a completion with Unsupported Request status on the PCIe
2. R_MA bit is set in “PCI Secondary Status and I/O Limit and Base Register”
3. R_MA bit is set in “PCIe Secondary Uncorrectable Error Status Register”
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4. Header is logged in the “PCIe Secondary Header Log 4 Register” and ERR_PTR is updated in the
“PCIe Secondary Error Capabilities and Control Register” if R_MA Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of R_MA bit in
“PCIe Secondary Uncorrectable Error Severity Register” if R_MA Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in “PCI Control and
Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status
Register”
6. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and the SERR Enable bit is set in “PCI Control and Status Register”
7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”
9.2.6 Received Target-Abort On PCI Interface
This section describes the functionality of the PEB383 when a Target-Abort is received on the PCI
Interface in response to posted, and non-posted transactions.
9.2.6.1 Target Abort On A Posted Transaction
9. Error Handling > PCIe as Originating Interface74
When the PEB383 receives Target-Abort on the PCI Interface for posted requests, it takes the
following actions:
1. Drops the entire transaction
2. R_TA bit is set in “PCI Secondary Status and I/O Limit and Base Register”
3. R_TA bit is set in “PCIe Secondary Uncorrectable Error Status Register”
4. Header is logged in the “PCIe Secondary Header Log 1 Register” and ERR_PTR is updated in the
“PCIe Secondary Error Capabilities and Control Register” if R_TA Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of R_TA bit in the
“PCIe Secondary Uncorrectable Error Severity Register” if R_TA Mask bit is clear in the “PCIe
Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in the “PCI Control
and Status Register”
or FTL_ERR_EN/NFTL_ERR_EN bit is set in the “PCIe Device Control and
Status Register”
6. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and the SERR_EN bit is set
7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”
9.2.6.2 Target-Abort On PCI Interface For Non-Posted Transaction
When the PEB383 receives a Target-Abort while forwarding a PCIe non-posted request to the PCI
Interface, it takes the following actions:
1. Returns a completion with Completer Abort status on the PCIe link
2. R_TA bit is set in “PCI Secondary Status and I/O Limit and Base Register”
3. R_TA bit is set in “PCIe Secondary Uncorrectable Error Status Register”
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9. Error Handling > PCI as Originating Interface 75
4. Header is logged in the “PCIe Secondary Header Log 1 Register” and ERR_PTR is updated in the
“PCIe Secondary Error Capabilities and Control Register” if R_TA Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of R_TA bit in
“PCIe Secondary Uncorrectable Error Severity Register” if R_TA Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in “PCI Control and
Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status
Register”
6. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and the SERR_EN bit is set in “PCI Control and Status Register”
7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”
9.3 PCI as Originating Interface
This section describes how the PEB383 handles errors for upstream transactions fr om PCI to PCIe (see
Figure 24). The bridge supports TLP poisoning as a Transmitter to permit proper forwarding of parity
errors that occur on the PCI Interface.
Figure 24: Transaction Error Forwarding with PCI as Originating Interface
PCIe
(Destination
Interface)
Requestor
or Delayed
Transact ion
completer
PCI
(Originating
Interface)
PEB38x Completer
Table 15 provides the error forwarding requirements for Uncorrectable data errors detected by the
PEB383 when a transaction targets the PCIe Interface. Posted and non-posted write data received on
the secondary PCI Interface with bad parity are forwarded to PCIe as Poisoned TLPs.
Table 15: Error Forwarding Requirements for Received PCI Errors
Received PCI Error Forwarded PCIe Error
Write with Uncorrectable Data Error Write request with Poisoned TLP
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9. Error Handling > PCI as Originating Interface76
Table 16 describes the PEB383 behavior on a PCI Delayed transaction that is forwarded by a bridge to
PCIe as a Memory Read request or an I/O Read/Write request, and the PCIe Interface returns a
completion with Unsupported Request or Completer Abort Completion status for the request.
Table 16: Error Forwarding Requirements for PCI Delayed Transaction
PCI Immediate Response
PCIe Completion Status
Unsupported Request (on Memory
or I/O Read)
Unsupported Request (on I/O
Write)
Completer Abort Target Abort Target Abort
Master-Abort Mode = 1
Target Abort Normal Completion, return
Target Abort Normal Completion
PCI Immediate Response
Master-Abort Mode = 0
0xFFFF_FFFF
9.3.1 Received PCI Errors
This section describes how the PEB383 handles PCI errors.
9.3.1.1 Uncorrectable Data Error on a Non-Posted Write Transaction PCI Mode
When the PEB383 receives non-posted write transaction that is addressed such that it crosses the
bridge, and the bridge detects an uncorrectable data error on its PCI Interface, it does the following:
1. D_PE bit is set in “PCI Secondary Status and I/O Limit and Base Register”
2. If S_PERESP bit is set in the “PCI Bridge Control and Interrupt Register”, then the transaction is
discarded and is not forwarded to PCIe and the PERR# pin is asserted on the PCI bus
3. If S_PERESP bit is not set in “PCI Bridge Control and Interrupt Register”, then the data is
forwarded to PCIe as a Poisoned TLP. M_DPE bit is set in “PCI Control and Status Register” if the
S_PERESP bit is set. The PERR# pin is not asserted on the PCI bus
4. UDERR bit is set in “PCIe Secondary Uncorrectable Error Status Register”
5. Header is logged in the “PCIe Secondary Header Log 1 Register” and ERR_PTR is updated in the
6. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of Uncorrectable
7. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
8. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”
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“PCIe Secondary Error Capabilities and Control Register” if UDERR Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
Data Error bit in “PCIe Secondary Uncorrectable Error Severity Register”, if UDERR Mask bit is
clear in “PCIe Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in
“PCI Control and Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device
Control and Status Register”
generated and the SERR_EN bit is set
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9.3.1.2 Uncorrectable Data Error on a Posted Write
When the PEB383 receives posted write transaction that is addressed such that it crosses the bridge and
the bridge detects an uncorrectable data error on its secondary PCI Interface, it does the following:
1. D_PE bit is set in “PCI Secondary Status and I/O Limit and Base Register”
2. If S_PERESP bit is set in “PCI Bridge Control and Interrupt Register”, PERR# signal is asserted
3. MDP_D bit is set in “PCI Secondary Status and I/O Limit and Base Register” if S_PERESP bit is
set in the “PCI Bridge Control and Interrupt Register”
4. UDERR bit is set in “PCIe Secondary Uncorrectable Error Status Register”
5. Header is logged in the “PCIe Secondary Header Log 1 Register” and ERR_PTR is updated in the
“PCIe Secondary Error Capabilities and Control Register” if UDERR Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
6. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of UDERR bit in
“PCIe Secondary Uncorrectable Error Severity Register” if UDERR Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in “PCI Control and
Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status
Register”
7. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and the SERR_EN bit is set in “PCI Control and Status Register”
8. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”
9.3.1.3 Uncorrectable Data Error on PCI Delayed Read Completions
When the PEB383 detects PERR# asserted by the initiating PCI master while forwarding a
non-poisoned read completion from PCIe to PCI, it does the following:
1. Forwards the remainder of completion
2. PERR_AD bit is set in “PCIe Secondary Uncorrectable Error Status Register”
3. Header is logged in the “PCIe Secondary Header Log 1 Register” and ERR_PTR is updated in the
“PCIe Secondary Error Capabilities and Control Register” if, PERR_AD Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
4. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of PERR_AD bit in
“PCIe Secondary Uncorrectable Error Severity Register”, if PERR_AD Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in “PCI Control and
Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status
Register”
5. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and the SERR_EN bit is set in “PCI Control and Status Register”
6. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”
When the PEB383 detects PERR# asserted by the initiating PCI master while forwarding a poisoned
read completion from PCIe to PCI, it does the above mentioned actions but no error message is
generated.
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9.3.1.4 Uncorrectable Address Error
When the PEB383 detects an Uncorrectable Address Error, and parity error detection is enabled using
the S_PERESP bit in “PCI Bridge Control and Interrupt Register”, the bridge takes the following
actions:
1. Transaction is terminated with a Target Abort and discarded
2. D_PE bit is set in “PCI Secondary Status and I/O Limit and Base Register” independent of
S_PERESP bit in “PCI Bridge Control and Interrupt Register”
3. S_TA bit is set in “PCI Secondary Status and I/O Limit and Base Register”
4. UADD_ERR bit is set in “PCIe Secondary Uncorrectable Error Status Register”
5. Header is logged in the Secondary Header Log register and ERR_PTR is updated in the “PCIe
Secondary Error Capabilities and Control Register” if UADD_ERR Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
6. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of UADD_ERR bit
in “PCIe Secondary Uncorrectable Error Severity Register” if UADD_ERR Mask bit is clear in
“PCIe Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in “PCI
Control and Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control
and Status Register”
9. Error Handling > PCI as Originating Interface78
7. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and the SERR_EN bit is set in “PCI Control and Status Register”
8. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”
9.3.1.5 Uncorrectable Attribute Error
When the PEB383 detects an Uncorrectable Attribute Error and parity error detection is enabled via the
Parity Error Response Enable bit in “PCI Bridge Control and Interrupt Register” then the bridge takes
the following actions:
1. Transaction is terminated with a Target Abort and discarded
2. D_PE bit is set in “PCI Secondary Status and I/O Limit and Base Register” independent of
S_PERESP bit in “PCI Bridge Control and Interrupt Register”
3. S_TA bit is set in “PCI Secondary Status and I/O Limit and Base Register”
4. UATT_ERR bit is set in “PCIe Secondary Uncorrectable Error Status Register”
5. Header is logged in the Secondary Header Log register and ERR_PTR is updated in the “PCIe
Secondary Error Capabilities and Control Register” if UATT_ERR Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” and ERR_PTR is not valid
6. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of UATT_ERR bit
in “PCIe Secondary Uncorrectable Error Severity Register” if UATT_ERR Mask bi t is clear in
“PCIe Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in “PCI
Control and Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control
and Status Register”
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9. Error Handling > Timeout Errors 79
7. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and the SERR_EN bit is set in “PCI Control and Status Register”
8. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”
9.3.2 Unsupported Request Completion Status
The PEB383 provides two methods for handling a PCIe completion received with Unsupported
Request status in response to a request originated by a secondary interface in PCI mode. The bridge’s
response to this completion is controlled by the MA_ERR bit in “PCI Bridge Control and Interrupt
Register”:
• MA_ERR bit set – When MA_ERR is set the PEB383 signals a Target-Abort to the originating
master of an upstream read or a non-posted write transaction if the corresponding request on the
PCIe link results in a completion with Unsupported Request status. The PEB383 also sets the
S_TA bit in the “PCI Secondary Status and I/O Limit and Base Register”.
• MA_ERR bit is cleared – This is the default PCI compatible mode where an Unsupported Request
Error is not considered an error. When a Read transaction initiated on the secondary interface
results in a completion with Unsupported Request status, the PEB383 returns 0xFFFF_FFFFto the
originating master and normally terminates the read transaction on the originating interface (by
asserting TRDY#). When a non-posted write transaction results in a completion with Unsupported
Request status, the PEB383 normally completes the write transaction on the originating bus (by
asserting TRDY#) and discards the write data.
In all cases of receiving Unsupported Request completion status on PCIe in response to a PCI request
initiated on the secondary interface, the PEB383 sets the R_MA in the “PCI Control and Status
Register”.
9.3.3 Completer Abort Completion Status
When the PEB383 receives a completion with Completer Abort status on the PCIe link in response to a
forwarded non-posted PCI transaction, it sets the R_TA bit in the “PCI Secondary Status and I/O Limit
and Base Register”.
A Completer Abort response on PCIe translates to a Delayed Transaction Ta rget-Abort if the secondary
interface is in PCI mode. The PEB383 provides data to the requesting agent up to the point where data
was successfully returned from the PCIe interface, and then signals Target-Abort. R_TA is set in “PCI
Control and Status Register” when signaling a Target-Abort to a PCI agent.
9.4 Timeout Errors
This section discusses how the PEB383 handles PCIe and PCI timeout errors.
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9.4.1 PCIe Completion Timeout Errors
The PCIe Completion Timeout function allows requestors to abort a non-posted request if the
completion does not arrive within a reasonable period of time. When bridges act as initiators on PCIe
on behalf of internally generated requests, and requests forwarded from a secondary interface in PCI
mode, they act as endpoints for requests that they take ownership. When the PEB383 detects a
completion timeout it responds as if a completion with Unsupported Req uest status has been received
and follows the rules for handling Unsupported Request Completions as described in “Unsupported
Request Completion Status”. In addition, the bridge takes the following actions:
1. CTO bit is set in “PCIe Uncorrectable Error Status Register”
2. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of the CTO bit in
“PCIe Uncorrectable Error Severity Register” if CTO Mask bit is clear in “PCIe Correctable Error
Mask Register” and either SERR_EN bit is set in “PCI Control and Status Register” or
FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status Register”
3. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and the SERR_EN bit is set in “PCI Control and Status Register”
9.4.2 PCI Delayed Transaction Timeout Errors
9. Error Handling > Other Errors80
If a delayed transaction timeout is detected the PEB383 does the following:
1. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of DTDTE bit in
“PCIe Secondary Uncorrectable Error Severity Register”, if DTDTE Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” or DISCARD_SERR bit is set “PCI Bridge
Control and Interrupt Register” and either SERR_EN bit is set in “PCI Control and Status
Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status
Register”
2. No Header is logged
3. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is
generated and SERR_EN bit is set in “PCI Control and Status Register”
9.5 Other Errors
PCI devices can assert SERR# when detecting errors that compromise system integrity. When the
PEB383 detects SERR# on the secondary interface, it does the following:
1. S_SERR bit is set in “PCI Secondary Status and I/O Limit and Base Register”
2. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of SERR_AD bit in
“PCIe Secondary Uncorrectable Error Severity Register” if SERR_AD Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask Register” or SERR_EN bit is set in “PCI Bridge Control and
Interrupt Register” and either SERR_EN bit is set in “PCI Control and Status Register” or
FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status Register”
3. SERR_AD bit is set in “PCIe Secondary Uncorrectable Error Status Register”
4. SUFEP field is updated in “PCIe Secondary Error Capabilities and Control Register”
5. No Header is Logged for SERR# assertion
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9. Error Handling > Error Handling Tables 81
9.6 Error Handling Tables
This section contains error handling information in a table format. Some of this information may
overlap with error information discussed in previous sections of this chapter.
Table 17: ECRC Errors
Error Details Primary Reporting Mechanism
ECRC Error 1. “PCIe Uncorrectable Error Status Register” [ECRC].
2. “PCI Control and Status Register” [D_PE].
3. “PCI Control and Status Register” [S_SERR] if an error
message is generated and [SERR_EN] bit is set in same
register.
4. “PCIe Device Control and Status Register”
[FTL_ERR_DTD/NFTL_ERR_DTD].
5. TLP is dropped.
Table 18: Poisoned TLP Errors
Error Details Primary Reporting Mechanism Secondary Reporting Mechanism
Poisoned TLP Error 1. “PCIe Device Control and Status
Register”[COR_ERR_DTD/FTL_ERR_DTD].
2. “PCIe Correctable Error Status Register”
[ANFE] in case of Advisory Non-Fatal
condition.
3. “PCIe Uncorrectable Error Status
Register” [PTLP].
4. “PCI Control and Status Register”
[S_SERR] if a Fatal error message is sent
and [SERR_EN] bit is set in same register.
5. “PCI Control and Status Register” [D_PE].
6. “PCI Control and Status Register”
[MDP_D] is set if the Poisoned TLP is a read
completion and [PERESP] is set in same
register.
1. “PCI Secondary Status and I/O Limit and
Base Register” [MDP_D] if [S_PERESP] is
set in “PCI Bridge Control and Interrupt
Register” and PCI_PERRn pin asserted
when forwarding a write request transaction
with bad parity to the PCI bus.
2. “PCIe Secondary Uncorrectable Error
Status Regist er” [PERR_AD].
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Table 19: Malformed TLP Errors
Error Details Primary Reporting Mechanism
9. Error Handling > Error Handling Tables82
Payload exceeds max_payload_size
Write TLP payload does not match length spec ified in
Completion TLP payload does not match length
Mismatch between TD and presence of ECRC
Address/Length combination crosses 4KByte
Received INTx message with TC > 0
Received Power Management message with TC > 0
Received Error message with TC > 0
Received Unlock message with TC > 0
TLP Type field uses undefined value
Illegal byte enables:
1. FBE = 0 when Length > 1DW.
2. LBE!= 0 when length = 1DW.
3. LBE = 0 when length > 1DW.
4. Non-contiguous byte enables when length = 2DW, and
non-Quadword aligned address.
5. Non-contiguous byte enables when length > 2DW.
1. “PCIe Uncorrectable Error Status Register” [MAL_TLP]
2. Optional ERR_FATAL or ERR_NONFATAL message sent.
3. “PCIe Device Control and Status Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
4. “PCI Control and Status Register” [S_SERR] if error
message is generated and [SERR_EN] is set in same
register.
5. TLP discarded.
IO request with TC > 0, or Attribute > 0 or Length > 1DW or
LBE > 0
Configuration request with TC>0, or Attribute > 0 or
Length >1DW or LBE > 0
Violations of RCB rules
CRS response to non-configuration request
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9. Error Handling > Error Handling Tables 83
Table 20: Link and Flow Control Errors
Error Details Primary Reporting Mechanisms
Receiver Overflow on header or data 1. “PCIe Uncorrectable Error Status Register” [RXO].
2. “PCIe Device Control and Status Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
3. Optional ERR_FATAL or ERR_NONFATAL message sent.
4. “PCI Control and Status Register” [S_SERR] if error
message is generated and [SERR_EN] is set in same
register.
Initial credits advertised are less than minimum 1. “PCIe Uncorrectable Error Status Register” [FCPE].
Received data credits > 2047, or header credits > 127
Initial infinite credit advertised, but subsequent UpdateFC
contains non-zero credit value.
2. “PCIe Device Control and Status
Register”[FTL_ERR_DTD]/[NFTL_ERR_DTD].
3. Optional ERR_FATAL or ERR_NONFATAL message sent.
4. “PCI Control and Status Register” [S_SERR] if error
message is generated and [SERR_EN] is set in same
register.
Invalid (that is, non-outstanding) AckNack_Seq_Num in
received Ack/Nak DLLP
TLP ends with EDB, but LCRC is not inverted 1. “PCIe Correctable Error Status Register” [B_TLP].
TLP ends with END, but LCRC is incorrect
TLP ends with END, LCRC is correct, but has invalid
DLLP has invalid CRC 1. “PCIe Correctable Error Status Register” [B_DLLP].
Replay number rolls over 1. “PCIe Correctable Error Status Register” [RN_RO].
Replay timer expires 1. “PCIe Correctable Error Status Register” [RT_TO].
1. “PCIe Uncorrectable Error Status Register” [DLPE].
2. “PCIe Device Control and Status Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
3. Optional ERR_FATAL or ERR_NONFATAL message sent.
4. “PCI Control and Status Register” [S_SERR] if error
message is generated and [SERR_EN] is set same register.
2. “PCIe Device Control and Status Register”
[COR_ERR_DTD].
3. Optional ERR_COR message sent.
2. “PCIe Device Control and Status Register”
[COR_ERR_DTD].
3. Optional ERR_COR message sent.
2. “PCIe Device Control and Status Register”
[COR_ERR_DTD].
3. Optional ERR_COR message sent.
2. “PCIe Device Control and Status Register”
[COR_ERR_DTD].
3. Optional ERR_COR message sent.
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Table 21: Uncorrectable Data/Address Errors
Error Details Primary Reporting Mechanism Secondary Reporting Mechanism
PCIe as Originating Interface
9. Error Handling > Error Handling Tables84
Uncorrectable Data Error on
the destination interface (PCI)
while receiving an immediate
response from the completer.
PCI_PERRn asserted on the
PCI Interface while forwarding
a non-posted write transaction
from PCIe.
PCI_PERRn asserted on the
PCI Interface while forwarding
a posted write transaction from
PCIe.
PCI_SERRn detected on the
PCI interface while forwarding
transactions from PCIe.
1. “PCI Control and Status Register” [D_PE].
2. PCI_PERRn is asserted on the PCI
Interface if the [S_PERESP] is set in “PCI
Bridge Control and Interrupt Register”.
3. “PCIe Device Control and S t atus Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
4. “PCI Control and Status Register”
[S_SERR] if an error message
(Fatal/Non-Fatal) is generated and
[S_SERR] is set in same register.
1. “PCIe Device Control and S t atus Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
2. “PCI Control and Status Register”
[S_SERR] if error message is sent and
[SERR_EN] is set in same register.
1. “PCI Secondary Status and I/O Limit and
Base Register” [MDP_D] if “PCI Bridge
Control and Interrupt Register” [S_PERESP]
is set.
2. “PCIe Secondary Uncorrectable Error
Status Register” [UDERR].
1. “PCIe Secondary Uncorrectable Error
Status Register” [PERR_AD]
2. “PCI Secondary Status and I/O Limit and
Base Register” [MDP_D] if “PCI Bridge
Control and Interrupt Register” [S_PERESP]
1. “PCI Secondary Status and I/O Limit and
Base Register” [MDP_D] if “PCI Bridge
Control and Interrupt Register” [S_PERESP]
2. “PCIe Secondary Uncorrectable Error
Status Register” [PERR_AD]
1. “PCI Secondary Status and I/O Limit and
Base Register” [S_SERR].
2. “PCIe Secondary Uncorrectable Error
Status Register” [SERR_AD].
Uncorrectable data error on a
non-posted write transaction
PCI mode.
Uncorrectable data error on a
posted write transaction.
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PCI as Originating Interface
1. “PCIe Device Control and S t atus Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
2. “PCI Control and Status Register”
[S_SERR] if error message is sent and
[SERR_EN] is set in same register.
1. If S_PERESP bit is set in “PCI Bridge
Control and Interrupt Register”
signal is asserted.
2. “PCIe Device Control and S t atus Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
3. “PCI Control and Status Register”
[S_SERR] if error message is sent and
[SERR_EN] is set in same register.
, PERR#
1. “PCI Secondary Status and I/O Limit and
Base Register” [D_PE].
2. “PCIe Secondary Uncorrectable Error
Status Register” [UDERR].
1. “PCI Secondary Status and I/O Limit and
Base Register” [D_PE].
2. “PCI Secondary Status and I/O Limit and
Base Register” [MDP_D] if [S_PERESP] bit
is set in the “PCI Bridge Control and Interrupt
Register”.
3. “PCIe Secondary Uncorrectable Error
Status Register” [UDERR].
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Table 21: Uncorrectable Data/Address Errors (Continued)
Error Details Primary Reporting Mechanism Secondary Rep o r ting Mechanism
Uncorrectable data error on
PCI delayed read completions.
Uncorrectable Address Error 1. “PCI Secondary Status and I/O Limit and
1. “PCIe Device Control and Status Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
2. “PCI Control and Status Register”
[S_SERR] if error message is sent and
[SERR_EN] is set in same register.
1. “PCIe Secondary Uncorrectable Error
Status Register” [PERR_AD]
Base Register” [D_PE].
2. “PCI Secondary Status and I/O Limit and
Base Register” [S_TA].
3. “PCIe Secondary Uncorrectable Error
Status Register” [UADD_ERR].
Table 22: Received Master/Target Abort Error
Error Details Primary Reporting Mechanism Secondary Reporting Mechanism
Master-Abort on the PCI bus
while forwarding a posted write
transaction from PCIe
1. “PCI Control and Status Register”
[S_SERR] if R_MA Mask bit is clear in “PCIe
Secondary Uncorrectable Error Mask
Register” or MA_ERR bit is set in “PCI
Bridge Control and Interrupt Regis t er” and
“PCI Control and Status Register”
[SERR_EN] is set.
2. “PCIe Device Control and Status Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
1. “PCI Secondary Status and I/O Limit and
Base Register” [R_MA].
2. “PCIe Secondary Uncorrectable Error
Status Regist er” [R_MA].
Master-Abort on the PCI bus
while forwarding a non-posted
write transaction from PCIe
Target-Abort on the PCI bus
while forwarding a posted
transaction from PCIe
Target-Abort on the PCI bus
while forwarding a non-posted
transaction from PCIe
1. “PCIe Device Control and Status Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
2. “PCI Control and Status Register”
[S_SERR] if error message is sent and
[SERR_EN] is set in same register.
1. “PCIe Device Control and Status Register”
[FTL_ERR_DTD]/[NFTL_ERR_DTD].
2. “PCI Control and Status Register”
[S_SERR] if error message is sent and
[SERR_EN] is set in same register.
1. “PCI Secondary Status and I/O Limit and
Base Register” [R_TA].
2. “PCIe Secondary Uncorrectable Error
Status Regist er” [R_TA].
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Table 23: Completion Errors
Error Details Primary Reporting Mechanism Secondary Reporting Mechanism
9. Error Handling > Error Handling Tables86
Completion received with
Unsupported Request in
response to a request
originated by a secondary
interface in PCI mode.
Completion received with
Completer Abort status on the
PCIe link in response to a
forwarded non-posted PCI
transaction.
Received Unexpected
Completion Error
Completion Timeout Error 1. “PCIe Uncorrectable Error Status
1. “PCI Control and Status Register” [R_MA]. 1. “PCI Secondary Status and I/O Limit and
1. “PCI Control and Status Register”[R_TA]. 1. “PCI Secondary Status and I/O Limit and
1. “PCIe Uncorrectable Error Status
Register” [UXC] if not masked.
2. “PCIe Device Control and Status Register”
[COR_ERR_DTD] if ANFE.
Register” [CTO] if not masked.
2. “PCIe Device Control and Status Register”
[COR_ERR_DTD] if ANFE.
Table 24: Request Errors
Base Register” [S_TA] is set if [MA_ERR] bit
in “PCI Bridge Control and Int errupt Register”
is set.
Base Register” [S_TA].
N/A
N/A
Error Details Primary Reporting Mechanism Secondary Reporting Mechanism
Received vendor message
(Type 0).
Non-configuration or message
received while in D1, D2 or D3
hot.
Configuration Type 0 access
with a non-zero function.
1. “PCIe Uncorrectable Error Status
Register” [UR] if not masked.
2. “PCIe Device Control and Status Register”
[UNS_REQ_DTD].
3. “PCIe Device Control and Status Register”
[COR_ERR_DTD] if ANFE.
N/A
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