IDT 89EBPES24T3G2 User Manual

®

IDT™ 89EBPES24T3G2

Evaluation Board Manual

(Eval Board: 18-657-000)

January 2008

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

DISCLAIMER

Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a Failure Analysis be performed.

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

LIFE SUPPORT POLICY

Table of Contents

®

Notes

Description of the EB24T3G2 Eval Board

Introduction .....................................................................................................................................1-1

Board Features ...............................................................................................................................1-2

Hardware ................................................................................................................................ 1-2

Software..................................................................................................................................1-2

Other....................................................................................................................................... 1-2

Revision History..............................................................................................................................1-2

Installation of the EB24T3G2 Eval Board

EB24T3G2 Installation....................................................................................................................2-1

Hardware Description .....................................................................................................................2-1

Reference Clocks............................................................................................................................2-1

Power Sources................................................................................................................................2-2

External Power Source...........................................................................................................2-2

PCI Express Analog High Power Voltage Converter.............................................................. 2-2

PCI Express Analog Power Voltage Converter ......................................................................2-2

PCI Express Transmitter Analog Power Voltage Converter ...................................................2-2

Core Logic Voltage Converter ................................................................................................2-2

3.3V I/O Voltage Regulator..................................................................................................... 2-2

Power-up Sequence ...............................................................................................................2-3

Reset...............................................................................................................................................2-3

Fundamental Reset ................................................................................................................2-3

Downstream Reset .................................................................................................................2-3

Boot Configuration Vector............................................................................................................... 2-3

SMBus Interfaces............................................................................................................................2-4

SMBus Slave Interface ...........................................................................................................2-4

SMBus Master Interface .........................................................................................................2-5

JTAG Header..................................................................................................................................2-6

Attention Buttons.............................................................................................................................2-6

Miscellaneous Jumpers, Headers................................................................................................... 2-7

LEDs ...............................................................................................................................................2-7

PCI Express Connectors.................................................................................................................2-8

EB24T3G2 Board Figure ..............................................................................................................2-10

Software for the EB24T3G2 Eval Board

Introduction .....................................................................................................................................3-1

Device Management Software........................................................................................................ 3-1

Schematics

Schematics .....................................................................................................................................4-1

EB24T3G2 Eval Board Manual i January 21, 2008

IDT Table of Contents

Notes

EB24T3G2 Eval Board Manual ii January 21, 2008

List of Tables

®

Notes

Table 2.1 Clock Source Selection .......................................................................................................2-1

Table 2.2 SMA Connectors - Onboard Reference Clock .................................................................... 2-2

Table 2.3 External Power Connector - J1 ........................................................................................... 2-2

Table 2.4 Downstream Reset Selection .............................................................................................2-3

Table 2.5 Boot Configuration Vector Signals ...................................................................................... 2-4

Table 2.6 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1) ........................................... 2-4

Table 2.7 Slave SMBus Interface Connector ......................................................................................2-5

Table 2.8 EEPROM SMBus Address Setting .....................................................................................2-5

Table 2.9 JTAG Connector Pin Out .................................................................................................... 2-6

Table 2.10 Attention Buttons ................................................................................................................2-6

Table 2.11 Miscellaneous Jumpers, Headers .......................................................................................2-7

Table 2.12 LED Indicators .................................................................................................................... 2-7

Table 2.13 PCI Express x8 Connector Pinout ......................................................................................2-8

EB24T3G2 Eval Board Manual iii January 21, 2008

IDT List of Tables

Notes

EB24T3G2 Eval Board Manual iv January 21, 2008

List of Figures

®

Notes

Figure 1.1 Function Block Diagram of the EB24T3G2 Eval Board ......................................................1-1

EB24T3G2 Eval Board Manual v January 21, 2008

IDT List of Figures

Notes

EB24T3G2 Eval Board Manual vi January 21, 2008

Chapter 1

Description of the EB24T3G2

Eval Board

®

Notes

Introduction

The 89HPES24T3G2 switch (also referred to as PES24T3G2 in this manual) is a member of IDT’s PCI Express® standard based line of products. It is a PCIe® Base Specification 2.0 compliant (Gen2) 3-port switch, with 8 serial lanes per port. One x8 upstream port is provided for connecting to the root complex (RC), and two x8 downstream ports are available for connecting to PCIe endpoints or to another switch. More information on this device can be found in the 89HPES24T3G2 User Manual.

The 89EBPES24T3G2 Evaluation Board (also referred to as EB24T3G2 in this manual) provides an evaluation platform for the PES24T3G2 switch. It is also a cost effective way to add PCIe ports (slots) to an existing system with limited number of PCIe ports/slots. The EB24T3G2 board is designed to function as an add-on card to be plugged into a x8 PCIe slot available on a motherboard hosting an appropriate root complex and microprocessor(s). The EB24T3G2 is a vehicle to test and evaluate the functionality of the PES24T3G2 switch. Customers can use this board to get a headstart on software development prior to the arrival of their own hardware. The EB24T3G2 is also used by IDT to reproduce system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block diagram representing the main parts of the EB24T3G2 board.

JTAG

Header

Clock

Fanout

Clock

Generator

25 MHz Crystal

Main

Reset

I/O Expander

PCA9555

EEPROM

24LC512

SMBUS

HEADER

PCI Express Switch

PES24T3G2

SMBus

PCIe x8 Upstream Edge

(lane reversed)

Figure 1.1 Function Block Diagram of the EB24T3G2 Eval Board

Port 2

Port 4

Port 0

x8

PCIe x8 Downstream Slot

Power Module PTH08T240

Voltages on board +12V, +3.3V, +2.5V, +1.0V

External Power Connector

EB24T3G2 Eval Board Manual 1 - 1 January 21, 2008

IDT Description of the EB24T3G2 Eval Board

Notes

Board Features

Hardware



PES24T3G2 PCIe 3 port switch

– Three x8 ports, 24 PCIe lanes – PCIe Base Specification Revision 2.0 compliant (Gen2 SerDes speeds of 5 GT/S) – Up to 2048 byte maximum Payload Size – Automatic lane reversal and polarity inversion supported on all lanes – Automatic per port link width negotiation to x8, x4, x2, x1 – Load configuration from an optional serial EEPROM via SMBUS



Upstream, Downstream Port

– One edge connector on the upstream port, to be plugged into a slot with at least x8 capable on a

host motherboard

– Two slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.

These slot connectors are x8 mechanically but open-ended for card widths greater than x8 (e.g. x16)



Numerous user selectable configurations set using onboard jumpers and DIP-switches

– Source of clock - host clock or onboard clock generator – Two clock rates (100/125 MHz) from an onboard clock generator – Boot mode selection



SMBUS Slave Interface (4 pin header)



SMBUS Master Interface connected to the Serial EEPROMs through I/O expander



“Attention” button for each downstream port to initiate a hot swap event on each port



Four pin connector for optional external power supply



Push button for Warm Reset



Several LEDs to display status, reset, power, “Attention”, etc.



One 10-pin JTAG connector (pitch 2.54 mm x 2.54 mm)

Software

There is no software or firmware executed on the board. However, useful software is provided along with the Evaluation Board to facilitate configuration and evaluation of the PES24T3G2 within host systems running popular operating systems.



Installation programs

– Operating Systems Supported: Windows2000, WindowsXP, Vista, Linux



GUI based application for Windows and Linux

– Allows users to view and modify registers in the PES24T3G2 – Binary file generator for programming the serial EEPROMs attached to the SMBUS.

Other



A metal bracket is provided to firmly hold in place two endpoints plugged into the EB24T3G2 board.



An external power supply may be required under some conditions.



SMBUS cable may be required for certain evaluation exercises.



SMA connectors are provided on the EB24T3G2 board for clock outputs.

Revision History

January 21, 2008: Initial publication of eval board manual.

EB24T3G2 Eval Board Manual 1 - 2 January 21, 2008

Chapter 2

Installation of the EB24T3G2

Eval Board

®

Notes

EB24T3G2 Installation

This chapter discusses the steps required to configure and install the EB24T3G2 evaluation board. All available DIP switches and jumper configurations are explained in detail.

The primary installation steps are:

1. Configure jumper/switch options suitable for the evaluation or application requirements.

2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.

3. Make sure that the host system (motherboard with root complex chipset) is powered off.

4. Insert the evaluation board into the host system.

5. Apply power to the host system.

The EB24T3G2 board is typically shipped with all jumpers and switches configured to their default settings. In most cases, the board does not require further modification or setup.

Hardware Description

The PES24T3G2 is a 24-lane, 3-port PCI Express® switch. It is a peripheral chip that performs PCI Express based switching with a feature set optimized for high performance applications such as servers and storage. It provides fan-out and switching functions between a PCI Express upstream port and downstream ports or peer-to-peer switching between downstream ports.

The EB24T3G2 has two PCI Express downstream ports, accessible through two x8 connectors. Both ports are capable of negotiating a x1, x2, x4, and x8 link width. All endpoint cards connected to the PES24T3G2 must support one of these link widths.

Basic requirements for the board to run are:

– Host system with a PCI Express root complex supporting at least x8 configuration through a PCI

– x1, x2, x4 or x8 PCI Express Endpoint Cards.

Express x8 or larger slot.

Reference Clocks

The PES24T3G2 requires a differential reference clock. The EB24T3G2 derives this clock from a common source which is user-selectable. The common source can be either the host system’s reference clock or it can be the onboard clock generator. Selection is made by stuffing resistors as in Table 2.1.

Clock Configuration Stuffing Option

W6 and W7 Clock Source

Pins 2 and 3 Onboard Reference Clock – Use onboard clock generator

Pins 1 and 2 Upstream Reference Clock – Host system provides clock (Default)

Table 2.1 Clock Source Selection

The source for the onboard clock is the ICS841484 clock generator device (U4) connected to a 25MHz oscillator (Y1). When using the onboard clock generator, the output frequency is fixed at 100MHz, therefore FSEL0 (S7, bit 8) is On as the default setting.

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IDT Installation of the EB24T3G2 Eval Board

Notes

The output of the onboard clock generator is accessible through two SMA connectors located on the Evaluation Board. See Table 2.2. This can be used to connect a scope for probing or capturing purposes and cannot be used to drive the clock from an external source.

Onboard Reference Clock Output (Differential) – J7, J6

J9 Positive Reference Clock

J10 Negative Reference Clock

Table 2.2 SMA Connectors - Onboard Reference Clock

Power Sources

The EB24T3G2 and both downstream ports are powered from the upstream port slot power. If add-in cards require more power than the upstream slot can support, an external source is required to supply this extra power via an auxiliary 4-pin power connector on the board. Header W1, W2, and W3 (see Table 2.1 are used to select proper power source for the switch and all downstream ports.

External Power Source

If necessary, external power is supplied to the EB24T3G2 board through a 4-pin auxiliary power connector attached to J4. The external power supply provides +12V to the EB24T3G2 as described in Table

2.3. The +5V is unused.

1)

Pin Signal

1+12V

2GND

3GND

4+5V

Table 2.3 External Power Connector - J1

PCI Express Analog High Power Voltage Converter

A DC-DC converter (U18) provides a 2.5V PCI Express analog high power voltage (shown as VDDHA) to the PES24T3G2.

PCI Express Analog Power Voltage Converter

A separate DC-DC converter (U16) provides a 1.0V PCI Express analog power voltage (VDDA) to the PES24T3G2.

PCI Express Transmitter Analog Power Voltage Converter

A separate DC-DC converter (U17) provides a 1.0V PCI Express transmitter analog power voltage (shown as VDDPETA) to the PES24T3G2.

Core Logic Voltage Converter

A separate DC-DC converter (U15) provides the 1.0V core voltage (VDDCORE) to the PES24T3G2.

3.3V I/O Voltage Regulator

A 12V to 3.3V voltage regulator (VR1) provides the 3.3V I/O voltage (VDDIO) to the PES24T3G2.

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IDT Installation of the EB24T3G2 Eval Board

Notes

Power-up Sequence

During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There are no other power-up sequence requirements for the various operating supply voltages.

Reset

The PES24T3G2 supports two types of reset mechanisms as described in the PCI Express specification:

– Fundamental Reset: This is a system-generated reset that propagates along the PCI Express

tree through a single side-band signal PERST# which is connected to the Root Complex, the PES24T3G2, and the endpoints.

– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to

another. Hot Reset may be initiated by software. This is further discussed in the 89HPES24T3G2 User Manual. The EB24T3G2 evaluation board provides seamless support for Hot Reset.

Fundamental Reset

There are two types of Fundamental Resets which may occur on the EB24T3G2 evaluation board:

– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI

Express Reset (PERSTN) input pin of the PES24T3G2.

– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be

initiated by two methods:

• Pressing a push-button switch (S1) located on EB24T3G2 board

• The host system board IO Controller Hub asserting PERST# signal, which propagates through

the PCIe upstream edge connector of the EB24T3G2. Note that one can bypass the onboard voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W4.

Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset (PERSTN) input of the PES24T3G2 while power is on.

Downstream Reset

The PES24T3G2 provides a a choice of either a software-controlled reset for each downstream port through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in Table 2.4.

Port # Jumper Selection

2 W19 [1-2] Software controlled reset through GPIO0

[2-3] Fundamental reset PERST# (default)

4 W18 [1-2] Software controlled reset through GPIO1

[2-3] Fundamental reset PERST# (default)

Table 2.4 Downstream Reset Selection

Boot Configuration Vector

A boot configuration vector consisting of the signals listed in Table 2.5 is sampled by the PES24T3G2 during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential parameters for switch operation and is set using DIP switches S7 and S8 as defined in Table 2.6.

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IDT Installation of the EB24T3G2 Eval Board

Notes

Signal Description

CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream

ports are using the same clock source as that provided to downstream devices. This pin is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in the downstream port’s PCIELSTS register. Default: 0x1

CCLKUS Common Clock Upstream. The assertion of this pin indicates that the upstream port is

using the same clock source as the upstream device. This pin is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. Default: 0x1

SWMODE[2:0] Switch Mode. These configuration pins determine the PES24T3G2 switch operating

mode. Default: 0x0 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM-based initialization 0x2 through 0x7 - Reserved

Signal Description Default

Table 2.5 Boot Configuration Vector Signals

S8[1] CCLKDS OFF

S8[2] CCLKUS OFF

S7[1] SWMODE[0] ON

S7[2] SWMODE[1] ON

S7[3] SWMODE[2] ON

Table 2.6 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1)

SMBus Interfaces

The System Management Bus (SMBus) is a two-wire interface through which various system compo-

2

nent chips can communicate. It is based on the principles of operation of I signals in the PCI Express connector is optional and may not be present on the host system. The SMBus interface consists of an SMBus clock pin and an SMBus data pin.

Note: MSMBADDR and SSMBADDR address pins are not available in the PES24T3G2. The MSMBADDR address is hardwired to 0x50, and the SSMBADDR address is hardwired to 0x77.

The PES24T3G2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface. The slave SMBus interface allows a SMBus Master device full access to all software-visible registers. The Master SMBus interface provides connection to the external serial EEPROM used for initialization and the I/O expanders used for hot-plug signals.

SMBus Slave Interface

On the PES24T3G2 board, the slave SMBus interface is accessible through the PCI Express edge connector as well as a 4-pin header as described in Table 2.7.

Note: The SMBus signals to the PCI Express edge connector is disabled by default. To enable them, place 0-ohm resistors at locations R160 and R161.

C. Implementation of the SMBus

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IDT Installation of the EB24T3G2 Eval Board

Notes

.

Slave SMBus Interface Connector J8

Pin Signal

1N/C

2SCL

3GND

4SDA

Table 2.7 Slave SMBus Interface Connector

The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. Initiation of any SMBus transaction other than those listed above produces undefined results. See the SMBus 2.0 specification for a detailed description of the following transactions:

– Byte and Word Write/Read – Block Write/Read

SMBus Master Interface

Connected to the master SMBus interface are four 16-bit I/O Expanders (PCA9555) and a serial EEPROM (24LC512). Four I/O Expanders are used as the interface for the onboard hot-plug controllers (MIC2591B). The lower three bits of the bus address for the I/O Expander0/1/2/4 are fixed as 0x0, 0x1, 0x2 and 0x4, respectively.

The seven bits address for the selected EEPROM device is 0b1010_000 by default and the lower three bit is configurable using switch S8 as described in 2.8.

S8[3] S8[4] S8[5] Bus Address

OFF OFF OFF 0b111

OFF OFF ON 0b110

OFF ON OFF 0101

OFF ON ON 0b100

ON OFF OFF 0b011

ON OFF ON 0b010

ON ON OFF 0b001

ON ON ON 0b000 (Default)

Table 2.8 EEPROM SMBus Address Setting

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IDT Installation of the EB24T3G2 Eval Board

Notes

JTAG Header

The PES24T3G2 provides a JTAG connector J5 for access to the PES24T3G2 JTAG interface. The connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.9 for the JTAG Connector J5 pin out.

JTAG Connector J5

Pin Signal Direction Pin Signal Direction

1 /TRST - Test reset Input 2 GND —

3 TDI - Test data Input 4 GND —

5 TDO - Test data Output 6 GND —

7 TMS - Test mode select Input 8 GND —

9 TCK - Test clock Input 10 GND —

Table 2.9 JTAG Connector Pin Out

Attention Buttons

The PES24T3G2 features three attention buttons, shown in 2.10. Each button corresponds to a particular port and is used to initiate hot-swapping events.

Button Description

S5 Port 2 Attention Button

S3 Port 4 Attention Button

Table 2.10 Attention Buttons

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IDT Installation of the EB24T3G2 Eval Board

Notes

Miscellaneous Jumpers, Headers

Ref.

Designator

W1-W3 Header 1-2 Shunted 1-2: 12.0V source from Upstream Port (Default)

W20 Header Shunted Disable EEPROM Write protect feature (Default)

S6[1] Switch ON ON: Port2, Force hot-plug controller on

S6[2] Switch ON ON: Port4, Force hot-plug controller on

W15 Header 2-3 Shunted 2-3: Port 2, +12V source from Upstream port (Default)

W9 Header 2-3 Shunted 2-3: Port 4, +12V source from Upstream port (Default)

W16 Header 2-3 Shunted 2-3: Port 2, +3.3V source from Upstream port (Default)

W10 Header 2-3 Shunted 2-3: Port 4, +3.3V source from Upstream port (Default)

W14 Header 2-3 Shunted 2-3: Port 2, +3.3AUX source from upstream port (Default)

W8 Header 2-3 Shunted 2-3: Port 4, +3.3AUX source from upstream port (Default)

Type Default Description

2-3: 12.0V source from external power connector

OFF: Port2, Power Enable bit controls hot-plug controller

OFF: Port4, Power Enable bit controls hot-plug controller

1-2: Port 2, +12V source from hot-plug controller

1-2: Port 4, +12V source from hot-plug controller

1-2: Port 2, +3.3V source from hot-plug controller

1-2: Port 4, +3.3V source from hot-plug controller

1-2: Port 2, +3.3V source from hot-plug controller

1-2: Port 4, +3.3V source from hot-plug controller

Table 2.11 Miscellaneous Jumpers, Headers

LEDs

There are several LED indicators on the EB24T3G2 which convey status feedback. A description of each is provided in Table 2.12.

Location Color Definition

DS21 Green Port 2: Power-is-good Indicator

DS15 Green Port 4: Power-is-good Indicator

DS20 Green Port 2: Power Indicator

DS14 Green Port 4: Power Indicator

DS19 Yellow Port 2: Attention Indicator

DS13 Yellow Port 4: Attention Indicator

DS18 Green Port 2: Activity Indicator

DS12 Green Port 4: Activity Indicator

DS17 Green Port 2: Linkup Indicator

DS11 Green Port 4: Linkup Indicator

Table 2.12 LED Indicators (Part 1 of 2)

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IDT Installation of the EB24T3G2 Eval Board

Notes

Location Color Definition

DS23 Green Port 0: Linkup Indicator

DS24 Green Port 0: Activity Indicator

DS7 Red Port 2: Power Fault Indicator

DS10 Red Port 4: Power Fault Indicator

DS25 Green GPIO8

DS5 Green GPIO9

DS26 Green GPIO10

DS6 Red Port 2: Manual Retention Latch Indicator

DS9 Red Port 4: Manual Retention Latch Indicator

DS8 Green Port 2: Presence Detect Indicator

DS27 Green Port 4: Presence Detect Indicator

Table 2.12 LED Indicators (Part 2 of 2)

PCI Express Connectors

Pin Side A Side B

1 +12V 12V power PRSNT1# Hot-Plug presence detect

2 +12V 12V power +12V 12V power

3 RSVD Reserved +12V 12V power

4 GND Ground GND Ground

5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p

6 SMDAT SMBus Data JTAG TDI (Test Data Input)

7 GND Ground JTAG TDO (Test Data Output)

8 +3.3V 3.3V power JTAG TMS (Test Mode Select)

9 JTAG1 TRST# (Test/Reset) resets

JTAG i/f

10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power

11 WAKE# Signal for Link reactivation PERST# Fundamental Reset

Mechanical Key

12 RSVD Reserved GND Ground

13 GND Ground REFCLK+ REFCLK Reference clock

14 PETp0 Transmitter differential REFCLK- (differential pair)

15 PETn0 pair, Lane 0 GND Ground

16 GND Ground PERp0 Receiver differential

17 PRSNT2# Hot-Plug presence detect PERn0 pair, Lane 0

+3.3V 3.3V power

18 GND Ground GND Ground

19 PETp1 Transmitter differential RSVD Reserved

Table 2.13 PCI Express x8 Connector Pinout (Part 1 of 2)

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IDT Installation of the EB24T3G2 Eval Board

Notes

Pin Side A Side B

20 PETn1 pair, Lane 1 GND Ground

21 GND Ground PERp1 Receiver differential

22 GND Ground PERn1 pair, Lane 1

23 PETp2 Transmitter differential GND Ground

24 PETn2 pair, Lane 2 GND Ground

25 GND Ground PERp2 Receiver differential

26 GND Ground PERn2 pair, Lane 2

27 PETp3 Transmitter differential GND Ground

28 PETn3 pair, Lane 3 GND Ground

29 GND Ground PERp3 Receiver differential

30 RSVD Reserved PERn3 pair, Lane 3

31 PRSNT2# Hot-Plug presence detect GND Ground

32 GND Ground RSVD Reserved

33 PETp4 Transmitter differential RSVD Reserved

34 PETn4 pair, Lane 4 GND Ground

35 GND Ground PERp4 Receiver differential

36 GND Ground PERn4 pair, Lane 4

37 PETp5 Transmitter differential GND Ground

38 PETn5 pair, Lane 5 GND Ground

39 GND Ground PERp5 Receiver differential

40 GND Ground PERn5 pair, Lane 5

41 PETp6 Transmitter differential GND Ground

42 PETn6 pair, Lane 6 GND Ground

43 GND Ground PERp6 Receiver differential

44 GND Ground PERn6 pair, Lane 6

45 PETp7 Transmitter differential GND Ground

46 PETn7 pair, Lane 7 GND Ground

47 GND Ground PERp7 Receiver differential

48 PRSNT2# Hot-Plug presence detect PERn7 pair, Lane 7

49 GND Ground GND Ground

Table 2.13 PCI Express x8 Connector Pinout (Part 2 of 2)

Note: These x8 PCI Express connectors comply with the PCIe specification. According to the

PCI Express specification, the PRSNT1# pin should be wired to the farthest available PRSNT2# pin on the connector. In the EB24T3G2, all PRSNT2# pins are tied together. This allows a board with a x1 or a x4 width to be installed.

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IDT Installation of the EB24T3G2 Eval Board

Slot 4

EB24T3G2 Board Figure

S8

S6

S7

Slot 2

EB24T3G2 Eval Board Manual 2 - 10 January 21, 2008

Chapter 3

Software for the EB24T3G2

Eval Board

®

Notes

Introduction

This chapter discusses some of the main features of the available software to give users a better understanding of what can be achieved with the EB24T3G2 evaluation board using the device management software.

Device management software and related user documentation are available on a CD which is included in the Evaluation Board Kit. This information is also available on IDT’s FTP site. For more information, contact IDT at ssdhelp@idt.com.

Device Management Software

The primary use of the Device Management Software package is to enable users of the evaluation board to access all the registers in the PES24T3G2 device. This access can be achieved using the PCI Express in-band configuration cycles through the upstream port on the PES24T3G2.

This software also enables users to save a snapshot of the current register set into a dump file which can be used for debugging purposes. An export/import facility is also available to create and use “Configuration” files which can be used to initialize the switch device with specific values in specific registers.

A conversion utility is also provided to translate a configuration file into an EEPROM programmable data structure. This enables the user to program an appropriate serial EEPROM with desirable register settings for the PES24T3G2, and then to populate that EEPROM onto the Evaluation Board. It is also possible to program the EEPROM directly on the Evaluation Board using a feature provided by the software package.

The front end of the Device Management Software is a user-friendly Graphical User Interface which allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the software in “simulation” mode with no real hardware attached, allowing the creation of configuration files for the PES24T3G2 in the absence of the actual device.

Much of the Device Management Software is written with device-independent and OS-independent code. The software will be guaranteed to work on Linux (/sys interface) and MS Windows XP. It may function flawlessly on various flavors of MS Windows, but may not be validated on all. The fact that the software is device-independent assures its scalability to future PCIe parts from IDT. Once users are familiar with the GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc.

EB24T3G2 Eval Board Manual 3 - 1 January 21, 2008

IDT Software for the EB24T3G2 Eval Board

Notes

EB24T3G2 Eval Board Manual 3 - 2 January 21, 2008

Chapter 4

Schematics

®

Notes

Schematics

EB24T3G2 Eval Board Manual 4 - 1 January 21, 2008

8

6

57

4

3

DCN

PCB-0148R01 1.0 INITIAL RELEASE 2008-01-17 T. TRAN

2

DESCRIPTION

REVISIONS

1

DATEREV

CHANGE BY

D

SHEET DESCRIPTION

------------------------------1 TITLE PAGE

2 RESET, POWER CONNECTOR

CC

3 POWER REGULATORS 4 CLOCKS 5 I/O EXP, WAKE, ATTN 6 HOT PLUG CONTROLLERS 7 HOT PLUG - MOSFETS 8 PORT 0 EDGE CONN (U/S) 9 PORT 2 CONNECTOR (D/S)

10 PORT 4 CONNECTOR (D/S)

BB

11 PES24T3G2 - EEPROM,JTAG 12 PES24T3G2 - POWER

-------------------------------

A

TITLE

A

89EBPES24T3G2

SIZE

DRAWING NO.

B

SCH-00146

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

8

7

65 4

2008

3

AUTHOR

K Leung / T Tran Thu Jan 17 16:48:53 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 1 OF 12

1

REV.

1.0

7

6

4

38 5

2

1

SILKSCREEN TABLE

D

5%

R1

BOARD RESET

2 7

1

C4

1.0UF

TLC7733D

RESINN SENSE CONTROL CT

U3

VCC

RESET

RESETN

GND

28

IN

PERST_N

10K

1 2

3

SN74LVC1G125

1

U2

VCC

OE* A

Y

GND

PB_SW

NC NO

5

4

2 43

5%

R2

10K

C C

S1

3_3V 3_3V3_3V 3_3V 3_3V3_3V

5%

R4

10K

28

8 6 5 43

RED

C7

47UF

_____________________

|

RESET SELECT

|

--------------------ON BOARD CIRCUIT

| |

--------------------EDGE CONNECTOR

---------------------

1

DS1

IN

5%

R5

330

PERST_N

3

W4

| |

1-2

|| | ||

2-3

W4

M_PERSTN

2

| |

POWER INDICATOR PLACE NEAR TOP EDGE LABEL 'POWER'

3_3V

R8

91011

OUT

330

DS2

LABEL 'GND'

TP4

WHT

TP19

WHT5%WHT

TP20

TP21

WHT

GRN

RESET

D

12_0V

1 2 3

W1

1 2

W2

W3

25V

C1

C2

10UF

3

1 2 3

25V

C3

10UF

25V

C306

10UF

25V

B B

J4

POWER CONN

+12V

GND

+5V

1 2 3 4

12V_DS

TP1 TP2

C9

16V

C5

10UF

330UF

25V

C6

10UF

25V

C305

10UF

25V

+12.0V -> +3.3V

VR1

PTH08T240WAD

R3

10

11

1%

2

1 9

8

Vin

Track SYNC TURBOTRANS Inhibit

Vo_Adj

VO_SEN+

Vout

VO_SEN-

GND2 GND1

VDDIO

R6

6 5 7 4

3

0

C8

47UF

VDD

PLACE W5 NEAR U1 AND USE A ISLAND FOR "3_3VIO" PLACE R7 NEAR U1 PLACE R6 NEAR VR1

C308

NOISE-FREE ROUTING

16V

330UF

R7

0

W5

3_3VIO3_3V

TP3

RED

FOR "VDD"

1.21K

A A

SILKSCREEN TABLE ________________________________

|

12V POWER SELECT

|

--------------------------------

|

EDGE CONNECTOR

|

-------------------------------EXTERNAL INPUT

--------------------------------

| |

1-2 | |

2-3 2-3

W1

| | || | ||

W2

| |

1-21-2

| |

2-3

8

W3

| | | | ||

TITLE

89EBPES24T3G2

RESET, POWER CONNECTOR

DRAWING NO.

SIZE

B

SCH-00146

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

67

2008

45

3

AUTHOR

K Leung / T Tran Thu Jan 17 16:46:18 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 2 OF 12

1

REV.

1.0

7

6

4

38 5

2

1

SILKSCREEN TEXT: CORE

3_3V

D

C235

10UF

R185

C224

10UF

10K

R186

DNP

C C

VDDCORE, 1.0V

PVIN PVIN PVIN PVIN

ENABLE

AVIN

SS ROCP NC NC NC NC NC NC NC NC NC PGND PGND PGND PGND PGND

EN5336QI

21 22 23 24

41 28

29 37

27 25

C225

26 30 31 34 36 42

0.015UF

43 44 45 17 18 19 20

U15

DNP

8

VOUT

9

VOUT

10

VOUT

11

VOUT

12

VOUT

13

VOUT

14

VOUT

33

XOVAGND

32

XFB

35

POK

1

NC

2

NC

3

NC

4

NC

5

NC

6

NC

7

NC

15

NC

16

NC

38

EAIN

39

EAOUT

40

COMP

R216 R220 R217

NA

TP15

RED

DNP DNPDNP DNP

R258R259

10K

665

2.0K

DNP

C248

C230

10UF

NANA

C228

REG_1V0_CORE

C239

C262

C260

C258

10UF

1.0UF

YEL

1%

+1.0V_CORE

RED

TP24

26NH

L1

6.5A

C253

1.0UF

0.1UF

0

C257

C282

10UF

1.0UF

VCORE

R226

0

PLACE R226 NEAR U15

C231C222

NOISE-FREE ROUTING

FOR "VCORE"

3_3V

C295

10UF

C242

10UF

VDDPETA, 1.0V

21

PVIN

22

PVIN

23 24

41 28

29 37

27 25 26 30 31 34 36 42 43 44 45 17 18 19 20

PVIN PVIN

ENABLE

AVIN AGND

SS ROCP NC NC NC NC NC NC NC NC NC PGND PGND PGND PGND PGND

DNP

R189

10K

C243

R190

DNP

0.015UF

U17

EN5336QI

C240

VOUT

VOUT VOUT VOUT VOUT VOUT VOUT

XOV XFB

POK

EAIN

EAOUT

COMP

DNP DNP

TP17

RED

3_3V3_3V

8 9 10 11 12 13 14

33 32

C264

R260

10UF

10K

C266

10UF

35 1

NC

2

NC

3

NC

4

NC

5

NC

6

NC

7

NC

15

NC

16

NC

38 39 40

R230

NA NA

R231

NA

665

2.0K

DNP

REG_1V0_VDDTA

C297

C272

C268

C270

10UF

1.0UF

YEL TP26TP22

R238R225

1%

R236R223

1%

R234

C246

DNP

0

C249

SILKSCREEN TEXT: PETA

+1.0V_VDDTA

RED

26NH

L2

6.5A

C254

C299

R242R243

C283C285

C301

0

1.0UF

0.1UF 10UF

1.0UF

VDDTA

R240

PLACE R240 NEAR U17 NOISE-FREE ROUTING FOR "VDDTA"

D

SILKSCREEN TEXT: PEA

+1.0V_VDDA +2.5V_VDDHA

TP25

VDDA, 1.0V

U16

DNP

PVIN PVIN PVIN PVIN

ENABLE

AVIN

SS ROCP NC NC NC NC NC NC NC NC NC PGND PGND PGND PGND PGND

EN5336QI

C223

DNP DNP

VOUT VOUT VOUT VOUT VOUT VOUT VOUT

XOVAGND XFB

POK

EAIN

EAOUT

COMP

NC NC NC NC NC NC NC NC

NC

21 22 23

R187

10K

C227

R188

DNP

0.015UF

24 41 28

29 37

27 25 26 30 31 34 36 42 43 44 45 17 18 19 20

C238

C226

B B

10UF

A A

RED

TP16

3_3V

8 9 10 11 12 13 14

33 32

35 1

2 3 4 5 6 7 15 16

38 39 40

R218 R221

NA

R219

NA

C232

C250

C259

C261

C263

10UF

10K

YEL TP23 TP27

C229

R224

1%

R222

1%

NA

665

2.0K

DNP DNP

REG_1V0_VDDA

C252

1.0UF

R227

0

C233 C241

DNP

26NH

6.5A

C256

C237 C236

R229 R228

0

1.0UF

0.1UF

VDDA

PLACE R227 NEAR U16 PLACE R241 NEAR U18 NOISE-FREE ROUTING FOR "VDDA"

RED

C284

10UF

C294

1.0UF

3_3V3_3V

C296

10UF

C244

10UF

VDDHA, 2.5V

21 22 23

R197

24 41 28

10K

29 37

27 25

C245

R198

26 30 31 34 36

DNP

42

0.015UF

43 44 45 17 18 19 20

DNP

PVIN PVIN PVIN PVIN

ENABLE

AVIN AGND

SS ROCP NC NC NC NC NC NC NC NC NC PGND PGND PGND PGND PGND

U18

EN5336QI

DNP DNP

RED

TP18

8

VOUT

9

VOUT

10

VOUT

11

VOUT

12

VOUT

13

VOUT

14

VOUT

33

XOV

32

XFB

35

POK

1

NC

2

NC

3

NC

4

NC

5

NC

6

NC

7

NC

15

NC

16

NC

38

EAIN

39

EAOUT

40

COMP

R232 R235

NA

R233

NA

3_3V

R261

10K

2.0K

DNP

C265

10UF

4.64K

DNP

C267

C269

C271

10UF

YEL

NA C247

REG_2V5_VDDHA

C298

C273

10UF

1.0UF

R239

1%

R237

1%

C251

DNP

0

SILKSCREEN TEXT: PEHA

RED

TP29 TP28

26NH

L4L3

6.5A

C300

R241

C255

1.0UF

0.1UF

0

VDDHA

C302

10UF

1.0UF

NOISE-FREE ROUTING FOR "VDDHA"

TITLE

89EBPES24T3G2

POWER REGULATORS

DRAWING NO.

NOTE: ALL POWER NETS USE PLANE OR WIDE TRACE

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

8

67

2008

45

3

SIZE

B

SCH-00146

AUTHOR

K Leung / T Tran Thu Jan 17 16:46:23 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 3 OF 12

1

REV.

1.0

7

6

4

3_3V

38 5

2

1

0.1

C20

600OHM

C21

FB2

500MA

D

1.0UF

0.1UF

C31

C12

0.1UF

CONNSMA

P0_REFCLKP P0_REFCLKN

10

C15

C14

0.1UF

R17

33

R18

33

R213

33

R214

33

J9

54 1

R16

5%

ONBRD_REFCLKP ONBRD_REFCLKN

R181

R13

R183

R184

R182

R14

49.9

BRD_T_CLKN

C18

C19

1.0UF

0.1UF

R21

R20

49.9

0R

11

PLACE NEAR U4

PLACE NEAR U5

1

1 3 1 3

W6

2

3

SM0805

1

2

3

SM0805

W7

96

5

IN

10

56

IN

11

IN

9

10

811

IN

8

9

10

IN

REFIN_CLKP REFIN_CLKN

P2_PWRGDN

P4_PWRGDN

SMA_ENABLE

M_SSMBCLK M_SSMBDATA

3_3V

R22

10K

R23

DNP

R26

R24

10K

DNP

R27

R25

10K

DNP

R30

R28

10K

DNP

R29

10K

2

VDD

19

VDD VDD

4

SRC_IN

5

SRC_IN#

6

OE0#

14

OE1#

15

OE2#

7

OE3#

43

OE4#

35

OE5#

36

OE6#

44

OE7#

27

DIFF_STOP

26

PD

28

HIGH_BW#

40

OE_INV

22

BYPASS#/PLL

23

SCLK

24

SDATA

1

SRC_DIV#

3

GND

10

GND

18

GND

8

IN

8

IN

3_3V

R36

0

VDD VDD VDD VDD

VDDA

nQ0

nQ1

nQ2

nQ3

4 14 24 29

28 21 5

Q0

6 7

Q1

8 10

Q2

11 12

Q3

13 15

NC

16

NC

17

NC

18

NC

0%

C13

10UF

TP14 YEL

SR_BRD_CLKP SR_BRD_CLKN SR_BRD_T_CLKP SR_BRD_T_CLKN

2

475

1%

R19

31

30 22

23 20 26

25 27

19 32 33

2

1 2

3

9

C234

22PF

XTAL_IN

XTAL_OUT

REF_IN

REF_SEL

FSEL0 FSEL1

OE_REFOUT MR_nOE IREF SSM BYPASS

GND GND GND PGND

C10

C11

1.0UF

0.1UF

ICS841484

REF_OUT

U4

PLACE R17/R18 NEAR U4

C17

Y1

crystal

22PF

1

C C

25.000MHZ 20PPM

TP13

3_3V

DNP DNP DNP

11

IN

11

IN

B B

6

IN

R11 R12 R10

R52

10K

R15

10K

R53

10K

YEL

REF_SEL FSEL0

FSEL1

REFOUT_EN CLK_GEN_MR_NOE

SS_MODE PLL_BYPASS

R9

10K

R255

1%

U5

ICS9DB803

OE_INV=1

C22

10UF

VDD VDD

VDDA

DIF_0

DIF_0#

DIF_1

DIF_1#

DIF_2

DIF_2#

DIF_3

DIF_3#

DIF_4

DIF_4#

DIF_5

DIF_5#

DIF_6

DIF_6#

DIF_7

DIF_7#

LOCK IREF

GNDA

GND GND

C24

C23

0.1UF

11 31 4839

8 9

12 13

16 17

20 21

30 29

34 33

38 37

42 41

45 46

47 32 25

C311

C310

C309

0.1UF

SR_M_CLKP SR_M_CLKN

SR_P2_CLKP SR_P2_CLKN

SR_P4_CLKP SR_P4_CLKN

SR_T_CLKP SR_T_CLKN

TP5

YEL

475

R41

33 33

1%

2.2

33 33

R256

5%

C313

C312

1.0UF

0.1UF

R33 R34

R31 R32

R37 R38

R39 R40

R46

R47

R50

49.9

REF_TESTOUT_CLKP

REF_TESTOUT_CLKN

1%

R43

R42

49.9

M_REFCLK1P M_REFCLK1N

P2_REFCLKP P2_REFCLKN

P4_REFCLKP P4_REFCLKN

R44

R51

R45

49.9

J6

CONNSMA

54

OUT OUT

11 11

9 9

10 10

1

32

J7

CONNSMA

54 1

32

A A

NOTE: CLOCK GENERATOR DEFAULT WORKING MODE: CRYSTAL INPUT

NO SPREAD

100MHZ OUTPUT

8

67

J10

CONNSMA

54

BRD_T_CLKP

1

32

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

2008

45

3

TITLE

89EBPES24T3G2

CLOCKS

DRAWING NO.

SIZE

B

SCH-00146

AUTHOR

K Leung / T Tran Thu Jan 17 16:46:36 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 4 OF 12

REV.

1.0

1

D

7

6

4

38 5

2

1

3_3V

C25

3_3V

5%

R54

3_3V

R56

NA

R59

NA

R62

D

11 5

511

11 5

TP7

5

11

0.1UF 10K

OUT

IN BI

5

IN

5

9

IN

6

IN

9

OUT

9

OUT

6

OUT

M_IOINTN0 M_SCL M_SDA

P2_APN P2_PDN P2_PFN P2_MRLN P2_AIN P2_PIN P2_PEP P2_ILOCKP

22 23

10 11

1

4 5 6 7 8 9

24

INT# SCL SDA

I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 I/O0.6 I/O0.7

U6

PCA9555

I/O1.0 I/O1.1 I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7

VSSVDD

DNP

21

A0

2

A1

3

A2

P4_APN

13

P4_PDN

14

P4_PFN

15 16

P4_MRLN

17

P4_AIN

18

P4_PIN

19

P4_PEP P4_ILOCKP

20

R69

0

R70

0

R71

0

5

IN

5

10

IN

55

6

IN

5

11

ININ

10

OUT

10

OUT

6

OUT

TP11

12

IO EXPANDER 0

C C

3_3V

5%

R251

U19

11 5

OUT

511

IN

11 5

BI

M_IOINTN0 M_SCL M_SDA

3_3V

10K

22 23

C26

B B

0.1UF

10 11

24

PCA9555

1

INT# SCL SDA

4

I/O0.0

5

I/O0.1

6

I/O0.2

7

I/O0.3

8

I/O0.4

9

I/O0.5 I/O0.6 I/O0.7

I/O1.0 I/O1.1 I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7

VSSVDD

A0 A1 A2

21 2 3

13 14 15 16 17 18 19

20

12

3_3V

NA

5%

R168

R169

DNP

2.7K

DNP

P2_PWRGDN P4_PWRGDN

NA

R170

DNP

0 0

R171 R172 R173

IN IN

9

46

10

3_3V

330 330 330

3_3V

330 330 330

S3

PB_SW

NC NO

1

PORT 4 ATTN

R63

5%

R66

5%

R67

5%

R68

5%

R76

5%

R79 DS27

5%

RED RED GRN

3_3V

R78

10K

2 43

5%

DS6 DS7 DS8

DS9 DS10

5%

R80

10K

P4_APN

P2_MRLN P2_PFN P2_PDN

P4_MRLN P4_PFN P4_PDN

OUT

11 5

IN

65

IN

95

IN

11 5

IN

65

IN

10

5

3_3VAUX

U9

IN

P4_WAKE_N

3_3VAUX

10K 10K

R75 R77

1

OE*

2

A

3

GND

SN74LVC1G125

VCC

5

4

Y

R81

0

0%

3_3V

P0_WAKE_N

OUT

8

IN

5

C304

D

IO EXPANDER 2

3_3V

C16

INT# SCL SDA

I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 I/O0.6 I/O0.7

U8

PCA9555

I/O1.0 I/O1.1 I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7

VSSVDD

21

A0

2

A1

3

A2

13 14 15 16 17 18 19

20

12

0.1UF

511

IN

11 5

BI

10

8

9

OUT OUT OUT

A A

M_SCL M_SDA

P0_LINKUPN P2_LINKUPN P4_LINKUPN

22 23

10 11

1

4 5 6 7 8 9

24

3_3V

5%

NA

R58

R64

R61

DNP

2.7K

P0_ACTIVEN P2_ACTIVEN P4_ACTIVEN

NA

DNP

0 0

OUT OUT OUT

R72 R73 R74

SILKSCREEN LABELS:

8

9

10

PB_SW

NC NO

1

PORT 2 ATTN

2 43

P2_APN

OUT

5

9

IN

P2_WAKE_N

TITLE

89EBPES24T3G2

U11

1

OE*

2

A

3

GND

SN74LVC1G125

VCC

5

4

Y

S5

0.1UF

IO EXP, WAKE, ATTN BUTTONS

IO EXPANDER 4

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

8

67

2008

45

3

K Leung / T Tran Thu Jan 17 16:46:40 2008

SIZE

B

SCH-00146

AUTHOR

DRAWING NO.

FAB P/N

18-657-000

CHECKED BY

REV.

1.0

D Huang

SHEET 5 OF 12

2

1

7

6

4

38 5

2

1

D

3_3VAUX

3_3V

12V_DS

3_3VAUX3_3VAUX3_3VAUX3_3VAUX

3_3V

12V_DS

R101

R100

R99

R92

R88

DNP

R89

10K

R93

R95

000

R96

10K

R97

10K

11 26

33 20

35

28 38

45 42 44 43

31 36

41 40 39

37 47

48

18 19 30

17 46

2

9 4

6 1

7

MIC2591B

VSTBYA VSTBYB

IREF

RFILTER

CFILTERA CFILTERB

FORCE_ONA_N FORCE_ONB_N GPI_A0 GPI_B0

AUXENA AUXENB ONA ONB

PWRGDA_N PWRGDB_N FAULTA_N FAULTB_N

A0 A1 A2

INT_N

SCL SDA

NC0 NC1 NC2 NC3

GND0 GND1

U12

VAUXA

12VINA

12VSENSEA

12VGATEA

12VOUTA

3VINA

3VSENSEA

3VGATEA

3VOUTA

VAUXB

12VINB

12VSENSEB

12VGATEB

12VOUTB

3VINB

3VSENSEB

3VGATEB

3VOUTB

15

5 8 3 10

12 13 14 16

22

32 29 34 27

25 24 23 21

C35

C34

C36

0.1UF

0.022UF

P2_VAUX

P2_12VSENSE P2_12VGATE P2_12VOUT

P2_3VSENSE P2_3VGATE P2_3VOUT

SM_SW8

1 2 3 4 5 6 7

S1A S2A S3A S4A S5A S6A S7A S8A

S6

OUT

BI BI BI

S1B S2B S3B S4B S5B S6B S7B S8B

16 15 14 13 12 11 10 98

7

7 7

7

7 7

7

3_3V

10K 10K 10K 10K

P2_F_ON P4_F_ON

P2_PWRGDN P4_PWRGDN B0 B1 B2 CLK_GEN_MR_NOE

10

R49 R55 R57 R60

R104

R105

R106

R111

R109

R113

R114

10K

R110

R112

0

10K

R115

10K

11 26

33 20

35

28 38

45 42 44 43

31 36

41 40 39

37 47

48

18 19 30

17 46

2

9 4

6

7

1

MIC2591B

VSTBYA VSTBYB

IREF

RFILTER

CFILTERA CFILTERB

FORCE_ONA_N FORCE_ONB_N GPI_A0 GPI_B0

AUXENA AUXENB ONA ONB

PWRGDA_N PWRGDB_N FAULTA_N FAULTB_N

A0 A1 A2

INT_N

SCL SDA

NC0 NC1 NC2 NC3

GND0 GND1

U13

VAUXA

12VINA

12VSENSEA

12VGATEA

12VOUTA

3VINA

3VSENSEA

3VGATEA

3VOUTA

VAUXB

12VINB

12VSENSEB

12VGATEB

12VOUTB

3VINB

3VSENSEB

3VGATEB

3VOUTB

15

5 8 3 10

12 13 14 16

22

32 29 34 27

25 24 23 21

P4_VAUX

P4_12VSENSE P4_12VGATE P4_12VOUT

P4_3VSENSE P4_3VGATE P4_3VOUT

C43

C42

C41

0.1UF

0.022UF

OUT

BI BI BI

7

7 7

7

C37

C38

C39

C40

100K

DNP

R107

R108

0.1UF

IN

OUT OUT

OUT

P4_F_ON

P4_PEP

P4_PWRGDN P4_PFN

P4_INTN

1%

R102

1%

R103

6

5

645 5

6

0

0.01UF

10K

110K

23.2K

SILKSCREEN LABEL:

SWITCH S6

OUT OUT OUT OUT OUT OUT OUT OUT

6 6

12 12 12 4

POS DESCRIPTION

----------------------1 PORT 2 - FORCE ON

946

5

2 PORT 4 - FORCE ON

5

10

46

3 PORT 2 - PWR GOOD 4 PORT 4 - PWR GOOD 8 CLOCK GEN ENABLE

-----------------------

R86

C28

C27

0.1UF

IN

P2_F_ON

6

R87

100K

C C

IN

OUT OUT

OUT

P2_PEP

P2_PWRGDN P2_PFN

P2_INTN

1%

R83

R82

110K

23.2K

1%

C30

C29

0.01UF

5

6459

5

6

B B

A A

3_3V

D

330

3_3V

R84 DS3

5%

RED

P2_INTN

IN

6

TITLE

89EBPES24T3G2

HOT PLUG CONTROLLERS

330

R85

5%

RED

8

DS4

P4_INTN

IN

6

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

67

2008

45

3

K Leung / T Tran Thu Jan 17 16:46:42 2008

SIZE

SCH-00146

B

AUTHOR

DRAWING NO.

FAB P/N

18-657-000

CHECKED BY

REV.

1.0

D Huang

SHEET 6 OF 12

2

1

7

6

4

38 5

2

1

D

3_3VAUX

6

IN

P4_VAUX

12V_DS

C C

6

BI

6

BI

6

BI

P4_12VSENSE P4_12VGATE P4_12VOUT

2%

R116

0.02

C44

0.022UF

15

R119 5%

1 2 3 4

P4_PCIE_3_3AUX

W8

Q2

S S S G

PMOSFET

5

D

6

D

7

D

8

D

W9

P4_12V

6

IN

6

BI

6

BI

6

BI

P2_VAUX

P2_12VSENSE P2_12VGATE P2_12VOUT

C45

6800PF

3_3VAUX

12V_DS

2%

R124

0.02

C48

0.022UF

C49

15

6800PF

R127

5%

1 2 3 4

P2_PCIE_3_3AUX

W14

Q6

S S S G

PMOSFET

5

D

6

D

7

D

8

D

P2_12V

W15

D

W10

P4_3_3V

3_3V3_3V

2%

R125

0.012

6

BI

6

BI

6

BI

P2_3VSENSE

P2_3VGATE P2_3VOUT

15

R126

5%

Q5

NMOSFET

1

S

2

S

3

S

4

G

5

D

6

D

7

D

8

D

B B

2%

R117

0.012

6

BI

6

BI

6

BI

P4_3VSENSE P4_3VGATE P4_3VOUT

15

R118

5%

Q1

NMOSFET

1

S

2

S

3

S

4

G

5

D

6

D

7

D

8

D

P2_3_3V

W16

A A

NOTE: USE PLANE OR WIDE TRACE FOR ALL POWER NETS

TITLE

89EBPES24T3G2

HOT PLUG - MOSFETS

DRAWING NO.

SIZE

SCH-00146

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

K Leung / T Tran Thu Jan 17 16:46:47 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 7 OF 12

1

REV.

1.0

7

6

4

38 5

2

1

D

3_3V

R158

1K

R159

J8

OUT BI

1K

4 3 2 1

M_SSMBCLK M_SSMBDATA

DNP DNP

11 11

5

IN

OUT OUT

LABEL PINS:

4 SMBDATA 3 GND 2 SMBCLK

1NC

9

10

11

4

9

10

114

C C

B B

3_3VAUX

R160 R161

P0_WAKE_N

P0_PERP7 P0_PERN7

P0_PERP6 P0_PERN6

P0_PERP5 P0_PERN5

P0_PERP4 P0_PERN4

P0_PERP3 P0_PERN3

P0_PERP2 P0_PERN2

P0_PERP1 P0_PERN1

P0_PERP0 P0_PERN0

P0_3_3V

C62

10UF

DNP

C63

10UF

R162

R244

12_0V

25V

PCIE_ADD_ON_PRESENT_N

P1

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

PCIe x8

+12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG_TRSTN

3.3VAUX WAKE#

RSVD GND PETP0 PETN0 GND PRSTN2# GND PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSTN2# GND PETP4 PETN4 GND GND PETP5 PETN5 GND GND PETP6 PETN6 GND GND PETP7 PETN7 GND PRSTN2# GND

EDGE

PRSTN1#

+12V +12V

GND JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

+3.3V +3.3V

PERST#

GND

REFCLK+ REFCLK-

GND

PERP0 PERN0

GND

RSVD

GND

PERP1 PERN1

GND

PERP2 PERN2

GND

PERP3 PERN3

GND

RSVD RSVD

GND

PERP4 PERN4

GND

PERP5 PERN5

GND

PERP6 PERN6

GND

PERP7 PERN7

GND

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

12_0V

P0_3_3V

25V

C64

10UF

PERST_N

P0_REFCLKP P0_REFCLKN

P0_PETP7 P0_PETN7

P0_PETP6 P0_PETN6

P0_PETP5 P0_PETN5

P0_PETP4 P0_PETN4

P0_PETP3 P0_PETN3

P0_PETP2 P0_PETN2

P0_PETP1 P0_PETN1

P0_PETP0 P0_PETN0

C65

10UF

OUT

OUT OUT

IN IN

2

4 4

11 11

D

A A

3_3V

P0 LINK P0 ACT

330 330

R163 5% R164 5%

GRN GRN

8

DS23 DS24

P0_LINKUPN P0_ACTIVEN

67

IN IN

5

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

2008

45

3

TITLE

89EBPES24T3G2

PORT 0 UPSTREAM EDGE CONN.

DRAWING NO.

SIZE

B

SCH-00146

AUTHOR

K Leung / T Tran Thu Jan 17 16:46:50 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 8 OF 12

1

REV.

1.0

7

6

4

38 5

2

1

P2_PCIE_3_3AUX

P2_12V P2_3_3V

W19

DS17 DS18 DS19 DS20 DS21

DS22

5%

R157

330

P2_PERST_N

P2_LINKUPN P2_ACTIVEN P2_AIN P2_PIN P2_PWRGDN

OUT

IN IN IN IN

IN

9

5

5 5

5

546

GRN

D

10

48

11

411

10

8

BI

C C

3_3V

R148

5.1K

B B

5

OUT

IN

5%

M_SSMBCLK M_SSMBDATA

5

OUT

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

DNP DNP

P2_WAKE_N

P2_PETP0 P2_PETN0

P2_PETP1 P2_PETN1

P2_PETP2 P2_PETN2

P2_PETP3 P2_PETN3

P2_PETP4 P2_PETN4

P2_PETP5 P2_PETN5

P2_PETP6 P2_PETN6

P2_PETP7 P2_PETN7

P2_PDN

R149 R150

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

PCIe x8

+12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG_TRSTN

3.3VAUX WAKE#

RSVD GND PETP0 PETN0 GND PRSTN2# GND PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSTN2# GND PETP4 PETN4 GND GND PETP5 PETN5 GND GND PETP6 PETN6 GND GND PETP7 PETN7 GND PRSTN2# GND

VERT OPEN

SOCKET

PRSTN1#

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

REFCLK+ REFCLK-

J3

+12V +12V

GND

+3.3V +3.3V

PERST#

GND

GND PERP0 PERN0

GND

RSVD

GND PERP1 PERN1

GND

GND PERP2 PERN2

GND

GND PERP3 PERN3

GND

RSVD RSVD

GND PERP4 PERN4

GND

GND PERP5 PERN5

GND

GND PERP6 PERN6

GND

GND PERP7 PERN7

GND

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

R151

0

0%

P2_PERST_N

P2_REFCLKP P2_REFCLKN

P2_PERP0 P2_PERN0

P2_PERP1 P2_PERN1

P2_PERP2 P2_PERN2

P2_PERP3 P2_PERN3

P2_PERP4 P2_PERN4

P2_PERP5 P2_PERN5

P2_PERP6 P2_PERN6

P2_PERP7 P2_PERN7

IN

IN IN

OUT OUT

25V

C59

C58

10UF

9

4 4

11 11

IN IN

M_P2_PERST_N M_PERSTN

11 11

P2 LINK P2 ACT

11

10

3_3V

11

2

330 330

P2 ATTN P2 PWR P2 PGOOD

330 330

R152

5%

R153

5%

R154

5%

R155

5%

R156

5%

C60

10UF

GRN GRN YEL330 GRN GRN

C61

10UF

D

A A

TITLE

89EBPES24T3G2

PORT 2 CONNECTOR

DRAWING NO.

SIZE

SCH-00146

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

K Leung / T Tran Thu Jan 17 16:46:55 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 9 OF 12

1

REV.

1.0

7

6

4

38 5

2

1

P4_PCIE_3_3AUX

P4_12V

P4_3_3V

P4_3_3VP4_12V

W18

DS11 DS12

DS14 DS15

DS16

5%

R147

330

P4_PERST_N

P4_LINKUPN P4_ACTIVEN P4_AIN P4_PIN P4_PWRGDN

OUT

IN IN IN IN

IN

10

5

5 5

5

645

GRN

D

11 9 4 8

41198

BI

C C

3_3V

R138

5.1K

B B

5

OUT

IN

5%

M_SSMBCLK M_SSMBDATA

5

OUT

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

DNP DNP

P4_WAKE_N

P4_PETP0 P4_PETN0

P4_PETP1 P4_PETN1

P4_PETP2 P4_PETN2

P4_PETP3 P4_PETN3

P4_PETP4 P4_PETN4

P4_PETP5 P4_PETN5

P4_PETP6 P4_PETN6

P4_PETP7 P4_PETN7

P4_PDN

R139 R140

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

PCIe x8

+12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG_TRSTN

3.3VAUX WAKE#

RSVD GND PETP0 PETN0 GND PRSTN2# GND PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSTN2# GND PETP4 PETN4 GND GND PETP5 PETN5 GND GND PETP6 PETN6 GND GND PETP7 PETN7 GND PRSTN2# GND

VERT OPEN

SOCKET

PRSTN1#

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

REFCLK+ REFCLK-

J1

+12V +12V

GND

+3.3V +3.3V

PERST#

GND

GND PERP0 PERN0

GND

RSVD

GND PERP1 PERN1

GND

GND PERP2 PERN2

GND

GND PERP3 PERN3

GND

RSVD RSVD

GND PERP4 PERN4

GND

GND PERP5 PERN5

GND

GND PERP6 PERN6

GND

GND PERP7 PERN7

GND

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

R141

0

0%

P4_PERST_N

P4_REFCLKP P4_REFCLKN

P4_PERP0 P4_PERN0

P4_PERP1 P4_PERN1

P4_PERP2 P4_PERN2

P4_PERP3 P4_PERN3

P4_PERP4 P4_PERN4

P4_PERP5 P4_PERN5

P4_PERP6 P4_PERN6

P4_PERP7 P4_PERN7

IN

IN IN

OUT OUT

10

4 4

11 11

P4 LINK P4 ACT P4 ATTN P4 PWR P4 PGOOD

11 2

9

3_3V

11

25V

C54

10UF

IN IN

330 330 330 330

330

25V

C55

10UF

C56

10UF

M_P4_PERST_N M_PERSTN

R142

5%

R143

5%

R144 DS13

5%

R145

5% R146

5%

C57

10UF

GRN GRN YEL GRN GRN

D

A A

TITLE

89EBPES24T3G2

PORT 4 CONNECTOR

DRAWING NO.

SIZE

SCH-00146

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

8

67

2008

45

3

AUTHOR

K Leung / T Tran Thu Jan 17 16:46:58 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 10 OF 12

1

REV.

1.0

1

SILKSCREEN LABEL LEDS:

3_3V

GPIO8 GPIO9 GPIO10

11

IN

11

IN

11

OUT

11

IN

11

IN

9

OUT

10

OUT

5

IN

C7 A8 D7 B8 C8

A12 B12 C12 D12 D13 C13 B13

V6 U6 K1 K2 K18 K17

R6 K15

2

WHT TP6

WHT TP9

WHT TP8

DS25 R178

DS26

R175

R176

10K

GRN GRN

M_TCK M_TDI M_TDO M_TMS JTAG_RST_N

M_P2_PERST_N M_P4_PERST_N M_IOINTN0 M_GPEN

R245

R246

R247

R248

R249

R250

3.01K

330 330 330GRN

TP12 YEL

5% R35DS5 5% R179 5%

NOTE: PLACE REF RES

NEAR U1

4

10

4

10

11 5

5

11

948

98

11 11

11 11 11

9

10

38 5

4

IN

4

IN

OUT

BI

IN

BI

IN IN

IN IN IN

2

IN

M_REFCLK1N M_REFCLK1P

M_SCL M_SDA

M_SSMBCLK M_SSMBDATA

M_CCLKDS M_CCLKUS

M_SWMODE0 M_SWMODE1 M_SWMODE2

M_PERSTN

C10

D10 B11 C11

D11

89HPES24T3G2 (1 of 3)

U2

PEREFCLKN1

V2

PEREFCLKP1

D8

MSMBCLK

A9

MSMBDAT

B9

SSMBCLK

C9

SSMBDAT

CCLKDS

D9

CCLKUS

SWMODE0 SWMODE1 SWMODE2

PERSTN

U1

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

GPIO0 GPIO1 GPIO2 GPIO7 GPIO8 GPIO9

GPIO10

REFRES0 REFRES1 REFRES2 REFRES3 REFRES4 REFRES5

NC0 NC1

7

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

P0_PERP0 P0_PERN0 P0_PERP1 P0_PERN1 P0_PERP2 P0_PERN2 P0_PERP3 P0_PERN3 P0_PERP4 P0_PERN4 P0_PERP5 P0_PERN5 P0_PERP6 P0_PERN6 P0_PERP7 P0_PERN7

P2_PERP0 P2_PERN0 P2_PERP1 P2_PERN1 P2_PERP2 P2_PERN2 P2_PERP3 P2_PERN3 P2_PERP4 P2_PERN4 P2_PERP5 P2_PERN5 P2_PERP6 P2_PERN6 P2_PERP7 P2_PERN7

P4_PERP0 P4_PERN0 P4_PERP1 P4_PERN1 P4_PERP2 P4_PERN2 P4_PERP3 P4_PERN3 P4_PERP4 P4_PERN4 P4_PERP5 P4_PERN5 P4_PERP6 P4_PERN6 P4_PERP7 P4_PERN7

10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8

9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9

D

C C

B B

R14 P14 R13 P13 R11 P11 R10 P10

B15 B14 C15 C14 E15 E14 F15 F14 H15 H14 J15 J14 L15 L14 M15 M14

89HPES24T3G2 (2 of 3)

PE0RP00 PE0RN00 PE0RP01 PE0RN01 PE0RP02 PE0RN02 PE0RP03 PE0RN03

R8

PE0RP04

P8

PE0RN04

R7

PE0RP05

P7

PE0RN05

R5

PE0RP06

P5

PE0RN06

R4

PE0RP07

P4

PE0RN07

M4

PE2RP00

M5

PE2RN00

L4

PE2RP01

L5

PE2RN01

J4

PE2RP02

J5

PE2RN02

H4

PE2RP03

H5

PE2RN03

F4

PE2RP04

F5

PE2RN04

E4

PE2RP05

E5

PE2RN05

C4

PE2RP06

C5

PE2RN06

B4

PE2RP07

B5

PE2RN07

PE4RP00 PE4RN00 PE4RP01 PE4RN01 PE4RP02 PE4RN02 PE4RP03 PE4RN03 PE4RP04 PE4RN04 PE4RP05 PE4RN05 PE4RP06 PE4RN06 PE4RP07 PE4RN07

PE0TP00 PE0TN00 PE0TP01 PE0TN01 PE0TP02 PE0TN02 PE0TP03 PE0TN03 PE0TP04 PE0TN04 PE0TP05 PE0TN05 PE0TP06 PE0TN06 PE0TP07 PE0TN07

PE2TP00 PE2TN00 PE2TP01 PE2TN01 PE2TP02 PE2TN02 PE2TP03 PE2TN03

PE2TP004

PE2TN04 PE2TP05 PE2TN05 PE2TP06 PE2TN06 PE2TP07 PE2TN07

PE4TP00 PE4TN00 PE4TP01 PE4TN01 PE4TP02 PE4TN02 PE4TP03 PE4TN03 PE4TP04 PE4TN04 PE4TP05 PE4TN05 PE4TP06 PE4TN06 PE4TP07 PE4TN07

V14

AC_P0_PETP0 AC_P0_PETN0

U14 V13

AC_P0_PETP1

U13

AC_P0_PETN1 AC_P0_PETP2

V11

AC_P0_PETN2

U11

AC_P0_PETP3

V10

AC_P0_PETN3

U10

AC_P0_PETP4

V8 U8

AC_P0_PETN4 AC_P0_PETP5

V7

AC_P0_PETN5

U7

AC_P0_PETP6

V5

AC_P0_PETN6

U5

AC_P0_PETP7

V4

AC_P0_PETN7

U4

AC_P2_PETP0

M1

AC_P2_PETN0

M2

AC_P2_PETP1

L1

AC_P2_PETN1

L2

AC_P2_PETP2

J1

AC_P2_PETN2

J2

AC_P2_PETP3

H1 H2

AC_P2_PETN3 AC_P2_PETP4

F1 F2

AC_P2_PETN4

E1

AC_P2_PETP5 AC_P2_PETN5

E2

AC_P2_PETP6

C1

AC_P2_PETN6

C2

AC_P2_PETP7

B1

AC_P2_PETN7

B2

B18

AC_P4_PETP0 AC_P4_PETN0

B17 C18

AC_P4_PETP1 AC_P4_PETN1

C17 E18

AC_P4_PETP2

E17

AC_P4_PETN2

F18

AC_P4_PETP3

F17

AC_P4_PETN3 AC_P4_PETP4

H18

AC_P4_PETN4

H17

AC_P4_PETP5

J18

AC_P4_PETN5

J17

AC_P4_PETP6

L18

AC_P4_PETN6

L17

AC_P4_PETP7

M18

AC_P4_PETN7

M17

6

0.1UF

0.1UF C190

0.1UF C191

0.1UF C192

0.1UF C193

0.1UF C286

0.1UF C287

0.1UF C288

0.1UF C289

0.1UF C194

0.1UF C195

0.1UF C196

0.1UF C197

0.1UF C290

0.1UF C291

0.1UF C292

0.1UF C293

0.1UF C198

0.1UF C199

0.1UF C200

0.1UF C201

0.1UF C202

0.1UF C203

0.1UF C204

0.1UF C205

C206 C207 C208 C209 C274 C275 C276 C277

C210 C211 C212 C213 C278 C279 C280 C281

C214 C215 C216 C217 C218 C219 C220 C221

P0_PETP0 P0_PETN0 P0_PETP1 P0_PETN1 P0_PETP2 P0_PETN2 P0_PETP3

P0_PETN3 P0_PETP4 P0_PETN4 P0_PETP5 P0_PETN5 P0_PETP6 P0_PETN6 P0_PETP7 P0_PETN7

P2_PETP0

P2_PETN0

P2_PETP1

P2_PETN1

P2_PETP2

P2_PETN2

P2_PETP3

P2_PETN3 P2_PETP4 P2_PETN4 P2_PETP5 P2_PETN5 P2_PETP6 P2_PETN6 P2_PETP7 P2_PETN7

P4_PETP0

P4_PETN0

P4_PETP1

P4_PETN1

P4_PETP2

P4_PETN2

P4_PETP3

P4_PETN3

P4_PETP4

P4_PETN4

P4_PETP5

P4_PETN5

P4_PETP6

P4_PETN6

P4_PETP7

P4_PETN7

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8

9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9

10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

3_3V

D

U1

NOTE:

PLACE ALL AC COUPLING CAPACITORS NEAR

3_3V 3_3V

C307

5%

R194

1K

R195

1K

6 5

3 2 1

U14

24LC512

VCC

SCL SDA

A2 A1 A0

WP

GND

52-298-000

0.1UF

A A

IN

IN IN IN

M_SCL M_SDA

M_MSMBADDR2 M_MSMBADDR1 M_MSMBADDR0

511

11 5

11 11 11

BI

5%

R196

2.7K

8

7

W20

4

8

EDGE CONNECTOR OR DOWNSTREAM SLOTS

3_3V

R205

1K

R206

1K

R207

1K

R208

1K

J5

JTAG HEADER

11 11 11 11 11

OUT

IN OUT OUT

JTAG_RST_N M_TDI M_TDO M_TMS M_TCK

67

33

R210

5%

R209

5%

1

1 3 5 7

9

1K

10

2 4 6 8

R215

2 43 65 87 10

10K 10K 10K 10K 10K 10K 10K 10K

S7

1 2 3 4 5 6 7

NOTE: BOTH BIT7 AND BIT8 DEFAULT ARE "ON".

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

R65 R174 R202 R211 R212 R191 R192 R193

SM_SW8

S1B

S1A

S2B

S2A

S3B

S3A

S4B

S4A

S5B

S5A

S6B

S6A

S7B

S7A

S8B

S8A

16 15 14 13 12 11 10

98

M_SWMODE0 M_SWMODE1 M_SWMODE2 P2_MRLN

P4_MRLN REF_SEL FSEL0

OUT OUT OUT OUT

OUT OUT OUT

11 11 11 5

5 4 4

TITLE

SIZE

AUTHOR

K Leung / T Tran

2008

45

3

Thu Jan 17 16:47:02 2008

3_3V

S1A S2A S3A S4A S5A S6A S7A S8A

S1B S2B S3B S4B S5B S6B S7B S8B

R257 R165 R166 R167 R203 R204

16 15 14 13 12 11 10 98

M_CCLKDS M_CCLKUS M_MSMBADDR2 M_MSMBADDR1 M_MSMBADDR0

SMA_ENABLE

OUT OUT OUT OUT OUT

OUT

11 11 11 11 11

4

10K 10K 10K 10K 10K 10K

S8

SM_SW8

1 2 3 4 5 6 7

89EBPES24T3G2

89HPES24T3G2 - EEPROM,JTAG

DRAWING NO.

B

SCH-00146

FAB P/N

18-657-000

CHECKED BY

D Huang

SHEET 11 OF 12

2

1

REV.

1.0

7

6

4

38 5

2

1

+1.0V_CORE

VDDCORE

C188

C187

47UF

C189

1.0UF

C128

C133

C138

C143

C148

C153

0.1UF

C158

C161

0.1UF

C164

C167

0.1UF

C170

C173

0.1UF

C175

C177

0.1UF

C178

C179

0.1UF

C180

C181

0.1UF

C182

C183

0.1UF

C184

C185

0.1UF

C186

0.1UF

C71

C76

C81

C86

C91

C96

C101

C105

C109

C113

C118

0.1UF

C123

0.1UF

C66

D

6

IN

B1

3_3VIO

0.1UF

+2.5V_VDDHA+1.0V_VDDA

+1.0V_VDDTA

0.1UF

+1.0V_VDDTA

VDDPETA

N10

M7

M6

M10

L7

L6

L13

J6

A13

VDDCORE1 VDDCORE2 VDDCORE3 VDDCORE4 VDDCORE5 VDDCORE6 VDDCORE7 VDDCORE8 VDDCORE9 VDDCORE10 VDDCORE11 VDDCORE12 VDDCORE13 VDDCORE14 VDDCORE15 VDDCORE16 VDDCORE17 VDDCORE18 VDDCORE19 VDDCORE20 VDDCORE21 VDDCORE22 VDDCORE23 VDDCORE24 VDDCORE25 VDDCORE26 VDDCORE27 VDDCORE28 VDDCORE29 VDDCORE30 VDDCORE31 VDDCORE32 VDDCORE33 VDDCORE34 VDDCORE35 VDDCORE36 VDDCORE37 VDDCORE38 VDDCORE39 VDDCORE40 VDDCORE41 VDDCORE42 VDDCORE43 VDDCORE44 VDDCORE45 VDDCORE46 VDDCORE47 VDDCORE48

VSS101

A10

VDDIO1

VSS100

VSS99

VDDIO3

VDDIO2

VSS98

VSS97

VDDIO5

VDDIO4

VSS96

VSS95

+1.0V_CORE

D14 F10

H9 P12 R16

C C

B B

A A

R17

R2

R3

R9 D15

D4

D5 E10 E11 E12 E13

E6

E7

E8

F8 G10 G14 G15

G4

G5

G8

G9 H10

H8 J10

J8 K10 K14

K4

K5

K8 N15

N4

N5 P15 P16 P17

P2

P3

P6

P9 R12 R15

VDDIO8

VDDIO7

VDDIO6

VSS94

VSS93

VSS92

D6

VDDIO9

VDDIO10

VSS91

VSS90

VDDPEA1

VSS89

VSS88

VDDPEA4

VDDPEA3

VDDPEA2

VSS87

VSS86

VSS85

VDDPEA6

VDDPEA5

VSS84

VSS83

H6

G12

B6

B10

A6

A2

A18

A17

A14

G6

G13

VDDPEA9

VDDPEA8

VDDPEA7

VSS82

VDDPEA11

VDDPEA10

89HPES24T3G2 (3 of 3)

VSS81

VSS80

VSS79

VSS78

N8

N11

M8

M11

L8

L11

H7

H13

H12

G7

VDDPEA14

VDDPEA13

VDDPEA12

U1

VSS77

VSS76

VSS75

J12

VDDPEHA1

VSS74

VSS73

VDDPEHA4

VDDPEHA3

VDDPEHA2

VSS72

VSS71

VSS70

VSS69

VDDPEHA5

VDDPEHA8

VDDPEHA7

VDDPEHA6

VSS68

VSS67

VSS66

J13

VDDPEHA9

VDDPEHA10

VSS65

VSS64

VSS63

VDDPETA3

VDDPETA2

VDDPETA1

VSS62

VSS61

VSS60

VDDPETA6

VDDPETA5

VDDPETA4

VSS59

VSS58

VSS57

VDDPETA7

VSS56

L10

K12

N9

N12

M9

M12

L9

L12

J7

K13

VDDPETA9

VDDPETA8

VDDPETA10

VSS55

VSS54

VSS53

K7

K6

VSS0

VDDPETA12

VDDPETA11

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49

VSS52

VSS51

VSS50

A1 A11 D18 F6 H16 L3

T13 V1

A15 A16 A7 B16 B3 C16 C3 D1 D16 D17 D2 D3 E16 E3 E9 F11 F12 F13 F16 F3 F7 F9 G1 G11 G16 G17 G18 G2 G3 H11 H3 J11 J16 J3 J9 K11 K16 K3 K9 L16

C77

C82

C87

C92

0.1UF

C97

C102

0.1UF

C106

C110

0.1UF

C114

0.1UF

C67

C72

0.1UF

+1.0V_VDDA

VDDPEA

C83

C88

C93

C98

C103

C107

C111

0.1UF

C115

0.1UF

C68

C73

0.1UF

+2.5V_VDDHA

VDDPEHA

C69

C74

C79 C78

C84

C89

C94

C99

C104

C108

C112

C116

0.1UF

3_3VIO 3_3V

0.1UF

VDDIO

C70

C75

0.1UF

C80

C85

0.1UF

C90

C95

0.1UF

C100

1.0UF

C117

0.1UF

C119

C124

0.1UF

C120

C125

0.1UF

C121

C126

0.1UF

C127

C122

0.1UF

C129

C134

0.1UF

C130

C135

0.1UF0.1UF

0.1UF

C131

C136

0.1UF

C132

C137

0.1UF

C139

C144

0.1UF

C140

C145

0.1UF

C146

C141

47UF

0.1UF

C142

C147

0.1UF

C149

C154

0.1UF

C155

C150

47UF

C151

C156

47UF

1.0UF

C157

C152

0.1UF

C159

C162

0.1UF

STIFF_6P

C160

C163

0.1UF

C165

47UF

1

2

C166

0.1UF

C168

47UF

M1

4

3

C169

0.1UF

C171

1.0UF

6

5

C172

0.1UF

C174

C176

0.1UF

D

A3B7C6V9V3

A5

A4

IN IN

B2 B0

6

V18

8

V17

V16

V15

V12

U9

U3

U18

U17

U1T9T8T7T6T5T4T3T2

U16

U15

U12

T18

T17

T16

T15

67

T14

T12

T11

T10T1R18R1P18

P1N7N6N3N2

N18

N17

N16

N14

N1

N13

M3

M16

M13

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT

2008

45

3

TITLE

89EBPES24T3G2

89HPES24T3G2 - POWER

DRAWING NO.

SIZE

SCH-00146

B

AUTHOR

K Leung / T Tran Thu Jan 17 16:47:05 2008

2

FAB P/N

18-657-000

CHECKED BY

D Huang

REV.

1.0

SHEET 12 OF 12

1