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®
October 2007
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284- 2775
Printed in U.S.A.
©2007 Integrated Device Technology, Inc.
IDT™ 89EBPES16T4G2
Evaluation Board Manual
(Eval Board: 18-634-000)
Page 2
DISCLAIMER
Integrated Device Technology, Inc. reserves t h e right to make changes to its produc ts or specifications at any time, without notice, in order to improve design or perfor mance
and to supply the best possible product. IDT does not assume any responsibility for use of any circui try described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analy sis be performed.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agr eement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for su rgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly us ed in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a significant injury to the user.
2. A critical co mpo nent is an y com pon en t s of a lif e sup po rt dev ice or sy s te m who se f ai lu re t o perform can be re aso na bl y exp ect ed to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT lo go, and Integrated Device Technology are trademarks or registered trademarks of I ntegrated Device Technology, Inc.
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Notes
EB16T4G2 Eval Board Manual i October 3, 2007
Table of Contents
®
Description of the EB16T4G2 Eval Board
Introduction.....................................................................................................................................1-1
Board Features...............................................................................................................................1-2
Hardware................................................................................................................................1-2
Software..................................................................................................................................1-2
Other.......................................................................................................................................1-2
Revision History..............................................................................................................................1-2
Installation of the EB16T4G2 Eval Board
EB16T4G2 Installation....................................................................................................................2-1
Hardware Description.....................................................................................................................2-1
Reference Clocks............................................................................................................................2-1
Power Sources................................................................................................................................2-2
External Power Source...........................................................................................................2-2
PCI Express Analog High Power Voltage Converter..............................................................2-3
PCI Express Analog Power Voltage Converter......................................................................2-3
PCI Express Transmitter Analog Power Voltage Converter...................................................2-3
Core Logic Voltage Converter................................................................................................2-3
3.3V I/O Voltage Regulator.....................................................................................................2-3
Power-up Sequence...............................................................................................................2-3
Required Jumpers..................................................................................................................2-3
Reset...............................................................................................................................................2-3
Fundamental Reset................................................................................................................2-4
Downstream Reset.................................................................................................................2-4
Boot Configuration Vector...............................................................................................................2-4
SMBus Interfaces............................................................................................................................2-6
SMBus Slave Interface...........................................................................................................2-6
SMBus Master Interface.........................................................................................................2-7
JTAG Header..................................................................................................................................2-7
Attention Buttons.............................................................................................................................2-7
Miscellaneous Jumpers, Headers...................................................................................................2-8
LEDs...............................................................................................................................................2-9
PCI Express Connectors...............................................................................................................2-10
EB16T4G2 Board Figure..............................................................................................................2-13
Software for the EB16T4G2 Eval Board
Introduction.....................................................................................................................................3-1
Device Management Software........................................................................................................3-1
Schematics
Schematics.....................................................................................................................................4-1
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IDT Table of Contents
EB16T4G2 Eval Board Manual ii October 3, 2007
Notes
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Notes
EB16T4G2 Eval Board Manual iii October 3, 2007
List of Tables
®
Table 2.1 Clock Source Selection .......................................................................................................2-1
Table 2.2 Clock Frequency Selection .................................................................................................2-2
Table 2.3 Clock Spread Spectrum Selection ......................................................................................2-2
Table 2.4 SMA Connectors - Onboard Reference Clock ....................................................................2-2
Table 2.5 External Power Connector - J1 ...........................................................................................2-3
Table 2.6 Downstream Reset Selection .............................................................................................2-4
Table 2.7 Boot Configuration Vector Signals ......................................................................................2-4
Table 2.8 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1) ...........................................2-5
Table 2.9 Slave SMBus Interface Connector ......................................................................................2-6
Table 2.10 SMBus Slave Interface Address Configuration ...................................................................2-6
Table 2.11 EEPROM SMBus Address Setting .....................................................................................2-7
Table 2.12 JTAG Connector Pin Out ....................................................................................................2-7
Table 2.13 Attention Buttons ................................................................................................................2-8
Table 2.14 Miscellaneous Jumpers, Headers .......................................................................................2-8
Table 2.15 LED Indicators ....................................................................................................................2-9
Table 2.16 PCI Express x16 Connector Pinout ..................................................................................2-10
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IDT List of Tables
EB16T4G2 Eval Board Manual iv October 3, 2007
Notes
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Notes
EB16T4G2 Eval Board Manual v October 3, 2007
List of Figures
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Figure 1.1 Function Block Diagram of the EB16T4G2 Eval Board ......................................................1-1
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IDT List of Figures
EB16T4G2 Eval Board Manual vi October 3, 2007
Notes
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Notes
EB16T4G2 Eval Board Manual 1 - 1 October 3, 2007
®
Chapter 1
Description of the EB16T4G2
Eval Board
Introduction
The 89HPES16T4G2 switch (also referred to as PES16T4G2 in this manual) is a member of IDT’s PCI
Express® standard (PCIe®) based line of products. It is a Gen2 4-port switch, with 4 serial lanes per port.
One upstream port is provided for connecting to the root complex (RC), and up to three downstream ports
are available for connecting to PCIe endpoints or to another switch. More information on this device can be
found in the 89HPES16T4G2 User Manual.
The 89EBPES16T4G2 Evaluation Board (also referred to as EB16T4G2 in this manual) provides an
evaluation platform for the PES16T4G2 switch. It is also a cost effective way to add a PCIe downstream
port (x4) to an existing system with a limited number of PCIe downstream ports. The EB16T4G2 eval board
is designed to function as an add-on card to be plugged into a x4 PCIe slot available on a motherboard
hosting an appropriate root complex, microprocessor(s), and three downstream ports. The EB16T4G2 is a
vehicle to test and evaluate the functionality of the PES16T4G2 chip. Customers can use this board to get a
headstart on software development prior to the arrival of their own hardware. The EB16T4G2 is also used
by IDT to reproduce system-level hardware or software issues reported by customers. Figure 1.1 illustrates
the functional block diagram representing the main parts of the EB16T4G2 board.
Figure 1.1 Function Block Diagram of the EB16T4G2 Eval Board
JTAG
Header
Main
Reset
I/O Expander
PCA9555
PCIe x4 Upstream Edge
EEPROM
24LC512
SMBUS
HEADER
PES16T4G2
PCI Express
Switch
External Power
PCIe x16 Downstream Slot
PCIe x16 Downstream Slot
x4
25 MHz
SSC Clock
Buffer
Clock
Fanout
SMBus
PCIe x16 Downstream Slot
Voltages on board
+12V, +3.3V, +2.5V, +1.0V
Connector
Power
Module
PTH08T240
x4
x4
x4
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IDT Description of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 1 - 2 October 3, 2007
Notes
Board Features
Hardware
PES16T4G2 PCIe 4 port switch
– Four x4 ports, 16 PCIe lanes
– PCIe Base Specification Revision 2.0 compliant
– 16 GBps (128 Gbps) aggregate switching capacity
– Up to 2048 byte maximum Payload Size
– Automatic lane reversal and polarity inversion supported on all lanes
– Automatic per port link width negotiation to x4, x2, x1
– Load configuration from an optional serial EEPROM via SMBUS
Upstream, Downstream Port
– One edge connector on the upstream port, to be plugged into a slot with at least x4 capable on a
host motherboard
– Three slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.
These slot connectors are x16 mechanically but electronically connected as x4 only.
Numerous user selectable configurations set using onboard jumpers and DIP-switches
– Source of clock - host clock or onboard clock generator
– Two clock rates and spread spectrum settings
– Boot mode selection
SMBUS Slave Interface (4 pin header)
SMBUS Master Interface connected to the Serial EEPROMs through I/O expander
“Attention” button for each downstream port to initiate a hot swap event on each port
Four pin connector for optional external power supply
Push button for Warm Reset
Several LEDs to display status, reset, power, “Attention”, etc.
One 10-pin JTAG connector (pitch 2.54 mm x 2.54 mm)
Software
There is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES16T4G2 within host systems
running popular operating systems.
Installation programs
– Operating Systems Supported: Windows2000, WindowsXP, Vista, Linux
GUI based application for Windows and Linux
– Allows users to view and modify registers in the PES16T4G2
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.
Other
A metal bracket is required to firmly hold in place three endpoints plugged into the EB16T4G2
board.
An external power supply may be required under some conditions.
SMBUS cable may be required for certain evaluation exercises.
SMA connectors are provided on the EB16T4G2 board for specific test points.
Revision History
August 13, 2007: Initial publication of board manual.
October 3, 2007: Updated Schematics: replace 0.1uF at C25/C26 with 0 ohm.
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Notes
EB16T4G2 Eval Board Manual 2 - 1 October 3, 2007
®
Chapter 2
Installation of the EB16T4G2
Eval Board
EB16T4G2 Installation
This chapter discusses the steps required to configure and install the EB16T4G2 evaluation board. All
available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.
3. Insert the evaluation board into the host system (motherboard with root complex chipset).
4. Apply power to the host system.
The EB16T4G2 board is shipped with all jumpers and switches configured to their default settings. In
most cases, the board does not require further modification or setup.
Hardware Description
The PES16T4G2 is a 16-lane, 4-port PCI Express® switch. It is a peripheral chip that performs PCI
Express based switching with a feature set optimized for high performance applications such as servers
and storage. It provides fan-out and switching functions between a PCI Express upstream port and 3 downstream ports or peer-to-peer switching between downstream ports.
The EB16T4G2 has three PCI Express downstream ports, accessible through three x16 connectors. All
three ports are capable of negotiating a x1, x2, or x4 link width. All endpoint cards connected to the
PES16T4G2 must support at least one of these link widths.
Basic requirements for the board to run are:
– Host system with a PCI Express root complex supporting x4 configuration through a PCI Express
x4 slot.
– x1, x2, or x4 PCI Express Endpoint Cards.
Reference Clocks
The PES16T4G2 requires a differential reference clock. The EB16T4G2 derives this clocks from a
common source which is user-selectable. The common source can be either the host system’s reference
clock or the onboard clock generator. Selection is made by stuffing resistors described in Table 2.1.
The source for the onboard clock is the ICS557-03 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB16T4G2 allows selection between multiple
clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively.
Spread Spectrum technology reduces peak EMI emissions by modulating the frequency to spread the peak
energy over a wider bandwidth.
Clock Configuration Stuffing Option
W6 and W7 Clock Source
Pins 2 and 3 Onboard Reference Clock – Use onboard clock generator
Pins 1 and 2 Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection
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EB16T4G2 Eval Board Manual 2 - 2 October 3, 2007
Notes
If the Clock Spread Spectrum is used to modulate data rate, then both ports must use same modulated
clock source. Therefore, if your system uses SSC, the on-board clock generator must be disabled and the
upstream reference clock should be used instead.
The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.4. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.
Power Sources
The EB16T4G2 and all downstream ports are powered from the upstream port slot power. If add-in
cards require more power than the upstream slot can support, an external source is required to supply this
extra power via an auxiliary 4-pin power connector on the board. Header W1, W2, and W3 (see Table 2.14)
are used to select proper power source for the switch and all downstream ports.
External Power Source
If necessary, external power is supplied to the EB16T4G2 board through a 4-pin auxiliary power
connector attached to J1. The external power supply provides +12V to the EB16T4G2 as described in Table
2.5. The +5V is unused.
Clock Frequency Switch - S2[2:1]
S2[2] S2[1] Clock Frequency
OFF OFF Reserved
OFF ON 125 MHz
ON OFF 100 MHz (Default)
ON ON <Reserved>
Table 2.2 Clock Frequency Selection
Clock Spread Spectrum Switch - S2[4:3]
S2[4] S2[3] Spread%
OFF OFF No Spread (Default)
OFF ON Down -0.75
ON OFF Down -0.50
ON ON Center ±0.25
Table 2.3 Clock Spread Spectrum Selection
Onboard Reference Clock Output (Differential) – J7, J6
J6 Positive Reference Clock
J7 Negative Reference Clock
Table 2.4 SMA Connectors - Onboard Reference Clock
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EB16T4G2 Eval Board Manual 2 - 3 October 3, 2007
Notes
PCI Express Analog High P ower Voltage Conv erter
A DC-DC converter (U18) provides a 2.5V PCI Express analog high power voltage (shown as VDDHA)
to the PES16T4G2.
PCI Express Analog Power Voltage Converter
A separate DC-DC converter (U16) provides a 1.0V PCI Express analog power voltage (VDDA) to the
PES16T4G2.
PCI Express Trans m itter Analog Power Voltage Converter
A separate DC-DC converter (U17) provides a 1.0V PCI Express transmitter analog power voltage
(shown as VDDPETA) to the PES16T4G2.
Core Logic Vo ltage Converter
A separate DC-DC converter (U15) provides the 1.0V core voltage (VDDCORE) to the PES16T4G2.
3.3V I/O Voltage Regulator
A 12V to 3.3V voltage regulator (VR1) provides the 3.3V I/O voltage (VDDIO) to the PES16T4G2.
Power-up Sequence
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There
are no other power-up sequence requirements for the various operating supply voltages.
Required Jumpers
To deliver power to the PES16T4G2 switch, the following jumpers must be shunted: W25, W21, W22,
W23, and W24. These jumpers were implemented so that the power consumption of the PES16T4G2 can
be measured.
Reset
The PES16T4G2 supports two types of reset mechanisms as described in the PCI Express specification:
– Fundamental Reset: This is a system-generated reset that propagates along the PCI Express
tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES16T4G2, and the endpoints.
– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Reset may be initiated by software. This is further discussed in the 89HPES16T4G2
User Manual. The EB16T4G2 evaluation board provides seamless support for Hot Reset.
Pin Signal
1+12V
2GND
3GND
4+5V
Table 2.5 External Power Connector - J1
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EB16T4G2 Eval Board Manual 2 - 4 October 3, 2007
Notes
Fundamental R eset
There are two types of Fundamental Resets which may occur on the EB16T4G2 evaluation board:
– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES16T4G2.
– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
• Pressing a push-button switch (S1) located on EB16T4G2 board
• The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB16T4G2. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W4.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES16T4G2 while power is on.
Downstream Reset
The PES16T4G2 provides a a choice of either a software-controlled reset for each downstream port
through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in
Table 2.6.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.7 is sampled by the PES16T4G2
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S7 and S8 as defined in Table 2.8.
Port # Jumper Selection
2 W19 [1-2] Software controlled reset through GPIO0
[2-3] Fundamental reset PERST# (default)
4 W17 [1-2] Software controlled reset through GPIO1
[2-3] Fundamental reset PERST# (default)
6 W18 [1-2] Software controlled reset through GPIO11
[2-3] Fundamental reset PERST# (default)
Table 2.6 Downstream Reset Selection
Signal Description
CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream
ports are using the same clock source as that provided to downstream devices. This pin is
used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers
for downstream ports. The value may be overridden by modifying the SCLK bit in the downstream port’s PCIELSTS register. Default: 0x1
CCLKUS Common Clock Upstream. The assertion of this pin indicates that the upstream port is
using the same clock source as the upstream device. This pin is used as the initial value of
the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value
may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. Default: 0x1
MSMBSMODE Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 kHz. Default: 0x0
Table 2.7 Boot Configuration Vector Signals (Part 1 of 2)
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IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 5 October 3, 2007
Notes
RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the
PES16T4G2 executes the reset procedure and remains in a reset state with the Master and
Slave SMBuses active. This allows software to read and write registers internal to the
device before normal device operation begins. The device exits the reset state when the
RSTHALT bit is cleared in the P0_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register.
Default: 0x0
SWMODE[2:0] Switch Mode. These configuration pins determine the PES16T4G2 switch operating
mode. Default: 0x0
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 through 0x7 - Reserved
REFCLKM PCI Express Reference Clock Mode Select. This signal selects the frequency of the ref-
erence clock input. Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz
MSMBADDR[2:0] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM
from which configuration information is loaded. Default: 0x0
Signal Description Default
S8[1] CCLKDS OFF
S8[2] CCLKUS OFF
S8[3] MSMBSMODE ON
S8[4] Not Used ON
S8[5] Not Used ON
S8[6] Not Used ON
S8[7] Not Used ON
S8[8] RSTHALT ON
S7[1] SWMODE[0] ON
S7[2] SWMODE[1] ON
S7[3] SWMODE[2] ON
S7[4] Not Used ON
S7[5] REFCLKM ON
S7[6] MSMBADDR[0] ON
S7[7] MSMBADDR[1] ON
S7[8] MSMBADDR[2] ON
Table 2.8 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1)
Signal Description
Table 2.7 Boot Configuration Vector Signals (Part 2 of 2)
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IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 6 October 3, 2007
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system component chips can communicate. It is based on the principles of operation of I
2
C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consists of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.
The PES16T4G2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface. The slave SMBus interface allows a SMBus Master device full access to all software-visible registers.
The Master SMBus interface provides connection to the external serial EEPROM used for initialization and
the I/O expanders used for hot-plug signals.
SMBus Slave Interface
On the PES16T4G2 board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.9.
Note: The SMBus signals to the PCI Express edge connector is disabled by default. To enable
them, place 0-ohm resistors at locations R160 and R161.
.
A fixed slave SMBus address (0b1100_000) specified by the SSMBADDR[5,3:1] pins is used.
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:
– Byte and Word Write/Read
– Block Write/Read
Slave SMBus Interface Connector J8
Pin Signal
1N/C
2SCL
3GND
4SDA
Table 2.9 Slave SMBus Interface Connector
Slave Interface Address Configuration
Address Bit Signal
1 SSMBUSADDR[1]
2 SSMBUSADDR[2]
3 SSMBUSADDR[3]
40
5 SSMBUSADDR[5]
61
71
Table 2.10 SMBus Slave Interface Address Configuration
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IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 7 October 3, 2007
Notes
SMBus Master Interface
Connected to the master SMBus interface are three 16-bit I/O Expanders (PCA9555) and a serial
EEPROM (24LC512). Three I/O Expanders are used as the interface for the onboard hot-plug controllers
(MIC2591B). The lower three bits of the bus address for the I/O Expander0/2/4 are fixed as 0x0, 0x2 and
0x4, respectively.
The seven bits address for the selected EEPROM devic e is 0b1010_000 by default and the lower
three bit is configurable using switch S7 as described in Table 2.11.
JTAG Header
The PES16T4G2 provides a JTAG connector J5 for access to the PES16T4G2 JTAG interface. The
connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.15 for the JTAG Connector J5
pin out.
Attention Buttons
The PES16T4G2 features three attention buttons, shown in Table 2.13. Each button corresponds to a
particular port and is used to initiate hot-swapping events.
S7[8] S7[7] S7[6] Bus Address
OFF OFF OFF 0b111
OFF OFF ON 0b110
OFF ON OFF 0101
OFF ON ON 0b100
ON OFF OFF 0b011
ON OFF ON 0b010
ON ON OFF 0b001
ON ON ON 0b000 (Default)
Table 2.11 EEPROM SMBus Address Setting
JTA G Connector J5
Pin Signal Direction Pin Signal Direction
1 /TRST - Test reset Input 2 GND —
3 TDI - Test data Input 4 GND —
5 TDO - Test data Output 6 GND —
7 TMS - Test mode select Input 8 GND —
9 TCK - Test clock Input 10 GND —
Table 2.12 JTAG Connector Pin Out
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IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 8 October 3, 2007
Notes
Miscellaneous Jumpers, Headers
Button Description
S5 Port 2 Attention Button
S3 Port 4 Attention Button
S4 Port 6 Attention Button
Table 2.13 Attention Buttons
Miscellaneous Jumpers, Headers
Ref.
Designator
Type Default Description
W1-W3 Header 1-2 Shunted 1-2: 12.0V source from Upstream Port (Default)
2-3: 12.0V source from external power connector
W20 Header Shunted Disable EEPROM Write protect feature (Default)
S6[1] Switch ON ON: Port2, Force hot-plug controller on
OFF: Port2, Power Enable bit controls hot-plug controller
S6[2] Switch On ON: Port4, Force hot-plug controller on
OFF: Port4, Power Enable bit controls hot-plug controller
S6[3] Switch On ON: Port6, Force hot-plug controller on
OFF: Port6, Power Enable bit controls hot-plug controller
W15 Header 2-3 Shunted 2-3: Port 2, +12V source from Upstream port (Default)
1-2: Port 2, +12V source from hot-plug controller
W9 Header 2-3 Shunted 2-3: Port 4, +12V source from Upstream port (Default)
1-2: Port 4, +12V source from hot-plug controller
W12 Header 2-3 Shunted 2-3: Port 6, +12 source from Upstream port (Default)
1-2: Port 6, +12 source from hot-plug controller
W16 Header 2-3 Shunted 2-3: Port 2, +3.3V source from Upstream port (Default)
1-2: Port 2, +3.3V source from hot-plug controller
W10 Header 2-3 Shunted 2-3: Port 4, +3.3V source from Upstream port (Default)
1-2: Port 4, +3.3V source from hot-plug controller
W13 Header 2-3 Shunted 2-3: Port 6, +3.3V source from Upstream port (Default)
1-2: Port 6, +3.3V source from hot-plug controller
W14 Header 2-3 Shunted 2-3: Port 2, +3.3AUX source from upstream port (Default)
1-2: Port 2, +3.3V source from hot-plug controller
W8 Header 2-3 Shunted 2-3: Port 4, +3.3AUX source from upstream port (Default)
1-2: Port 4, +3.3V source from hot-plug controller
W11 Header 2-3 Shunted 2-3: Port 6, +3.3AUX source from upstream port (Default)
1-2: Port 6, +3.3V source from hot-plug controller
Table 2.14 Miscellaneous Jumpers, Headers
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IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 9 October 3, 2007
Notes
LEDs
There are several LED indicators on the EB16T4G2 which convey status feedback. A description of
each is provided in Table 2.15.
Location Color Definition
DS21 Green Port 2: Power-is-good indicator
DS9 Green Port 4: Power-is-good indicator
DS15 Green Port 6: Power-is-good indicator
DS20 Green Port 2: Power Indicator
DS8 Green Port 4: Power Indicator
DS14 Green Port 6: Power Indicator
DS19 Yellow Port 2: Attention Indicator
DS7 Yellow Port 4: Attention Indicator
DS13 Yellow Port 6: Attention Indicator
DS18 Green Port2: Activity Indicator
DS6 Green Port4: Activity Indicator
DS12 Green Port6: Activity Indicator
DS17 Green Port2: Linkup Indicator
DS5 Green Port4: Linkup Indicator
DS11 Green Port6: Linkup Indicator
DS23 Green Port0: Linkup Indicator
DS24 Green Port0: Activity Indicator
DS3 Red Port2/4: Power Fault Indicator
DS4 Red Port6: Power Fault Indicator
DS25 Green GPIO3
DS26 Green GPIO5
DS27 Green GPIO6
DS28 Green GPIO8
DS29 Green GPIO9
DS30 Green GPIO10
DS31 Green GPIO12
DS32 Green GPIO15
Table 2.15 LED Indicators
Page 20
IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 10 October 3, 2007
Notes
PCI Express Connectors
Pin Side A Side B
1 +12V 12V power PRSNT1# Hot-Plug presence detect
2 +12V 12V power +12V 12V power
3 RSVD Reserved +12V 12V power
4 GND Ground GND Ground
5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p
6 SMDAT SMBus Data JTAG TDI (Test Data Input)
7 GND Ground JTAG TDO (Test Data Output)
8 +3.3V 3.3V power JTAG TMS (Test Mode Select)
9 JTAG1 TRST# (Test/Reset) resets
JTAG i/f
+3.3V 3.3V power
10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power
11 WAKE# Signal for Link reactivation PERST# Fundamental Reset
Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ REFCLK Reference clock
14 PETp0 Transmitter differential REFCLK- (d iffere ntia l pair)
15 PETn0 pair, Lane 0 GND Ground
16 GND Ground PERp0 Receiver differential
17 PRSNT2# Hot-Plug presence detect PERn0 pair, Lane 0
18 GND Ground GND Ground
19 PETp1 Transmitter differential RSVD Reserv ed
20 PETn1 pair, Lane 1 GND Ground
21 GND Ground PERp1 Receiver differential
22 GND Ground PERn1 pair, Lane 1
23 PETp2 Transmitter differential GND Ground
24 PETn2 pair, Lane 2 GND Ground
25 GND Ground PERp2 Receiver differential
26 GND Ground PERn2 pair, Lane 2
27 PETp3 Transmitter differential GND Ground
28 PETn3 pair, Lane 3 GND Ground
29 GND Ground PERp3 Receiver differential
30 RSVD Reserved PERn3 pair, Lane 3
31 PRSNT2# Hot-Plug presence detect GND Ground
32 GND Ground RSVD Reserved
33 PETp4 Transmitter differential RSVD Reserv ed
Table 2.16 PCI Express x16 Connector Pinout (Part 1 of 3)
Page 21
IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 11 October 3, 2007
Notes
34 PETn4 pair, Lane 4 GND Ground
35 GND Ground PERp4 Receiver differential
36 GND Ground PERn4 pair, Lane 4
37 PETp5 Transmitter differential GND Ground
38 PETn5 pair, Lane 5 GND Ground
39 GND Ground PERp5 Receiver differential
40 GND Ground PERn5 pair, Lane 5
41 PETp6 Transmitter differential GND Ground
42 PETn6 pair, Lane 6 GND Ground
43 GND Ground PERp6 Receiver differential
44 GND Ground PERn6 pair, Lane 6
45 PETp7 Transmitter differential GND Ground
46 PETn7 pair, Lane 7 GND Ground
47 GND Ground PERp7 Receiver differential
48 PRSNT2# Hot-Plug presence detect PERn7 pair, Lane 7
49 GND Ground GND Ground
50 PETp8 Transmitter differential RSVD Reserv ed
51 PETn8 pair, Lane 8 GND Ground
52 GND Ground PERp8 Receiver differential
53 GND Ground PERn8 pair, Lane 8
54 PETp9 Transmitter differential GND Ground
55 PETn9 pair, Lane 9 GND Ground
56 GND Ground PERp9 Receiver differential
57 GND Ground PERn9 pair, Lane 9
58 PETp10 Trans mitter diff erenti al GND Ground
59 PETn10 pair, Lane 10 GND Ground
60 GND Ground PERp10 Receiver differential
61 GND Ground PERn10 pair, Lane 10
62 PETp11 Trans mitter diff erenti al GND Ground
63 PETn11 pair, Lane 11 GND Ground
64 GND Ground PERp11 Receiver differential
65 GND Ground PERn11 pair, Lane 11
66 PETp12 Trans mitter diff erenti al GND Ground
67 PETn12 pair, Lane 12 GND Ground
68 GND Ground PERp12 Receiver differential
69 GND Ground PERn12 pair, Lane 12
70 PETp13 Trans mitter diff erenti al GND Ground
Pin Side A Side B
Table 2.16 PCI Express x16 Connector Pinout (Part 2 of 3)
Page 22
IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 12 October 3, 2007
Notes
Note: These x16 PCI Express connectors comply with the PCIe specification. However, the
downstream ports on the EB16T4G2 are electronically connected in x4 configuration. According
to the PCI Express specification, the PRSNT1# pin should be wired to the farthest available
PRSNT2# pin on the connector. In the EB16T4G2, all PRSNT2# pins are tied together. This
allows the board to be installed in a x1 or a x4 slot via a slot reducer.
71 PETn13 pair, Lane 13 GND Ground
72 GND Ground PERp13 Receiver differential
73 GND Ground PERn13 pair, Lane 13
74 PETp14 Trans mitter diff erenti al GND Ground
75 PETn14 pair, Lane 14 GND Ground
76 GND Ground PERp14 Receiver differential
77 GND Ground PERn14 pair, Lane 14
78 PETp15 Trans mitter diff erenti al GND Ground
79 PETn15 pair, Lane 15 GND Ground
80 GND Ground PERp15 Receiver differential
81 PRSNT2# Hot-Plug presence detect PERn15 pair, Lane 15
82 RSVD Reserved GND Ground
Pin Side A Side B
Table 2.16 PCI Express x16 Connector Pinout (Part 3 of 3)
Page 23
IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 13 October 3, 2007
EB16T4G2 Board Figure
Page 24
IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 14 October 3, 2007
Notes
Page 25
Notes
EB16T4G2 Eval Board Manual 3 - 1 October 3, 2007
®
Chapter 3
Software for the EB16T4G2
Eval Board
Introduction
This chapter discusses some of the main features of the available software to give users a better understanding of what can be achieved with the EB16T4G2 evaluation board using the device management software.
Device management software and related user documentation are available on a CD which is included
in the Evaluation Board Kit. This information is also available on IDT’s FTP site. For more information,
contact IDT at ssdhelp@idt.com.
Device Management Software
The primary use of the Device Management Software package is to enable us ers of the evaluation
board to access all the registers in the PES16T4G2 device. This access can be achieved using the PCI
Express in-band configuration cycles through the upstream port on the PES16T4G2.
This software also enables users to save a snapshot of the current register set into a dump file which
can be used for debugging purposes. An export/import facility is also available to create and use “Configuration” files which can be used to initialize the switch device with specific values in specific registers.
A conversion utility is also provided to translate a configuration file into an EEPROM programmable data
structure. This enables the user to program an appropriate serial EEPROM with desirable register settings
for the PES16T4G2, and then to populate that EEPROM onto the Evaluation Board. It is also possible to
program the EEPROM directly on the Evaluation Board using a feature provided by the software package.
The front end of the Device Management Software is a user-friendly Graphical User Interface which
allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the
software in “simulation” mode with no real hardware attached, allowing the creation of configuration files for
the PES16T4G2 in the absence of the actual device.
Much of the Device Management Software is written with device-independent and OS-independent
code. The software will be guaranteed to work on Linux (/sys interface) and MS Windows XP. It may function flawlessly on various flavors of MS Windows, but may not be validated on all. The fact that the software
is device-independent assures its scalability to future PCIe parts from IDT. Onc e users are familiar with the
GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each
device through an XML device description file which includes information on the number of ports, registers,
types of registers, information on bit-fields within each register, etc.
Page 26
IDT Software for the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 3 - 2 October 3, 2007
Notes
Page 27
Notes
EB16T4G2 Eval Board Manual 4 - 1 October 3, 2007
®
Chapter 4
Schematics
Schematics
Page 28
11 PORT 6 CONNECTOR (D/S)
-------------------------------
13 PES16T4G2 - POWER
12 PES16T4G2 - EEPROM.JTAG
10 PORT 4 CONNECTOR (D/S)
9 PORT 2 CONNECTOR (D/S)
8 PORT 0 EDGE CONN (U/S)
7 HOT PLUG - MOSFETS
6 HOT PLUG CONTROLLERS
5 I/O EXP, WAKE, ATTN
4 CLOCKS
3 POWER REGULATORS
2 RESET, POWER CONNECTOR
1 TITLE PAGE
-------------------------------
SHEET DESCRIPTION
Tue Oct 02 16:57:16 2007 SHEET 1 OF 13
K. LEUNG
2007
STGSCH-00114
B.OH
1.0
18-634-000
89EBPES16T4G2
B
STGC-0114R01 1.0 INITIAL RELEASE 2007-10-02 K. LEUNG
6
A
TITLE
CHECKED BY
DCN
DESCRIPTION
DATE
REV
8
8
65 4
4
2
2
D
D
CC
BB
A
1
1
REV.
SIZE
3
COPYRIGHT (C) IDT
AUTHOR
DRAWING NO.
REVISIONS
CHANGE BY
3
7
FAB P/N
57
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
Page 29
LABEL 'POWER'
LABEL 'GND'
FOR "VDD"
+12.0V -> +3.3V
BOARD RESET
POWER INDICATOR
PLACE NEAR TOP EDGE
NOISE-FREE ROUTING
PLACE R6 NEAR VR1
PLACE R7 NEAR U1
Fri Jun 15 14:48:00 2007 SHEET 2 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
TP20
TP21
TP19
R6
TP3
TP4
TP1
TP2
W5
C5
C6
R3
C8
C9
R7
5
7
6
8
2
9
10
1
11
4
3
VR1
C1C2C3
W3
W2
W1
4
3
2
1
J1
W4
R1
R2
R4
4
5
1
3
2
U2
43
2
1
S1
C4
8
7
2
5
6
43
1
U3
C7
DS1
R5
DS2
R8
RESET, POWER CONNECTOR
16V
M_PERSTN
PERST_N
1UF
YEL
YEL
330
PERST_N
330GRN
RED
5%
47UF
12V_DS
5%
10K
10K
5%
5%
10K
RED
00
10V
220UF
47UF
10V
1.21K
1%
22UF
25V
22UF
25V
25V
10UF
25V
10UF
22UF
25V
10V
WHT
WHT
WHT
WHT
5%
121110
9
28
28
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
PB_SW
NC NO
TLC7733D
GND
RESETN
RESET
VCC
CT
CONTROL
SENSE
RESINN
OUT
3_3VIO
3_3V
PTH08T240WAD
SYNC
Vout
VO_SEN-
Vin
VO_SEN+
TURBOTRANS
Track
GND2
GND1
Vo_Adj
Inhibit
12_0V
POWER CONN
+5V
GND
GND
+12V
3_3V 3_3V3_3V 3_3V 3_3V3_3V
SN74LVC1G125
VCC
Y
GND
A
OE*
3_3V
Page 30
FOR "VCORE"
VDDCORE, 1.0V VDDPETA, 1.0V
VDDHA, 2.5V
NOISE-FREE ROUTING FOR "VDDTA"
NOISE-FREE ROUTING FOR "VDDA"
VDDA, 1.0V
NOISE-FREE ROUTING FOR "VDDHA"
PLACE R240 NEAR U17
PLACE R243 NEAR U1
PLACE R241 NEAR U18
PLACE R229 NEAR U1
PLACE R227 NEAR U16
PLACE R228 NEAR U1
NOISE-FREE ROUTING
PLACE R226 NEAR U15
PLACE R242 NEAR U1
Fri Jun 15 14:47:59 2007 SHEET 3 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
C267
C265
C269
C273
C271
C232
C250
C259
C261
C263
C264
C272
C266
C268
C270
C262
C260
C258
C248
C230
W25
C225C227
C245
R217
R216 R220
R219
R218
R221
R233
R232 R235
R231
R230
C228
C231
C222
C223
C229
C233
C241
C247
C251
C240
C246
C237 C236
C255
R238R225
R236
R223
R227
R226 R240
R229 R228
R242R243
W21
C234
FB3
FB4
FB5
C238
W22
W23
TP17TP18
TP15TP16
W24
8
2
3
29
31
34
38
18
17
16
15
14
13
19
36
30
28
27
26
25
35
37
23
22
21
20
12
11
10
9
24
765
4
1
32
33
U16
R222
R224
C226
8
2
3
29
31
34
38
18
17
16
15
14
13
19
36
30
28
27
26
25
35
37
23
22
21
20
12
11
10
9
24
765
4
1
32
33
U15
C235
FB8
FB7
FB6
C239
C244 C243
C224
C242
8
2
3
29
31
34
38
18
17
16
15
14
13
19
36
30
28
27
26
25
35
37
23
22
21
20
12
11
10
9
24
765
4
1
32
33
U18
R237
8
2
3
29
31
34
38
18
17
16
15
14
13
19
36
30
28
27
26
25
35
37
23
22
21
20
12
11
10
9
24
765
4
1
32
33
U17
R234
C249
C253
FB14
FB13
FB12
R241
C257
C252
C254
FB11
FB9
FB10
C256
R239
400MA
DNP
DNP
1UF
400MA
400MA
400MA
1UF
0.1UF
400MA
1UF
10UF
10UF
NA
DNP
499
RED
0.1UF
16V
10UF
10UF
10UF
10UF10UF
10UF
10UF
400MA
400MA
400MA
1UF
120OHM
120OHM
120OHM
16V
1UF
0
0.015UF
0
16V
10UF
10UF
10UF
10UF10UF
10UF
10UF
10UF
1UF
0.1UF
400MA
120OHM
120OHM
400MA
16V
120OHM
1%
16V
1UF
0.1UF
1UF
16V
0
120OHM
120OHM
120OHM
0.015UF
0
16V
120OHM
400MA
120OHM
400MA
120OHM
16V
10UF
DNP
DNP
DNP
NA
DNP
NA
DNP
NA
DNP
NA
DNP
NA
DNP
NA
DNP
NA
DNP
NA
NA
DNP
NA NA
DNP
DNP
DNP
DNP
DNP DNP
DNP
DNP
DNP DNP
RED
POWER REGULATORS
RED
RED
25V
25V
10UF
1%
1.07K
499
1%
0
00
0
2.0K
1%
1%
2.0K
1%
2.0K
1%
499
499
1%
10UF
25V
0.015UF 0.015UF
25V
10UF
10UF10UF
10UF
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
EN5330
ENABLE
ROCP
NCNCVDRAIN
EAOUT
EAIN
COMP
PGND
XOV
VSENSE
VOUT_PAD
VOUT6
VOUT5
VOUT4
VOUT1
VIN
VS1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
POK
AGND
XFB
VOUT3
VOUT2
VS0
VS2
VIN
SOFTSTART
AVIN
PGND
VIN
VIN
3_3V
3_3V3_3V
+1.0V_CORE +1.0V_VDDTA
+1.0V_VDDA +2.5V_VDDHA
EN5330
ENABLE
ROCP
NCNCVDRAIN
EAOUT
EAIN
COMP
PGND
XOV
VSENSE
VOUT_PAD
VOUT6
VOUT5
VOUT4
VOUT1
VIN
VS1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
POK
AGND
XFB
VOUT3
VOUT2
VS0
VS2
VIN
SOFTSTART
AVIN
PGND
VIN
VIN
EN5330
ENABLE
ROCP
NCNCVDRAIN
EAOUT
EAIN
COMP
PGND
XOV
VSENSE
VOUT_PAD
VOUT6
VOUT5
VOUT4
VOUT1
VIN
VS1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
POK
AGND
XFB
VOUT3
VOUT2
VS0
VS2
VIN
SOFTSTART
AVIN
PGND
VIN
VIN
3_3V
EN5330
ENABLE
ROCP
NCNCVDRAIN
EAOUT
EAIN
COMP
PGND
XOV
VSENSE
VOUT_PAD
VOUT6
VOUT5
VOUT4
VOUT1
VIN
VS1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
POK
AGND
XFB
VOUT3
VOUT2
VS0
VS2
VIN
SOFTSTART
AVIN
PGND
VIN
VIN
Page 31
PLACE NEAR U9
1|1
|
____________
OFF
______
|
______
|
|
|
0
|
______
|
______
ON
______
|
______
ON
______
|
OFF
|
|
SPREAD SELECTION
|
|
______
______
OFF
______
|
|
______
______
0
1
||
|
|
|
|
|
|
|
____
____
____
____
|
|
|
|
|
|
|
|
SPREAD %
125M
200M
SS0
0
|||
S1
S0
|
|||
|
||
||
0
|
|
1
|
||
|
0|1
ON
ON
OFF
SS1
1
0
|
|
|
|
0
0
1
|
|
|
|
|
ON
|
|
|
|
|
|
______
|
______
|
______
OFF
OFF
ON
ON
S2:2
______
______
______
|
|
|
|
|
|
|
______
OFF
OFF
ON
S2:4
|
|
|
|
|
|
|
________________
|
________________
S2:3
______
|
25M
________________
CLK (1:0)
|
|
|
______
S2:1
______
OUTPUT SELECT
SILKSCREEN:
________________
|
________________
100M
________________
|
________________
|
1
________________
NO SPREAD
________________
DOWN -0.75
________________
DOWN -0.5
________________
CENTER +-0.25
________________
____
____
PLACE NEAR U4
Tue Oct 02 17:02:58 2007 SHEET 4 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
48
R31
R32
11
0
C26
C25
M_REFCLK1N
0
M_REFCLK1P
33
R33
P6_REFCLKP
11
11
9
9
R35
34
26
TP5
R15
R16
54
32
1
J7
54
32
1
J6
R13
C18
C19
C17
R40
R39
R18
R17
3
2
1
W6
3
2
1
W7
R26
R24
C24
R36
R51
R45
R44
R46
R47
R50
R34
C23
FB2
C22
C21
C20
R30
R22
R28
R48
R49
R38
R37
R41
39
3119
2
5
4
1
24
23
40
44
36
35
43
7
15
14
6
45
46
28
47
32
25
18
10
3
27
41
42
37
38
33
29
30
21
20
17
16
13
12
9
8
22
U5
R23
R29
R27
R25
R9
R11
R10
R12
C15
C13
C14
C12
R21
R20
R43
R42
FB1
C11
C10
5
4
16
12
8
3
2
1
6
9
7
13
11
15
14
10
U4
R14
R19
98
10
7
11
6
12
5
13
4
14
3
15
2
16
1
S2
4
3
1
2
Y1
C16
81291011
81291011
659
65
11
65
10
12
12
10
10
8
8
M_SSMBCLK
M_SSMBDATA
P2_PWRGDN
P6_PWRGDN
P4_PWRGDN
33
33
33
0.001UF
33
CONNSMA
CONNSMA
10K
DNP
0.1UF
33
1%
49.9
49.9
49.9
49.9
33
49.9
49.9
1%
33
10K
DNP
10K
DNP
10K
10K
49.9
33
33
P6_REFCLKN
P2_REFCLKP
49.9
1%
DNP
120OHM
1UF
0.1UF
P4_REFCLKN
49.9
475
P2_REFCLKN
25MHZ
1%
22UF
0.1UF
1UF
475
SM0805
P4_REFCLKP
1%
0R
0R
1K
CLOCKS
0.1UF
0.1UF
1UF
1UF
0.1UF
5%
10
5%
5.1K
33
25V
P0_REFCLKN
1%
49.9
1%
1%
49.9
33
P0_REFCLKP
49.9
5%
SSC_SS0
SSC_SS1
SSC_S1
SSC_S0
10K
10K
10K
10K
SM0805
16V
16V
16V
16V
10UF
25V
1UF
YEL
0.1UF
16V
33
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
3_3V
SM_SW8
S1A
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S8A
S7A
S6A
S5A
S4A
S3A
S2A
OE_INV=1
ICS9DB803
DIFF_STOP
GND
GND
GND
SCLK
SDATA
SRC_DIV#
OE_INV
BYPASS#/PLL
PD
HIGH_BW#
OE7#
OE5#
OE6#
OE4#
OE2#
OE3#
OE1#
OE0#
SRC_IN#
SRC_IN
VDD
VDD
VDD
GND
GNDA
GND
DIF_7#
LOCK
IREF
DIF_7
DIF_6
DIF_6#
DIF_5#
DIF_5
DIF_4
DIF_4#
DIF_3
DIF_3#
DIF_2
DIF_2#
DIF_1#
DIF_0#
DIF_1
DIF_0
VDDA
VDD
VDD
OUT
VCC
GND
OE
IN
IN
3_3V
3_3V
IN
IN
IN
3_3V
3_3V
IN
IN
2
1
3
2
1
3
3_3V
OUT
OUT
OUT
OUT
ICS557-03
CLK1P
X1/ICLK
CKL1N
CLK0P
SS1
SS0
GNDODA
GNDXD
IREF
OE
X2
S0
S1
CLK0NVDDXD
VDDODA
OUT
OUT
OUT
OUT
3_3V
Page 32
IO EXPANDER 0
PORT 2 ATTN
SILKSCREEN LABELS:
IO EXPANDER 4
PORT 4 ATTN
PORT 6 ATTN
IO EXPANDER 2
Fri Jun 15 14:48:01 2007 SHEET 5 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
TP11
TP10
TP9
TP8
TP7
TP6
R74
R73
R72
R68
R67
R71
R70
R69
R66
R53
R65R52
R77
R76
R75
4
5
1
3
2
U11
4
5
1
3
2
U9
R81
4
5
1
3
2
U10
R58
R64
R61
12
24
23
22
1
20
19
18
17
16
15
14
13
11
10
9
8
7
6
5
4
3
2
21
U8
R54
R56
R59
R62
12
24
23
22
1
20
19
18
17
16
15
14
13
11
10
9
8
7
6
5
4
3
2
21
U6
R78
R80
R79
43
2
1
S5
R55
12
24
23
22
1
20
19
18
17
16
15
14
13
11
10
9
8
7
6
5
4
3
2
21
U7
R57
R60
R63
43
2
1
S4
43
2
1
S3
8
10
11
11
6
6
11
5
649
12
5
5
12
12
64
11
64
10
9
6
9
6
9
5
5
12
12
5
8
5
5
9
9
10
11
9
10
11
5
12
12
5
8
5
10
12
6
6
10
10
5
11
0%
0
P0_WAKE_N
P4_WAKE_N
NA
DNP
5%
2.7K
NA
DNP
P6_AIN
P6_PIN
P6_PEP
P6_PFN
P6_PDN
P6_APN
P2_PWRGDN
M_SDA
M_SCL
M_IOINTN2
P6_PWRGDN
P4_PWRGDN
0
DNP
0
0%
0
P2_PIN
P2_PEP
P2_AIN
P2_PFN
P2_PDN
P2_APN
M_SCL
M_SDA
0
0
0
DNP
0
0
P0_ACTIVEN
P2_APN
P6_APN
P2_WAKE_N
P2_ACTIVEN
P4_ACTIVEN
P6_ACTIVEN
P2_LINKUPN
P4_LINKUPN
P6_LINKUPN
M_SCL
M_SDA
P0_LINKUPN
P4_APN
0
0%
0
P4_PDN
IO EXP, WAKE, ATTN BUTTONS
M_IOINTN0
0%
YEL
P2_MRLN
YEL
P2_ILOCKP
YEL
YEL
P6_MRLN
P6_ILOCKP
P4_PFN
P4_PEP
P4_PIN
P4_AIN
P4_APN
P6_WAKE_N
YEL
P4_ILOCKP
YEL
P4_MRLN
10K
5%
5%
10K5%10K
10K
10K
2.7K
5%
NA
DNPNADNP
DNP
NA
DNPNADNP
NA
5%
10K10K
5%
10K
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
PB_SW
NC
NO
PB_SW
NC
NO
OUT
OUT
IN
IN
IN
SN74LVC1G125
VCC
Y
GND
A
OE*
SN74LVC1G125
VCC
Y
GND
A
OE*
OUT
3_3VAUX
3_3VAUX
SN74LVC1G125
VCC
Y
GND
A
OE*
OUTOUT
OUT
OUT
OUT
IN
IN
3_3V
OUT
OUT
OUT
3_3V
PCA9555
VSSVDD
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
I/O0.1
I/O0.0
I/O1.7
I/O1.6
I/O1.5
I/O1.4
I/O1.3
I/O1.2
I/O1.1
I/O1.0
INT#
SCL
A0
A2
A1
SDA
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
3_3V
3_3V
PCA9555
VSSVDD
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
I/O0.1
I/O0.0
I/O1.7
I/O1.6
I/O1.5
I/O1.4
I/O1.3
I/O1.2
I/O1.1
I/O1.0
INT#
SCL
A0
A2
A1
SDA
OUT
OUT
OUT
IN
IN
IN
IN
OUT
PB_SW
NC
NO
3_3V
IN
IN
OUT
3_3V
PCA9555
VSSVDD
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
I/O0.1
I/O0.0
I/O1.7
I/O1.6
I/O1.5
I/O1.4
I/O1.3
I/O1.2
I/O1.1
I/O1.0
INT#
SCL
A0
A2
A1
SDA
IN
IN
3_3V
Page 33
4 PORT 2 - PWR GOOD
5 PORT 4 - PWR GOOD
6 PORT 6 - PWR GOOD
-----------------------
3 PORT 6 - FORCE ON
2 PORT 4 - FORCE ON
1 PORT 2 - FORCE ON
-----------------------
POS DESCRIPTION
SWITCH S6
SILKSCREEN LABEL:
Fri Jun 15 14:48:02 2007 SHEET 6 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
98
10
7
11
6
12
5
13
4
14
3
15
2
16
1
S6
R85
R84 DS3
DS4
R102
R103
C39
C40
R107
R108
R110
R112
C43
C42
C41
C37
C38
R104
R105
R106
R111
R109
R113
R114
R115
26
11
22
15
48
47
20
31
6
43
44
30
19
18
7
33
37
38
4
46
17
28
9
36
1
35
2
42
45
39
40
41
24
13
21
16
25
12
23
14
29
8
27
10
32
5
34
3
U13
C33
C31
C35
C34
C36
C32
C30
C29
R83
R82
C28
C27
R101
R100
R99
R89
R91
R93
R97
R95
R90
R92
R98
R96
R86
R87
R88
R94
26
11
22
15
48
47
20
31
6
43
44
30
19
18
7
33
37
38
4
46
17
28
9
36
1
35
2
42
45
39
40
41
24
13
21
16
25
12
23
14
29
8
27
10
32
5
34
3
U12
645
11
6459
645
10
7
7
7
645
9
645
10
5
5
6
6
7
6
6
6
7
7
7
7
7
7
7
77
7
7
7
6
6
5
5
6 6
5
645
11
7
6
7
7
5
7
7
P6_PWRGDN
P2_PWRGDN
P4_PWRGDN
12V_DS
12V_DS
P2_12VSENSE
P2_12VGATE
10K
0.01UF
23.2K
1%
0.01UF
0.1UF
0.1UF
0.1UF
0.1UF
10K
10K
10K
10K
10K
10K
0.1UF
0.022UF
0.1UF
0.022UF
0.1UF
0.1UF
0.01UF
1%
23.2K
10K
10K
10K
000
0.022UF
DNP
110K
1%
0.01UF
000
10K
10K
10K
12V_DS
P4_12VOUT
DNP
DNP
P2_PWRGDN
P4_PWRGDN
P2_PFN
P4_PFN
P2_F_ON
P4_F_ON
P4_3VGATE
P2_F_ON
P6_F_ON
P4_F_ON
HOT PLUG CONTROLLERS
P6_12VSENSE
P6_12VGATE
P6_12VOUT
P4_12VGATE
P6_3VSENSE
P6_3VGATE
P6_3VOUT
P6_VAUXP2_VAUX
P4_12VSENSE
P4_VAUX
P2_3VSENSE
P24_INTN
P6_INTN
P4_PEP
P2_PEP
10K
10K
10K
10K
10K
10K
110K
0.1UF
0.1UF
5%
330 RED
330
5%
RED
P24_INTN
1%
P6_INTN
P6_PFN
P6_PWRGDN
P2_12VOUT
P6_F_ON
P2_3VGATE
P2_3VOUT
P6_PEP
P4_3VOUT
P4_3VSENSE
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN IN
SM_SW8
S1A
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S8A
S7A
S6A
S5A
S4A
S3A
S2A
3_3V3_3V
3_3V
3_3V
IN
IN
3_3V
3_3V 3_3V
OUT
OUT
OUT
IN
3_3V 3_3V
BI
BI
BI
BI
BI
BI
OUT
MIC2591B
NC3
NC2
NC1
NC0
RFILTER
GND1
GND0
INT_N
SCL
SDA
A0
A1
A2
GPI_B0
GPI_A0
FORCE_ONB_N
FORCE_ONA_N
FAULTB_N
FAULTA_N
PWRGDB_N
PWRGDA_N
CFILTERB
CFILTERA
AUXENB
AUXENA
ONB
ONA
VAUXB
VAUXA
VSTBYB
VSTBYA
IREF
3VGATEB
3VGATEA
12VGATEB
12VGATEA
3VSENSEB
3VSENSEA
12VSENSEB
12VSENSEA
12VOUTB
12VOUTA
3VOUTB
3VOUTA
3VINB
3VINA
12VINB
12VINA
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
OUT
3_3V
OUT
OUT
OUT
OUT
OUT
IN
IN
3_3V
MIC2591B
NC3
NC2
NC1
NC0
RFILTER
GND1
GND0
INT_N
SCL
SDA
A0
A1
A2
GPI_B0
GPI_A0
FORCE_ONB_N
FORCE_ONA_N
FAULTB_N
FAULTA_N
PWRGDB_N
PWRGDA_N
CFILTERB
CFILTERA
AUXENB
AUXENA
ONB
ONA
VAUXB
VAUXA
VSTBYB
VSTBYA
IREF
3VGATEB
3VGATEA
12VGATEB
12VGATEA
3VSENSEB
3VSENSEA
12VSENSEB
12VSENSEA
12VOUTB
12VOUTA
3VOUTB
3VOUTA
3VINB
3VINA
12VINB
12VINA
Page 34
Fri Jun 15 14:48:04 2007 SHEET 7 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
W15
W16
W12
W13
W9
W10
R126
R125
C49
8
7
6
5
4
3
2
1
Q5
C48
R127
R124
W14
8
7
6
5
4
3
2
1
Q6
R122
R121
C47
8
7
6
5
4
3
2
1
Q3
C46
R123
R120
8
7
6
5
4
3
2
1
Q4
W11
W8
R118
R117
C45
R119
C44
R116
8
7
6
5
4
3
2
1
Q2
8
7
6
5
4
3
2
1
Q1
6
6
6
6
6 6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
PMOSFET PMOSFETPMOSFET
12V_DS 12V_DS
5%
15
2%
0.012
6800PF
0.022UF
5%
15
0.02
2%
15
5%
6800PF
0.022UF
15
5%
2%
0.02
15
5%
2%
0.012
6800PF
5%
15
0.022UF
0.012
2%
0.02
2%
P6_PCIE_3_3AUX
P6_12V
P6_3_3V
12V_DS
P2_PCIE_3_3AUX
P2_12V
P2_3_3V
P4_PCIE_3_3AUX
P4_12V
P4_3_3V
P4_3VSENSE
P4_3VGATE
P6_12VGATE
P6_12VOUT
P6_3VOUT
P2_3VOUT
P2_3VGATE
P2_3VSENSE
P2_12VOUT
P2_12VGATE
P2_12VSENSE
P4_3VOUT
P4_12VOUT
P4_12VGATE
P4_12VSENSE
P4_VAUX
P6_3VGATE
P6_VAUX
P6_12VSENSE
P2_VAUX
HOT PLUG - MOSFETS
P6_3VSENSE
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
3_3V3_3V3_3V
BI
BI
BI
NMOSFET
S
S
S
G
D
D
D
D
BI
BI
BI
3_3VAUX
IN
SSD
D
DDS
G
BI
BI
BI
NMOSFET
S
S
S
G
D
D
D
D
BI
BI
BI
3_3VAUX
SSD
D
DDS
G
IN
3_3VAUX
IN
BI
BI
BI
BI
BI
BI
SSD
D
DDS
G
NMOSFET
S
S
S
G
D
D
D
D
Page 35
1NC
P0 ACT
P0 LINK
LABEL PINS:
3 GND
4 SMBDATA
2 SMBCLK
Fri Jun 15 14:47:57 2007 SHEET 8 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
J8
R158
R159
R162
DS23
DS24
R163
R164
C62
C65
C63
C64
B9
B8
B7
B6
B5
B4
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A8
A7
A6
A5
A4
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
P1
R161
R160
12
12
12
12
12
5
12
12
12
4
12
12
12
4
12
2
5
12
12
12
12
12
491011
5
124910
11
P0_3_3V
P0_3_3V
10UF
25V
P0_PETN0
P0_PETN2
P0_PETP3
P0_PERN3
DNP
DNP
P0_PERN1
P0_WAKE_N
P0_PERN2
P0_PETP2
P0_PETN1
P0_REFCLKN
P0_PETP1
P0_PETP0
P0_PETN3
PORT 0 UPSTREAM EDGE CONN.
P0_REFCLKP
P0_PERP0
PERST_N
P0_ACTIVEN
P0_PERP1
P0_PERP3
P0_PERP2
1K
1K
P0_PERN0
M_SSMBCLK
P0_LINKUPN
DNP
5%
330
10UF
25V
10UF
25V
10UF
25V
GRN
GRN330
5%
M_SSMBDATA
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUT
OUT
IN
3_3VAUX
12_0V
IN
IN
OUT
12_0V
3_3V
3_3V
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
PCIE_X4_EDGE
JTAG_TDI
JTAG_TCK
GND
GND
RSVD
GND
GND
PETP3
GND
PRSTN2#
GND
PETN2
PETN0
PETP0
GND
GND
PRSTN2#
PETP1
PETN1
PETP2
GND
RSVD
WAKE#
JTAG_TRSTN
3.3VAUX
GND
+3.3V
SMDAT
SMCLK
RSVD
+12V
+12V
GND
RSVD
PERN3
GND
PERP3
GND
GND
PERP2
PERN2
GND
PERN1
GND
RSVD
GND
PERP1
PERN0
GND
PERP0
GND
GND
+3.3V
PERST#
+3.3V
JTAG_TMS
JTAG_TDO
GND
+12V
+12V
PRSTN1#
PETN3
REFCLK-
REFCLK+
OUT
OUT
Page 36
P2 PWR
P2 PGOOD
P2 LINK
P2 ACT
P2 ATTN
Fri Jun 15 14:47:57 2007 SHEET 9 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
R157
DS22
DS17
DS18
R152
R153
DS21
R155
R154
R156
DS20
DS19
R148
R149
R150
R151
C58
C59
W19
C60
C61
B9
B82
B81
B80
B8
B79
B78
B77
B76
B75
B74
B73
B72
B71
B70
B7
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B6
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B5
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B4
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A82
A81
A80
A8
A79
A78
A77
A76
A75
A74
A73
A72
A71
A70
A7
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A6
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A5
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A4
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J4
5
5
12
12
4
4
9
12
12
12
12
12
12
5
12
12
12
12
12
12
12
12
12
81241011
21011
12
5
5
5
645
9
8
12410
11
25V
P2_LINKUPN
P2_ACTIVEN
P2_PERP1
P2_PERN3
P2_REFCLKN
P2_REFCLKP
P2_PERST_N
P2_PERP0
P2_PERN0
P2_PERN1
P2_PERN2
P2_PERP2
P2_PERP3
P2_WAKE_N
P2_PETP2
P2_PETN1
P2_PETP1
P2_PETP0
P2_PETN0
P2_PETN2
P2_PETP3
P2_PETN3
P2_PCIE_3_3AUX
PORT 2 CONNECTOR
0%
0
GRN
GRN
5%
330
330
5%
GRN
5%
330
5%
330
GRN
YEL
5%
5.1K
10UF
10UF
25V
10UF
25V
10UF
25V
DNP
DNP
P2_12V
P2_3_3V
P2_12V
P2_3_3V
5%
330
GRN
M_P2_PERST_N
330
M_SSMBDATA
M_PERSTN
P2_PDN
5%
P2_AIN
P2_PIN
P2_PWRGDN
P2_PERST_N
M_SSMBCLK
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUT
OUT
IN
IN
OUT
PCI_X16_CONN
PETP12
GND
GND
PERN15
PERP15
GND
GND
PERN14
PERP14
GND
GND
PERN13
PERP13
GND
GND
PERN12
PERP12
GND
GND
PERN11
PERP11
GND
GND
PERN10
PERP10
GND
GND
PERN9
PERP9
GND
GND
PERN8
PERT8
GND
RSVD
RSVD
PRSTN2#
GND
PETN15
PETP15
GND
GND
PETN14
PETP14
GND
GND
PETN13
PETP13
GND
GND
PETN12
GND
PETN11
PETP11
GND
GND
PETN10
PETP10
GND
GND
PETN9
PETP9
GND
GND
PETN8
PETP8
GND GND
GND
PERN3
RSVD
RSVD
GND
PERN4
PERP4
GND
GND
PERP5
GND
PERN5
GND
PERP6
PERN6
GND
GND
PERP7
PERN7
GND
PETP4
PRSTN2#
PETN4
RSVD
GND
PETP5
GND
GND
PETN5
GND
GND
GND
PETN6
PETP6
PRSTN2#
PETN7
GND
PETP7
REFCLK-
REFCLK+
PRSTN1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
PERST#
+3.3V
GND
GND
PERP0
GND
PERN0
PERP1
GND
RSVD
GND
PERN1
GND
PERN2
PERP2
GND
GND
PERP3
GND
+12V
+12V
RSVD
SMCLK
SMDAT
+3.3V
GND
3.3VAUX
JTAG1
WAKE#
RSVD
GND
PETP2
PETN1
PETP1
PRSTN2#
GND
GND
PETP0
PETN0
PETN2
GND
PETP3
PETN3
GND
GND
GND
GND
IN
IN
IN
3_3V
IN
IN
OUT
3_3V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
Page 37
P4 ATTN
P4 ACT
P4 PWR
P4 PGOOD
P4 LINK
Fri Jun 15 14:48:04 2007 SHEET 10 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
R137
DS10
DS5R132
DS6R133
R136
DS9
R134 DS7
DS8R135
R128
C51
C50
C53
C52
W17
B9
B82
B81
B80
B8
B79
B78
B77
B76
B75
B74
B73
B72
B71
B70
B7
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B6
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B5
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B4
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A82
A81
A80
A8
A79
A78
A77
A76
A75
A74
A73
A72
A71
A70
A7
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A6
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A5
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A4
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J2
R129
R130
R131
12
4
4
10
12
12
12
12
12
12
12
5
12
12
12
12
12
12
12
12
5
5
10
12
645
5
5
29
11
12
5
8
124911
81249
11
P4_12V
P4_PERN3
P4_REFCLKN
P4_REFCLKP
P4_PERST_N
P4_PERP0
P4_PERN0
P4_PERP1
P4_PERN1
P4_PERN2
P4_PERP2
P4_PERP3
P4_WAKE_N
P4_PETP2
P4_PETN1
P4_PETP1
P4_PETP0
P4_PETN0
P4_PETN2
P4_PETP3
P4_PETN3
5%
5.1K
330
5%
GRN
YEL
5%
330
GRN
10UF
25V
10UF
25V
10UF
25V
10UF
25V
P4_12V
P4_3_3V
P4_PCIE_3_3AUX
P4_3_3V
DNP
DNP
GRN
330
5%
P4_ACTIVEN
P4_AIN
GRN
P4_PERST_N
M_P4_PERST_N
PORT 4 CONNECTOR
P4_PWRGDN
P4_PIN
P4_LINKUPN
330
M_PERSTN
P4_PDN
0%
0
M_SSMBDATA
M_SSMBCLK
GRN
5%
330
5%
5%
330
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
3_3V
IN
IN
3_3V
OUT
IN
IN
PCI_X16_CONN
PETP12
GND
GND
PERN15
PERP15
GND
GND
PERN14
PERP14
GND
GND
PERN13
PERP13
GND
GND
PERN12
PERP12
GND
GND
PERN11
PERP11
GND
GND
PERN10
PERP10
GND
GND
PERN9
PERP9
GND
GND
PERN8
PERT8
GND
RSVD
RSVD
PRSTN2#
GND
PETN15
PETP15
GND
GND
PETN14
PETP14
GND
GND
PETN13
PETP13
GND
GND
PETN12
GND
PETN11
PETP11
GND
GND
PETN10
PETP10
GND
GND
PETN9
PETP9
GND
GND
PETN8
PETP8
GND GND
GND
PERN3
RSVD
RSVD
GND
PERN4
PERP4
GND
GND
PERP5
GND
PERN5
GND
PERP6
PERN6
GND
GND
PERP7
PERN7
GND
PETP4
PRSTN2#
PETN4
RSVD
GND
PETP5
GND
GND
PETN5
GND
GND
GND
PETN6
PETP6
PRSTN2#
PETN7
GND
PETP7
REFCLK-
REFCLK+
PRSTN1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
PERST#
+3.3V
GND
GND
PERP0
GND
PERN0
PERP1
GND
RSVD
GND
PERN1
GND
PERN2
PERP2
GND
GND
PERP3
GND
+12V
+12V
RSVD
SMCLK
SMDAT
+3.3V
GND
3.3VAUX
JTAG1
WAKE#
RSVD
GND
PETP2
PETN1
PETP1
PRSTN2#
GND
GND
PETP0
PETN0
PETN2
GND
PETP3
PETN3
GND
GND
GND
GND
OUT
IN
IN
IN
IN
IN
IN
IN
Page 38
P6 LINK
P6 PGOOD
P6 PWR
P6 ATTN
P6 ACT
Fri Jun 15 14:48:05 2007 SHEET 11 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
R147
DS16
DS15
DS11
DS12
R142
R143
R146
R145
R144 DS13
DS14
R138
R139
R140
C54
C55
W18
C56
R141
C57
B9
B82
B81
B80
B8
B79
B78
B77
B76
B75
B74
B73
B72
B71
B70
B7
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B6
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B5
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B4
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A82
A81
A80
A8
A79
A78
A77
A76
A75
A74
A73
A72
A71
A70
A7
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A6
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A5
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A4
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J3
12
12
4
12
12
81249
10
645
5
5
8
124910
29
1012
11
12
5
5
5
12
12
12
12
12
12
12
5
12
12
12
12
11
4
12
0
0%
5%
5.1K
GRN
YEL
5%
330
5%
330
5%
330
5%
330
GRN
GRN
GRN
10UF
25V
10UF
25V
10UF
25V
10UF
25V
DNP
DNP
P6_3_3V
P6_12V
P6_PCIE_3_3AUX
P6_3_3V
P6_12V
P6_PETP0
P6_PERP2
P6_REFCLKP
GRN
330
5%
P6_PERN1
P6_PERP1
330
5%
PORT 6 CONNECTOR
M_SSMBCLK
P6_PWRGDN
P6_LINKUPN
P6_ACTIVEN
M_SSMBDATA
M_PERSTN
P6_PERST_N
M_P6_PERST_N
P6_PDN
P6_PIN
P6_AIN
P6_PETN3
P6_PETP3
P6_PETN2
P6_PETN0
P6_PETP1
P6_PETN1
P6_PETP2
P6_WAKE_N
P6_PERP3
P6_PERN2
P6_PERN0
P6_PERP0
P6_PERST_N
P6_REFCLKN
P6_PERN3
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
IN
3_3V
IN
IN
OUT
3_3V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
PCI_X16_CONN
PETP12
GND
GND
PERN15
PERP15
GND
GND
PERN14
PERP14
GND
GND
PERN13
PERP13
GND
GND
PERN12
PERP12
GND
GND
PERN11
PERP11
GND
GND
PERN10
PERP10
GND
GND
PERN9
PERP9
GND
GND
PERN8
PERT8
GND
RSVD
RSVD
PRSTN2#
GND
PETN15
PETP15
GND
GND
PETN14
PETP14
GND
GND
PETN13
PETP13
GND
GND
PETN12
GND
PETN11
PETP11
GND
GND
PETN10
PETP10
GND
GND
PETN9
PETP9
GND
GND
PETN8
PETP8
GND GND
GND
PERN3
RSVD
RSVD
GND
PERN4
PERP4
GND
GND
PERP5
GND
PERN5
GND
PERP6
PERN6
GND
GND
PERP7
PERN7
GND
PETP4
PRSTN2#
PETN4
RSVD
GND
PETP5
GND
GND
PETN5
GND
GND
GND
PETN6
PETP6
PRSTN2#
PETN7
GND
PETP7
REFCLK-
REFCLK+
PRSTN1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
PERST#
+3.3V
GND
GND
PERP0
GND
PERN0
PERP1
GND
RSVD
GND
PERN1
GND
PERN2
PERP2
GND
GND
PERP3
GND
+12V
+12V
RSVD
SMCLK
SMDAT
+3.3V
GND
3.3VAUX
JTAG1
WAKE#
RSVD
GND
PETP2
PETN1
PETP1
PRSTN2#
GND
GND
PETP0
PETN0
PETN2
GND
PETP3
PETN3
GND
GND
GND
GND
Page 39
GPIO15
GPIO5
GPIO3
LABEL LEDS:
GPIO8
GPIO6
GPIO10
GPIO12
GPIO9
SILKSCREEN
Fri Jun 15 14:47:58 2007 SHEET 12 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
TP14
TP13
TP12
R169
R168
R167
R166
R165
R175
R176
R177
R170
R171
R172
R173
R174
DS32
DS31
DS30
DS29
DS28
R185
R184
R183
R182
R181
DS27
DS26
DS25
R180
R178
R179
C2
C1
B1
B2
B3
B4
C3
C4
B5
C5
B6
B7
B8
T2
U2
T4
Y1
W1
A20
A21
B21
C21
D21
C20
D20
E21
E20
F21
G21
H21
Y21
Y22
AA22
AA21
U1
R210
C7
C10
C16
C19
C6
C9
C15
C18
A5
A8
A14
A17
A6
A9
A15
A18
G20
K20
T20
W20
F20
J20
R20
V20
E22
H22
P22
U22
F22
J22
R22
V22
T3
N3
G3
D3
U3
P3
H3
E3
V1
R1
J1
F1
U1
P1
H1
E1
Y16
Y13
Y7
Y4
Y17
Y14
Y8
Y5
AB18
AB15
AB9
AB6
AB17
AB14
AB8
AB5
U1
R214
R213
R212
R211
AA18
Y18
AA17
Y20
B20
Y19
AB11
AB12
B11
L21
M2
AA12
B10
K21
N2
AA13
AA20
AA19
AA15
AA16
U1
R194
R195
R196
W20
7
8
5
6
4
3
2
1
U14
R209
9
87
65
43
2
10
1
J5
R215
R208
R206
R207
R205
98
10
7
11
6
12
5
13
4
14
3
15
2
16
1
S8
R203
R204
R202
R201
R200
R198
R199
R197
98
10
7
11
6
12
5
13
4
14
3
15
2
16
1
S7
R193
R192
R191
R190
R188
R189
R186
R187
C221
C219
C220
C218
C202
C205
C203
C204
C196
C197
C195
C194
C211
C210
C213
C212
C201
C200
C217
C199
C216
C214
C215
C198
C193
C192
C209
C191
C190
C208
C206
C207
P0_PERN0
P0_PERP0
P0_PERN1
P0_PERP1
M_SDA
1K
M_TCK
M_TDI
M_TMS
M_TDO
YEL
GRN
GRN
GRN
330
5%
330
5%
330
330
5%
5%
330
5%
5%
5%
M_MSMBADDR1
M_MSMBADDR2
M_MSMBADDR0
1K
2.7K
5%
M_TMS
M_TCK
M_TDO
M_TDI
JTAG_RST_N
33
5%
33
1K
DNP
DNP
DNP
DNP
DNP
0
0
0
0
0
M_MSMBSMODE
M_MSMBADDR0
M_SCL
M_SSMBCLK
M_SSMBDATA
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
P0_PETP2
P0_PETN1
P0_PETN2
P0_PETP3
P2_PETP0
P0_PETN3
P2_PETN0
P2_PETP3
P4_PETP0
P4_PETP1
P4_PETP2
P4_PETP3
P4_PETN0
P2_PETN3
P4_PETN1
P4_PETN2
P4_PETN3
P6_PETN1
P6_PETP0
P6_PETP1
P6_PETP2
P6_PETP3
P6_PETN0
P6_PETN2
P6_PETN3
0.1UF
3.01K
1%
3.01K
1%
1%
3.01K
3.01K
1%
M_REFCLK1N
M_REFCLKM
M_REFCLK1P
M_CCLKUS
M_CCLKDS
M_RSTHALT
M_PERSTN
M_SWMODE0
M_SWMODE1
M_SWMODE2
89HPES16T4G2 - EEPROM,JTAG
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
M_SWMODE0
M_SWMODE1
M_CCLKDS
M_CCLKUS
M_MSMBSMODE
M_RSTHALT
M_REFCLKM
M_SWMODE2
M_MSMBADDR0
M_MSMBADDR1
M_MSMBADDR2
5%
10K
M_MSMBADDR1
M_MSMBADDR2
1K
1K
1K
1K
330
5%
330
5%
330
5%
GRN
GRN
GRN
GRN
GRN
10K
10K
10K
5%
52-298-000
P0_PETP1
P0_PETN0
P0_PETP0
M_P6_PERST_N
M_SDA
M_SCL
JTAG_RST_N
M_P2_PERST_N
M_P4_PERST_N
M_IOINTN0
M_IOINTN2
YEL
YEL
M_GPEN
12
5
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
5
1110948
1110948
8
8
8
8
9
9
9
8
9
9
9
9
10
10
10
10
10
9
10
10
10
11
11
11
11
11
11
11
11
8
4
12
4
12
12
12
111092
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
8
8
8
11
5
12
12
5
12
9
10
5
5
8
8
8
8
8
8
8
9
9
9
9
9
10
10
10
10
10
10
10
11
11
11
11
11
11
10
11
11
9
9
9
P2_PETN2
P2_PETP2
P2_PETN1
P2_PETP1
0.1UF
P0_PERP3
P0_PERN3
P0_PERP2
P0_PERN2
P2_PERN0
P2_PERP0
P2_PERN1
P2_PERP1
P2_PERN2
P2_PERP2
P2_PERN3
P2_PERP3
P4_PERN0
P4_PERP0
P4_PERN1
P4_PERP1
P4_PERN2
P4_PERP2
P4_PERN3
P4_PERP3
P6_PERN0
P6_PERP0
P6_PERN1
P6_PERP1
P6_PERN2
P6_PERP2
P6_PERN3
P6_PERP3
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
BI
BI
IN
BI
IN
IN
IN
IN
OUT
IN
IN
OUT
IN
OUT
IN
OUT
IN
IN
3_3V
3_3V
89HPES16T4G2 (2 of 4)
JTAG_TRST_N
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO09
GPIO08
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
GPIO02
GPIO01
GPIO00
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
SSMBDAT
SSMBCLK
SSMBADDR1
SSMBADDR2
SSMBADDR3
SSMBADDR5
MSMBDAT
MSMBCLK
MSMBSMODE
MSMBADDR4
MSMBADDR1
MSMBADDR2
MSMBADDR3
IN
IN
IN
IN
IN
IN
IN
IN
89HPES16T4G2 (3 of 4)
PE6TN0
PE6TP0
PE6TN1
PE6TP1
PE6TN2
PE6TP2
PE6TN3
PE6TP3
PE4TN0
PE4TP0
PE4TN1
PE4TP1
PE4TN2
PE4TP2
PE4TN3
PE4TP3
PE2TN0
PE2TP0
PE2TN1
PE2TP1
PE2TN2
PE2TP2
PE2TN3
PE2TP3
PE0TN0
PE0TP0
PE0TN1
PE0TP1
PE0TN2
PE0TP2
PE0TN3
PE0TP3
PE6RN3
PE6RP3
PE6RN2
PE6RP2
PE6RN1
PE6RP1
PE6RN0
PE6RP0
PE4RN3
PE4RP3
PE4RN2
PE4RP2
PE4RN1
PE4RP1
PE4RN0
PE4RP0
PE2RN3
PE2RP3
PE2RN2
PE2RP2
PE2RN1
PE2RP1
PE2RN0
PE2RP0
PE0RN3
PE0RP3
PE0RN2
PE0RP2
PE0RN1
PE0RP1
PE0RN0
PE0RP0
89HPES16T4G2 (1 of 4)
REFCLKM
SWMODE2
SWMODE1
SWMODE0
RSTHALT
PERSTN
P6_REFRES
P4_REFRES
P2_REFRES
P0_REFRES
CCLKDS
CCLKUS
PE0REFCLKP
PE0REFCLKN
NC6
NC5
NC3
NC4
NC1
NC2
IN
IN
IN
IN
IN
IN
IN
3_3V 3_3V
24LC512
SCL
A2
A1
A0
SDA
WP
GND
VCC
IN
IN
IN
IN
JTAG HEADER
1
3
10
8
6
4
2
9
7
5
3_3V
IN
SM_SW8
S1A
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S8A
S7A
S6A
S5A
S4A
S3A
S2A
OUT
OUT
OUT
OUT
3_3V
3_3V
SM_SW8
S1A
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S8A
S7A
S6A
S5A
S4A
S3A
S2A
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
Page 40
VDDPEHA
VDDPEA
VDDPETA
VDDCORE
VDDIO
Fri Jun 15 14:48:05 2007 SHEET 13 OF 13
1.0
18-634-000
B.OH
2007
K. LEUNG
STGSCH-00114
89EBPES16T4G2
B
65432
1
M1
C70
C75
C80
C85
C90
C100
C117
C122
C69
C74
C68
C73
C79
C78
C84
C89
C94
C99
C104
C108
C112
C116
C121
C126
C83
C88
C93
C98
C103
C107
C111
C115
C120
C125
C67
C72
C66
C71
C76C77
C82
C87
C92
C97
C102
C106
C110
C114
C119
C124
C81
C86
C91
C96
C101
C105
C109
C113
C118
C123
C127
C132
C137
C147
C142
C157
C152
C160
C163
C166
C169
C172
C174
C176
C131
C136
C141
C146
C151
C156
C130
C135
C140
C150
C145
C155
C129
C134
C139
C149
C144
C154
C159
C162
C165
C168
C128
C133
C138
C143
C148
C153
C158
C161
C164
C167
C171
C170
C173
C175
C177
C178
C179
C180
C181
C182
C183
C184
C185
C186
C187
C188
C189
C95
H2
A12J2A11
M22
L22
L1M1W2V2V3
W3
A22L2B22
G22
W22
AB22
M21
P21
R21
U21
V21
AB21
AA2
L20
N20
P20
B19
F19
J19
M19
P19
U19
AB19
AB2
B18
B17
D17
W17
B15
B14
C14
D14
W14
C13A1B12
D12
Y12
C11
W11
AA11
Y10
D9
W9
Y9
D1
AA9
AA8
D6
W6
AA6
AA5
F4
J4
L4
P4
AA1
U4
AA4
J3
K3
M3
AA3
AB3
A2
E2
F2
AB1
W13
D10W8D7D4H4N4R3
D19
G19
K19
R19
W19
W16
D15
W4
AA10
B9
AA7
Y6
F3
L3
G2
J21
K2
N21
T21
M20
U20
C17
B16
AA14
B13
C12
Y11
P2
W10
D8
W7
D5
G4
K4
M4
E19
R4
H19
L19
N19
T19
W18
D16
W15
D13
W12
D11
V4
AB20
A19
Y15
C8
A3
Y3
D2
R2
C22
W21
H20
Y2
AB7W5A4E4AB4G1K1
D22
K22
N22N1T22
V19
D18
A16
AB16
A13
AB13
A10
AB10
A7
T1
U1
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
47UF
10V
47UF
10V
1UF
16V
0.1UF
0.1UF
16V
1UF
10V
47UF
10V
47UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1UF
10V
47UF
16V
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10V
47UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
47UF
10V
0.1UF
47UF
10V
0.1UF
0.1UF
0.1UF
0.1UF
89HPES16T4G2 - POWER
0.1UF
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
+1.0V_VDDA
+2.5V_VDDHA
+1.0V_VDDTA
+1.0V_CORE
STIFF_6P
3_3VIO
3_3V
+1.0V_VDDA
+2.5V_VDDHA +1.0V_CORE +1.0V_VDDTA
89HPES16T4G2 (4 of 4)
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VDDCORE22
VDDCORE21
VDDCORE19
VDDCORE20
VSS44
VSS17
VSS16
VSS15
VSS41
VSS42
VSS48
VSS49
VDDCORE18
VDDCORE17
VDDCORE16
VDDCORE15
VDDCORE14
VDDCORE13
VDDCORE12
VDDCORE11
VDDCORE10
VDDCORE9
VDDCORE8
VDDCORE7
VDDCORE6
VDDCORE5
VDDCORE4
VDDCORE3
VDDCORE2
VDDCORE1
VDDPETA7
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS47
VSS46
VSS45
VSS43
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VDDPEHA20
VDDPEHA19
VDDPEHA18
VDDPEHA17
VDDPEHA16
VDDPEHA15
VDDPEHA14
VDDPEHA13
VDDPEHA12
VDDPEHA10
VDDPEHA9
VDDPEHA8
VDDPEHA7
VDDPEHA6
VDDPEHA5
VDDPEHA4
VDDPEHA3
VDDPEHA2
VDDPEHA1
VDDPEA20
VDDPEA19
VDDPEA18
VDDPEA17
VDDPEA16
VDDPEA13
VDDPEA12
VDDPEA11
VDDPEA10
VDDPEA9
VDDPEA8
VDDPEA7
VDDPEA6
VDDPEA5
VDDPEA4
VDDPEA3
VDDPEA2
VDDPEA1
VDDIO12
VDDIO11
VDDIO10
VDDIO9
VDDIO8
VDDIO7
VDDIO6
VDDIO5
VDDIO4
VDDIO3
VDDIO2
VDDIO1
VDDPETA2
VDDPETA1
VDDPETA3
VDDPETA5
VDDPETA4
VDDPETA8
VDDPETA6
VDDPETA10
VDDPETA9
VDDPETA12
VDDPETA13
VDDPETA11
VDDPETA14
VDDPETA15
VDDPETA16
VDDPEA15
VDDPEA14
VDDPEHA11
3_3VIO
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