IDT 89EBPES16NT2 User Manual

®

IDT™ 89EBPES16NT2

Evaluation Board Manual

(Eval Board: 18-642-000)

November 2007

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: [phone] • [phone] • FAX: [phone]

©2007 Integrated Device Technology, Inc.

Printed in U.S.A.

Integrated Device Technology, Inc. reserves t h e right to make changes to its produc ts or specifications at any time, without notice, in order to improve design or perfor mance
and to supply the best possible product. IDT does not assume any responsibility for use of any circui try described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

DISCLAIMER

Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analy sis be performed.

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agr eement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for su rgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly us ed in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a significant injury to the user.

2. A critical co mpo nent is an y com pon en t s of a lif e sup po rt dev ice or sy s te m who se f ai lu re t o perform can be re aso na bl y exp ect ed to cause the failure of the life support device
or system, or to affect its safety or effectiveness.

IDT, the IDT lo go, and Integrated Device Technology are trademarks or registered trademarks of I ntegrated Device Technology, Inc.

LIFE SUPPORT POLICY

Table of Contents

®

Notes

Description of the EB16NT2 Eval Board

Introduction.....................................................................................................................................1-1

Board Features...............................................................................................................................1-2

Hardware................................................................................................................................1-2

Software..................................................................................................................................1-2

Other.......................................................................................................................................1-2

Revision History..............................................................................................................................1-2

Installation of the EB16NT2 Eval Board

EB16NT2 Installation......................................................................................................................2-1

PCI Express Adapter Card..............................................................................................................2-1

Hardware Description.....................................................................................................................2-1

Reference Clocks............................................................................................................................2-2

Power Sources................................................................................................................................2-3

PCI Express Serial Data Transmit Termination Voltage Converter........................................2-3

PCI Express Digital Power Voltage Converter........................................................................2-3

PCI Express Analog Power Voltage Converter......................................................................2-3

Core Logic Voltage Converter................................................................................................2-3

3.3V I/O Power Module...........................................................................................................2-3

Power-up Sequence...............................................................................................................2-3

Required Jumpers..................................................................................................................2-3

Reset...............................................................................................................................................2-3

Fundamental Reset................................................................................................................2-4

Boot Configuration Vector...............................................................................................................2-4

SMBus Interfaces............................................................................................................................2-5

SMBus Slave Interface...........................................................................................................2-6

SMBus Master Interface.........................................................................................................2-6

JTAG Header..................................................................................................................................2-7

Miscellaneous Jumpers, Headers...................................................................................................2-7

LEDs...............................................................................................................................................2-7

PCI Express Edge Connector.........................................................................................................2-8

PCI Express Cable x8 Wire Connections...............................................................................2-9

PCI Express Cable x8 Connector Definition.........................................................................2-11

EB16NT2 Eval Board Figure.........................................................................................................2-13

Software for the EB16NT2 Eval Board

Introduction.....................................................................................................................................3-1

Device Management Software........................................................................................................3-1

Schematics

Schematics.....................................................................................................................................4-1

EB16NT2 Eval Board Manual i November 13, 2007

IDT Table of Contents

Notes

EB16NT2 Eval Board Manual ii November 13, 2007

List of Tables

®

Notes

Table 2.1 Clock Source Selection .......................................................................................................2-2

Table 2.2 Clock Frequency Selection .................................................................................................2-2

Table 2.3 SMA Connectors - Onboard Reference Clock ....................................................................2-2

Table 2.4 Boot Configuration Vector Signals ......................................................................................2-4

Table 2.5 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1) ...........................................2-5

Table 2.6 Slave SMBus Interface Connector ......................................................................................2-6

Table 2.7 SMBus Slave Interface Address Configuration ...................................................................2-6

Table 2.8 JTAG Connector Pin Out ....................................................................................................2-7

Table 2.9 Miscellaneous Jumpers, Headers .......................................................................................2-7

Table 2.10 LED Indicators ....................................................................................................................2-7

Table 2.11 PCI Express x8 Edge Connector Pinout .............................................................................2-8

Table 2.12 PCI Express Cable x8 Wire Connections ...........................................................................2-9

Table 2.13 PCI Express x8 Connector Definitions ..............................................................................2-11

EB16NT2 Eval Board Manual iii November 13, 2007

IDT List of Tables

Notes

EB16NT2 Eval Board Manual iv November 13, 2007

List of Figures

®

Notes

Figure 1.1 Function Block Diagram of the EB16NT2 Eval Board ........................................................1-1

Figure 2.1 PCIe Adapter Card .............................................................................................................2-1

EB16NT2 Eval Board Manual v November 13, 2007

IDT List of Figures

Notes

EB16NT2 Eval Board Manual vi November 13, 2007

Chapter 1

Description of the EB16NT2

Eval Board

®

Notes

Introduction

The 89HPES16NT2 switch (also referred to as PES16NT2 in this manual) is a member of IDT’s PCI
Express® standard (PCIe®) based line of products. It is a 16-lane, 2-port peripheral chip that provides high­performance switching and non-transparent bridging (NTB) function between an upstream port and an NTB
downstream port.

The 89EBPES16NT2 Evaluation Board (also referred to as EB16NT2 in this manual) provides an evalu­ation platform for the PES16NT2 switch. It is designed to function as an add-on card to be plugged into a x8
PCIe slot available on a motherboard hosting an appropriate root complex, microprocessor(s), and an NTB
downstream port to be connected to another root complex, microprocessor(s) via a PCI Express cable. The
EB16NT2 is a vehicle to test and evaluate the functionality of the PES16NT2 chip. Customers can use this
board to get a headstart on software development prior to the arrival of their own hardware. The EB16NT2
is also used by IDT to reproduce system-level hardware or software issues reported by customers. Figure

1.1 illustrates the functional block diagram representing the main parts of the EB16NT2 board.

JTAG

Header

Main

Reset

Clock

Fanout

SSC Clock
Buffer

25 MHz

EEPROM

24LC512

SMBUS
HEADER

PCI Express
Switch

PES16NT2

SMBus

PCIe x8 Upstream Edge

Figure 1.1 Function Block Diagram of the EB16NT2 Eval Board

x8

x8

PTH08T240

Power

Module

+12V, +3.3V, +1.5V, +1.0V

x8 PCI Express Connector

Voltages on board

EB16NT2 Eval Board Manual 1 - 1 November 13, 2007

IDT Description of the EB16NT2 Eval Board

Notes

Board Features

Hardware



PES16NT2 PCIe 2-port Non-Transparent switch

– Two ports, 16 PCIe lanes
– PCIe Base Specification Revision 1.0a compliant
– 8 GBps (64Gbps) aggregate switching capacity
– Up to 2048 byte maximum Payload Size
– Automatic lane reversal and polarity inversion supported on all lanes
– Automatic per port link width negotiation to x8, x4, x2, x1
– Load configuration from an optional serial EEPROM via SMBUS



Upstream, Transparent/Non-Transparent Port

– One edge connector on the upstream port, to be plugged into a slot with x8 capable on a host

motherboard

– Transparent or Non-Transparent port via x8 PCI Express connector



Numerous user selectable configurations set using onboard jumpers and DIP-switches

– Source of clock - host clock or onboard clock generator
– Two clock rates
– Boot mode selection



SMBUS Slave Interface (4 pin header)



SMBUS Master Interface connected to the Serial EEPROMs through I/O expander



Push button for Warm Reset



Several LEDs to display status, reset, power, etc.



One 10-pin JTAG connector (pitch 2.54 mm x 2.54 mm)

Software

There is no software or firmware executed on the board in transparent mode. However, useful software
is provided along with the Evaluation Board to facilitate configuration and evaluation of the PES16NT2
within host systems running popular operating systems. In non-transparent mode, IDT provides Windows
XP or a Linux device driver for PES16NT2 Non-Transparent Bridge endpoints. This driver includes two
separate drivers, PCI endpoint driver and NDIS Ethernet miniport driver. Please contact [e-mail]
for additional information.



Installation programs

– Operating Systems Supported: Windows2000, WindowsXP, Linux



GUI-based application for Windows and Linux

– Allows users to view and modify registers in the PES16NT2
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.

Other



A metal bracket is required to firmly hold in place the four endpoints plugged into the EB16NT2
board.



SMBUS cable may be required for certain evaluation exercises.



SMA connectors are provided on the EB16NT2 board for specific test points.

Revision History

November 13, 2007: Initial publication of board manual.

EB16NT2 Eval Board Manual 1 - 2 November 13, 2007

Chapter 2

Installation of the EB16NT2

Eval Board

®

Notes

EB16NT2 Installation

This chapter discusses the steps required to configure and install the EB16NT2 evaluation board. All
available DIP switches and jumper configurations are explained in detail.

The primary installation steps are:

1. Configure jumper/switch options suitable for the evaluation or application requirements.

2. Insert the evaluation board into the host system (motherboard with root complex chipset).

3. Connect the NTB port to a remote system via a PCI Express® cable. An PCI Express adapter card
to PCI Express Cable connector can be used on a remote system.

4. Apply power to the host system.

The EB16NT2 board is shipped with all jumpers and switches configured to their default settings. In

most cases, the board does not require further modification or setup.

PCI Express Adapter Card

The PCI Express adapter card is an x8 link PCI Express card. It can be instal led in a remote system. A
(x8 lane) PCIe® cable is used to connect a remote system to EB16NT2 NTB port. See Figure 2.1 for the
graphical presentation of this connection.

PCIe Connector

x8 (NTB )

PES16NT2

x8 (upstream)

(x8) PCIe Cable

EB16NT2 Eval Board Install in Host PC PCI Express Adapter Card Install

Figure 2.1 PCIe Adapter Card

Tx
Rx

in Remote P C

x8

Hardware Description

The 89HPES16NT2 is a member of the IDT PRECISE™ family of PCI Express switching solutions offering
the next-generation I/O interconnect standard. The PES16NT2 is a 16-lane, 2-port peripheral chip that pro­vides high-performance switching and non-transparent bridging (NTB) functions between a PCIe upstream

EB16NT2 Eval Board Manual 2 - 1 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

port and an NTB downstream port. The PES16NT2 is a part of the IDT PCIe System Interconnect
Products family and is intended to be used with IDT PCIe System Interconnect Switches. Together, the
chipset targets multi-host and intelligent I/O applications such as communications, storage, and blade serv­ers, where inter-domain communication is required.

The EB16NT2 non-transparent port is accessible through x8 PCI Express cable connectors.

Basic requirements for the board to run are:

– Host system with a PCI Express root complex supporting x8 configuration through a P CI Express

x8 slot.

– A secondary remote system with a PCI Express root complex supporting x8 configuration through

a PCI Express x8 slot.

Reference Clocks

The PES16NT2 requires a pair of differential reference clocks. The EB16NT2 derives these clocks from
a common source which is user-selectable. The common source can be either the host system’s reference
clock or the onboard clock generator. Selection is made by stuffing resistors described in Table 2.1. Typical
usage model for the EB16NT2 in non-transparent mode includes two root complexes: one connects to the
upstream port and the other connects to a NTB port. Each root complex most likely will have its own clock
source. SSC (Spread Spectrum Clock) must be disabled in this configuration.

Clock Configuration Stuffing Option

W7 and W8 Clock Source

Pins 2 and 3 Onboard Reference Clock – Use onboard clock generator
Pins 1 and 2 Upstream Reference Clock – Host system provides clock (Default)

Table 2.1 Clock Source Selection

The source for the onboard clock is the ICS557-03 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB16NT2 allows selection between multiple
clock rates via DIP switches as described in Table 2.2.

Clock Frequency Switch - S2[2:1]

S2[2] S2[1] Clock Frequency

OFF OFF Reserved
OFF ON 125 MHz

ON OFF 100 MHz (Default)
ON ON <Reserved>

Table 2.2 Clock Frequency Selection

The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.3. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.

Onboard Reference Clock Output (Differential) – J2, J3

J2 Positive Reference Clock
J3 Negative Reference Clock

Table 2.3 SMA Connectors - Onboard Reference Clock

EB16NT2 Eval Board Manual 2 - 2 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

Power Sources

The EB16NT2 is powered from the upstream port slot power.

PCI Express Serial Data Transmit Termination Voltage Converter

A DC-DC converter (U6) provides a 1.5V PCI Express serial data transmit termination voltage (shown
as VPETVTT) to the PES16NT2.

PCI Express Digital Power Voltage Converter

A separate DC-DC converter (U3) provides a 1.0V PCI Express digital power voltage (VDDPE) to the
PES16NT2.

PCI Express Analog Power Voltage Converter

A separate DC-DC converter (7) provides a 1.0V PCI Express analog power voltage (shown as
VDDPEA) to the PES16NT2.

Core Logic Vo ltage Converter

A separate DC-DC converter (U1) provides the 1.0V core voltage (VDDCORE) to the PES16NT2.

3.3V I/O Power Module

A 12V to 3.3V power module (U26) provides the 3.3V I/O voltage (VDD_3V3) to the PES16NT2.

Power-up Sequence

The power-up sequence must be as following:

1. VDDIO - 3.3V

2. VDDCORE, VDDPEA, VDDPE - 1.0V

3. VTTPE - 1.5V

When powering up, each voltage level must ramp up and stabiliz e prior to applying the next voltage in
the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations
between sequential valid power level requirements. To insure that the sequencing requirements are met, a

0.015UF is used at the SOFTSTART cap on the VTTPE and VTTPEA voltage converter (U3 and U7 pin 36)
in the EB16NT2.

Required Jumpers

To deli ver power to the PES16NT2 switch, the following jumpers must be shunted: W10, W22-W25.
These jumpers were implemented so that the power consumption of the PES16NT2 can be measured.

Reset

The PES16NT2 supports two types of reset mechanisms as described in the PCI Express specification:

– Fundamental Reset: This is a system-generated reset that propagates along the PCI Express

tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES16NT2, and the endpoints.

– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to

another. Hot Reset may be initiated by software. This is further discussed in the 89HPES16NT2
User Manual. The EB16NT2 evaluation board provides seamless support for Hot Reset.

EB16NT2 Eval Board Manual 2 - 3 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

Fundamental R eset

There are two types of Fundamental Resets which may occur on the EB16NT2 evaluation board:

– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI

Express Reset (PERSTN) input pin of the PES16NT2.

– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be

initiated by two methods:

• Pressing a push-button switch (S1) located on EB16NT2 board

• The host system board IO Controller Hub asserting PERST# signal, which propagates through

the PCIe upstream edge connector of the EB16NT2. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the resistor from pin 1-2 to pin 2-3 on W27.

Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES16NT2 while power is on.

An external side fundamental reset is initiated when the switch is configured to operate in non-trans­parent mode and the PCI Express Non-Transparent Bridge Reset (PENTBRST#) signal is asserted. This
results in the resetting of the transaction, data link, and PHY layers associated with the external side of the
non-transparent bridge. The initialization of all registers associated with the external side of the non-trans­parent bridge are set to their initial values except those with a read and write when unlocked attribute and
those associated with the non-transparent bridge configuration capability structure.

Boot Configuration Vector

A boot configuration vector consisting of the signals listed in Table 2.4 is sampled by the PES16NT2
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S5 and S6 as defined in Table 2.5.

Signal Description

CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream

ports are using the same clock source as that provided to downstream devices. This pin is
used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers
for downstream ports. The value may be overridden by modifying the SCLK bit in the down­stream port’s PCIELSTS register. Default: 0x1

CCLKUS Common Clock Upstream. The assertion of this pin indicates that the upstream port is

using the same clock source as the upstream device. This pin is used as the initial value of
the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value
may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. Default: 0x1

MSMBSMODE Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus

should operate at 100 KHz instead of 400 kHz. Default: 0x0

RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the

PES16NT2 executes the reset procedure and remains in a reset state with the Master and
Slave SMBuses active. This allows software to read and write registers internal to the
device before normal device operation begins. The device exits the reset state when the
RSTHALT bit is cleared in the P0_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register.

Default: 0x0

Table 2.4 Boot Configuration Vector Signals (Part 1 of 2)

EB16NT2 Eval Board Manual 2 - 4 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

Signal Description

SWMODE[2:0] Switch Mode. These configuration pins determine the PES16NT2 switch operating mode.

Default: 0x1

0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode serial EEPROM initialization
0x7 - 0xF Reserved

Default: 0x0

REFCLKM PCI Express Reference Clock Mode Select. This signal selects the frequency of the ref-

erence clock input. Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz

MSMBADDR[2:0] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM

from which configuration information is loaded. Default: 0x0

Table 2.4 Boot Configuration Vector Signals (Part 2 of 2)

Signal Description Default

S6[1] CCLKDS OFF
S6[2] CCLKUS OFF
S6[3] SWMODE[3] ON
S6[4] SWMODE[2] ON
S6[5] SWMODE[1] ON
S6[6] SWMODE[0] ON
S6[7] Not Used ON
S6[8] Not Used ON
S5[1] MSMBADDR[4] ON
S5[2] MSMBADDR[3] ON
S5[3] MSMBADDR[2] ON
S5[4] MSMBADDR[1] ON
S5[5] REFCLKM ON
S6[6] RSTHALT# ON
S6[7] MSMBSMODE ON
S5[8] Not Used ON

Table 2.5 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1)

SMBus Interfaces

The System Management Bus (SMBus) is a two-wire interface through which various system compo-

2

nent chips can communicate. It is based on the principles of operation of I
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consists of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.

C. Implementation of the SMBus

EB16NT2 Eval Board Manual 2 - 5 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

The PES16NT2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus inter­face. The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all
software-visible registers. The Master SMBus interface provides connection to the external serial
EEPROMs used for initialization.

SMBus Slave Interface

On the PES16NT2 board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.6.

Note: The SMBus signals to the PCI Express edge connector is disabled by default. To enable
them, place 0-ohm resistors at locations R74 and R75.

.

Slave SMBus Interface Connector

J10

Pin Signal

1N/C
2SCL
3GND
4SDA

Table 2.6 Slave SMBus Interface Connector

A fixed slave SMBus address (0b1110_111) specified by the SSMBADDR[5,3:1] pins is used.

Slave Interface Address Configuration

Address Bit Signal

1 SSMBUSADDR[1]
2 SSMBUSADDR[2]
3 SSMBUSADDR[3]
40
5 SSMBUSADDR[5]
61
71

Table 2.7 SMBus Slave Interface Address Configuration

The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:

– Byte and Word Write/Read
– Block Write/Read

SMBus Master Interface

The seven bits address for the selected EEPROM device is 0b1010_000 by default.

EB16NT2 Eval Board Manual 2 - 6 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

JTAG Header

The PES16NT2 provides a JTAG connector J4 for access to the PES16NT2 JTAG interface. The
connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.8 for the JTAG Connector J4
pin out.

JTA G Connector J5

Pin Signal Direction Pin Signal Direction

1 /TRST - Test reset Input 2 GND —
3 TDI - Test data Input 4 GND —
5 TDO - Test data Output 6 GND —
7 TMS - Test mode select Input 8 GND —
9 TCK - Test clock Input 10 GND —

Table 2.8 JTAG Connector Pin Out

Miscellaneous Jumpers, Headers

Miscellaneous Jumpers, Headers

Ref.

Designator

Type Default Description

W12 Header Shunted Disable EEPROM Write protect feature (Default)

W2 Header Open Force remote (PCIe Cable) power on

W32 Header Open Tie PCIe Cable 3.3V power to on board VCC_3V3

Table 2.9 Miscellaneous Jumpers, Headers

LEDs

There are several LED indicators on the EB16NT2 which convey status feedback. A description of each
is provided in Table 2.10.

Location Color Definition

DS2 Green VCC_3V3Power indicator
DS1 Red Reset

DS4 Green GPIO0
DS29 Green GPIO3
DS30 Green GPIO5
DS31 Green GPIO7
DS33 Green GPIO2
DS34 Green GPIO4
DS35 Green GPIO5
DS29 Green GPIO9

Table 2.10 LED Indicators (Part 1 of 2)

EB16NT2 Eval Board Manual 2 - 7 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

Location Color Definition

DS30 Green GPIO10
DS31 Green GPIO12
DS32 Green GPIO15

Table 2.10 LED Indicators (Part 2 of 2)

PCI Express Edge Connector

Pin Side B Side A

1 +12V 12V power PRSNT1# Hot-Plug presence detect
2 +12V 12V power +12V 12V power
3 RSVD Reserved +12V 12V power
4 GND Ground GND Ground
5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p
6 SMDAT SMBus Data JTAG TDI (Test Data Input)
7 GND Ground JTAG TDO (Test Data Output)
8 +3.3V 3.3V power JTAG TMS (Test Mode Select)
9 JTAG1 TRST# (Test/Reset) resets

JTAG i/f
10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power
11 WAKE# Signal for Link reactivation PERST# Fundamental Reset

Mechanical Key

12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ REFCLK Reference clock
14 PETp0 Transmitter differential REFCLK- (differentia l pair)
15 PETn0 pair, Lane 0 GND Ground
16 GND Ground PERp0 Receiver differential
17 PRSNT2# Hot-Plug presence detect PERn0 pair, Lane 0
18 GND Ground GND Ground
19 PETp1 Transmitter differential RSVD Reserv ed
20 PETn1 pair, Lane 1 GND Ground
21 GND Ground PERp1 Receiver differential
22 GND Ground PERn1 pair, Lane 1
23 PETp2 Transmitter differential GND Ground
24 PETn2 pair, Lane 2 GND Ground

+3.3V 3.3V power

25 GND Ground PERp2 Receiver differential
26 GND Ground PERn2 pair, Lane 2

Table 2.11 PCI Express x8 Edge Connector Pinout (Part 1 of 2)

EB16NT2 Eval Board Manual 2 - 8 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

Pin Side B Side A

27 PETp3 Transmitter differential GND Ground
28 PETn3 pair, Lane 3 GND Ground
29 GND Ground PERp3 Receiver differential
30 RSVD Reserved PERn3 pair, Lane 3
31 PRSNT2# Hot-Plug presence detect GND Ground
32 GND Ground RSVD Reserved
33 PETp4 Transmitter differential RSVD Reserv ed
34 PETn4 pair, Lane 4 GND Ground
35 GND Ground PERp4 Receiver differential
36 GND Ground PERn4 pair, Lane 4
37 PETp5 Transmitter differential GND Ground
38 PETn5 pair, Lane 5 GND Ground
39 GND Ground PERp5 Receiver differential
40 GND Ground PERn5 pair, Lane 5
41 PETp6 Transmitter differential GND Ground
42 PETn6 pair, Lane 6 GND Ground
43 GND Ground PERp6 Receiver differential
44 GND Ground PERn6 pair, Lane 6
45 PETp7 Transmitter differential GND Ground
46 PETn7 pair, Lane 7 GND Ground
47 GND Ground PERp7 Receiver differential
48 PRSNT2# Hot-Plug presence detect PERn7 pair, Lane 7
49 GND Ground GND Ground

Table 2.11 PCI Express x8 Edge Connector Pinout (Part 2 of 2)

PCI Express Cable x8 Wire Connections

Pin# Cable Side A CableSide B Pin#

A1 A4 A7 A10 A13
A16 A22 A25 A28
A31 A34 B1 B4 B7
B10 B13 B22 B25

B28 B31 B34

A2 PETp0 Differential Pair PERp0 B2
A3 PETn0 PERn0 B3

GND Drain Wires GND

A1 A4 A7 A10 A13
A16 A22 A25 A28
A31 A34 B1 B4 B7
B10 B13 B22 B25

B28 B31 B34

A5 PETp1 Differential Pair PERp1 B5
A6 PETn1 PERn1 B6

Table 2.12 PCI Express Cable x8 Wire Connections (Part 1 of 3)

EB16NT2 Eval Board Manual 2 - 9 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

Pin# Cable Side A CableSide B Pin#

A8 PETp2 Differential Pair PERp2 B8

A9 PETn2 PERn2 B9
A11 PETp3 Differential Pair PERp3 B11
A12 PETn3 PERn3 B12
A14 CREFCLKp Differ enti al Pair CREFCLKp A14
A15 CREFCLKn CREFCLKn A15
A17 RSVD NC RSVD A17
A18 RSVD NC RSVD A18
A19 SB_RTN Hook-up Wire SB_RTN A19
A20 CPRSNT Hook-up Wire CPRSNT A20
A21 CPWRON Hook-up Wire CPWRON A21
A23 PETp4 Differential Pair PERp4 B23
A24 PETn4 PERn4 B24
A26 PETp5 Differential Pair PERp5 B26
A27 PETn5 PERn5 B27
A29 PETp6 Differential Pair PERp6 B29
A30 PETn6 PERn6 B30
A32 PETp7 Differential Pair PERp7 B32
A33 PETn7 PERn7 B33

B2 PERp0 Differential Pair PETp0 A2

B3 PERn0 PETn0 A3

B5 PERp1 Differential Pair PETp1 A5

B6 PERn1 PETn1 A6

B8 PERp2 Differential Pair PETp2 A8

B9 PERn2 PETn2 A9
B11 PERp3 Differential Pair PETp3 A11
B12 PERn3 PETn3 A12
B14 PWR NW PWR B14
B15 PWR NW PWR B15
B16 PWR NW PWR B16
B17 PWR_RTN NW PWR_RTN B17
B18 PWR_RTN NW PWR_RTN B18
B19 PWER_RTN NW PWER_RTN B19
B20 CWAKE# Hook-up Wire CWAKE# B20
B21 CPERST# Kook-up Wire CPERST# B21
B23 PERp4 Differential Pair PETp4 A23
B24 PERn4 PETn4 A24

Table 2.12 PCI Express Cable x8 Wire Connections (Part 2 of 3)

EB16NT2 Eval Board Manual 2 - 10 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

Pin# Cable Side A CableSide B Pin#

B26 PERp5 Differential Pair PETp5 A26
B27 PERn5 PETn5 A27
B29 PERp6 Differential Pair PETp6 A29
B30 PERn6 PETn6 A30
B32 PERp7 Differential Pair PETp7 A32
B33 PERn7 PETn7 A33

Backshell Chassis Ground Overall Cable Braid Backshell Chassis Ground

CableSide B Pin#

Table 2.12 PCI Express Cable x8 Wire Connections (Part 3 of 3)

PCI Express Cable x8 Connector Definition

Pin # Signal Description

A1 A4 A7 A10 A13

A16 A22 A25 A28

A31 A34 B1 B4 B7

B10 B13 B22 B25

B28 B31 B34

GND Ground Reference for Transmitter and

Receiver Lanes

A2 PETp0 Differential Pair
A3 PETn0
A5 PETp1 Differential Pair
A6 PETn1
A8 PETp2 Differential Pair

A9 PETn2
A11 PETp3 Differential Pair
A12 PETn3
A14 CREFCLKp Differential 100 MHz Cable Reference Clock
A15 CREFCLKn
A17 RSVD NC
A18 RSVD NC
A19 SB_RTN Signal Return for Single Ended Sideband Sig-

nals

A20 CPRSNT Used for detection of whether a cable is

installed and the downstream subsystem is

powered

A21 CPWRON Upstream Subsystem’s Power Valid Notifica-

tion

Table 2.13 PCI Express x8 Connector Definitions

EB16NT2 Eval Board Manual 2 - 11 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

Pin # Signal Description

A23 PETp4 Differential Pair
A24 PETn4
A26 PETp5 Differential Pair
A27 PETn5
A29 PETp6 Differential Pair
A30 PETn6
A32 PETp7 Differential Pair
A33 PETn7

B2 PERp0 Differential Pair

B3 PERn0

B5 PERp1 Differential Pair

B6 PERn1

B8 PERp2 Differential Pair

B9 PERn2
B11 PERp3 Differential Pair
B12 PERn3
B14 PWR +3.3V Power
B15 PWR +3.3V Power
B16 PWR +3.3V Power
B17 PWR_RTN Return for +3.3V Power
B18 PWR_RTN Return for +3.3V Power
B19 PWER_RTN Return for +3.3V Power
B20 CWAKE# Power Management Signal for Wakeup Events
B21 CPERST# Cable PERST#
B23 PERp4 Differential Pair
B24 PERn4
B26 PERp5 Differential Pair
B27 PERn5
B29 PERp6 Differential Pair
B30 PERn6
B32 PERp7 Differential Pair
B33 PERn7

Table 2.13 PCI Express x8 Connector Definitions

EB16NT2 Eval Board Manual 2 - 12 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

EB16NT2 Eval Board Figure

EB16NT2 Eval Board Manual 2 - 13 November 13, 2007

IDT Installation of the EB16NT2 Eval Board

Notes

EB16NT2 Eval Board Manual 2 - 14 November 13, 2007

Chapter 3

Software for the EB16NT2

Eval Board

®

Notes

Introduction

This chapter discusses some of the main features of the available software to give users a better under­standing of what can be achieved with the EB16NT2 evaluation board using the device management soft­ware.

Device management software and related user documentation are available on a CD which is included
in the Evaluation Board Kit. This information is also available on IDT’s FTP site. For more information,
contact IDT at [e-mail].

Device Management Software

The primary use of the Device Management Software package is to enable us ers of the evaluation
board to access all the registers in the PES16NT2 device. This access can be achieved using the PCI
Express in-band configuration cycles through the upstream port on the PES16NT2.

This software also enables users to save a snapshot of the current register set into a dump file which
can be used for debugging purposes. An export/import facility is also available to create and use “Configu­ration” files which can be used to initialize the switch device with specific values in specific registers.

A conversion utility is also provided to translate a configuration file into an EEPROM programmable data
structure. This enables the user to program an appropriate serial EEPROM with desirable register settings
for the PES16NT2, and then to populate that EEPROM onto the Evaluation Board. It is also possible to
program the EEPROM directly on the Evaluation Board using a feature provided by the software package.

The front end of the Device Management Software is a user-friendly Graphical User Interface which
allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the
software in “simulation” mode with no real hardware attached, allowing the creation of configuration files for
the PES16NT2 in the absence of the actual device.

Much of the Device Management Software is written with device-independent and OS-independent
code. The software will be guaranteed to work on Linux (/sys interface) and MS Windows XP. It may func­tion flawlessly on various flavors of MS Windows, but may not be validated on all. The fact that the software
is device-independent assures its scalability to future PCIe parts from IDT. Onc e users are familiar with the
GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each
device through an XML device description file which includes information on the number of ports, registers,
types of registers, information on bit-fields within each register, etc.

EB16NT2 Eval Board Manual 3 - 1 November 13, 2007

IDT Software for the EB16NT2 Eval Board

Notes

EB16NT2 Eval Board Manual 3 - 2 November 13, 2007

Chapter 4

Schematics

®

Notes

Schematics

EB16NT2 Eval Board Manual 4 - 1 November 13, 2007

8

7

6

5

4

3

DCN

STGC-0125R01 1.0 INITIAL RELEASE 2007-10-09 J.HU

REV

2

DESCRIPTION

REVISIONS

DATE

1

CHANGE BY

D

C C

02_DESIGN_TOP

D

B B

A

TITLE

shasta 16NT2 eval board

DRAWING NO.

SIZE

B

STGSCH-00124

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

7

6

2007

45

3

AUTHOR

jhu
Tue Oct 09 13:22:13 2007

2

FAB P/N

18-642-000

CHECKED BY

B.LE

PAGE 1 OF 9

1

REV.

1.0

A

8

7

6

5

3

2

1

D

D

08_PORT_C_IF

SLAVE SMBUS CONNECTOR

HDR_1X4_100

4
3
2

J10

1

PERST_N

03_POWER_SUPPLY

PERST_N

M_SSMBDATA

M_SSMBCLK

04_clocks

U_REFCLK_P
M_SSMBDATA

M_SSMBCLK

M_PERST_N

M_REFCLK1_PU_REFCLK_N
M_REFCLK1_N

M_REFCLK0_P
M_REFCLK0_N

M_PERST_N

M_REFCLK1_P
M_REFCLK1_N

M_REFCLK0_P
M_REFCLK0_N

U_WAKE_N

M_PERST_N

M_SSMBDATA
M_SSMBCLK

M_REFCLK1_P
M_REFCLK1_N

M_REFCLK0_P
M_REFCLK0_N

05_89HPES16NT2_TOP

C_PERST_N

C_PETP<7..0>
C_PETN<7..0>

C_PERP<7..0>
C_PERN<7..0>

PORT_C_PRSNT

C_PERST_N
C_PETP<7..0>

C_PETN<7..0>
C_PERP<7..0>

C_PERN<7..0>
PORT_C_PRSNTN

U_WAKE_N

C_PERST_N
C_PETP<7..0>

C_PETN<7..0>
C_PERP<7..0>

C_PERN<7..0>
PORT_C_PRSTN

1K
1K
1K
1K

R93
R92
R94
R91

VCC_3V3

5%
5%
5%
5%

CC

BB

PERST_N
U_WAKE_N

M_SSMBCLK
M_SSMBDATA

U_REFCLK_P
U_REFCLK_N

PERST_N

09_PORT_A_IF

U_WAKE_N
M_SSMBCLK

M_SSMBDATA
U_REFCLK_P

U_REFCLK_N

U_PETP<7..0>
U_PETN<7..0>

U_PERP<7..0>
U_PERN<7..0>

U_PETP<7..0>
U_PETN<7..0>

U_PERP<7..0>
U_PERN<7..0>

U_PETP<7..0>
U_PETN<7..0>

U_PERP<7..0>
U_PERN<7..0>

JTAG_RST_N

M_TDI
M_TDO
M_TMS
M_TCK

JTAG_RST_N
M_TDI
M_TDO
M_TMS
M_TCK

33.2

R99

1%

JTAG HEADER

J4

1

1

3

3
5

7

7

9

9

1K

2
4
6
8

10

R101

2
4
65
8
10

5%

AA

TITLE

BLOCK DIAGRAM

SIZE

DRAWING NO.

B

STGSCH-00124

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

7

6

5442

2007

3

AUTHOR

jhu

FAB P/N

18-642-000

CHECKED BY

B.LE

PAGE 2 OF 9Mon Jul 16 15:08:19 2007

1

REV.

1.0

8

7

VCC_3V3

5%

D

R1

6

5

3

SACTTER ACROSS BOARD

2

POWER INDICATOR
PLACE NEAR TOP EDGE
LABEL 'POWER'

E6

E5

E1

1

11111

1

1E21E31E41

1

1

VCC_3V3

5%

R14DS2

D

VCC_3V3

C1

25V

C2

22UF

0.015UF

2C6^

IN

25
26
27
28

32

30
36
34
31

29

33

10
11
12

6

9

8

10K

PERST_N

VDD_CORE 1.0V

U1

VIN
VIN
VIN
VIN

AVIN

ENABLE
ROCP
SOFTSTART
VS0
VS1
VS2

AGND

PGND
PGND
PGND
PGND

COMP

1

EN5330

EAOUT

EAIN

5

4

NC

VDRAIN

7

19

VOUT_PAD

VSENSE

NC

24

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

XOV
XFB
POK

PGND
PGND
PGND
PGND
PGND

13
14
15
16
17
18
38
3

8
2

35

37
23
22
21
20

PSOP-5

U2

1
2

3

1

3

VCC

OE*
A

GND

SN74LVC1G125

S1

PB_SW

NC

S

BOARD RESET

VCC_1V0VC

TP1

RED

1%

1%

R4

R2

499

499

C7

1%

1%

R5

R3

47UF

2K

2K

7

ROUTE SIGNAL U4.7 AS SENSE

VCC_3V3

5

10K

4

Y

NO

2
4

R6

5%

2
7

1
3

C12

16V

TLC7733D

RESINN
SENSE
CONTROL
CT

10UF

VCC_3V3

VDDPE, 1.0V

25

10V

C8

25V

C9

22UF

0.015UF

26
27
28

32

30
36
34
31

29

33

10
11
12

6

9

VIN
VIN
VIN
VIN

AVIN

ENABLE
ROCP
SOFTSTART
VS0
VS1
VS2

AGND

PGND
PGND
PGND
PGND

6

COMP

1

EN5330

EAOUT

EAIN

5

4

U4

U3

NC

VDRAIN

7

19

RESETN

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

VOUT_PAD

VSENSE

PGND
PGND
PGND
PGND
PGND

NC

24

VCC

RESET

GND

XOV
XFB
POK

13
14
15
16
17
18

38
3

8
2

35

37
23
22
21
20

VCC_3V3

8
6
5
4

C13

47UF

R8

499

R9

2K

W27

1

1

2

M_PERST_N

5%

R10

0R

3

SM0805

2

3

OUT

2C5^

VCC_EXT3V3

VCC_3V3

DS1

10V

RED
R13

10K

STR8

BLOCK
5%2K

VCC_12V

C279

25V

22UF

TP17

YEL

R7

C280

16V

DNP

330UF

U/S +12V -> +3.3V

U26

PTH08T240WAD

R207

1%

NA

10

11

2

1
9

8

Vin

Track
SYNC
TURBOTRANS

Inhibit

Vo_Adj

1.21K

VO_SEN+

Vout

VO_SEN-

GND2
GND1

6
5
7
4

3

330

VCC_3V3

C30

10UF

RED

TP4

VCC_1V0VA

1%

1%

R11

499

1%

1%

R12

C14

10V

47UF

VCC_3V3

C17

25V

22UF

C18

0.015UF

VPETVTT, 1.5V

25
26
27
28

32

30
36
34
31

29

33

10
11
12

6

9

VIN
VIN
VIN
VIN

AVIN

ENABLE
ROCP
SOFTSTART
VS0
VS1
VS2

AGND

PGND
PGND
PGND
PGND

COMP

1

EN5330

EAIN

4

U6

VDRAIN

EAOUT

5

19

VOUT_PAD

NC

NC

7

24

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

VSENSE

XOV
XFB
POK

PGND
PGND
PGND
PGND
PGND

13
14
15
16
17
18

38
3

8
2

35

37
23
22
21
20

VCC_1V5VA

RED

TP5

C27

10V

47UF

TITLE

POWER SUPPLY

SIZE

DRAWING NO.

STGSCH-00124

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

5442

2007

3

AUTHOR

jhu

W36

C282

C281

10V

10V

47UF

220UF

25
26
27
28

32

6

30

16V

36
34
31

C33

29

33

9

10

0.015UF

11
12

TP10

RED

C19

C20

0.1UF

0.1UF

VDDPEA, 1.0V

VIN
VIN
VIN
VIN

AVIN

ENABLE
ROCP
SOFTSTART
VS0
VS1
VS2

AGND

PGND
PGND
PGND
PGND

NC

1

EN5310

NC

NC

5

4

FAB P/N

U7

NC

7

VOUT_PAD

NC

NC

19

24

VSENSE

18-642-000

CHECKED BY

B.LE

C21

0.1UF

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

XOV
XFB
POK

PGND
PGND
PGND
PGND
PGND

C22

C23

0.1UF

0.1UF

13
14
15
16
17
18

38
3

8
2

35

37
23
22
21
20

PAGE 3 OF 9Mon Jul 16 15:08:24 2007

330

GRN

0603

C24

C25

0.1UF

0.1UF

VCC_1V0VB

TP7

RED

1%

R15

499

1%

R16

2K

1

VCC_3V3

C26

0.1UF

1%

R17

499

C38

25V

1%

R18

22UF

2K

1.0

CC

BB

AA

REV.

8

7

6

5

3

2

1

D

VCC_3V3

C39

C40

25V

22UF

0.001UF

S2

SM_SW8

1

S1A

2

S2A

3

S3A

4

S4A

5

S5A

6

S6A

7

S7A
S8A

SG-8002CA25.0000M-PCBB:ROHS

1

OE

2

GND

25MHZ

Y1

S1B
S2B
S3B
S4B
S5B
S6B
S7B
S8B

16
15
14
13
12
11
10
98

VCC
OUT

VCC_3V3

OSC_ENA

SSC_S0
SSC_S1
SSC_SS0
SSC_SS1

4

3

1

0R

3

1

0R

3

VCC_3V3

5%

TP6

WHT

33

1

W5

2

3

SM0805

1

W6

2

3

SM0805

10K

10K

10K

R21

R20

R22

R19

5%

5%

5% 10K

VCC_3V3A_CLK

C43

1UF

12
16

8

3

2

1

R23
5%

4
5

6

2

2

OUTPUT SELECT

S2:2

ON
ON
OFF
OFF

C44

16V

16V

10UF

ICS557-03

VDDODA

SS1
SS0

S1
S0

X1/ICLK

X2
OE

S2:1

ON
OFF
ON
OFF

FB1

400MA

C46

C45

0.1UF

0.1UF

U8

GNDODA

2B6^

2B6^

120OHM

CLK0P
CLK0NVDDXD

CLK1P
CKL1N

IREF

GNDXD

S10S0

0
0

1

1

0

1

1

0805

U_REFCLK_P

IN

U_REFCLK_N

IN

VCC_3V3

C41

16V

C42

1UF

0.1UF

14
11

10

33
33

R26

R27
R28

5%

R29

33

15

33

9
13

7

475

1%

R25

CLK (1:0)

25M

100M
125M

200M

PLACE RESISTORS

L_REFCLK_P

L_REFCLK_N

5%
5%

5%

1%

1%

1%

1%

R31

R30

R33

R32

49.9

49.9

49.9

49.9

1

SM0805

0R

W7

3

1

1

W8

2

3

3

SM0805

2

2

CLOSE TO U9

1

0R

3

VCC_3V3

1

0R

3

1

0R

3

1

0R

3

1

0R

3

1

0R

3

1

0R

3

1

1

0R

3

2B6^
2B6^

2

SCR_IN_P

SRC_IN_N

1

0R

3

1

W9

2

2

3

1

0R

3

1

W11

2

2

3

1

0R

3

1

W13

2

2

3

1

0R

3

1

W14

2

2

3

1

1

0R

3

1

W30

2

2

3

1

1

0R

3

1

W15

2

2

3

1

SM0805

0R

3

W16

2

2

3

IN
IN

1

W17

2

3

1

W18

2

3

1

W19

2

3

1

W20

2

3

W35

2

2

3

W21

2

2

3

1

W26

2

3

M_SSMBCLK
M_SSMBDATA

2B5^
2B5^

2B5^
2B5^

D

CC

BB

AA

VCC_3V3

FB2
120OHM

400MA

0805

C49

16V

C51

C50

2

2

2

2

2

VCC_3V3A_BUFF

2

VDD

19

VDD

39

VDD

4

SRC_IN

5

SRC_IN#

6

OE0#

14

OE1#

15

OE2#

7

OE3#

43

OE4#

35

OE5#

36

OE6#

44

OE7#

27

SRC_STOP

26

PD

28

HIGH_BW#

40

OE_INV

22

BYPASS#/PLL

23

SCLK

24

SDATA

1

SRC_DIV#

3

GND

10

GND

18

GND

ICS9DB801

U9

VDD
VDD

VDDA

DIF_0

DIF_0#

DIF_1

DIF_1#

DIF_2

DIF_2#

DIF_3

DIF_3#

DIF_4

DIF_4#

DIF_5

DIF_5#

DIF_6

DIF_6#

DIF_7

DIF_7#

LOCK
IREF

GNDA

GND
GND

11

31

48
8

9
12

13
16

17
20

21

30

29

34
33

38
37

42
41

45
46

47

32

25

1UF

R_REFCLK1P
R_REFCLK1N

R_REFCLK0P

R_REFCLK0N

475

R55

0.1UF

1%

0.1UF

33
33

33
33

33
33

33
33

33
33

33
33

33
33

33
33

GRN

0603

STR8
5%

R35 DS3

330

R46
R47

R48
R57

R56
R58

R49
R50

R51
R52

R53
R54

R36
R37

R38
R39

C47

1UF

5%
5%

5%
5%

16V

5%
5%

5%
5%

5%
5%

5%
5%

5%
5%

5%
5%

R40

49.9

C48

0.1UF

C_REFCLK1P
C_REFCLK1N

C_REFCLK0P

C_REFCLK0N

1%

1%

R43

R41

R68

49.9

49.9

49.9

1%

1%

1%

R67

R42

49.9

49.9

1%

R70

49.9
1%

R63

R69

49.9

49.9

1%

R64

49.9

1%

1%

R60

49.9
1%

R59

49.9

1%

R62

49.9
1%

R61

49.9

0.1UF

0.1UF

1%

R66

49.9

1%

R65

49.9

0.1UF

0.1UF

C55

C53

C56

C54

R_REFCLKN

R_REFCLKP

1%

M_REFCLK1_P
M_REFCLK1_N

M_REFCLK0_P

M_REFCLK0_N

CONNSMA

54

J3

OUT
OUT

OUT
OUT

1

2

221789-3

J2

CONNSMA

54

3

1
2

221789-3

3

TITLE

CLOCK GENERATION

SIZE

DRAWING NO.

STGSCH-00124

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

7

6

5442

2007

3

AUTHOR

jhu

FAB P/N

18-642-000

CHECKED BY

B.LE

PAGE 4 OF 9Mon Jul 16 15:08:21 2007

1

REV.

1.0

8

7

6

5

3

2

1

06_89HPES16NT2_PORTS

C_LREV
U_LREV

6C6v

2A5^
6D6v

U_PERP<7..0>

IN

D

6C6v

6A6v

6A6v

2A5^
6D6v

2B3^
6B6v

2B3^
6B6v

2C5^

U_PERN<7..0>

IN

C_PERP<7..0>

IN

C_PERN<7..0>

IN

IN

C_PERST_N

IN

M_PERST_N

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

VCC_3V3

U_PERP<7>
U_PERN<7>
U_PERP<6>
U_PERN<6>
U_PERP<5>
U_PERN<5>
U_PERP<4>
U_PERN<4>
U_PERP<3>
U_PERN<3>
U_PERP<2>
U_PERN<2>
U_PERP<1>
U_PERN<1>
U_PERP<0>
U_PERN<0>

C_PERP<7>
C_PERN<7>
C_PERP<6>
C_PERN<6>
C_PERP<5>
C_PERN<5>
C_PERP<4>
C_PERN<4>
C_PERP<3>
C_PERN<3>
C_PERP<2>
C_PERN<2>
C_PERP<1>
C_PERN<1>
C_PERP<0>
C_PERN<0>

1

1

W28

2

0R

3

3

1

1

W29

2

0R

3

3

U_PERP7
U_PERN7
U_PERP6
U_PERN6
U_PERP5
U_PERN5
U_PERP4
U_PERN4
U_PERP3
U_PERN3
U_PERP2
U_PERN2
U_PERP1
U_PERN1
U_PERP0
U_PERN0

C_PERP7
C_PERN7
C_PERP6
C_PERN6
C_PERP5
C_PERN5
C_PERP4
C_PERN4
C_PERP3
C_PERN3
C_PERP2
C_PERN2
C_PERP1
C_PERN1
C_PERP0
C_PERN0

2

1

1

0R

3

3

2

1

1

0R

3

3

W31

2

W33

2

U_PETP7
U_PETN7
U_PETP6
U_PETN6
U_PETP5
U_PETN5
U_PETP4
U_PETN4
U_PETP3

PORT APORT C

U_PETN3
U_PETP2
U_PETN2
U_PETP1
U_PETN1
U_PETP0
U_PETN0

C_PETP7
C_PETN7
C_PETP6
C_PETN6
C_PETP5
C_PETN5
C_PETP4
C_PETN4
C_PETP3
C_PETN3
C_PETP2
C_PETN2
C_PETP1
C_PETN1
C_PETP0
C_PETN0

1

1

W3

2

0R

3

3

2

2

S5

SM_SW8

1

S1A

2

S2A

3

S3A

4

S4A

5

S5A

6

S6A

7

S7A
S8A

S1B
S2B
S3B
S4B
S5B
S6B
S7B
S8B

16
15
14
13
12
11
10
98

U_PETP<7> U_PETP<7..0>
U_PETN<7>
U_PETP<6>
U_PETN<6>
U_PETP<5>
U_PETN<5>
U_PETP<4>
U_PETN<4>
U_PETP<3>
U_PETN<3>
U_PETP<2>
U_PETN<2>
U_PETP<1>
U_PETN<1>
U_PETP<0>
U_PETN<0>

C_PETP<7>
C_PETN<7>
C_PETP<6>
C_PETN<6>
C_PETP<5>
C_PETN<5>
C_PETP<4>
C_PETN<4>
C_PETP<3>
C_PETN<3>
C_PETP<2>
C_PETN<2>
C_PETP<1>
C_PETN<1>
C_PETP<0>
C_PETN<0>

2B5^

IN

2B5^

IN

2B5^

IN

2B5^

IN

2

2B5^

IO

2B5^

IO

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

M_REFCLK1_P
M_REFCLK1_N

M_REFCLK0_P
M_REFCLK0_N

M_PECRSTN

M_SSMBCLK

M_SSMBDATA

M_SSMBADDR5
M_SSMBADDR3
M_SSMBADDR2
M_SSMBADDR1

M_MSMBADDR4

M_MSMBADDR3
M_MSMBADDR2
M_MSMBADDR1
M_REFCLKM
M_RSTHALT
M_MSMBSMODE

U_PETN<7..0>

C_PETP<7..0>

C_PETN<7..0>

HDR_1X4_100

W34

OUT
OUT

OUT

OUT

M_SCL
M_SDA

2B5^

6C4v

2A5^

6B4v
2B3^
6A4v

6B4v
2B3^
6A4v

M_MSMBADDR3
M_MSMBADDR2
M_MSMBADDR1

Y21
Y22

P1

P2
AA19
AB15

AA15

Y15

AB10
AA10

Y9

AA9
AB9

Y8

AB8
AA8
Y18

Y7

AA7
AB7

Y6

6D4v6C4v
6D4v

VCC_3V3

R96

2.7K

5%

R95

2.7K

U10

PEREFCLKP1
PEREFCLKN1

PEREFCLKP0
PEREFCLKN0

REFCLKM

PERST_n
PENTBRST_n
RSTHALT

SSMBCLK

SSMBDAT

SSMBADDR_5
SSMBADDR_3
SSMBADDR_2
SSMBADDR_1

MSMBCLK
MSMBDAT
MSMBSMODE

MSMBADDR_4
MSMBADDR_3
MSMBADDR_2
MSMBADDR_1

5%

EEPROM

24LC512

6

SCL

5

SDA

3

A2

2

A1

1

A0

53R-1063-000

C_LREV
U_LREV

PLACE EEPROM ON SOCKET

VCC_3V3

5%

R100

5%

R221

U13

8

VCC

7

WP

4

GND

GPIO_05_FAILOVERP
GPIO_04_PCLINKUPN

GPIO_02_PALINKUPN

GPIO_01_PECRSTN

JTAG_TCK

JTAG_TRST_n

2.7K

GPIO_07
GPIO_06

GPIO_03

GPIO_00

JTAG_TMS
JTAG_TDI
JTAG_TDO

CCLKUS
CCLKDS

SWMODE_3
SWMODE_2
SWMODE_1
SWMODE_0

W12

1

2

AA18
AB18
Y17
AA17
AB17
Y16
AA16
AB16

AB5
AA6
AB6
AA5
Y5

Y10
Y11

AA14
AB14
Y13
AA13

330

0603

0603

GRN

DS31

R225

330

GRN

DS35

5%

R220

330

0603

GRN

DS30

07_89HPES16NT2_POWER

R219

330

0603

0603

GRN

DS29

5%

R223

3305%330

GRN

DS33

0R

R76DS4

GRN

0603

STR8

1

3

TITLE

GPIO_7
GPIO_6
U_FAILOVERP

GPIO_3

PORT_C_PRSNT

1

W1

2

2

3

SM0805

M_TCK
JTAG_RST_N
M_TMS
M_TDI

M_TDO

5%5%5%

R224

330

0603

GRN

DS34

M_TDO_BYPASS
M_CCLKUS
M_CCLKDS

M_SWMODE3
M_SWMODE2
M_SWMODE1
M_SWMODE0

YEL
TP11
YEL
TP12
YEL
TP13
YEL
TP8
YEL
TP14
YEL
TP9
YEL
TP16

IN

IN
IN
IN
IN

OUT

2B3^

2A3^
2B3^
2A3^
2B3^

2A3^

VCC_3V3

5%10K

5%

R44

R81

10K

10K
5%

R82

R45

10K

5%

R79

10K
5%

R71

10K

D

CC

5%

R72

BB

10K
5%

5%

R73

10K

S6

SM_SW8

16

S1B

15

S2B

14

S3B

13

S4B

12

S5B

11

S6B

10

S7B

98

S8B

S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A

1
2
3
4
5
6
7

AA

5%

10K
10K

VCC_3V3

8

7

10K
10K
10K

R109
R108
R107
R106
R105
R104
R103

5%

5%10K
5%10K
5%
5%
5%

16NT2 DEVICE TOP

SIZE

DRAWING NO.

STGSCH-00124

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

6

5442

2007

3

AUTHOR

jhu

FAB P/N

18-642-000

CHECKED BY

B.LE

PAGE 5 OF 9Mon Jul 16 15:08:27 2007

1

REV.

1.0

8

7

6

5

3

2

1

D

D

U10

5D7^
5D7^

5D7^
5D7^

5D7^
5D7^

5D7^
5D7^

5D7^
5D7^

5D7^
5D7^

5D7^
5D7^

5D7^
5C7^

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN

U_LREV

U_PERP7
U_PERN7

U_PERP6
U_PERN6

U_PERP5
U_PERN5

U_PERP4
U_PERN4

U_PERP3
U_PERN3

U_PERP2
U_PERN2

U_PERP1
U_PERN1

U_PERP0
U_PERN0

Y12

C4
D4

D6
C6

C8
D8

D10
C10

D12
C12

C14
D14

D16
C16

C18
D18

PEALREV

PEARP07
PEARN07

PEARP06
PEARN06

PEARP05
PEARN05

PEARP04
PEARN04

PEARP03
PEARN03

PEARP02
PEARN02

PEARP01
PEARN01

PEARP00
PEARN00

UPETP7

PEATP07
PEATN07

PEATP06
PEATN06

PEATP05
PEATN05

Port A

PEATP04
PEATN04

PEATP03
PEATN03

PEATP02
PEATN02

PEATP01
PEATN01

PEATP00
PEATN00

B5
A5

B7
A7

B9
A9

B11
A11

A13
B13

B15
A15

A17
B17

B19
A19

UPETN7
UPETP6

UPETN6
UPETP5

UPETN5
UPETP4

UPETN4

UPETP3
UPETN3

UPETP2
UPETN2

UPETP1
UPETN1

UPETP0
UPETN0

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C159

C158

C157

C156

C155

C154

C153

C152

C167

C166

C165

C164

C163

C162

C161

C160

U_PETP7
U_PETN7

U_PETP6
U_PETN6

U_PETP5
U_PETN5

U_PETP4
U_PETN4

U_PETP3
U_PETN3

U_PETP2
U_PETN2

U_PETP1
U_PETN1

U_PETP0
U_PETN0

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

5D6^
5D6^

5D6^
5D6^

5D6^
5D6^

5D6^
5D6^

5D6^
5D6^

5D6^
5D6^

5D6^
5D6^

5D6^
5C6^

CC

U10

5C7^
5C7^

5C7^
5C7^

5C7^
5C7^

5C7^
5C7^

5C7^
5C7^

5C7^
5C7^

5C7^
5C7^

5C7^
5C7^

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN

C_LREV

C_PERP7
C_PERN7

C_PERP6
C_PERN6

C_PERP5
C_PERN5

C_PERP4
C_PERN4

C_PERP3
C_PERN3

C_PERP2
C_PERN2

C_PERP1
C_PERN1

C_PERP0
C_PERN0

Y14
E20

E19
G19

G20
J20

J19
L20

L19
N19

N20
R20

R19
U19

U20
W20

W19

PECLREV

PECRP07
PECRN07

PECRP06
PECRN06

PECRP05
PECRN05

PECRP04
PECRN04

PECRP03
PECRN03

PECRP02
PECRN02

PECRP01
PECRN01

PECRP00
PECRN00

PECTP07
PECTN07

PECTP06
PECTN06

PECTP05

Port B

PECTN05

PECTP04
PECTN04

PECTP03
PECTN03

PECTP02
PECTN02

PECTP01
PECTN01

PECTP00
PECTN00

D21
D22

F21
F22

H21
H22

K22
K21

M21
M22

P21
P22

T21
T22

V21
V22

CPETP7
CPETN7

CPETP6
CPETN6

CPETP5
CPETN5

CPETP4
CPETN4

CPETP3
CPETN3

CPETP2
CPETN2

CPETP1
CPETN1

CPETP0
CPETN0

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C95

C94

C93

C92

C91

C90

C89

C88

C103

C102

C101

C100

C99

C98

C97

C96

C_PETP7
C_PETN7

C_PETP6
C_PETN6

C_PETP5
C_PETN5

C_PETP4
C_PETN4

C_PETP3
C_PETN3

C_PETP2
C_PETN2

C_PETP1
C_PETN1

C_PETP0
C_PETN0

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

5C6^
5C6^

5C6^
5C6^

5C6^
5C6^

5C6^
5C6^

5C6^
5C6^

5C6^
5C6^

5C6^
5C6^

5C6^
5C6^

BB

AA

TITLE

16NT2 INTERFACES US/DS

SIZE

DRAWING NO.

STGSCH-00124

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

7

6

5442

2007

3

AUTHOR

jhu

FAB P/N

18-642-000

CHECKED BY

B.LE

PAGE 6 OF 9Mon Jul 16 15:08:35 2007

1

REV.

1.0

8

7

6

5

3

2

1

ROUTE CONNECTIONS TO W25 W10 W22 W23 W24 AS POWER 100 MILLS MIN

VCC_3V3

W10

D

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C57

16V

0.1UF

1UF

VCC_1V0VC

W25

1

1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

47UF
47UF

2

C245

16V
C221
C222
C223
C224
C225
C226
C227
C228
C229
C230
C231
C232
C247
C248
C249
C250
C251
C252
C253
C254
C255
C256
C257
C258
C259
C260
C261
C262
C263
C264
C265
C266
C267
C268
C269
C270

C243

10V

C244

10V

VCC_1V0_VA

W22

1

2

1UF

47UF
47UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C212

16V

C189

C190

A3
AA12
AA20

AA3
AA4

B3

C1

C2

C20
C21
C22

C3

E1

E2

E4

F3

G1

G2

G4

H10
H13
H15

H3

H6

H8

J10
J12
J14

J2

J4

J8

K11
K13
K15

K3

K6

K9

L10
L12
L14

L2

L4

U10

VDDCORE_00
VDDCORE_01
VDDCORE_02
VDDCORE_03
VDDCORE_04
VDDCORE_05
VDDCORE_06
VDDCORE_07
VDDCORE_08
VDDCORE_09
VDDCORE_10
VDDCORE_11
VDDCORE_12
VDDCORE_13
VDDCORE_14
VDDCORE_15
VDDCORE_16
VDDCORE_17
VDDCORE_18
VDDCORE_19
VDDCORE_20
VDDCORE_21
VDDCORE_22
VDDCORE_23
VDDCORE_24
VDDCORE_25
VDDCORE_26
VDDCORE_27
VDDCORE_28
VDDCORE_29
VDDCORE_30
VDDCORE_31
VDDCORE_32
VDDCORE_33
VDDCORE_34
VDDCORE_35
VDDCORE_36
VDDCORE_37
VDDCORE_38
VDDCORE_39
VDDCORE_40
VDDCORE_41

VCC_1V0_VC

VDDCORE_42
VDDCORE_43
VDDCORE_44
VDDCORE_45
VDDCORE_46
VDDCORE_47
VDDCORE_48
VDDCORE_49
VDDCORE_50
VDDCORE_51
VDDCORE_52
VDDCORE_53
VDDCORE_54
VDDCORE_55
VDDCORE_56
VDDCORE_57
VDDCORE_58
VDDCORE_59
VDDCORE_60
VDDCORE_61
VDDCORE_62
VDDCORE_63
VDDCORE_64
VDDCORE_65
VDDCORE_66
VDDCORE_67
VDDCORE_68
VDDCORE_69
VDDCORE_70
VDDCORE_71
VDDCORE_72
VDDCORE_73
VDDCORE_74
VDDCORE_75
VDDCORE_76
VDDCORE_77
VDDCORE_78
VDDCORE_79
VDDCORE_80
VDDCORE_81
VDDCORE_82
VDDCORE_83

L8
M11
M13
M15
M17
M6
M9
N10
N12
N14
N3
N4
N8
P11
P13
P15
P9
R3
R4
R6
T11
T12
T15
T9
U16
U17
U18
U4
V1
V10
V12
V14
V16
V18
V3
V7
W2
W4
W9
Y1
Y3
Y4

VCC_3V3_A

1

2

C215
C216
C217
C218
C219
C220

VCC_1V0VA

C191
C192
C193
C194
C195
C196
C197
C198
C199
C200
C201
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211

10V
10V

U10

F6

VDDIO_00

G11

VDDIO_01

G16

VDDIO_02

G17

VDDIO_03

G7

VDDIO_04

J6

VDDIO_05

L6

VDDIO_06

P6

VDDIO_07

T10

VDDIO_08

T13

VDDIO_09

T14

VDDIO_10

T16

VDDIO_11

T17

VDDIO_12

T6

VDDIO_13

T7

VDDIO_14

T8

VDDIO_15

W11

VDDIO_16

W14

VDDIO_17

W16

VDDIO_18

W6

VDDIO_19

W8

VDDIO_20

D11

VDDPE_00

E12

VDDPE_01

E16

VDDPE_02

E8

VDDPE_03

F11

VDDPE_04

F12

VDDPE_05

F15

VDDPE_06

F18

VDDPE_07

F8

VDDPE_08

H17

VDDPE_09

L17

VDDPE_10

L18

VDDPE_11

P17

VDDPE_12

P18

VDDPE_13

U21

VDDPE_14

V19

VDDPE_15

VCC_1V0VB

W24

1

2

C187

16V

C188

1UF

0.1UF

VTTPE_00
VTTPE_01
VTTPE_02
VTTPE_03
VTTPE_04
VTTPE_05
VTTPE_06
VTTPE_07
VTTPE_08
VTTPE_09
VTTPE_10
VTTPE_11
VTTPE_12
VTTPE_13
VTTPE_14
VTTPE_15

VDDAPE_00
VDDAPE_01
VDDAPE_02
VDDAPE_03
VDDAPE_04
VDDAPE_05
VDDAPE_06
VDDAPE_07
VDDAPE_08
VDDAPE_09
VDDAPE_10
VDDAPE_11
VDDAPE_12
VDDAPE_13
VDDAPE_14
VDDAPE_15

120OHM

0805

120OHM

0805

120OHM

0805

C13
C15
D7
D9
E10
E13
E15
E7
H18
H19
K19
K20
N21
N22
U22
V20

E9
F10
F13
F14
F9
G14
J16
J18
K17
N17
N18
N5
N6
R17
R18
T20

FB3

400MA

FB4

400MA

FB5

400MA

VCC_1V5_VA

C235

C236

C233

C234

C213

16V

0.1UF

0.1UF

0.1UF

0.1UF

1UF

W23

1

1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C169

C168

C237

C238

C239

0.1UF

0.1UF

0.1UF

VCC_1V5VA

2

C170

16V

C171
C172
C173
C174
C175
C176
C177
C178
C179
C180
C181
C182
C183
C184
C185
C186

47UF

10V

47UF

10V

VCC_1V0_VB

C240

C241

C242

C52

C271

C272

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C274

C273

C275

0.1UF

0.1UF

0.1UF

C277

C276

47UF

0.1UF

10V

C278

10V

47UF

A1
A10
A12
A14
A16
A18

A2
A20
A21
A22

A4

A6

A8
AA1

AA11

AA2

AA21
AA22

AB1

AB11
AB12
AB13
AB19

AB2

AB20
AB21
AB22

AB3
AB4

B1
B10
B12
B14
B16
B18

B2
B20
B21
B22

B4

B6

B8
C11
C17
C19

C5

C7

C9

D1
D13
D15
D17
D19

D2
D20

D3

D5

U10

VSS_000
VSS_001
VSS_002
VSS_003
VSS_004
VSS_005
VSS_006
VSS_007
VSS_008
VSS_009
VSS_010
VSS_011
VSS_012
VSS_013
VSS_014
VSS_015
VSS_016
VSS_017
VSS_018
VSS_019
VSS_020
VSS_021
VSS_022
VSS_023
VSS_024
VSS_025
VSS_026
VSS_027
VSS_028
VSS_029
VSS_030
VSS_031
VSS_032
VSS_033
VSS_034
VSS_035
VSS_036
VSS_037
VSS_038
VSS_039
VSS_040
VSS_041
VSS_042
VSS_043
VSS_044
VSS_045
VSS_046
VSS_047
VSS_048
VSS_049
VSS_050
VSS_051
VSS_052
VSS_053
VSS_054
VSS_055
VSS_056

VSS_057
VSS_058
VSS_059
VSS_060
VSS_061
VSS_062
VSS_063
VSS_064
VSS_065
VSS_066
VSS_067
VSS_068
VSS_069
VSS_070
VSS_071
VSS_072
VSS_073
VSS_074
VSS_075
VSS_076
VSS_077
VSS_078
VSS_079
VSS_080
VSS_081
VSS_082
VSS_083
VSS_084
VSS_085
VSS_086
VSS_087
VSS_088
VSS_089
VSS_090
VSS_091
VSS_092
VSS_093
VSS_094
VSS_095
VSS_096
VSS_097
VSS_098
VSS_099
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112

E11
E14
E17
E18
E21
E22
E3
E5
E6
F1
F16
F17
F19
F2
F20
F4
F5
F7
G10
G12
G13
G15
G18
G21
G22
G3
G5
G6
G8
G9
H1
H11
H12
H14
H16
H2
H20
H4
H5
H7
H9
J1
J11
J13
J15
J17
J21
J22
J3
J5
J7
J9
K1
K10
K12
K14

K16
K18

K2
K4
K5
K7
K8

L1
L11
L13
L15
L16
L21
L22

L3

L5

L7

L9

M1
M10
M12
M14
M16
M18
M19

M2
M20

M3

M4

M5

M7

M8

N1
N11
N13
N15
N16

N2

N7

N9
P10
P12
P14
P16
P19
P20

P3

P4

P5

P7

P8

R1
R10
R11
R12
R13

U10

VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168

VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224

R14
R15
R16
R2
R21
R22
R5
R7
R8
R9
T1
T18
T19
T2
T3
T4
T5
U1
U10
U11
U12
U13
U14
U15
U2
U3
U5
U6
U7
U8
U9
V11
V13
V15
V17
V2
V4
V5
V6
V8
V9
W1
W10
W12
W13
W15
W17
W18
W21
W22
W3
W5
W7
Y19
Y2
Y20

D

CC

BB

AA

TITLE

16NT2 DEVICE POWER

SIZE

DRAWING NO.

STGSCH-00124

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

7

6

5442

2007

3

AUTHOR

jhu

FAB P/N

18-642-000

CHECKED BY

B.LE

PAGE 7 OF 9Mon Jul 16 15:08:31 2007

1

REV.

1.0

8

7

6

5

3

2

1

D

VCC_EXT3V3

D

VCC_3V3AUX

VCC_EXT3V3

TP15

RED

PERST_N

OUT

OUT
OUT

2B6^

2A6^
2A6^

0

1

2

3

4

5

6

7

CC

0

1

2

U_PETP<7..0>
U_PETN<7..0>

IN
IN

2B5^
2A5^

BB

3

4

5

6

7

2A5^
2A5^

OUT
OUT

U_PERP<7..0>
U_PERN<7..0>

2B6^
2A6^

M_SSMBCLK

OUT

M_SSMBDATA

OUT

2B6^

IN

DNP
DNP

U_WAKE_N

0

0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

R74
R75

U_PERP<0>
U_PERN<0>

U_PERP<1>
U_PERN<1>

U_PERP<2>
U_PERN<2>

U_PERP<3>
U_PERN<3>

U_PERP<4>
U_PERN<4>

U_PERP<5>
U_PERN<5>

U_PERP<6>
U_PERN<6>

U_PERP<7>
U_PERN<7>

VCC_12V

C149

C148

16V

25V

P1

PCIE_X8_EDGE

B1

+12V

B2

10UF

10UF

R77

0

0%

R78

0

0%

B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

+12V
RSVD
GND
SMCLK
SMDAT
GND
+3.3V
JTAG_TRSTN

3.3VAUX

WAKE#

RSVD
GND
PETP0
PETN0
GND
PRSTN2#
GND
PETP1
PETN1
GND
GND
PETP2
PETN2
GND
GND
PETP3
PETN3
GND
RSVD
PRSTN2#
GND
PETP4
PETN4
GND
GND
PETP5
PETN5
GND
GND
PETP6
PETN6
GND
GND
PETP7
PETN7
GND
PRSTN2#
GND

PRSTN1#

+12V
+12V

GND
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

+3.3V
+3.3V

PERST#

GND

REFCLK+
REFCLK-

GND

PERP0
PERN0

GND

RSVD

GND

PERP1
PERN1

GND

GND

PERP2
PERN2

GND

GND

PERP3
PERN3

GND

RSVD
RSVD

GND

PERP4
PERN4

GND

GND

PERP5
PERN5

GND

GND

PERP6
PERN6

GND

GND

PERP7
PERN7

GND

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

VCC_12V

TP18

RED

C150

C151

16V

25V

10UF

10UF

U_REFCLK_P
U_REFCLK_N

U_PETP<0>
U_PETN<0>

U_PETP<1>
U_PETN<1>

U_PETP<2>
U_PETN<2>

U_PETP<3>
U_PETN<3>

U_PETP<4>
U_PETN<4>

U_PETP<5>
U_PETN<5>

U_PETP<6>
U_PETN<6>

U_PETP<7>
U_PETN<7>

AA

TITLE

UPSTREAM CONNECTOR PORT A

SIZE

DRAWING NO.

STGSCH-00124

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

7

6

5442

2007

3

AUTHOR

jhu

FAB P/N

18-642-000

CHECKED BY

B.LE

PAGE 8 OF 9Mon Jul 16 15:08:36 2007

1

REV.

1.0

8

7

6

5

3

2

1

VCC_3V3

D

1%

R24

D

LANE REVERSAL AT THE CONNECTOR TO IMPROVE ROUTING.

2B2^

OUT

2B2^

PORT_C_PRSTN

WHT

TP19

C_PETP<7..0>

IN

C_PETN<7..0>

IN

VCC_3V3

1%

R80

WHT
TP2
WHT

1K

REMOTE POWER ON

TP3

W2

1K

C_PETP<7>

7

C_PETN<7>

7

C_PETP<6>

6

C_PETN<6>

6

C_PETP<5>

5

C_PETN<5>

5

C_PETP<4>

4

C_PETN<4>

4

C_REFCLK_P
C_REFCLK_N

DNP

2
1

3

2

1

0

CPOWERON

C_PETP<3>

3

C_PETN<3>
C_PETP<2>

2

C_PETN<2>
C_PETP<1>

1

C_PETN<1>
C_PETP<0>

0

C_PETN<0>

R34

NA

A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34

A1
A2
A3
A4
A5
A6
A7
A8
A9

J5

GND00
PETp0
PETn0
GND01
PETp1
PETn1
GND02
PETp2
PETn2
GND03
PETp3
PETn3
GND04

CREFCLKp

CREFCLKn
GND05
RSVD0
RSVD1
SB_RTN
CPRSNT_n
CPWRON
GND06
PETp4
PETn4
GND07
PETp5
PETn5
GND08
PETp6
PETn6
GND09
PETp7
PETn7
GND10

PCIe X8

GND11
PERp0
PERn0
GND12
PERp1
PERn1
GND13
PERp2
PERn2
GND14
PERp3
PERn3
GND15

PWR0
PWR1

PWR2
PWR_RTN0
PWR_RTN1
PWR_RTN2

CWAKE_n

CPERST_n

GND16
PERp4
PERn4
GND17
PERp5
PERn5
GND18
PERp6
PERn6
GND19
PERp7
PERn7
GND20

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34

C_PERP<7>
C_PERN<7>

C_PERP<6>
C_PERN<6>

C_PERP<5>
C_PERN<5>

C_PERP<4>
C_PERN<4>

VCC_C3V3

C_WAKE_N
C_PERST_N

C_PERP<3>
C_PERN<3>

C_PERP<2>
C_PERN<2>

C_PERP<1>
C_PERN<1>

C_PERP<0>
C_PERN<0>

7

7

6

6

5

4

5

4

VCC_3V3

C_PERP<7..0>
C_PERN<7..0>

W32

1

2

OUT
OUT

2B2^
2B2^2B2^

PLACE NEAR CONNECTOR

CC

C106

C107

16V

OUT

3

3

2

2

1

1

0

0

VCC_3V3AUX

R234

5%

16V

10UF

10UF

VCC_3V3

ZERO

1
2
3
4
5

Shield0
Shield1
Shield2
Shield3
Shield4
Shield5

J1

10K

C_WAKE_N

U22

1

OE*

2

A

3

GND

SN74LVC1G125

PSOP-5

VCC

Y

5

4

WAKE_R

8K3

3

1

W4

1

3

2

BB

2

U_WAKE_N

R235

0

0%

OUT

2C2^

AA

TITLE

DOWNSTREAM CONNECTOR PORTC

SIZE

DRAWING NO.

STGSCH-00124

B

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC.
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
COPYRIGHT (C) IDT

8

7

6

5442

2007

3

AUTHOR

jhu

FAB P/N

18-642-000

CHECKED BY

B.LE

PAGE 9 OF 9Tue Oct 09 11:21:44 2007

1

REV.

1.0