ICT PEEL22CV10AZJ-25, PEEL22CV10AZJI-25, PEEL22CV10AZP-25, PEEL22CV10AZPI-25, PEEL22CV10AZS-25 Datasheet

Commercial/

Industrial

PEEL™ 22CV10AZ

CMOS Programmable Electrically Erasable Logic Device

Features

■

Ult ra Low Power Operation

CC

= 5 Volts ±10%

- V

- Icc = 10 µA (typical) at standby

- Icc = 2 mA (typical) at 1 MHz

PD

= 25ns.

- t

■

CMOS Electrically Erasable Technology

- Superior factory testing

-

Reprogrammable in plastic package

-

Reduces retrofit and development costs

■

Development/Programmer Support

- Third party software and programmers

- ICT PLACE Development Software and PDS-3
programmer

General Description

The PEEL™22CV10AZ is a Programmable Electrically
Erasable Logic (PEEL™) device that provides a low power
alternative to ordinary PLDs. The PEEL™22CV10AZ is
available in 24-pin DIP, SOIC, TSSOP and 28-pin PLCC
packages (see Figure 19).

A “zero-power” (100µA max. I
PEEL™22CV10AZ ideal for power sensitive applications
such as handhe ld meters, portable communication e quip­ment and laptop computers/ peripherals. EE-reprogramma­bility provides the convenience of instant reprogramming
for development and a reusable producti on inventory mini­mizing the impact of programming changes or errors. EE­reprogrammability also improves factory testability, thus
ensuring the highest quality possible.

CC

) standby mode makes the

-25

■

Architectural Flexibility

-

133 product terms x 44 input AND array

-

Up to 22 inputs and 10 I/O pins

-

12 possible macrocell configurations

-

Synchronous preset, asynchronous clear

-

Independent output enables

-

Programmable clock source and polarity

-

24-pin DIP/SOIC/TSSOP and 28-pin PLCC

■

Application Versatility

-

Replaces random logic

-

Pin and JEDEC compatible with 22V10

-

Ideal for power-sensitive systems

The PEEL™22CV10AZ is JEDEC file compatible with stan­dard 22V10 PLDs. Eight additional configurations per mac­rocell (a total of 12) are also available by using the “+”
software/programming option (i.e., 22CV10AZ+). The addi­tional macrocell con figurations allow more logic to be put
into every device, potentially reducing the design's compo­nent count and lowering the power requirements even fur­ther.

Development and programming support for the
PEEL™22CV10AZ is provided by popular third-party pro­grammers and development software. ICT also offers free
PLACE development software and a low-cost development
system (PDS-3).

Figure 19 Pin Configuration

I/CLK

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8
910I

I

11

I

12

GND

DIP

PLCC

TSSOP

SOIC

Figure 19 Block Diagram

24

VCC

23

I/O

22

I/O

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O
I/O

16

I/O

15

I/O

14

I

13

1 of 10

I/CLK

PEEL™ 22CV10AZ

(OPTIONAL)

132

0

2

9

10

(2)

ASYNCHRONOUS CLEAR
(TO ALL MACROCELLS)

MACRO

CELL

I/O

(27)

MACRO

20

I

21

(3)

33

I

34

(4)

48

I

49

(5)

65

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

I/O

(26)

I/O

(25)

I/O

(24)

I/O

(23)

I

66

(6)

MACRO

CELL

82

I/O

(21)

I

83

(7)

97

I

98

(9)

110

I

111

(10)

121

I

124

(11)

130

I

(12)

131

I

(13)

Figure 21 PEEL™22CV10AZ Logic Array Diagram

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MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

SYNCHRONOUS PRESET
(TO ALL MACROCELLS)

I/O

(20)

I/O

(19)

I/O

(18)

I/O

(17)

I

(16)

PEEL™ 22CV10AZ

Funct ion De scription

The implements logic functions as sum-of-products expres­sions in a programmable-AND/fixed-OR logic array. User­defined functions are created by programming the connec­tions of input signals into the array. User-conf igurable out­put structures in the form of I/O macrocells further increase
logic flexibility.

Architecture Overview

The architecture is illustrated in the block diagram of Figure

19. Twelve dedicated inputs and 10 I/Os provide up to 22
inputs and 10 outputs for creating logic functions (see Fig­ure 21). At the core of the device is a programmable electri­cally-erasable AND array that drives a fixed OR array. With
this structure, the PEEL™ 22CV10AZ can implem ent up to
10 sum-of-products logic expressions.

Associated with each of the ten OR functions is an I/O mac­rocell that can be independently programmed to one of four
different configurations in standard 22V10 mode, or any
one of 12 configurations using the special “Plus” mode. The
programmable macrocells allow each I/O to be used to cre­ate sequential or combinatorial logic functions of active­high or active-low polarity, while providing three different
feedback paths into the AND array.

AND/OR Logic Array

The programmable AND array of the PEEL™22CV10AZ
(shown in Figure 21) is formed by input lines intersecting
product terms. The input lines and product terms are used
as follows:

■

44 Input Line s :

– 24 input lines c arry the tr ue and complement of the

signals applied to the 12 input pins

– 20 additional lines carry the true and complement

values of feedback or input signals from the 10 I/Os

When programming the PEEL™22CV10AZ, the device
programmer first performs a bulk erase to remo v e t he previ­ous pattern. The e rase cycle opens every logical connec­tion in the array. The device is configured to perform the
user-defined function by programming selected connec­tions in the AND array. (Note that PEEL™ device program­mers automatically program all of the connections on
unused product terms so that they will have no effect on the
output function).

Variable Product Term Distri bution

The PEEL™22CV10AZ provides 120 product terms to
drive the 10 OR functions. These product terms are distrib­uted among the outputs in groups of 8, 10, 12, 14, and 16
to form logical sums (see Figure 21). This distribution
allows optimum use of the device resources.

Programmable I/O Macrocell

The unique twelve-configuration outpu t macrocell provides
complete control over the architecture of each output. The
ability to configure each output independently lets you to
tailor the co n fi g u r a tion of the PEEL ™22 CV1 0 AZ to the pre­cise requirements of your design.

Macrocell Architecture

Each I/O macrocell, as shown in Figure 20, consists of a D­type flip-flop and two signal-select multiplexers. The config­uration of the macrocell is determined by four EEPROM
bits that control the multiplexers. These bits determine the
output polarity, output type (registered or non-registered)
and input-feedback path (bidirectional I/O, combinatorial
feedback). Refer to Table 1. for details. Four of these mac­rocells duplicate the functionality of the industry-standard
PAL22V10 . (See Figure 21 and Ta ble 1.)

■

133 Product Terms:

– 1 20 product ter ms (arranged in 2 groups of 8, 10, 12,

14, and 16) are used to form sum of product functions

– 10 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term

At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not
there is a logical connection at that intersection. Each prod­uct term is essentially a 44-input AND gate. A product term
that is connected to both t he true and complement of an
input signal will always be FALSE and therefore will not
affect the OR function that it drives. When all the connec­tions on a product term are opened, a “don’t care” state
exists and that term will always be TRUE.

Figure 20 Block Diagram of the
PEEL™22CV10A I/O Macrocell

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