ICT PEEL22CV10AJ-10, PEEL22CV10AJ-15, PEEL22CV10API-10, PEEL22CV10API-15, PEEL22CV10API-25 Datasheet

Commercial/

Industrial

PEEL™ 22CV10A

CMOS Programmable Electrically Erasable Logic Device

Features

■■■■

High Speed/Low Power

- Speeds ranging from 7ns to 25ns

- Power as low as 30mA at 25MHz

■■■■

Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

■■■■

Development/Programmer Support

- Third party software and programmers

- ICT PLACE Development Software

General Description

The PEEL™22CV10A is a Programmable Electrically Eras­able Logic (PEEL™) de vic e provid in g an attrac tive a lterna­tive to ordinary PLDs. The PEEL™22CV10A offers the
performance, flexibility, ease of design and production
practicality needed by logic designers today. The
PEEL™22CV10A is availa ble i n 24- pin DIP, SOIC, TSSOP
and 28-pin PLCC packages (see Figure 1), with speeds
ranging from 7ns to 25 ns and with power consumpt ion as
low as 30mA. EE-reprogrammability provides the conve­nience of instant reprogramming for development and a
reusable production inventory, minimizing the impact of
programming changes or errors. EE-reprogrammability

-7/-10/-15/-25

■■■■

Architectural Flexibility

- 132 product term X 44 input AND array

- Up to 22 inputs and 10 outputs

- Up to 12 configurations per macrocell

- Synchronous preset, asynchronous clear

- Independent output enables

- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC

■■■■

Application Versatility

- Replaces random logic

- Pin and JEDEC compatible with 22V10

- Enhanced Architecture fits more logic
than ordinary PLDs

also improves factory testability, thus ensuring the highest
quality possible. The PE EL™22CV 10A is JE DEC file com­patible with standard 22V10 PLDs. Eight additional configu­rations per macrocell (a total of 12) are also available by
using the “+” software/programming option (i.e.,
22CV10A+). The addi tional macrocell configurat ions allow
more logic to b e put into every design. Prog ramming and
development support for the PEEL™22CV10A are pro­vided by popular third-party programmers and develop­ment software. ICT also offers free PLACE development
software.

Figure 1. Pin Configuration Figure 2. Block Diagram

24

VCC

23

I/O

22

I/O

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O
I/O

16

I/O

15

I/O

14

I

13

DIP

PLCC

*Optional extra ground pin for

-7/I-7 speed grade.

I/CLK

I
I
I
I
I
I
I
I
I

I

GND

TSSOP

1
2
3
4
5
6
7
8
9
10
11
12

SOIC

1 of 10

04-02-009F

PEELTM 22CV10A

I/CLK

0

2

9

10

20

I

21

33

I

34

48

I

49

65

ASYNCHRONOUS CLEAR
(TO ALL MACROCELLS)

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

I/O

I/O

I/O

I/O

I/O

I

66

82

I

83

97

I

98

110

I

111

121

I

124

130

I

131

I

Figure 3. PEEL™22CV10A Logic Array Diagram

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

SYNCHRONOUS PRESET
(TO ALL MACROCELLS)

I/O

I/O

I/O

I/O

I/O

I

2 of 10

04-02-009F

PEELTM 22CV10A

Function Description

The PEEL™22CV10A imp lements logic functions as su m­of-products expressions in a programmable-AND/ fixed-OR
logic array. User-defined functions are created by program­ming the connections of input si gnals into the array. User­configurable output structu res in the fo rm of I/O macroc ells
further increase logic flexibi lity.

Architecture Overview

The PEEL™22CV10A architecture is illustrated in the block
diagram of Figure 2. Twelve dedicated inputs and 10 I/Os
provide up to 22 inputs and 10 outp uts for cre ation of log ic
functions. At the core of the device is a programmable elec­trically-erasabl e AND array which drives a fixed OR ar ray.
With this structure, the PEEL™22CV10A can implement up
to 10 sum-of-products logic expressions.

Associated with each of the 10 OR functions is an I/O mac­rocell which can be indep endentl y progr ammed to on e of 4
different configurations. The programmable macrocells
allow each I/O to cre ate sequential or combinatorial logic
functions with either active-high or active-low polarity.

AND/OR Logic Array

The programmable AND array of the PEEL™22CV10A
(shown in Figure 3) is formed by input lines intersecting
product terms. Th e input lines a nd product te rms are use d
as follows:

programming selected connections in the AND array. (Note
that PEEL™ device programmers automatically program
the connections on u nused product term s so that they will
have no effect on the output function.)

Variable Product Term Distribution

The PEEL™22CV10A pro vides 120 produc t terms to drive
the 10 OR functions. The se product terms are distributed
among the outputs in groups of 8, 10, 12, 14 and 16 to form
logical sums (see Figure 3). This distribution allows opti­mum use of device re-sources.

Programmable I/O Macrocell

The output macrocell provides complete control over the
architecture of each output. The ability to configure each
output independently permi ts users to tailor the configura­tion of the PEEL™22CV 10A to the pr ec ise r eq uir em ent s o f
their designs.

Macrocell Architecture

Each I/O macroc ell, as s hown in Figure 4, consists of a D­type flip-flop and two signal-select multiplexers. The config­uration of each macrocell is determined by the two
EEPROM bits contr olling these mu ltiplexers (r efer to Table

1). These bits determine output polarity and output type
(registered or non-registered). Equivalent circuits for the
four macro-cell configurations are illustrated in Figure 5.

44 Input Lines:

24 input lines carry the true and complement
of the signals applied to the 12 input pins
20 additional lines carry the true and complement
values of feedback or input signals from
the 10 I/Os

132 product terms:

120 product terms (arranged in 2 groups of 8,
10, 12, 14 and 16) used to form logical sums
10 output enable terms (one for each I/O)
1 global synchronous present term
1 global asynchronous clear term

At each input-line/product-term intersection there is an
EEPROM memory cell which determines whether or not
there is a logical connection at that intersection. Each prod­uct term is essentiall y a 44- i npu t AND gate . A p roduc t te rm
which is connected to b oth the true and complem ent of an
input signal will al ways be FALSE, and thus will not affect
the OR function that i t drives. When al l the connec tions on
a product term are opened, a “don ’t care” state exists and
that term will always be TRUE. When programming the
PEEL™22CV10A, the device programmer first performs a
bulk erase to remove the previous pattern. The erase cycle
opens every logical co nnection in the array. The device is
then configured to perform the user-defined function by

Output Type

The signal from the OR array ca n be fed di re ct ly to the out­put pin (combinatorial function) or latched in the D-type flip­flop (registered func tion). The D-type flip-flop la tches data
on the rising edge of the clock and is cont roll ed by the glo­bal preset and c lear terms. When th e synchronous prese t
term is satisfied, the Q output of the register will be set
HIGH at the next rising edg e of the clock input. Satis fying
the asynchronou s clear te rm will se t Q LOW, regardless o f
the clock state. If bo th terms are satisfied simult aneously,
the clear will override the preset.

Output Polarity

Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.

Output Enable

The output of each I/O macrocell can be enabled or dis­abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is driven into the high-impedance state.

Under the control of the output enable term, the I/O pin can
function as a dedicated inp ut, a dedicated output, or a bi­directional I/O. Opening every connection on the output

3 of 10

04-02-009F