ICST MK2771-16R, MK2771-16RTR Datasheet
MK2771-16
ICRO
C
LOCK
Description
The MK2771-16 is a low cost, low jitter, high
performance VCXO and clock synthesizer
designed for set-top boxes. The on-chip Voltage
Controlled Crystal Oscillator accepts a 0 to 3V
input voltage to cause the output clocks to vary by
±100 ppm. Using ICS/MicroClock’s patented
VCXO and analog Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive
13.5 MHz crystal input to produce multiple
output clocks including a selectable processor
clock, a selectable audio clock, two
communications clocks, a 13.5 MHz clock, and
three 27 MHz clocks. All clocks are frequency
locked to the 27.00MHz output (and to each
other) with zero ppm error, so any output can be
used as the VCXO output.
Block Diagram
VDD5
VCXO and Set-Top Clock Source
Features
• Packaged in 28 pin SSOP (QSOP)
• On-chip patented VCXO with pull range
of 200ppm (minimum)
• VCXO tuning voltage of 0 to 3V
• Processor frequency include 16.66, 20, 25, 32, 40,
and 50 MHz
• Audio clocks support 32 kHz, 44.1 kHz, 48 kHz
and 96 kHz sampling rates
• Zero ppm synthesis error in all clocks (all exactly
track 27MHz VCXO)
• Uses an inexpensive 13.5 MHz crystal
• Full CMOS output swings with 25mA output
drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 5V operating voltage with 3.3V capable I/O
GND
VDDIO
AS2:0
PS1, PS0
CS1, CS0
13.5 MHz
pullable
crystal
VIN
X2
X1
3
2
2
Voltage
Controlled
Crystal
Oscillator
PLL
Clock
Synthesis
Circuitry
x2
PLL
÷2
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffers
Output
Buffer
ACLK
PCLK
CCLK1
CCLK2
3
27.000 MHz
13.500 MHz
MDS 2771-16 C 1 Revision 102099 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
MK2771-16
Pin Assignment
PS0
GND
VDD5
VIN
VDDIO
VDD5
CS1
GND
GND
PCLK
CCLK2
ACLK
1
2
X2
3
4
X1
5
6
7
8
9
10
11
12
13
14
VDD5=5V±10%
VDDIO=3.3V±10%
VIN=0 to 3.0V (3.3V OK)
ICRO
28
AS1
27
AS0
26
CS0
25
27M
24
GND
23
27M
22
VDD5
21
AS2
20
GND
19
GND
18
27M
17
CCLK1
16
PS1
15
13.5M
C
LOCK
VCXO and Set-Top Clock Source
Audio Clock (MHz)
AS2 AS1 AS0 ACLK
0 0 0 8.192
0 0 1 11.2896
0 1 0 12.288
0 1 1 5.6448
1 0 0 18.432
1 0 1 16.9344
1 1 0 49.152
1 1 1 24.576
0 = connect directly to GND
M = leave unconnected (floating)
1 = connect directly to VDDIO
Communications Clocks (MHz)
CS1 CS0 CCLK1 CCLK2
0 0 Low 33.333
0 1 Low 24.576
1 0 11.0592 18.432
1 1 11.0592 3.6864
Processor Clock (MHz)
PS1 PS0 PCLK
0 0 50
0 1 16.667
M 0 25
M 1 32
1 0 40
1 1 20
Number Name Type Description
1 PS0 I Processor Clock Select 0. Selects PCLK frequency. See table above. Internal pull-up.
2 X2 XO Crystal connection. Connect to a pullable 13.5 MHz crystal.
3, 10, 11 GND P Connect to ground.
4 X1 XI Crystal connection. Connect to a pullable 13.5 MHz crystal.
5, 8, 22 VDD5 P Connect to +5V.
6 VIN I Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
7 VDDIO P Connect to +3.3V or +5V. Amplitude of inputs and outputs will match this.
9 CS1 I Communications clock select pin 1 . Selects CCLK 1 and 2 per table above. Internal pull-up.
12 PCLK O Processor Clock output. Determined by status of PS1, PS0.
13 CCLK2 O Communications Clock output 2 determined by status of CS1,CS0 per table above.
14 ACLK O Audio Clock Output. Determined by status of AS2:0 per table above.
15 13.5M O 13.50 MHz VCXO clock output.
16 PS1 TI Processor Clock Select 1. Selects PCLK frequency. See table above. Self-biased to M.
17 CCLK1 O Communications Clock output 1 determined by status of CS1, CS0 per table above.
18, 23, 25 27M O 27.00 MHz VCXO clock output.
19, 20, 24 GND P Connect to ground.
21 AS2 I Audio Clock Select 2. Selects ACLK on pin 14 per table above. Internal pull-up.
26 CS0 I Communications clocks select pin 0. Selects CCLK1 and 2 per table above. Internal pull-up.
27 AS0 I Audio Clock Select 0. Selects ACLK on pin 14. See table above. Internal pull-up.
28 AS1 I Audio Clock Select 1. Selects ACLK on pin 14. See table above. Internal pull-up.
Key: I = Input; TI = Tri-level input; O = output; P = power supply connection; XI, XO = crystal connections
MDS 2771-16 C 2 Revision 102099 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
Loading...