ICST MK2771-15RTR, MK2771-15R Datasheet
MK2771-15
VCXO and Set-Top Clock Source
Description
The MK2771-15 is a low cost, low jitter, high
performance VCXO and clock synthesizer
designed for set-top boxes. The on-chip Voltage
Controlled Crystal Oscillator accepts a 0 to 3V
input voltage to cause the output clocks to vary by
±100 ppm. Using ICS/MicroClock’s patented
VCXO and analog Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive
13.5 MHz pullable crystal input to produce
multiple output clocks including two selectable
processor clocks, a selectable audio clock, two
communications clocks, and three fixed clocks. All
clocks are frequency locked to the 27.00MHz
output (and to each other) with zero ppm error, so
any output can be used as the VCXO output.
Features
• Packaged in 28 pin SSOP (QSOP)
• Ideal for systems using Oak’s MPEG decoders
• On-chip patented VCXO with pull range
of 200ppm
• VCXO tuning voltage of 0 to 3 V
• Processor frequencies include 33.3, 40, 50, 66.6,
81, and 100 MHz
• Audio clocks of 8.192 MHz, 11.2896 MHz,
12.288 MHz and 18.432 MHz
• Zero ppm synthesis error in all clocks (all exactly
track 27 MHz VCXO)
• Uses an inexpensive 13.5 MHz pullable crystal
• Full CMOS output swings with 25 mA output
drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 5 V operating voltage with 3.3 V capable I/O
Block Diagram
PCS2:0
ACS1:0
SC
VIN
13.5 MHz
pullable
crystal
MDS 2771-15 E 1 Revision 122899 Printed 11/16/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 •(408) 295-9800tel• www.icst.com
X1
X2
Controlled
Oscillator
VDD GND
3
2
Voltage
Crystal
Clock
Synthesis
Circuitry
VDDIO
÷ 2
÷ 2
Output
Buffers
Output
Buffer
Output
Buffers
Output
Buffer
Output
Buffer
Output
Buffer
2
Processor Clocks
Audio Clock
2
Comm. Clocks
54.00 MHz
27.000 MHz
13.500 MHz
MK2771-15
VCXO and Set-Top Clock Source
Pin Assignment
PCS0
X2
X1
VDD
VDD
VIN
VDDIO
VDD
SC
GND
PCLK1
PCLK2
PCS1
ACLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ACS1
ACS0
54M
27M
GND
CCLK1
VDD
VDD
PCS2
GND
GND
CCLK2
13.5M
DC
Pin Descriptions
Number Name Type Description
1 PCS0 I Processor Clock Select 0. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
2 X2 XO Crystal connection. Connect to a pullable 13.5 MHz crystal.
3 X1 XI Crystal connection. Connect to a pullable 13.5 MHz crystal.
4, 5, 8 VDD P Connect to +5V.
6 VIN I Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
7 VDDIO P Connect to +3.3V or +5V. Amplitude of inputs must, and outputs will, match this.
9 SC TI Communications clock select pin. Biased to M level if floating.
10, 18, 19, 24 GND P Connect to ground.
11 PCLK1 O Processor Clock output number 1. Determined by status of PCS2:0
12 PCLK2 O Processor Clock output number 2. Determined by status of PCS2:0
13 PCS1 I Processor Clock Select 1. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
14 ACLK O Audio Clock Output. Determined by status of ACS1, ACS0 per table above.
15 DC - Don't Connect anything to this pin.
16 13.5M O 13.50 MHz VCXO clock output.
17 CCLK2 O Communications Clock Output 2 determined by status of SC per table above.
20 PCS2 I Processor Clock Select 2. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
21, 22 VDD P Connect to +5V.
23 CCLK1 O Communications Clock Output 1 determined by status of SC per table above.
25 27M O 27.00 MHz VCXO clock output.
26 54M O 54.00 MHz VCXO clock output.
27 ACS0 I Audio Clock Select 0. Selects ACLK on pin 14. See table above. Internal pull-up.
28 ACS1 I Audio Clock Select 1. Selects ACLK on pin 14. See table above. Internal pull-up.
Processor Clock Select Table (MHz)
PCS2 PCS1 PCS0 PCLK1 PCLK2
0 0 0 27.500 Off
0 0 1 33.333 66.666
0 1 0 33.326 83.314
0 1 1 50.000 100.000
1 0 0 32.400 81.000
1 0 1 40.000 33.333
1 1 0 TEST TEST
1 1 1 TEST TEST
Audio Clock Table
ACS1 ACS0 ACLK (MHz)
0 0 8.192
0 1 11.2896
1 0 12.288
1 1 18.432
0 = connect directly to ground, 1 = connect directly
to VDDIO, M = leave floating or unconnected
Comm Clock Table (MHz)
SC CCLK1 CCLK2
0 18.432 24.576
M 11.0592 18.432
1 11.0592 24.576
Key: I = Input; TI = Tri-level input; O = output; P = power supply connection; XI, XO = crystal connections
MDS 2771-15 E 2 Revision 122899 Printed 11/16/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 •(408) 295-9800tel• www.icst.com
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