ICST MK2049-03SITR, MK2049-03STR, MK2049-03S, MK2049-02S, MK2049-02SITR Datasheet
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MK2049-02/03
Communications Clock PLLs
Description
The MK2049-02 and MK2049-03 are PhaseLocked Loop (PLL) based clock synthesizers that
accept multiple input frequencies. With an 8 kHz
clock input as a reference, the MK2049-02/03
generate T1, E1, T3, E3, ISDN, xDSL, and other
communications frequencies. This allows for the
generation of clocks frequency-locked and phaselocked to an 8 kHz backplane clock, simplifying
clock synchronization in communications systems.
The MK2049-02/03 can also accept a T1, E1, T3,
or E3 input clock and provide the same output for
loop timing. All outputs are frequency-locked
together and to the input.
These parts also have a jitter-attenuated buffer
capability. In this mode, the MK2049-02/03 are
ideal for filtering jitter from 27 MHz video clocks
or other clocks with high jitter.
ICS/MicroClock can customize these devices for
many other different frequencies. Contact your
ICS/MicroClock representative for more details.
Features
• Packaged in 20 pin SOIC
• Fixed input-output phase relationship on most
clock selections
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accept multiple inputs: 8 kHz backplane clock,
Loop Timing frequencies, or 10-28 MHz
• Lock to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of
10–28 MHz input and x1/x0.5 or x2/x4 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and OC3 submultiples
• 5 V ±5% operation. Refer to MK2049-34 for 3.3 V
Block Diagram
RESET
FS3:0
Clock
Input
Reference
Crystal
MDS 2049-02/03 B 1 Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
4
External/
Loop Timing
Mux
X1
Crystal
Oscillator
X2
VDD GND
4 3
Synthesis,
Control, and
Attenuation
Circuitry
CAP1
PLL
Clock
Jitter
CAP2
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
CLK3
8 kHz
(External
Mode only)
Pin Assignment
MK2049-02/03
Communications Clock PLLs
FS1 FS0
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
CLK3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
20 pin (300 mil) SOIC
Pin Descriptions
Number Name Type Description
1 FS1 I Frequency Select 1. Determines CLK input/outputs per tables on pages 4 & 5.
2 X2 XO Crystal connection. Connect to a MHz crystal as shown in the tables on pages 4 & 5.
3 X1 XI Crystal connection. Connect to a MHz crystal as shown in the tables on pages 4 & 5.
4 VDD P Connect to +5V.
5 VDD P Connect to +5V.
6 VDD P Connect to +5V.
7 GND P Connect to ground.
8 CLK2 O Clock 2 output determined by status of FS3:0 per tables on pages 4 & 5.
9 CLK1 O Clock 1 output determined by status of FS3:0 per tables on pages 4 & 5. Always 1/2 of CLK2.
10 CLK3 O Clock 3 as shown in tables on pages 4 &5; typically recovered 8 kHz clock output.
11 FS2 I Frequency Select 2. Determines CLK input/outputs per tables on pages 4 & 5.
12 FS3 I Frequency Select 3. Determines CLK input/outputs per tables on pages 4 & 5.
13 ICLK I Input clock connection. Connect to 8 kHz backplane or MHz clock.
14 GND P Connect to ground.
15 VDD P Connect to +5V.
16 CAP1 LF Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.
17 GND P Connect to ground.
18 CAP2 LF Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.
19 RESET I Reset pin. Resets internal PLL when low. Outputs will stop low. Internal pull-up resistor.
20 FS0 I Frequency Select 0. Determines CLK input/outputs per tables on pages 4 & 5.
Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter
connections
MDS 2049-02/03 B 2 Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MK2049-02/03
ABSOLUTE MAXIMUM RATINGS (Note 1)
DC CHARACTERISTICS (VDD = 5V unless noted)
AC CHARACTERISTICS (VDD = 5V unless noted)
Communications Clock PLLs
Electrical Specifications
Parameter Conditions Minimum Typical Maximum Units
Supply Voltage, VDD Referenced to GND 7 V
Inputs and Clock Outputs -0.5 VDD+0.5 V
Ambient Operating Temperature MK2049-0xS 0 70 °C
MK2049-0xSI -40 85 °C
Soldering Temperature Max of 10 seconds 250 °C
Storage Temperature -65 150 °C
Operating Voltage, VDD 4.75 5 5.25 V
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input High Voltage, VIH Pin 19 only VDD-0.5 V
Input Low Voltage, VIL Pin 19 only 0.5 V
Output High Voltage IOH=-4 mA VDD-0.4 V
Output High Voltage IOH=-8 mA 2.4 V
Output Low Voltage IOL=8 mA 0.4 V
Operating Supply Current, IDD No Load, VDD=5.0V 20 mA
Short Circuit Current Each output ±100 mA
Input Capacitance, FS3:0 7 pF
Input Frequency, External Mode ICLK 8.000 kHz
Input Clock Pulse Width 10 ns
Propagation Delay ICLK to CLK2 0 2 ns
Output-Output Skew, Zero Delay Selections CLK1 to CLK2, Note 2 500 ps
Output Clock Rise Time 0.8 to 2.0 V 1.5 ns
Output Clock Fall Time 2.0 to 0.8 V 1.5 ns
Output Clock Duty Cycle, High Time At VDD/2 40 60 %
Actual mean frequency error versus target Any clock selection 0 0 ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CLK1 in the MK2049-02 may have the rising or falling edge aligned with the rising edge of CLK2. See the INPUT AND
OUTPUT SYNCHRONIZATION section for more details.
MDS 2049-02/03 B 3 Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
Communications Clock PLLs
MK2049-02 Output Decoding Table – External Mode (MHz)
ICLK FS3 FS2 FS1 FS0 CLK1 CLK2 Crystal CLK3
(Note 3)
8 kHz 0 0 0 0 1.544 3.088 12.352 8 kHz
8 kHz 0 0 0 1 2.048 4.096 12.288 8 kHz
8 kHz 0 0 1 0 22.368 44.736 11.184 8 kHz
8 kHz 0 0 1 1 17.184 34.368 11.456 8 kHz
8 kHz 0 1 0 0 19.44 38.88 12.96 8 kHz
8 kHz 0 1 0 1 16.384 32.768 8.192 8 kHz
8 kHz 0 1 1 0 24.576 49.152 12.288 8 kHz
8 kHz 0 1 1 1 25.92 51.84 12.96 8 kHz
8 kHz 1 1 0 0 10.24 20.48 10.24 8 kHz
8 kHz 1 1 0 1 4.096 8.192 12.288 8 kHz
MK2049-02 Output Decoding Table – Loop Timing Mode (MHz)
ICLK FS3 FS2 FS1 FS0 CLK1 CLK2 Crystal CLK3
(Note 3)
1.544 1 0 0 0 1.544 3.088 12.352 N/A
2.048 1 0 0 1 2.048 4.096 12.288 N/A
44.736 1 0 1 0 22.368 44.736 11.184 N/A
34.368 1 0 1 1 17.184 34.368 11.456 N/A
MK2049-02/03
MK2049-02 Output Decoding Table – Buffer Mode (MHz)
ICLK FS3 FS2 FS1 FS0 CLK1 CLK2 Crystal CLK3
(Note 3)
19 - 28 1 1 1 0 ICLK/2 ICLK ICLK/2 N/A
10 - 14 1 1 1 1 2*ICLK 4*ICLK ICLK N/A
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
= No Zero (Fixed) I/O Delay for these selections shown in the shaded boxes.
Note 3: CLK1 rising or falling edge may align with the input clock. See Figure 1 on page 6
for more details.
MDS 2049-02/03 B 4 Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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