ICST AV9250F-08, ICS9250F-08 Datasheet
ICS9250-08
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
Block Diagram
Frequency Generator & Integrated Buffers for Celeron & PII/III™
9250-08 Rev H 10/8/99
Functionality
Pin Configuration
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
• 3 - CPUs @2.5V, up to 150MHz.
• 17 - SDRAM @ 3.3V, up to 150MHz.
• 7 - PCI @3.3V
• 2 - IOAPIC @ 2.5V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 150MHz frequency support
• Support power management: CPU, PCI, stop and Power
down Mode form I
2
C programming.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• Uses external 14.318MHz crystal
Key Specifications:
• CPU – CPU: <175ps
• CPU – PCI: min = 1ns max = 4ns
• PCI – PCI: <250ps
• SDRAM - SDRAM: <500ps
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
VDDREF
* REF1
*PCI_STOP/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
**FS3/PCICLK0
GND
VDDPCI
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
FS2/
VDDLIOAPIC
IOAPIC0
IOAPIC_F
GND
CPUCLK_F
CPUCLK1
VDDLCPU
CPUCLK2
GND
CPU_STOP#
SDRAM_F
VDDSDR
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDD48
24MHz/FS0*
48MHz/FS1*
ICS9250-08
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
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I
C
2
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UPC
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1110 421)4/UPC(13
1101 051)4/UPC(5.73
1100 041)4/UPC(53
1011 501)3/UPC(53
1010 011)3/UPC(76.63
1001 511)3/UPC(33.83
1000 021)3/UPC(00.04
0111 3.001)3/UPC(34.33
0110 331)3/UPC(33.44
0101 211)3/UPC(33.73
0100 301)2/UPC(33.43
0011 8.66)2/UPC(04.33
0010 3.38)2/UPC(56.14
0001 57)2/UPC(5.73
0000 421)2/UPC(33.14
CPU_STOP#
PCI_STOP#
PLL2
PLL1
Spread
Spectrum
48MHz
IOAPIC0
CPUCLK [2:1]
CPUCLK_F
IOAPIC_F
SDRAM [15:0]
SDRAM_F
PCICLK [5:0]
PCICLK_F
X1
X2
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
STOP
÷2
STOP
STOP
POR
SDATA
SCLK
FS[3:0]
MODE
{
I
C
2
Control
Logic
Config.
Reg.
REF [1:0]
24MHz
LATCH
1
2
2
16
66
4
BUFFERIN
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS92 50-08
Third party brands and names are the property of their respective owners.
Pin Configuration
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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3
ICS92 50-08
Third party brands and names are the property of their respective owners.
General Description
The ICS9250-08 is the single chip clock solution for Desktop/
designs using BX, Appollo Pro 133 type of chip sets. It provides
all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9250-08
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Power Groups
VDDREF = REF [1:0], X1, X2
VDDPCI = PCICLK_F, PCICLK [5:0]
VDDSDR = SDRAM [15:0], supply for PLL core,
VDD48 = 48MHz, 24MHz
VDDLIOAPIC = IOAPIC_F
VDDLCPU = CPUCLK_F [2:1]
Mode Pin - Power Management Input Control
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4
ICS92 50-08
Third party brands and names are the property of their respective owners.
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
AC
K
Byte Count
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte 4
ACK
Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
ACK
Byte 2
AC
K
Byte 3
AC
K
Byte 4
AC
K
Byte 5
AC
K
Stop Bit
How to Write:
5
ICS92 50-08
Third party brands and names are the property of their respective owners.
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211
301
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1100
0100
8.66
3.38
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1000
0000
57
421
)2/UPC(5.73
)3/UPC(33.14
1111
0111
331
421
)4/UPC(52.33
)4/UPC(00.13
1011
0011
051
041
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)4/UPC(00.53
1101
0101
501
011
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1001
0001
511
021
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Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 2, 4, 5,
6 are default to 0000, and if bit 3 is written to a 1 to use Bits 2, 6:4, then these
should be defined to desired frequency at same write cycle.
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